Epitaxial silicon wafer and method for manufacturing same

Abstract

The epitaxial silicon wafer includes: a silicon wafer in which the entire surface (excluding an edge region from the outermost edge to 2 mm inward) is a COP region; and an epitaxial silicon layer formed on the surface of the silicon wafer. The average COP size in a peripheral region located within 5 mm inward from the outermost edge of the silicon wafer is 75 nm or less.

Description

Technical Field

[0001] The invention relates to an epitaxial silicon wafer and a method for manufacturing the same. Background Art

[0002] Epitaxial silicon wafers are widely used as substrate materials for semiconductor devices. Epitaxial silicon wafers are formed by growing a silicon epitaxial layer on a silicon wafer, and have the characteristics of high crystal integrity.

[0003] Heavy metal impurities in epitaxial silicon wafers can cause defects in the characteristics of semiconductor devices, so it is desirable to minimize such impurities as much as possible. One technique for reducing the effects of heavy metal impurities is gettering, which can be intrinsic gettering (IG), in which oxygen precipitates (bulk micro defects: BMDs) are formed within the silicon wafer to capture heavy metal impurities. In recent years, epitaxial silicon wafers have been required to have a BMD density of 1×10 8 / cm 3 or higher to improve the impurity absorption capacity.

[0004] Patent Document 2 describes an epitaxial silicon wafer in which the nitrogen concentration is adjusted to 1×10 12 ~1×10 13 atoms / cm 3 , and a silicon epitaxial film is formed on the surface of the silicon wafer consisting of the COP region. The BMD density within the silicon wafer subjected to the evaluation heat treatment ranges from 1×10 8 Up to 3×10 9 / cm 3 In addition, the average BMD density in the peripheral region (defined in Patent Document 2 as within 1 to 10 mm from the outermost edge of the silicon wafer) is lower than that in the central region, and the BMD density variation in the peripheral region is 3 or less. The residual oxygen concentration in the peripheral region is 8×10 17 atoms / cm 3 or higher.

[0005] [Prior art literature]

[0006] [Patent Document]

[0007] [Patent Document 2] Japanese Patent No. 6493105 Summary of the invention

[0008] [Problems to be Solved by the Invention]

[0009] Most silicon single crystals used as substrate materials for epitaxial silicon wafers are manufactured by a pulling method (Czochralski method, CZ method). Conventionally, in the manufacture of silicon single crystals for epitaxial silicon wafers, productivity is prioritized over crystal quality, and the silicon single crystal is pulled at a maximum pulling speed that does not cause crystal deformation. This is because it is believed that the crystal quality of the silicon substrate has little effect on the quality of the semiconductor device because the surface of the silicon substrate will be covered with an epitaxial silicon film.

[0010] However, the faster the pulling speed, the more crystal-derived particles (COPs) are generated in the silicon single crystal, and the larger the COP size becomes. COPs are void defects formed by the aggregation of vacancies, which are point defects, and the larger the COP size, the more vacancies are consumed in the silicon single crystal, and the fewer residual vacancies are left. There is a proportional relationship between residual vacancies and BMD (bulk microdefect) density, so when the number of residual vacancies decreases, the BMD density in the silicon wafer also decreases. Epitaxial wafers made from conventional silicon wafers (substrates) tend to have a lower BMD density, especially in the periphery. In the present disclosure, the periphery means within 5 mm inward from the outermost edge of the silicon wafer. The reduction in BMD density leads to a decrease in the ability to get rid of impurities, which can lead to a lower yield of semiconductor devices.

[0011] BMDs grow from BMD nuclei by applying heat. The formation of BMDs is further caused by the consumption of residual vacancies. Therefore, a low number of residual vacancies may reduce the BMD density.

[0012] Therefore, the object of the present invention is to provide an epitaxial silicon wafer and a method for manufacturing the same, which can improve the uniformity of the distribution of BMD density. In the present invention, "BMD variation" means the variation of the BMD density in an area of ​​the wafer. The BMD variation can be quantified by the following steps: obtaining the difference between the maximum BMD density and the minimum BMD density in an area of ​​the wafer, and then dividing such a difference by the average BMD density in the area of ​​the wafer. The measurement of BMD density can be carried out at intervals of 5mm over most of the wafer. Near the edge of the wafer, the BMD density can be obtained at smaller intervals, such as 1mm. The BMD variation mentioned herein means "in-plane" variation, which means measuring across the horizontal plane of the wafer to measure the BMD density.

[0013] [Methods used to solve the problem]

[0014] In order to solve the above-mentioned problems, an epitaxial silicon wafer according to the present invention comprises a silicon wafer having a COP and an epitaxial silicon layer formed on the surface of the silicon wafer. The wafer is characterized in that the average COP size in the peripheral region is 75 nm or less, and the peripheral region is located within 5 mm inward from the outermost edge of the silicon wafer.

[0015] According to the present invention, it is possible to prevent a decrease in BMD density caused by an increase in the size of COP in the peripheral region of a wafer. Therefore, an epitaxial silicon wafer having a high gettering ability can be provided.

[0016] The average COP size in the central region of the silicon wafer is preferably 120 nm or less, but greater than 100 nm. This improves the uniformity of the BMD density. Additionally, increasing the average COP size to above 100 nm allows for higher crystal pulling rates, thereby improving the productivity of the single crystal.

[0017] It is difficult to measure COP near the edge of the wafer. In particular, the measurement of COP within 2 mm from the edge of the wafer (the "edge region") may be inaccurate. Therefore, the BMD density currently disclosed may not be accurate in this edge region. However, as long as the rest of the surface (excluding the edge region) contains a measurable COP, the effects of the present invention can be fully obtained.

[0018] After subjecting the wafer to oxygen precipitation evaluation heat treatment at 780° C. for 3 hours and 1000° C. for 16 hours, the BMD density in the silicon wafer (excluding the edge region (i.e., within 2 mm from the edge)) is preferably 5×10 8 / cm 3 Up to 7×10 9 / cm 3 , and the BMD variation is preferably 0.6 or less. In another embodiment, the BMD variation is more preferably 0.5 or less. This allows providing an epitaxial silicon wafer with consistently high gettering capability across the wafer surface.

[0019] In one embodiment, BMD variation may be determined by measuring BMD density in a radial direction at 5 mm intervals from the center to 139 mm and at 1 mm intervals from 139 mm to 148 mm (referred to herein as the "outer region").

[0020] In another embodiment, the BMD density is preferably 5×10 8 / cm 3 Up to 7×10 9 / cm 3 , and the BMD variation is preferably 0.35 or less. This allows provision of an epitaxial silicon wafer having a uniformly high gettering capability across the wafer surface.

[0021] BMD is caused by oxygen precipitates (Oi) in the wafer. The Oi concentration in a 300 mm wafer (measured by ASTM_F121, 1979) is preferably 10×10 17 atoms / cm3 Up to 14×10 17 atoms / cm 3 , which allows to obtain sufficient BMD density in the wafer.

[0022] After the oxygen precipitation evaluation heat treatment, the Oi concentration (ASTM_F121, 1979) of the peripheral region (i.e., the region located within 5 mm inward from the outermost edge of the silicon wafer) is preferably 8×10 17 atoms / cm 3 Up to 13×10 17 atoms / cm 3 This ensures the desired BMD density in the peripheral region of the wafer while suppressing the reduction in wafer strength due to the lack of residual oxygen concentration. Therefore, it is possible to prevent the occurrence of slip dislocations in the peripheral region of the wafer while ensuring the desired gettering capability by a sufficient BMD density.

[0023] The nitrogen concentration in the silicon wafer is preferably 3×10 12 atoms / cm 3 Up to 9×10 13 atoms / cm 3 The nitrogen-doped silicon wafer forms thermally stable oxygen precipitation nuclei during the growth stage of the silicon single crystal, and these oxygen precipitation nuclei are less likely to disappear even during high-temperature heat treatment in the epitaxial process, thereby preventing a decrease in the BMD density. As a method for measuring the nitrogen concentration, for example, SIMS (Secondary Ion Mass Spectrometry) or low-temperature FT-IR using infrared absorption spectroscopy of a NO donor (nitrogen-oxygen composite donor) can be used.

[0024] The COP size of the silicon wafer can be measured using the LST (Light Scattering Tomography) method, in which the output power of the laser irradiated onto the silicon wafer is 100 mW, the transmittance of the ND filter used to reduce the amount of scattered light to within the dynamic range is between 20% and 50%, the scanning distance of the laser is 2000 μm, and the measurement depth of the scattered light is between 88.4 μm and 348.4 μm. This configuration improves the accuracy of COP measurement in silicon wafers.

[0025] Usually, the size of the COP formed in the silicon wafer is uneven. And the shape of COP is usually octahedral, and therefore the measurement of its size is difficult and requires certain estimation. In the present invention, the COP size is defined as the diameter of a sphere, which is estimated to have a volume similar to the COP being considered in the indicated measurement area of ​​the silicon wafer. First, the light intensity from the COP is measured using the LST method. Then, a sphere with the same light intensity is determined. Finally, the size of the COP is considered to be the diameter of such a sphere. Therefore, the average size of the COP is the average diameter (that is, the sum of the diameters divided by the total number of COPs) of multiple COPs. In a preferred embodiment, the average size of the COP means the sum of 50 or more diameters (corresponding to 50 or more COPs) divided by the total number of COPs.

[0026] When measuring the average COP size, laser scanning is performed in the radial direction within a range of ±1000 μm from the measurement point. Preferably, the average COP size is determined based on 50 or more COPs. If fewer than 50 COPs are identified in a single laser scanning measurement, the scanning position is shifted circumferentially within a range of ±1000 μm, and the laser scanning is repeated until the cumulative number of COPs exceeds 50. This means that the measurement range is expanded circumferentially to evaluate the COP.

[0027] The method for manufacturing an epitaxial silicon wafer according to the present invention comprises the steps of growing a silicon single crystal using a Czochralski (CZ) method, processing the silicon single crystal to form a silicon wafer having a diameter of 300 mm, and forming an epitaxial silicon film on the surface of the silicon wafer. The step of growing the silicon single crystal is characterized by satisfying the following Voronkov ratio (V / G):

[0028] 0.1830≤V / G≤(0.1035×CR1)-0.0350, where

[0029] 2.105≤CR1≤2.839,

[0030] Wherein, V represents the pulling speed of the silicon single crystal (mm / min), G represents the temperature gradient from the silicon melting point (about 1412°C) to 1350°C along the direction of crystal growth (°C / mm), and CR1 represents the cooling rate of the silicon single crystal at 1100°C at a distance of about 145 mm from the central axis of the crystal (°C / min). A positive value of the cooling rate indicates that the temperature decreases with the passage of time, while a negative value indicates that the temperature increases with the passage of time.

[0031] According to the present invention, it is possible to manufacture a silicon wafer in which the average COP size in the peripheral region (located within 5 mm inward from the outermost edge) is 75 nm or less. Therefore, it is possible to prevent the BMD density from decreasing in the peripheral region of the wafer due to an increase in the COP size and to provide an epitaxial silicon wafer having a uniformly high gettering capability across the entire surface.

[0032] In the present invention, it is preferred that the step of growing a silicon single crystal satisfies the following V / G conditions:

[0033] 0.1740≤V / G≤(0.1096×CR2)-0.0387, where

[0034] 1.940≤CR2≤2.624,

[0035] Among them, V represents the pulling speed of the silicon single crystal (mm / min), G represents the temperature gradient from the silicon melting point (about 1412°C) to 1350°C along the direction of crystal growth (°C / mm), and CR2 represents the cooling rate of the silicon single crystal at 1100°C around the central axis of the crystal (°C / min).

[0036] In addition, the method for manufacturing an epitaxial silicon wafer according to the present invention includes the steps of growing a silicon single crystal using a CZ method, processing the silicon single crystal to form a silicon wafer having a diameter of 300 mm, and forming an epitaxial silicon film on the surface of the silicon wafer. The step of growing a silicon single crystal involves using a water cooling body to cool a silicon single crystal pulled from a silicon melt, so that the entire surface of the silicon wafer (excluding an edge region within 2 mm from the outermost edge) is a COP region, and the average COP size in the peripheral region (located within 5 mm inward from the outermost edge of the silicon wafer) is 75 nm or less. This is achieved under the following process conditions: the crystal pulling speed is 60% to 90% of the maximum pulling speed without causing crystal deformation or damage, the gap between the heat shielding member and the melt surface is 40 to 80 mm, and the strength of the magnetic field applied near the solid-liquid interface is 2000 to 4000 Gauss.

[0037] According to the present invention, it is possible to manufacture a silicon wafer having an average COP size of 75 nm or less in a region within 5 mm from the edge ("peripheral region"), thereby preventing a decrease in BMD density caused by an increase in COP size in the peripheral region of the wafer, thereby providing an epitaxial silicon wafer having a uniformly high gettering capability across the wafer surface.

[0038] In the step of growing a silicon single crystal, it is preferred that a cooling rate CR1 (°C / min) at 1100°C at a position 145 mm from the central axis of the crystal in a radial direction is within a range of 2.105≤CR1≤2.839. This ensures that the average COP size at a position 145 mm from the central axis of the crystal is 75 nm or less, thereby improving the uniformity of the BMD density.

[0039] The method for manufacturing an epitaxial silicon wafer according to the present invention further comprises the following steps: experimentally determining a pulling speed of the silicon single crystal that results in an average COP size of 75 nm or less in the peripheral region by studying the COP distribution in a plurality of silicon wafer samples obtained from silicon single crystal samples pulled at various pulling speeds. This allows the manufacture of silicon wafers having an average COP size of 75 nm or less in the peripheral region.

[0040] [Effects of the Invention]

[0041] According to the present invention, it is possible to provide an epitaxial silicon wafer and a method for manufacturing the same, which are capable of improving the uniformity of distribution of BMD density. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] [ Figure 1 ] Figure 1 Schematic diagram of an epitaxial silicon wafer according to an embodiment of the present invention, wherein (a) is a schematic perspective view, and (b) is a schematic cross-sectional view.

[0043] [ Figure 2 ] Figure 2 is a flow chart schematically illustrating a method for manufacturing an epitaxial silicon wafer.

[0044] [ Figure 3 ] Figure 3 is a graph showing the general relationship between V / G and the type and distribution of crystal defects.

[0045] [ Figure 4 ] Figure 4 is a cross-sectional view schematically showing the structure of a single crystal pulling apparatus used in manufacturing a silicon single crystal by the CZ method.

[0046] [ Figure 5 ] Figure 5 shows the distribution of the average COP size of the epitaxial wafer, where Figure 5 (a) shows the distribution of average COP sizes in Comparative Examples 1 to 3, and Figure 5 (b) shows the distribution of average COP sizes in Examples 1 to 4.

[0047] [ Figure 6 ] Figure 6shows the distribution of BMD density of epitaxial wafers, where Figure 6 (a) shows the distribution of BMD density in Comparative Examples 1 to 3, and Figure 6 (b) shows the distribution of BMD density in Examples 1 to 4.

[0048] [ Figure 7 ] Figure 7 is a graph showing the relationship between the average COP size and BMD variation at a position within 5 mm inward from the outermost edge of the wafer.

[0049] [ Figure 8 ] Figure 8 shows the distribution of oxygen concentration in the epitaxial wafer before the oxygen precipitation evaluation heat treatment, where Figure 8 (a) shows the measurement results of oxygen concentration in Comparative Examples 1 to 3, and Figure 8 (b) shows the measurement results of oxygen concentration in Examples 1 to 4.

[0050] [ Fig. 9 ] Fig. 9 The distribution of residual oxygen concentration (Oi) in the epitaxial wafer after performing the oxygen precipitation evaluation heat treatment to show BMD is shown, where Fig. 9 (a) shows the distribution of residual Oi concentration in silicon wafers in Comparative Examples 1 to 3, and Fig. 9 (b) shows the distribution of residual Oi concentration in the silicon wafers in Examples 1 to 4.

[0051] [ Fig.10 ] Fig.10 is a graph showing a region where the average COP size at a position 145 mm from the central axis of the crystal becomes 75 nm or less on a two-axis graph representing the cooling rate CR2 (° C. / min) and V / G (mm 2 / (℃·min)).

[0052] [ Fig.11 ] Fig.11 is a graph showing a region where the average COP size at the crystal center axis becomes 120 nm or less on a two-axis graph representing the cooling rate (°C / min) and V / G (mm / min) of a silicon single crystal at 1100°C. 2 / (℃·min)).

[0053] Fig.12 A cross-sectional view of an epitaxial wafer of the present invention featuring a gettering layer (bulk region) 124 is depicted. DETAILED DESCRIPTION

[0054] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 Schematic diagram of an epitaxial silicon wafer according to an embodiment of the present invention, wherein (a) is a schematic perspective view, and (b) is a schematic cross-sectional view.

[0056] like Figure 1 As shown in (a) and (b) of FIG. 1 , an epitaxial silicon wafer 1 is composed of a silicon wafer 2 made of silicon single crystal, and an epitaxial silicon film 3 formed on the surface of the silicon wafer 2 .

[0057] In a preferred embodiment, the silicon wafer 2 is made of a silicon single crystal grown by a CZ method, and its diameter R is 300 mm (radius r=150 mm). The silicon single crystal may be an n-type semiconductor doped with an n-type dopant such as phosphorus, arsenic, or antimony, or it may be a p-type semiconductor doped with a p-type dopant such as boron. The silicon wafer 2 contains nitrogen, and the nitrogen concentration is preferably 3×10 12 Up to 9×10 13 atoms / cm 3 The nitrogen-doped silicon single crystal forms thermally stable oxygen precipitation nuclei during the growth stage of the silicon single crystal, and these oxygen precipitation nuclei resist high temperature heat treatment during the epitaxial process, thus preventing the reduction of the BMD density.

[0058] In a preferred embodiment, a silicon wafer 2 having a diameter of 300 mm includes COPs throughout. However, the COP in the edge region E (within 2 mm from the wafer edge PE) is difficult to measure. Moreover, in a preferred embodiment, the average COP size in the peripheral region PX (within 5 mm from the wafer edge PE) is 75 nm or less. The preferred average COP size at the center PO is 120 nm or less. The entire surface of the silicon wafer 2 (excluding the edge region E) is composed of COP regions, and the average COP size in the peripheral region PX (located within 5 mm from the outermost edge PE of the silicon wafer 2) is preferably 75 nm or less. In the case of a 300 mm wafer, the measurement position of the COP in the peripheral region PX is a position 145 mm away from the center PO of the wafer in the radial direction. In addition, the average COP size at the center PO of the silicon wafer 2 is preferably 120 nm or less. As will be described in detail until this time, by reducing the COP size, the BMD density at the peripheral region PX is maintained at a high level and uniform.

[0059] COP is the void defect formed by the aggregation of vacancies. These are point defects and are generally considered to have an octahedral shape. Therefore, the measurement of COP size is complicated and requires certain estimation. In the present invention, COP size is defined as the diameter of a sphere, which is estimated to have a volume similar to the COP being considered in the indicated measurement area of ​​a silicon wafer. First, the light intensity from COP is measured using the LST method. Then, a sphere with the same light intensity is determined. Finally, the size of COP is considered to be the diameter of such a sphere. Therefore, the average size of COP is the average diameter (that is, the sum of diameters divided by the total number of COPs) of multiple COPs. In a preferred embodiment, the average size of COP means the sum of 50 or more diameters (corresponding to 50 or more COPs) divided by the total number of COPs.

[0060] The COP may preferably be measured from a silicon wafer 2 (or silicon substrate) by using a light scattering tomography (LST) method. To determine the average size of the COP, preferably 50 or more COPs are taken for measurement in space anywhere in the wafer. The specific depth or location of the wafer used for this measurement is not important.

[0061] In order to measure the BMD density and calculate the BMD variation, the epitaxial silicon wafer 1 was first heated at 780°C for 3 hours and then at 1000°C for 16 hours. The preferred BMD density on the silicon wafer 2 was thus measured to be between 5×10 8 Up to 7×10 9 / cm 3 The BMD variation (BV) is calculated as:

[0062] BV=(Dmax–Dmin) / Davg, where

[0063] Dmax is the maximum BMD density

[0064] Dmin is the minimum BMD density

[0065] Davg is the average BMD density,

[0066] BMD density is from PO to the outer region (OR, see Figure 1 ) is measured at intervals of 5 mm. Figure 1 As shown in , for a 300 mm wafer, the OR is the area from 139 mm to 148 mm. Within the OR, the BMD density is measured at 1 mm intervals.

[0067] Fig.12A cross-sectional view of an epitaxial wafer 120 of the present invention is depicted. The epitaxial wafer 120 includes an epitaxial layer 121, a silicon substrate 122. The epitaxial wafer 120 is heated to form clean zones (DZs) 123, 125, and a gettering layer (body region) 124. When heated, the gettering layer 124 formed between the first clean zone 123 and the second clean zone 125 provides BMD. As mentioned above, the measurement of BMD density is performed from the gettering layer 124 at a desired interval. Preferably, the BMD measurement is performed using the LST method. As long as the BMD measurement is performed from the gettering layer 124, the specific depth or position of the silicon substrate 122 is not important.

[0068] The BMD density can be measured at 5 mm intervals throughout most of the wafer. However, toward the edge of the wafer, in the outer region from about 139 mm to about 148 mm from the center, the BMD density can be obtained at smaller intervals (such as 1 mm).

[0069] As a result of intensive research, the inventors have found that it is possible to even out the distribution of BMD density by controlling the size of the COP in the peripheral region of the silicon single crystal. Whether or not nitrogen doping is present, the BMD density depends on the density of residual vacancies after the COP is formed, but due to the outward diffusion of vacancies, the density of residual vacancies tends to decrease toward the peripheral region of the silicon single crystal. Therefore, the BMD density tends to decrease toward the periphery of the silicon single crystal. However, the inventors have found that the density of residual vacancies in the periphery of the silicon single crystal can be adjusted by controlling the size of the COP formed in the periphery.

[0070] Additionally, when silicon melt is doped with nitrogen, BMD can be roughly divided into two types: one is BMD caused by nitrogen and vacancy aggregation before COP formation (hereinafter referred to as "NV precipitates"), and the other is BMD caused by residual vacancies after COP formation.

[0071] The BMD caused by NV precipitates depends on the distribution of vacancies before the COP is formed. Since the vacancy density decreases toward the periphery of the silicon single crystal, the BMD density caused by NV precipitates also decreases toward the periphery of the silicon single crystal.

[0072] The BMD caused by NV precipitates is determined by the nitrogen concentration and temperature gradient during crystal pulling, while the BMD caused by residual vacancies after COP formation can be adjusted by controlling the size of the COP. In other words, by controlling the size of the COP in the periphery of the silicon single crystal, it is possible to adjust the BMD density caused by residual vacancies after COP formation in the periphery of the silicon single crystal. As a result, the final distribution of the BMD density, which is the sum of the BMD density caused by NV precipitates and the BMD density caused by residual vacancies, can be made uniform.

[0073] Figure 2 is a flow chart schematically showing a method for manufacturing an epitaxial silicon wafer 1 .

[0074] like Figure 2 As shown in , the method for manufacturing epitaxial silicon wafer 1 includes step S11 of growing silicon single crystal using CZ method, step S12 of processing silicon single crystal to manufacture silicon wafer 2, and step S13 of forming epitaxial silicon film 3 on the surface of silicon wafer 2.

[0075] In step S11 of growing a silicon single crystal using the CZ method, a seed crystal is immersed in the surface of a silicon melt contained in a quartz crucible, and the seed crystal and the quartz crucible are rotated while gradually pulling the seed crystal upward, thereby causing a large single crystal to grow from the lower end of the seed crystal. Specifically, the following steps are performed in order: a seeding step in which the seed crystal contacts the silicon melt; a necking step in which the crystal diameter is narrowed by a Das neck method; a shoulder growth step in which the crystal diameter is gradually increased until it reaches a desired diameter; a main body growth step in which the desired diameter is maintained as the single crystal continues to grow; and a tail growth step in which the crystal diameter is gradually narrowed before separation from the silicon melt.

[0076] When growing a silicon single crystal using the CZ method, the type and distribution of defects in the single crystal depends on the so-called Voronkov ratio V / G, where V is the pulling speed of the single crystal and G is the temperature gradient near the solid-liquid interface along the direction of crystal growth.

[0077] Figure 3 is a graph showing the general relationship between V / G and the type and distribution of crystal defects.

[0078] like Figure 3As shown in , when V / G is large, there are too many vacancies, resulting in the formation of COPs, which are aggregates of vacancies. On the other hand, when V / G is small, there are too many interstitial silicon atoms, resulting in the formation of dislocation clusters, which are aggregates of interstitial silicon. Both COPs and dislocation clusters are native (Grown-in) defects that appear during crystal growth. In addition, between the regions where COPs and dislocation clusters are formed, there are three regions listed in order of increasing V / G—OSF, Pv, and Pi. The OSF region is a region where OSF (oxidation induced stacking faults) appear when the crystal is thermally oxidized at high temperatures (1000-1200°C). The Pv region and the Pi region are defect-free regions that do not contain native defects. The Pv region contains oxygen precipitation nuclei in the as-grown state, and oxygen precipitates tend to form in this region when subjected to two-step heat treatments at low and high temperatures (e.g., 800°C and 1000°C). The Pi region is a region in which oxygen precipitates are unlikely to form even when subjected to two-step heat treatment.

[0079] The V / G range that allows the growth of silicon single crystals without native defects is very narrow, so V / G must be strictly controlled to grow such crystals. V / G must be controlled to fall within the appropriate range in both the radial and axial directions of the single crystal. Since the pull speed V is constant at all positions along the radial direction of the single crystal, the hot zone inside the CZ furnace must be designed so that the temperature gradient G falls within the specified range. In order to keep V / G within the appropriate range, the pull speed V must be strictly controlled to be within the specified range.

[0080] Therefore, it is very delicate to control the pulling process of silicon single crystals without native defects. However, in the case of epitaxial silicon wafers, since the surface of the silicon wafer 2 is covered with an epitaxial silicon film 3 and the crystal integrity of the wafer surface is high, the silicon wafer 2 does not necessarily need to be defect-free, but it can contain native defects. Therefore, conventionally, the silicon single crystal is pulled at the maximum possible pulling speed to prioritize manufacturing efficiency, specifically at the maximum pulling speed that will not cause crystal deformation. The maximum pulling speed refers to the highest speed that can be achieved while maintaining the straight shape of the cylindrical body of the crystal in the longitudinal direction. Specifically, this refers to the following maximum pulling speed, at which the eccentricity of the center of the horizontal cross section of the cylindrical body and the line connecting the center points of the horizontal cross section at the two ends of the cylindrical body does not exceed 4mm.

[0081] In contrast, the preferred pulling speed of the present invention is in the range of 60% to 90% of the conventional maximum speed. Such a slower pulling speed helps to keep the average COP size in the peripheral region PX relatively small, at 75nm or less. This pulling speed range can be determined by measuring the COP size of multiple wafer samples of crystals from different pulling speeds. In other words, before the step of growing a silicon single crystal, the pulling speed that results in an average COP size of 75nm or less in the peripheral region PX of the silicon wafer 2 can be determined experimentally.

[0082] For example, by repeatedly performing a pulling process of a silicon single crystal and evaluating the distribution of COP in the crystal, it is possible to determine in advance the relationship between the crystal pulling speed and the average COP size in the peripheral region of the wafer. This allows identification of an appropriate pulling speed at which the average COP size in the peripheral region of the wafer becomes 75 nm or less. For example, if the COP in the peripheral region of a wafer sample pulled at a certain speed is greater than 75 nm, the pulling speed is adjusted down or up based on a predetermined relationship between the crystal pulling speed and the average COP size in the peripheral region to reduce the average COP size, and the silicon single crystal is pulled again. By repeating this process of pulling a silicon single crystal and evaluating the distribution of COP, it is possible to identify an appropriate pulling speed that results in an average COP size of 75 nm or less in the peripheral region of the wafer.

[0083] Figure 4 is a cross-sectional view schematically showing the configuration of a single crystal pulling apparatus for manufacturing a silicon single crystal by a CZ method.

[0084] like Figure 4 As shown in FIG. 1 , the single crystal pulling device 10 includes a chamber 11 (CZ furnace), a quartz crucible 12 for accommodating a silicon melt 4 inside the chamber 11, a carbon susceptor 13 for supporting the quartz crucible 12, a rotating shaft 14 supporting the carbon susceptor 13, a shaft driving mechanism 15 for rotating and moving the rotating shaft 14 up and down, a heater 16 arranged around the carbon susceptor 13, a heat shielding member 17 arranged above the quartz crucible 12, a cylindrical cooling system 18 arranged inside the heat shielding member 17, a wire 19 for pulling a single crystal arranged coaxially with the rotating shaft 14 above the quartz crucible 12, and a wire winding mechanism 20 arranged above the chamber 11. The single crystal pulling device 10 is also equipped with a magnetic field generating device 21 arranged outside the chamber 11.

[0085] The chamber 11 is composed of a main chamber 11a and an elongated cylindrical pulling chamber 11b connected to the upper opening of the main chamber 11a. The quartz crucible 12, the carbon susceptor 13, the heater 16, the heat shielding member 17 and the cooling system 18 are all located inside the main chamber 11a. A gas inlet 11c for introducing an inert gas (e.g., argon) or a doping gas into the main chamber 11a is located at the top of the pulling chamber 11b, and a gas outlet 11d for exhausting the atmosphere inside the main chamber 11a is located at the bottom of the main chamber 11a.

[0086] The quartz crucible 12 is a quartz glass container having a cylindrical side wall and a curved bottom. The carbon susceptor 13 is used to maintain the shape of the quartz crucible 12 softened at high temperature, and it maintains the entire circumference of the bottom and outer surface of the quartz crucible 12. The quartz crucible 12 and the carbon susceptor 13 together form a double-walled crucible that supports the silicon melt inside the chamber 11.

[0087] The carbon susceptor 13 is fixed to the upper end of a rotating shaft 14 , the lower end of which passes through the bottom of the chamber 11 and is connected to a shaft driving mechanism 15 located outside the chamber 11 .

[0088] The heater 16 is used to melt the polysilicon material filled in the quartz crucible 12 to generate the silicon melt 4 and maintain the molten state of the silicon melt 4. The heater 16 is a resistance heating carbon heater and is arranged around the quartz crucible 12 inside the carbon susceptor 13.

[0089] The heat shield member 17 is installed to suppress temperature fluctuations in the silicon melt 4 and form an appropriate hot zone near the crystal growth interface, and to prevent the silicon single crystal 5 from being heated by radiant heat from the heater 16 and the quartz crucible 12. The heat shield member 17 is a substantially cylindrical graphite member, and is arranged to cover the area above the silicon melt 4 (excluding the pulling path of the silicon single crystal 5).

[0090] The opening diameter at the lower end of the heat shield member 17 is larger than the diameter of the silicon single crystal 5, thereby ensuring a pulling path for the silicon single crystal 5. Additionally, the outer diameter of the lower end of the heat shield member 17 is smaller than the diameter of the quartz crucible 12, so the lower end of the heat shield member 17 is positioned inside the quartz crucible 12. This prevents interference between the heat shield member 17 and the quartz crucible 12, even if the upper edge of the quartz crucible 12 rises above the lower end of the heat shield member 17.

[0091] The gap H between the heat shield member 17 and the silicon melt 4 is preferably 40 to 80 mm. Keeping the gap within this range promotes the formation of the same type of crystal defects (e.g., COP) across the radial direction of the single crystal. This improves the yield of epitaxial silicon wafers in which COP defects are formed across the entire wafer surface.

[0092] The cooling system 18 is a cylindrical component surrounding the pulling path of the silicon single crystal 5. In one embodiment, the cooling system 18 includes a liquid cooling jacket, such as a water cooling jacket. In a preferred embodiment, the cooling system 18 is positioned in such a path, that is, in the path, the outer part of the crystal reaches 1100°C and the COP formed without any temperature control is too large and adversely affects the BMD density. Without proper temperature control, wafers from conventional crystals show reduced BMD density at the peripheral area PX and lack of effective doping. The cooling system 18 of the present invention controls the cooling rate of the crystal at the critical temperature of 1100°C and helps to maintain a small COP size, especially in the outer part of the crystal and thus in the peripheral part PX of the resulting wafer.

[0093] The wire winding mechanism 20 is located above the pulling chamber 11b, and the wire 19 extends downward from the wire winding mechanism 20 through the pulling chamber 11b, wherein the tip of the wire 19 reaches the inner space of the main chamber 11a. The figure shows that the silicon single crystal 5 is suspended from the wire 19 during its growth. During the pulling of the silicon single crystal 5, the quartz crucible 12 and the silicon single crystal 5 are rotated, and the wire 19 is gradually pulled upward to grow the silicon single crystal 5.

[0094] As the silicon single crystal 5 grows, the amount of silicon melt in the quartz crucible 12 decreases. However, by raising the quartz crucible 12 to maintain a constant melt surface level, the gap H between the heat shield member 17 and the melt surface can be kept constant, thereby improving the stability of the temperature gradient G from the silicon melting point to 1350° C. along the crystal growth direction.

[0095] The magnetic field generating device 21 applies a horizontal magnetic field to the silicon melt 4. The intensity of the magnetic field applied near the solid-liquid interface is preferably 1500 to 6000 G, and more preferably 2000 to 4000 G. By applying a magnetic field near the solid-liquid interface, convection of the melt in a direction perpendicular to the magnetic field lines can be suppressed. For example, the area "near the solid-liquid interface" can refer to a point 30 mm below the intersection of the solid-liquid interface and the central axis of the crystal.

[0096] The preferred magnetic field strength near the solid-liquid interface is 2000 to 4000 G. Applying a magnetic field of 2000 to 4000 G to the silicon melt in the crucible stabilizes convection in the silicon melt 4, further improving the stability of the crystal pulling rate and facilitating control of the size of the COP formed in the single crystal.

[0097] In order to start the manufacture of the silicon single crystal 5, the quartz crucible 12 is placed inside the carbon base 13, and the polycrystalline silicon material is loaded into the quartz crucible. Then, the material inside the quartz crucible 12 is heated and melted by the heater 16 to produce a silicon melt 4. Next, the seed crystal attached to the lower end of the wire 19 is lowered into the silicon melt 4. After that, while maintaining contact with the silicon melt 4, the seed crystal is gradually pulled upward, allowing the silicon single crystal 5 to grow. During the crystal growth process, after forming a shoulder section by gradually increasing the diameter, the diameter is maintained to form a cylindrical section. After forming a cylindrical section of the desired length, the diameter is gradually reduced, and the single crystal is separated from the silicon melt 4. In this way, a silicon single crystal ingot is completed.

[0098] When the cooling system 18 is used during the growth of the single crystal, controlling the pull rate to be within the range of 60% to 90% of the maximum pull rate allows the cooling rate at 1100° C. at a position 145 mm from the central axis of the crystal (i.e., the peripheral region on a 300 mm wafer) to be controlled to be within the range of 2.105 to 2.839° C. / min. This allows the formation of COP defects in the single crystal, and in particular enables the average COP size in the peripheral region of the single crystal to be reduced to 75 nm or less.

[0099] The reason for controlling the crystal cooling rate at 1100°C is as follows. When the silicon melt solidifies at the solid-liquid interface to form a single crystal, vacancies are incorporated into the single crystal. When the crystal cools during growth, the vacancies in the single crystal become supersaturated, thereby forming a COP defect, which is an aggregate of vacancies. COP formation occurs around 1100°C. Therefore, by increasing the cooling rate at 1100°C, the COP size can be effectively reduced.

[0100] As described above, according to the method for manufacturing a silicon single crystal of this embodiment, a silicon single crystal is pulled at a specified pulling speed, wherein the average COP size in the peripheral region is 75 nm or less, thereby enabling the manufacture of a silicon single crystal having a high BMD density in the outer region and a uniformly distributed BMD density.

[0101] Next, the silicon single crystal 5 is processed into a silicon wafer 2 (polished wafer) ( Figure 2 The silicon wafer 2 is manufactured by cutting a silicon single crystal ingot into a predetermined block size, rounding the crystal diameter (outer diameter grinding), and then undergoing slicing, chamfering, grinding, etching, polishing, and cleaning processes. The entire surface of the processed silicon wafer 2 is composed of COPs, and the average COP size in the peripheral region is 75 nm or less.

[0102] The COP region refers to an area where the COP can be detected by the observation and evaluation described below. First, the silicon wafer undergoes SC-1 cleaning (i.e., cleaning with a mixture of ammonia, hydrogen peroxide, and ultrapure water in a ratio of 1:1:15). Then, a surface defect inspection device (e.g., SURFSCAN SP-2 from KLA-Tencor) is used to observe and evaluate the surface of the cleaned silicon wafer, and bright spot defects (LPD: light point defects) are identified, which are presumed to be surface pits. The observation mode is set to the bevel mode (oblique incidence mode), and the surface pits are estimated based on the detection size ratio of the wide and narrow channels. Then, an atomic force microscope (AFM) is used to evaluate the identified LPDs to determine whether they are COPs. The area where the COP is observed through such observation and evaluation is defined as the COP region. If LPD is observed across the entire surface of the wafer (excluding the edge region within 2 mm from the outermost edge), and LPD at the center of the wafer and 5 mm inward from the outermost edge is identified as a COP defect by AFM, then the entire surface of the wafer (excluding the edge region within 2 mm from the outermost edge) can be considered as a COP region.

[0103] Next, an epitaxial silicon film 3 ( Figure 2 The thickness of the epitaxial silicon film 3 is preferably between 0.2 and 10 μm. The method of forming the epitaxial silicon film 3 is not particularly limited, but for a large-diameter silicon wafer having a diameter of 300 mm or more, a single-wafer CVD (chemical vapor deposition) device is preferably used. The silicon wafer 2 is set in the chamber of the CVD device, and a raw material gas (such as trichlorosilane (SiHCl 3 )) together with a carrier gas (such as H 2 Gas) and doping gas are introduced into the chamber. Silicon is deposited on a silicon wafer 2 heated to 1000-1200°C at a deposition rate of 0.5-6.0 μm / min by thermal decomposition or reduction of the raw material gas. Afterwards, the silicon wafer is cleaned, thereby completing the epitaxial silicon wafer 1.

[0104] The BMD density distribution of the epitaxial silicon wafer 1 thus manufactured can be confirmed by performing an evaluation heat treatment (oxygen precipitation evaluation heat treatment) simulating a device process that grows oxygen precipitation nuclei. After the oxygen precipitation evaluation heat treatment, the BMD in the silicon wafer 2 can be observed by cutting the wafer in the thickness direction and observing the wafer using the LST method (light scattering tomography). In this embodiment, the BMD density in the silicon wafer 2 after the oxygen precipitation evaluation heat treatment is between 5×10 8 / cm 3 and 7×10 9 / cm 3 between, where the BMD change was 0.6 or less.

[0105] As described above, the epitaxial silicon wafer 1 according to the present invention includes a silicon wafer 2 having a COP, and an epitaxial silicon film 3 formed on the surface of the silicon wafer 2. The average COP size in the peripheral region PX (located 5 mm inward from the edge PE of the silicon wafer 2) is 75 nm or less. This prevents the BMD density in the peripheral region of the wafer from decreasing and improves the uniformity of the distribution of the BMD density.

[0106] The above explanation describes the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the present invention. These modifications are also within the scope of the present invention.

[0107] For example, in the above embodiment, an epitaxial silicon wafer with a diameter of 300 mm is used as an example, but the present invention is not limited to a wafer with such a diameter. A wafer smaller than 300 mm, such as a 200 mm wafer, or a larger wafer, such as a 450 mm wafer, may also be used.

[0108] [Example]

[0109] Various crystals were used to realize the wafer of the present invention and compile data related thereto. 12 Up to 9×10 13 atoms / cm 3 A nitrogen concentration of 100 Å was added to each of the silicon melts from which the sample crystals were pulled.

[0110] Cooling system 18 (see Figure 4 ) was used in each of the pulled crystals and showed a reduction in the COP size in the peripheral region of the resulting wafer. In contrast, the cooling system 18 was not used in the sample of the conventional crystal (comparative example). In both the inventive sample and the comparative sample, a magnetic field of 2000 to 4000 G was used. Again, in both samples, the crystal rotation speed was 8.5 to 10 rpm, and the crucible rotation speed was 0.2 to 0.4 rpm.

[0111] For the samples of the present invention, the crystal was pulled at 60% to 90% of the maximum pull rate to ensure that COPs were formed over the wafer surface and that smaller COPs were formed particularly at the peripheral regions. Speeds exceeding the maximum pull rate caused structural deformation of the crystal. The maximum pull rate was used for conventional comparative samples.

[0112] 300 mm wafer samples A1 to A6 and B1 to B3 were obtained from various crystals grown using the method of the present invention.

[0113] Next, epitaxial silicon films having a thickness of about 2 μm were formed on the surfaces of the silicon wafer samples A1 to A6 and B1 to B3 by CVD, thereby completing epitaxial silicon wafers (epitaxial wafers) of Examples 1 to 6 and Comparative Examples 1 to 3.

[0114] Next, the distribution of COP, the distribution of BMD density, and the distribution of oxygen concentration in the epitaxial wafers of Examples 1 to 6 and Comparative Examples 1 to 3 were evaluated.

[0115] The distribution of COP was evaluated using the LST method using an infrared scattering tomography device (Mitsui Mining & Smelting Co., Ltd.: MO-441). In the LST method, a wafer is cut and an infrared laser is irradiated on the surface of the wafer. The size and density of defects within the wafer are measured by receiving scattered light emitted from the cut surface using a CCD sensor.

[0116] The CCD sensor captures the cut surface through an ND filter. The CCD sensor outputs the intensity of the light scattered by the micro-defects in the wafer as an electrical signal with a 16-bit scale (65536 grayscales), and the maximum value of the electrical signal is regarded as the scattering intensity. The scattering intensity is a relative value, which is proportional to the sixth power of the COP size. The COP size is determined by referring to a calibration table showing the relationship between the scattering intensity and the COP size. As described above, the average COP size is calculated as the average value of the diameters of the multiple COPs present in the measurement area.

[0117] The conditions for measuring COP using an infrared scattering tomography apparatus are as follows: the laser output level is 100 mW, the ND filter transmittance is 20 to 50% to reduce the amount of scattered light, the laser scanning distance along the cut surface is 2000 μm, and the measurement depth of the scattered light from the surface of the epitaxial film in the depth direction is 88.4 to 348.4 μm. The measurement points of COP are the wafer surface irradiated from the epitaxial film side at 0 mm, 37.5 mm (1 / 4×r), 75 mm (1 / 2×r), 112.5 mm (3 / 4×r), and 145 mm (r-5 mm) from the center of the epitaxial wafer in the radial direction. The average COP size at each position is determined.

[0118] Oxygen precipitation evaluation heat treatments were performed sequentially on the epitaxial wafers (at O 2After the treatment of 780℃×3h+1000℃×16h in atmosphere and oxide film removal, the distribution of BMD density was evaluated using the LST method using an infrared scattering tomography device (Semilab: LST-310A). The measurement conditions of BMD density are: laser output level of 51μW, laser beam diameter of 8μm, laser scanning distance along the cut surface of 375μm, the measurement depth of scattered light from the surface of the epitaxial film in the depth direction is 76.5-280.5μm, and the depth is 8μm. The measurement is performed in the radial direction from the center of the wafer, starting from the center and measuring every 5mm from 0mm to 139mm and every 1mm from 139mm to 148mm (outer area).

[0119] When measuring the BMD density, laser scanning is performed within a range of ±188 μm in the radial direction from the measurement point on the wafer. The BMD density is calculated by dividing the number of BMDs contained in a rectangular volume formed by the scanning distance (width), the laser spot diameter (depth), and the specified distance in the depth direction by the volume of the rectangle. The BMD density corresponds to the number of BMDs per unit volume (cm 3 By expanding the scanning area to increase the number of BMDs, the measurement accuracy of BMD density can be improved.

[0120] The distribution of oxygen concentration was evaluated for both crystals before and after the oxygen precipitation evaluation heat treatment. The distribution of oxygen concentration was measured at intervals of 5 mm from the center of the wafer to a radius of 145 mm using an FT-IR device (QS1200LTS).

[0121] The results are shown in the table below. Figure 1 , where point PO represents the center point of the wafer, PE represents the edge of the wafer, PX represents 5 mm inward from PE, the area between 2 mm from PE and PX is represented as the outer area, PMi represents a distance of 0.25×r from PO, where r is the radius of the wafer, PMm represents 0.5×r from PO, and PMo represents 0.75×r from PO. With these points determined, Examples 1-4 and Comparative Examples 1-3 are summarized as follows.

[0122] Table 1 shows the average size of the COP of the conventional wafers of Comparative Examples 1 to 3. Table 2 shows the average size of the COP at various locations on the wafers of the present invention of Examples 1 to 4. The average size of the COP of the wafers of the present invention at PX ranges from 65.5 to 71.9 nm, while the conventional wafers are characterized by a significantly larger average value in the range of 79.6 to 85.7 nm. Moreover, at PO, the average value of the present invention ranges from 103.8 to 119.8 nm, while the average value of the conventional wafers ranges from 141.8 to 145.0 nm. Overall, the wafers of the present invention examples include smaller COPs throughout the entire wafer and improved BMD variation.

[0123] Table 1

[0124]

[0125] Table 2

[0126]

[0127] Figure 5 The above distribution of the average COP size in the epitaxial wafer is shown graphically.

[0128] exist Figure 5 In (a), the average COP size of the conventional wafers of Comparative Examples 1 to 3 ranges from 141.8 to 145.0 nm at the wafer center, and ranges from 79.6 to 85.7 nm in the peripheral area (at about 145 mm from the wafer center). Figure 5 (b) shows that the average COP size of the inventive wafers of Examples 1 to 4 ranges from 103.8 to 119.8 nm at the wafer center and ranges from 65.5 to 71.9 nm in the peripheral region (at about 145 mm from the wafer center). Figure 5 (b) shows that the average COP size of the wafer of the present invention is significantly smaller than the average COP size of the conventional wafer. Moreover, Figure 5 (b) shows that the average COP sizes at the peripheral regions are all less than 75 nm.

[0129] Figure 6 The BMD density at various locations of the epitaxial wafer is shown. Figure 6 (a) shows the BMD density of the conventional wafers of Comparative Examples 1 to 3, and Figure 6 (b) shows the BMD density of the wafers of the present invention of Examples 1 to 4.

[0130] Figure 6(a) provides the BMD density of three conventional 300 mm wafers as comparative examples 1 to 3. Each of these wafers shows that the BMD density begins to decrease at about 130 mm from the center in the radial direction. In contrast, Figure 6 (b) shows that the BMD density of the wafers of the present invention as Examples 1 to 4 remains uniform across the wafer from the center to the edge.

[0131] Figure 7 Shown are the relationships between BMD variations and average COP sizes at the peripheral regions of conventional wafers of Comparative Examples 1 to 3 and inventive wafers of Examples 1 to 6. Conventional wafers are shown as white marks, and inventive wafers are shown as black marks. Figure 7 It is shown that conventional wafers with significantly larger average COP sizes result in higher BMD variations, which are significantly greater than the preferred 0.6. Figure 7 It is shown that the wafers of the present invention with smaller average COP size (less than 75 nm) result in a substantial improvement in BMD variation, which is below 0.6. As mentioned above, BMD variation (BV) can be calculated as (Dmax-Dmin) / Davg, where Dmax means the maximum BMD density, Dmin means the minimum BMD density, and Davg means the average BMD density.

[0132] [Table 3]

[0133]

[0134] like Figure 7 As shown in Table 3, the average COP size in the peripheral region of the conventional wafers of Comparative Examples 1 to 3 was 85.7 nm, wherein each average value was greater than 75 nm. The average COP size in the peripheral region of the inventive wafer examples 1 to 6 was 71.9 nm, wherein each average value was less than 75 nm.

[0135] Figure 7 It is further shown that in the main body area (ie, Fig.12 The BMD variation in the gettering layer 124 in the bulk region (i.e., the gettering layer 124) ranged from 0.622 to 0.822. On the other hand, the BMD variation in the bulk region (i.e., the gettering layer 124) of the inventive wafers of Examples 1 to 6 was significantly lower, ranging from 0.375 to 0.499. This shows that the BMD variation in the bulk region of the inventive wafers was less than 0.5.

[0136] Table 3 shows that the BMD variation of the conventional wafers of Comparative Examples 1 to 3 in the region (130 to 148 mm radially from the center of the wafer) ranges from 0.385 to 0.780. The BMD variation of the wafer of the present invention in the same region (130 to 148 mm) is significantly lower, ranging from 0.077 to 0.348. This shows that the BMD variation of the wafer of the present invention in this region is less than 0.350, and its uniformity is greatly improved over the conventional wafer.

[0137] Figure 8 A graph showing the distribution of oxygen concentration in an epitaxial wafer before oxygen precipitation evaluation heat treatment. Figure 8 (a) shows the measurement results of epitaxial wafers in Comparative Examples 1 to 3 of conventional wafers, and Figure 8 (b) shows the measurement results of the epitaxial wafers of the present invention in Examples 1 to 4.

[0138] like Figure 8 As shown in (a), the distribution of oxygen concentration in the epitaxial wafers of Comparative Examples 1 to 3 is approximately uniform, falling within 10.7×10 17 to 11.7×10 17 atoms / cm 3 Similarly, if Figure 8 As shown in (b), the distribution of oxygen concentration in the epitaxial wafers of Examples 1 to 4 is also approximately uniform, with a value of 11.0×10 17 Up to 12.0×10 17 atoms / cm 3 within the range.

[0139] Fig. 9 A graph showing the distribution of residual oxygen concentration (Oi) in an epitaxial wafer after performing an oxygen precipitation evaluation heat treatment to make BMD visible. Fig. 9 (a) shows the measurement results of the epitaxial wafers in Comparative Examples 1 to 3, and Fig. 9 (b) shows the measurement results of the epitaxial wafers in Examples 1 to 4.

[0140] like Fig. 9 As shown in (a), the distribution of the residual Oi concentration in the epitaxial wafers of Comparative Examples 1 to 3 is approximately uniform, and no reduction in the residual Oi concentration is observed in the outer region. Fig. 9 As shown in (b), the distribution of the residual Oi concentration in the epitaxial wafers of Examples 1 to 4 is also approximately uniform, and there is no reduction in the residual Oi concentration in the outer region. Figure 6As indicated in (b), the epitaxial wafers of Examples 1 to 4 have an increased BMD density in the outer region compared to the epitaxial wafers of Comparative Examples 1 to 3, raising concerns about reduced residual Oi concentration and potential slip dislocations due to insufficient strength. However, the residual Oi concentration in the peripheral region of the epitaxial wafers of Examples 1 to 4 is 10×10 17 atoms / cm 3 or higher, sufficient strength is ensured. Therefore, there is no need to worry about slip dislocation due to a decrease in residual Oi concentration.

[0141] Fig.10 The relationship between the Voronkov ratio (V / G) and the cooling rate when the crystal reaches 1100°C in the peripheral region (about 145 mm from the center of the wafer) is shown. Fig.10 The triangles in depict the region where an average COP size of 75 nm or less can be obtained. The triangular regions were determined based on the inventive wafers in Examples 1 to 6, which were obtained from crystals grown by the preferred method of the present invention. Fig.10 It is further shown that the pulling conditions of the conventional crystal include a lower cooling rate (due to the absence of the cooling system 18), resulting in a larger COP size for the conventional wafers of Comparative Examples 1 to 3. The larger COP size in the peripheral region forces a reduction in the BMD density. Fig.10 The triangles in are representations of the V / G and cooling rate conditions obtained from crystals grown by the preferred method of the present invention, which results in the present invention wafers of Examples 1 to 6 having smaller COP sizes in the peripheral region.

[0142] [Table 4]

[0143]

[0144] like Fig.10 As shown in Table 4, the relationship between the cooling rate CR1 at 1100° C. at about 145 mm from the central axis of the crystal and the V / G required for growing a silicon single crystal having an average COP size of 75 nm or less in the peripheral region can be derived from the growth conditions of the silicon single crystal according to the method of the present invention. In Table 4, the crystal pulling speed is provided as a ratio to the maximum pulling speed. The maximum pulling speed may vary from crystal to crystal and according to the diameter of the crystal, and it refers to the speed (m / min) at which the crystal is grown at the fastest rate without causing any structural damage.

[0145] Fig.10 The triangle in depicts the acceptable V / G1 as a function of CR1 obtained from 300 mm wafers of the present invention (shown as Examples 1 to 6). This relationship can be expressed as follows:

[0146] 0.183≤V / G1≤(0.1035×CR1)-0.0350, where

[0147] 2.105≤CR1≤2.839,

[0148] Wherein, V represents the pulling speed of the silicon single crystal (mm / min), and G1 represents the temperature gradient obtained at a distance of about 145 mm from the central axis of the crystal in the radial direction. In particular, G1 is the temperature change rate from the silicon melting point to 1350°C along the direction of crystal growth (°C / mm). CR1 represents the cooling rate of the silicon single crystal at 1100°C at a distance of about 145 mm from the central axis of the crystal in the radial direction (°C / min).

[0149] again, Fig.10 Table 4 shows that the crystals producing the conventional wafers of Comparative Examples 1 to 3 were grown without using the cooling system 18 and included a larger COP. As a result, the conventional wafers of Comparative Examples 1 to 3 included a COP size larger than the preferred size of 75 nm or less, and therefore had a lower BMD density in the peripheral region thereof.

[0150] exist Fig.10 and Table 4, it should be noted that V / G1 less than 0.183 will result in a low vacancy concentration in the crystal and COP may not be formed.

[0151] Fig.10 Table 4 further illustrates that the range of the cooling rate CR1 at 1100° C. at about 145 mm from the center is as follows: 2.105≤CR1≤2.839. If the cooling rate CR1 is less than 2.105, the average COP size may exceed 75 nm. On the other hand, if the cooling rate CR1 exceeds 2.839, the thermal stress within the crystal may cause fractures in the crystal.

[0152] If Fig.10 The preferred embodiment illustrated in Table 4 shows that controlling the crystal pull speed and thermal conditions (ie, cooling rate) within the triangular region facilitates achieving an average COP size of 75 nm or less in the peripheral region of the resulting wafer.

[0153] Fig.11Table 5 and Table 5 show the relationship between the Voronkov ratio (V / G2) and the cooling rate (CR2) of the crystal at the central axis of the crystal at 1100°C. Here, the triangular area represents an area where the average COP size is 120nm or less. The triangular area is determined by the wafers of the present invention of Examples 1 to 6 of the crystal grown by the preferred method of the present invention. Table 5 shows that the average COP size of the wafers of the present invention (Examples 1 to 6) ranges from 76.8 to 119.8nm. In comparison, Table 5 further shows that the average COP size of the conventional wafers of Comparative Examples 1 to 3 ranges from 141.8 to 145.0nm and is significantly greater than the preferred 120nm or less. Table 5 also shows that the cooling rate (CR2) of the conventional crystal at the central axis is significantly lower, at 1.858 (due to the lack of use of the cooling system 18), compared to the cooling rate of the crystal of the present invention (which ranges from 1.940 to 2.624). Here again, Table 5 shows the pulling rate relative to the maximum pulling rate.

[0154] [Table 5]

[0155]

[0156]

[0157] like Fig.11 The relationship between the Voronkov ratio V / G2 and the crystal cooling rate CR2 shown in Table 5 was determined based on crystals grown by the preferred method of the present invention. The determination of the triangular area (which represents an average COP size of 120 nm or less) was based on the measurement of the COP size at the center of the wafer of the present invention obtained from these crystals.

[0158] Fig.11 The relationship in can be expressed as follows:

[0159] 0.174≤V / G2≤(0.1096×CR2)-0.0387, where

[0160] 1.940≤CR2≤2.624,

[0161] Wherein, V represents the pulling speed of the silicon single crystal (mm / min), G2 (similar to G1) represents the temperature gradient around the central axis of the crystal from the silicon melting point to 1350°C along the direction of crystal growth (°C / mm), and CR2 (°C / min) represents the cooling rate around the central axis of the crystal at 1100°C.

[0162] exist Fig.11In Table 5, the conventional wafers of Comparative Examples 1 to 3 include a larger COP mainly due to the lack of sufficient cooling rate (1.858, see Table 5). This is due to the fact that these wafers were obtained from a conventional crystal that lacked the use of the cooling system 18.

[0163] Further, Fig.11 It is shown that V / G2 needs to be 0.174 or greater in order to promote the COP of the formed wafer.

[0164] In addition, the preferred range of the cooling rate CR2 at 1100°C at the crystal center axis is: 1.940≤CR2≤2.624. Fig.11 As shown in , CR2 less than this range will not promote an average COP size of 120 nm or less. CR2 greater than this range will cause thermal stress, which can cause cracks in the crystal.

[0165] Based on these results, it was determined that Fig.11 Controlling the crystal pulling conditions within the triangular region depicted in FIG. 1 provides appropriate crystal pulling conditions to achieve an average COP size of 75 to 120 nm at the central axis of the crystal.

[0166] The cooling rates CR1 and CR2 (°C / min) and V / G (mm / min) at 1100°C were obtained from the furnace heat transfer analysis using numerical simulation. 2 / (℃·min)) falls within Fig.10 and Fig.11 By pulling a silicon single crystal in the triangular region shown in FIG, it is possible to grow a silicon single crystal having an average COP size of 75 nm or less in the peripheral region and 120 nm or less at the central axis of the crystal. The cooling rates CR1 and CR2 (°C / min) and V / G (mm / min) of the silicon single crystal at 1100°C are controlled. 2 / (°C·min)) process conditions include parameters such as the installation of the crystal cooling system 18, the pulling speed V and the gap H. Therefore, if the cooling rates CR1 and CR2 (°C / min) or V / G (mm 2 / (℃·min)) falls within Fig.10 or Fig.11 If the values ​​are outside the triangular area in the figure, adjusting parameters such as the installation of the cooling system, the pulling speed V or the gap H can bring these values ​​into the triangular area.

[0167] [Industrial Applicability]

[0168] The epitaxial silicon wafer according to the present invention is widely used as a substrate material for semiconductor devices. The semiconductor device is, for example, incorporated in a smart phone, thereby contributing to its versatility and high performance. For example, the present invention enables the simultaneous execution of multiple applications or the smooth processing of high-resolution images and videos through improved graphics processing capabilities. The present invention promotes the development of various industrial fields (such as information and communication industries, and transportation infrastructure) through semiconductor devices, and can significantly contribute to the solution of various social and environmental problems.

[0169] [reference numerals]

[0170] 1: Epitaxial silicon wafer

[0171] 2: Silicon wafer (silicon substrate)

[0172] 3: Epitaxial silicon film

[0173] 4: Silicon melt

[0174] 5: Silicon single crystal

[0175] 10: Single crystal pulling equipment

[0176] 11: Chamber

[0177] 11a: Main chamber

[0178] 11b: Pulling chamber

[0179] 11c: Gas inlet

[0180] 11d: Gas outlet

[0181] 12: Quartz crucible

[0182] 13: Carbon base

[0183] 14: Rotation axis

[0184] 15: Shaft drive mechanism

[0185] 16: Heater

[0186] 17: Heat shielding components

[0187] 18: Cooling system

[0188] 19: Line

[0189] 20: Wire winding mechanism

[0190] 21: Magnetic Field Generator

[0191] 120: Epitaxial wafer

[0192] 121: Epitaxial layer

[0193] 122: Silicon substrate

[0194] 123: First clean area

[0195] 124: Gettering layer (main region)

[0196] 125: Second clean area

[0197] E: Edge area of ​​the wafer

[0198] H: Clearance

[0199] OR: External area

[0200] PO: Center of wafer

[0201] PX: peripheral area of ​​the chip

[0202] PE: The outermost edge of the wafer

[0203] S11: Silicon single crystal growth process

[0204] S12: Silicon Wafer Manufacturing Process

[0205] S13: Epitaxy process

Claims

1. An epitaxial wafer comprising a silicon substrate and an epitaxial layer on top of the silicon substrate, the epitaxial wafer also comprising crystal-produced particles (COPs) throughout the silicon substrate, wherein: The average size of COPs in a region within 5 mm in the radial direction of the wafer edge is 75 nm or less.

2. The epitaxial wafer according to claim 1, in, When laser is applied, each of the COPs in the silicon substrate reflects a light intensity corresponding to the diameter of a sphere that is similar in volume to the COP, and the size of the COP is considered to be equal to such diameter, and the average size of the COP is equal to the average of 50 or more such diameters.

3. The epitaxial wafer according to claim 2, in, The average size of the COP at the center of the silicon substrate is 120 nm or less.

4. The epitaxial wafer according to claim 1, in, The epitaxial wafer had a diameter of 300 mm.

5. The epitaxial wafer according to claim 1, in, The epitaxial wafer had a diameter of 200 mm.

6. The epitaxial wafer according to claim 1, further comprising 3.0×10 12 to 8.4×10 13 atoms / cm 3 of nitrogen concentration.

7. An epitaxial wafer comprising a silicon substrate and an epitaxial layer on top of the silicon substrate, The epitaxial wafer also includes crystal-originated particles (COPs) throughout the silicon substrate, When heated, the silicon substrate forms bulk micro defects (BMDs) in the gettering layer, and A BMD variation in the density of the BMDs throughout the silicon substrate is 0.6 or less.

8. The epitaxial wafer according to claim 7, in, The BMDs are formed in the gettering layer when heated to about 780° C. for 3 hours and then heated to about 1000° C. for 16 hours.

9. The epitaxial wafer according to claim 7, in, The BMD changes refer to: BMD change = (Max BMD - Min BMD) / Avg BMD, where Max BMD means the maximum density of BMD. Min BMD means the minimum density of BMD, and Avg BMD means the average density of BMD, and The density of BMDs can be measured from the gettering layer at intervals from the center to the edge of the epitaxial wafer in a radial direction.

10. The epitaxial wafer according to claim 9, in, The silicon substrate provides an outer region which is a region 2 to 11 mm away from an edge of the silicon substrate in a radial direction, and The spacing is 5 mm from the center to the outer region and 1 mm within the outer region.

11. The epitaxial wafer according to claim 7, further comprising 3.0×10 12 to 8.4×10 13 atoms / cm 3 of nitrogen concentration.

12. The epitaxial wafer according to claim 7, in, The BMD change was 0.5 or less.

13. The epitaxial wafer according to claim 7, in, The epitaxial wafer had a diameter of 300 mm.

14. The epitaxial wafer according to claim 7, in, The epitaxial wafer had a diameter of 200 mm.

15. A method for manufacturing an epitaxial wafer having a diameter of 300 mm, the method comprising: Providing a silicon melt in a crucible and doping the silicon melt with nitrogen; Pulling a crystal from the silicon melt at a pulling speed of 60% to 90% of a maximum pulling speed, wherein the silicon melt and the crystal form an interface; When an outer portion of the crystal reaches a temperature of about 1100° C., applying a cooling system to the crystal to achieve a cooling rate of 2.1 to 2.8° C. / min at the outer portion, the outer portion being about 145 mm from a central axis of the crystal; applying a magnetic field of 2000 to 4000 Gauss to the silicon melt; providing a gap of 40 to 80 mm between the silicon melt and the heat shield; cutting the crystal into a plurality of silicon substrates; as well as forming an epitaxial layer on at least one of the silicon substrates; The maximum pulling speed refers to the pulling speed above which the crystal begins to deform.

16. The method according to claim 15, in, The ratio (V / G) of the pulling speed (V) to the temperature gradient (G) is between 0.183 and 0.218 mm 2 / °C min, wherein G means the temperature gradient adjacent to the outer portion along the growth direction of the crystal between the temperature at the interface and about 1350°C.

17. The method according to claim 16, in, The ratio (V / G) is set to form a COP throughout the crystal, and further, each silicon substrate includes a COP.

18. The method according to claim 15, in, The average size of COPs in each silicon substrate is 75 nm or less.

19. The method according to claim 18, in, When laser is applied, each of the COPs in the silicon substrate reflects a light intensity corresponding to the diameter of a sphere that is similar in volume to the COP, and the size of the COP is considered to be equal to such diameter, and the average size of the COP is equal to the average of 50 or more such diameters.

20. A method for manufacturing an epitaxial wafer having a diameter of 300 mm, the method comprising: Providing a silicon melt in a crucible and doping the silicon melt with nitrogen; Pulling a crystal from the silicon melt at a pulling speed (V) of 60% to 90% of a maximum pulling speed, wherein the silicon melt and the crystal form an interface; When an outer portion of the crystal reaches a temperature of about 1100° C., applying a cooling system to the crystal to achieve a cooling rate (CR) of 2.105 to 2.839° C. / min at the outer portion, the outer portion being radially about 145 mm from a central axis of the crystal; applying a magnetic field of 2000 to 4000 Gauss to the silicon melt; Provide a gap of 40 to 80 mm between the silicon melt and the heat shield in order to maintain: 0.183≤V / G≤(0.1035×CR)-0.0350, where 2.105≤CR≤2.839, and wherein G means a temperature gradient around the outer portion along the growth direction of the crystal between the temperature at the interface and about 1350°C; cutting the crystal into a plurality of silicon substrates; and forming an epitaxial layer on top of at least one of the plurality of silicon substrates; The maximum pulling speed refers to the pulling speed above which the crystal begins to deform.

21. The method according to claim 20, wherein: V / G is set to form a COP throughout the crystal, and The at least one silicon substrate includes a COP.

22. The method according to claim 20, in, An average size of the COP in a region approximately 145 mm radially away from a center of the at least one of the plurality of silicon substrates is 75 nm or less.

23. The method according to claim 22, in, When laser is applied, each of the COPs in the silicon substrate reflects a light intensity corresponding to the diameter of a sphere that is similar in volume to the COP, and the size of the COP is considered to be equal to such diameter, and the average size of the COP is equal to the average of 50 or more such diameters.

24. A method for manufacturing an epitaxial wafer having a diameter of 300 mm, the method comprising: Providing a silicon melt in a crucible and doping the silicon melt with nitrogen; Pulling a crystal from the silicon melt at a pulling speed (V) of 60% to 90% of a maximum pulling speed, wherein the silicon melt and the crystal form an interface; When the central axis of the crystal reaches a temperature of about 1100° C., applying a cooling system to the crystal to achieve a cooling rate (CR) of 1.940 to 2.624° C. / min at the central axis; applying a magnetic field of 2000 to 4000 Gauss to the silicon melt; Provide a gap of 40 to 80 mm between the silicon melt and the heat shield in order to maintain: 0.174≤V / G≤(0.1096×CR)-0.0387, where 1.940≤CR≤2.624, and wherein G means the temperature gradient around the central axis along the growth direction of the crystal between the temperature at the interface and about 1350°C; cutting the crystal into a plurality of silicon substrates; and forming an epitaxial layer on top of at least one of the plurality of silicon substrates; The maximum pulling speed refers to the pulling speed above which the crystal begins to deform.

25. The method according to claim 24, in, V / G is set to form a COP throughout the crystal, and further, the at least one silicon substrate includes the COP.

26. The method according to claim 24, in, An average size of the COP at the center of the at least one of the plurality of silicon substrates is 120 nm or less.

27. The method according to claim 26, in, When laser is applied, each of the COPs in the silicon substrate reflects a light intensity corresponding to the diameter of a sphere that is similar in volume to the COP, and the size of the COP is considered to be equal to such diameter, and the average size of the COP is equal to the average of 50 or more such diameters.

Images