Method of monitoring and characterizing mos transistor bimodality

Abstract

The application discloses a method for monitoring and characterizing double-peak effect of MOS transistor, comprising: testing a first IdVg curve of the MOS transistor under the condition of no back gate voltage; testing a second IdVg curve under the condition of back gate voltage; obtaining first and second peak gate voltages corresponding to the double-peak of the MOS transistor according to the second IdVg curve; performing voltage mapping, comprising: obtaining first and second drain currents corresponding to the first and second peak gate voltages from the second IdVg curve, and obtaining third and fourth gate voltages corresponding to the currents from the first IdVg curve; performing double-peak characterization value calculation, comprising: obtaining the double-peak characterization value from first and second voltage differences between the second and first peak gate voltages and between the fourth and third gate voltages; and performing double-peak effect judgment, comprising: judging that the double-peak effect exists when the double-peak characterization value is greater than 0, otherwise, the double-peak effect does not exist. The application can monitor and evaluate the double-peak effect of the transistor in time.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit manufacturing process, and more particularly to a method for monitoring and characterizing the double-peak effect of MOS transistors. Background Technology

[0002] Due to the development of submicron technology, the transition between the active and isolated regions has become more abrupt, leading to a significant parasitic angle effect and premature turn-on of parasitic transistors, manifested as a bimodal effect in the IdVg curve, which greatly increases subthreshold leakage.

[0003] The formation of parasitic transistors is mainly due to two factors: first, the difference in doping between the transistor center and edge caused by boron segregation into the adjacent STI oxide layer; and second, the high mechanical stress at the interface between the STI and the active region of silicon, which reduces the thickness of the gate oxide at the corners, resulting in a lower threshold voltage for the parasitic transistor at the edge compared to the threshold voltage of the transistor itself. Many solutions have been proposed to address this double-peak problem. The most common methods are passivation of the sharp corners at the top of the STI or increasing the doping concentration at the channel edges.

[0004] Current research on the bimodal effect focuses primarily on understanding and correcting the process steps that lead to this phenomenon, with less emphasis on its characterization and modeling. Existing methods mainly characterize the bimodal effect by observing the hump on the IdVg curve; however, this primary characterization method is lagging and cannot provide timely feedback on the phenomenon. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for monitoring and characterizing the bimodal effect of MOS transistors, which can monitor and evaluate the bimodal effect of transistors online and in a timely manner, saving test resources and greatly improving evaluation efficiency.

[0006] To address the aforementioned technical problems, the method for monitoring and characterizing the double-peak effect of a MOS transistor provided by this invention includes the following steps:

[0007] The first IdVg curve of the MOS transistor was tested without applying back gate voltage.

[0008] The second IdVg curve of the MOS transistor is tested under the condition of applying back gate voltage, where Id represents the drain current of the MOS transistor and Vg represents the gate voltage of the MOS transistor.

[0009] The first peak gate voltage and the second peak gate voltage corresponding to the double peak of the MOS transistor are obtained from the second IdVg curve, and the second peak gate voltage is greater than the first peak gate voltage.

[0010] Voltage mapping includes: obtaining the first drain current corresponding to the first peak gate voltage and the second drain current corresponding to the second peak gate voltage from the second IdVg curve; and obtaining the third gate voltage corresponding to the first drain current and the fourth gate voltage corresponding to the second drain current from the first IdVg curve.

[0011] The calculation of the bimodal characterization value includes: subtracting the first peak gate voltage from the second peak gate voltage to obtain a first voltage difference, subtracting the third gate voltage from the fourth gate voltage to obtain a second voltage difference, and subtracting the second voltage difference from the first voltage difference to obtain the bimodal characterization value.

[0012] The determination of the bimodal effect includes: when the bimodal characteristic value is greater than 0, determining that the MOS transistor has a bimodal effect; when the bimodal characteristic value is less than or equal to 0, determining that the MOS transistor does not have a bimodal effect.

[0013] A further improvement is that it also includes fitting the first IdVg curve to obtain the first IdVg function.

[0014] The second IdVg function is obtained by fitting the second IdVg curve.

[0015] A further improvement is that the first peak gate voltage and the second peak gate voltage are obtained by maximizing the H(Vg) function.

[0016] The formula for the H(Vg) function is:

[0017]

[0018] Wherein, Gm represents the transconductance of the MOS transistor.

[0019] A further improvement is that when the MOS transistor is tested without the back gate voltage applied, the back gate voltage is equal to the source voltage of the MOS transistor.

[0020] A further improvement is that when testing the MOS transistor under the condition of applying the back gate voltage, the back gate voltage is equal to the drain voltage of the MOS transistor.

[0021] A further improvement is that the MOS transistor is an NMOS transistor, and when testing the MOS transistor, the drain voltage is applied to the power supply voltage;

[0022] A further improvement is that the MOS transistor is a PMOS transistor, and when testing the MOS transistor, a negative power supply voltage is applied to the drain voltage.

[0023] This invention utilizes the characteristic that back-gate voltage can amplify the bimodal effect of MOS transistors. It obtains corresponding IdVg curves (first and second IdVg curves) under both conditions with and without back-gate voltage. The second IdVg curve yields two peak gate voltages. Mapping the currents corresponding to these peak gate voltages onto the first IdVg curve yields two corresponding gate voltages (third and fourth gate voltages). Comparing the difference between these two peak gate voltages (first voltage difference) and the difference between the third and fourth gate voltages (second voltage difference) provides a quantified bimodal characteristic value. A value greater than 0 indicates the presence of a bimodal effect; otherwise, no bimodal effect is observed. Therefore, this invention quantifies the presence of a bimodal effect in a transistor by utilizing the difference between the two sets of Vg values ​​with and without back-gate voltage. This allows for online monitoring and timely evaluation of the transistor's bimodal effect, timely feedback of reliability risks, and targeted assessment. It also saves testing resources and significantly improves evaluation efficiency. Attached Figure Description

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0025] Figure 1 This is a flowchart of a method for monitoring and characterizing the bimodal effect of a MOS transistor according to an embodiment of the present invention;

[0026] Figure 2 These are two IdVg curves of the method for monitoring and characterizing the double-peak effect of MOS transistors according to embodiments of the present invention;

[0027] Figure 3 This is a graph of the H(Vg) function model corresponding to the bimodal effect curve of the method for monitoring and characterizing the bimodal effect of MOS transistors according to an embodiment of the present invention. Detailed Implementation

[0028] like Figure 1 The diagram shown is a flowchart of a method for monitoring and characterizing the double-peak effect of a MOS transistor according to an embodiment of the present invention; as shown... Figure 2 The figures shown are two IdVg curves of the method for monitoring and characterizing the double-peak effect of a MOS transistor according to an embodiment of the present invention. The method for monitoring and characterizing the double-peak effect of a MOS transistor according to an embodiment of the present invention includes the following steps:

[0029] Step S101: Test the first IdVg curve 101 of the MOS transistor under the condition of no back gate voltage.

[0030] In this embodiment of the invention, when the MOS transistor is tested without the back gate voltage applied, the back gate voltage is equal to the source voltage of the MOS transistor.

[0031] In some embodiments, the MOS transistor is an NMOS transistor. When testing the MOS transistor, the drain voltage is applied to the power supply voltage, i.e., V. DD .

[0032] In some embodiments, the MOS transistor can also be a PMOS transistor, and when testing the MOS transistor, the drain voltage is applied to a negative power supply voltage, i.e., -V. DD .

[0033] In some embodiments, it also includes:

[0034] The first IdVg function is obtained by fitting the first IdVg curve 101.

[0035] Right now Figure 1 In step S101, V B =0, Vd = -V DD At that time, IdVg was measured and is given as IdVg1. Where V B Vd represents the back gate voltage, and Vd represents the drain voltage. DD Id represents the power supply voltage, Id represents the drain current, Vg represents the gate voltage, IdVg represents the data of Id and Vg, and IdVg1 represents the first IdVg curve 101. Figure 2 In the first IdVg curve 101, the ordinate is the logarithm of Id, i.e., log(Id).

[0036] Step S102: Test the second IdVg curve 102 of the MOS transistor under the condition of applying a back gate voltage. Id represents the drain current of the MOS transistor, and Vg represents the gate voltage of the MOS transistor. Figure 1 In, V B =-V DD Vd = -V DD At that time, IdVg is measured and is recorded as IdVg2. IdVg2 represents the second IdVg curve 102.

[0037] In some embodiments, when testing the MOS transistor under the applied back gate voltage, the back gate voltage is equal to the drain voltage of the MOS transistor. In other embodiments, the back gate voltage can also be less than the drain voltage, as long as the PN junction between the source and body regions of the MOS transistor is reverse biased; wherein, the effect of the back gate voltage being equal to the drain voltage of the MOS transistor is optimal, and no additional power supply voltage is required.

[0038] In some embodiments, it also includes:

[0039] The second IdVg function is obtained by fitting the second IdVg curve 102.

[0040] Step S103: Obtain the first peak gate voltage V corresponding to the double peak of the MOS transistor according to the second IdVg curve 102. max1 Second peak gate voltage V max2 The second peak gate voltage V max2 Greater than the first peak gate voltage V max1 .

[0041] like Figure 2 As shown, the bimodal effect in the second IdVg curve 102 will increase because, after the back gate voltage is introduced, the threshold voltage of the MOS transistor will increase, and the change of Id with Vg will slow down, thus amplifying the bimodal effect.

[0042] To better determine the first peak gate voltage V max1 and the second peak gate voltage V max2 In this embodiment of the invention, an H(Vg) function is also introduced. The first peak gate voltage V is obtained by maximizing the H(Vg) function. max1 and the second peak gate voltage V max2 .

[0043] The formula for the H(Vg) function is:

[0044]

[0045] Wherein, Gm represents the transconductance of the MOS transistor.

[0046] like Figure 3 The figure shown is a graph of the H(Vg) function model corresponding to the bimodal effect curve of the method for monitoring and characterizing the bimodal effect of MOS transistors according to an embodiment of the present invention. Figure 3 In the figure, curve 103 is the H(Vg) function model curve. It can be seen that curve 103 has two peaks, the first peak being the gate voltage V. max1 and the second peak gate voltage V max2 The values ​​of Vg corresponding to the two maxima of H(Vg), i.e. the peak values.

[0047] Figure 1 In the text, step S103 is represented as: using the function Calculations on IdVg2 yield two maxima V. max1 V max2 .

[0048] Step S104: Perform voltage mapping, including: Figure 2 As shown, the first peak gate voltage V is obtained from the second IdVg curve 102. max1 The corresponding first drain current and the second peak gate voltage Vmax2 The corresponding second drain current; from the first IdVg curve 101, the third gate voltage V1 corresponding to the first drain current and the fourth gate voltage V2 corresponding to the second drain current are obtained.

[0049] Figure 1 In step S104, V1 and V2 are respectively V max1 and V max2 The corresponding ID in V B The gate voltage corresponding to 0.

[0050] Step S105: Calculate the bimodal characterization value, including: Calculating the value based on the second peak gate voltage V. max2 Subtract the first peak gate voltage V max1 The first voltage difference is obtained, the second voltage difference is obtained by subtracting the third gate voltage V1 from the fourth gate voltage V2, and the bimodal characterization value is obtained by subtracting the second voltage difference from the first voltage difference.

[0051] Figure 1 Step S105 is also expressed as: ΔV0=V2-V1, ΔVH=V max2 -V max1 N hump =ΔV H -ΔV0.

[0052] Where ΔV0 represents the second voltage difference, ΔVH represents the first voltage difference, and N hump This represents the bimodal characterization value.

[0053] Step S106: Determine the bimodal effect. Figure 1 In step S106, Nhump > 0, that is, determining whether Nhump is greater than 0.

[0054] Step S107: When the bimodal characterization value is greater than 0, it is determined that the MOS transistor has a bimodal effect, that is, IdVg has a bimodal effect.

[0055] Step S108: When the bimodal characterization value is less than or equal to 0, it is determined that the MOS transistor does not have a bimodal effect, that is, IdVg has no bimodal effect.

[0056] This invention utilizes the characteristic that back-gate voltage can amplify the double-peak effect of a MOS transistor. IdVg curves (first IdVg curve 101 and second IdVg curve 102) are obtained by testing with and without back-gate voltage. Two peak gate voltages are obtained from the second IdVg curve 102. Mapping the currents corresponding to these two peak gate voltages onto the first IdVg curve 101 yields two corresponding gate voltages (third and fourth gate voltages V2). Comparing the difference between the two peak gate voltages (first voltage difference) and the difference between the third and fourth gate voltages (V1, second voltage difference) yields a quantified double-peak characterization value. If the double-peak characterization value is greater than 0, a double-peak effect is present; otherwise, no double-peak effect is present. Therefore, this invention quantifies the presence or absence of a double-peak effect by utilizing the difference between the two sets of Vg values ​​with and without back-gate voltage. This allows for online monitoring and timely evaluation of the transistor's double-peak effect, timely feedback of reliability risks, and targeted assessment, saving testing resources and significantly improving evaluation efficiency.

[0057] In this embodiment of the invention, by applying a back gate voltage, the bimodal effect of the transistor can be amplified. By using the difference between the two sets of Vg values ​​with and without the back gate voltage, the presence or absence of the bimodal effect of the transistor can be quantified, thereby enabling online monitoring and timely evaluation of the bimodal effect of the transistor. This saves testing resources, greatly improves evaluation efficiency, and allows for timely feedback of reliability risks and targeted evaluation, making it a beneficial supplement to traditional testing methods.

[0058] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method of monitoring and characterizing MOS transistor bipolar effects, characterized in that, The method comprises the following steps: testing a first IdVg curve of a MOS transistor under a condition without a back gate voltage, wherein Id represents a drain current of the MOS transistor, and Vg represents a gate voltage of the MOS transistor; testing a second IdVg curve of the MOS transistor under a condition with the back gate voltage; obtaining a first peak gate voltage and a second peak gate voltage corresponding to a double peak of the MOS transistor according to the second IdVg curve, wherein the second peak gate voltage is greater than the first peak gate voltage; performing voltage mapping, comprising: obtaining a first drain current corresponding to the first peak gate voltage and a second drain current corresponding to the second peak gate voltage from the second IdVg curve; obtaining a third gate voltage corresponding to the first drain current and a fourth gate voltage corresponding to the second drain current from the first IdVg curve; performing double peak characterization value calculation, comprising: obtaining a first voltage difference by subtracting the first peak gate voltage from the second peak gate voltage, obtaining a second voltage difference by subtracting the third gate voltage from the fourth gate voltage, and obtaining the double peak characterization value by subtracting the second voltage difference from the first voltage difference; performing double peak effect judgment, comprising: when the double peak characterization value is greater than 0, judging that the MOS transistor has a double peak effect; and when the double peak characterization value is less than or equal to 0, judging that the MOS transistor does not have a double peak effect; further comprising fitting the first IdVg curve to obtain a first IdVg function; further comprising fitting the second IdVg curve to obtain a second IdVg function; obtaining the first peak gate voltage and the second peak gate voltage by maximizing the H(Vg) function; the formula of the H(Vg) function is: wherein Gm represents a transconductance of the MOS transistor.

2. The method of monitoring and characterizing the dual peak effect of a MOS transistor of claim 1, wherein: when the MOS transistor is tested under the condition without the back gate voltage, the back gate voltage is equal to a source voltage of the MOS transistor.

3. The method of monitoring and characterizing the dual peak effect of a MOS transistor of claim 2, wherein: when the MOS transistor is tested under the condition with the back gate voltage, the back gate voltage is equal to a drain voltage of the MOS transistor.

4. The method of monitoring and characterizing the dual peak effect of a MOS transistor of claim 3, wherein: the MOS transistor is an NMOS transistor, and when the MOS transistor is tested, the drain voltage plus a power supply voltage; 5. The method of monitoring and characterizing the dual peak effect of a MOS transistor of claim 3, wherein: the MOS transistor is a PMOS transistor, and when the MOS transistor is tested, the drain voltage plus a negative power supply voltage.

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