PCIe Gen5 interface testing device and method thereof
By designing a PCIe Gen5 interface test device including PCIe switch, complex programmable logic device and substrate management controller, the problems of poor testing convenience and insufficient coverage in the prior art are solved, and a comprehensive test of PCIe Gen5 interface signals are realized.
Patent Information
- Application Number
- CN202311658498.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-05
- Publication Date
- 2025-06-06
AI Technical Summary
The prior art has poor testing convenience and insufficient coverage when testing motherboards, especially when testing differential clock signals and other types of PCIe signals.
A PCIe Gen5 interface test device is designed, including a test motherboard, a first daughterboard and a second daughterboard. The test motherboard is equipped with a PCIe switch, multiple slots and N MCIO connectors through which the board is electrically connected to the board under test. The first daughterboard contains complex programmable logic devices for testing input/output signals, differential clock signals, and serial communication signals; the second daughterboard contains substrate management controllers to execute test programs to drive complex programmable logic devices for testing.
Through this device and method, the differential signal, differential clock signal, input/output signal and I2C signal of the PCIe Gen5 interface can be effectively tested, improving the convenience and coverage of the test.
Smart Images
Figure CN120103102A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a testing device and a testing method thereof, in particular to a PCIe Gen5 interface testing device and a testing method thereof. Background Art
[0002] In recent years, with the popularization and vigorous development of semiconductor technology, various electronic products have sprung up like mushrooms after rain. However, the motherboards of electronic products have many components and complex circuits. How to ensure the good condition of the motherboard has always been one of the problems that manufacturers are eager to solve.
[0003] Generally speaking, the traditional way to test motherboards is to use a large number of MCIO (Mini Cool Edge IO) connectors to lead out the PCIe bus, and then connect it to external devices such as the backplane through connecting cables. When testing these PCIe signals, it is necessary to connect a large number of external boards and use various PCIe devices, such as hard drives, various PCIe expansion cards, etc. However, this method is not only relatively complicated and costly, but also cannot fully cover all types of motherboards. For example, when using the MCIO to PCIe CEM slot connected to the AIC Riser, there will be more differential clock signals that cannot be tested, and these signals may be used in other forms of configuration. Therefore, the traditional method has the problems of poor testing convenience and insufficient coverage.
[0004] In summary, it can be seen that the existing technology has long had problems with poor testing convenience and insufficient coverage, so it is necessary to propose improved technical means to solve this problem. Summary of the invention
[0005] The invention discloses a PCIe Gen5 interface testing device and a method thereof.
[0006] First, the present invention discloses a PCIe Gen5 interface test device, which includes: a test motherboard, a first daughterboard and a second daughterboard. The test motherboard includes: a PCIe switch, a plurality of slots and N MCIO connectors. The PCIe switch is used to expand and manage the connection of the PCIe bus, provide multi-channel connection and data exchange; the slots include at least a first slot and a second slot; one end of each of the MCIO connectors is connected to the PCIe switch, and the other end of each of the MCIO connectors is connected to the PCIe interface of the unit under test (UUT) through a corresponding MCIO connection line, wherein N is a positive integer. Next, in the part of the first daughter board, it is inserted into the first slot to be electrically connected to the test motherboard, this first daughter board includes a complex programmable logic device (CPLD), wherein the complex programmable logic device includes input / output (I / O) signals, differential clocks (REFCLK) and multiple serial communication test logic circuits suitable for the test board; and the second daughter board is inserted into the second slot to be electrically connected to the test motherboard, this second daughter board includes a baseboard management controller (BMC) for executing a test program, and the test program drives the complex programmable logic device to test the input / output signals, differential clocks and the serial communication.
[0007] In addition, the present invention also discloses a PCIe Gen5 interface testing method, the steps of which include: electrically connecting a test motherboard and a board to be tested, the test motherboard includes a PCIe switch, a plurality of slots and N MCIO connectors, one end of each of the MCIO connectors is connected to the PCIe switch, and the other end of each of the MCIO connectors is connected to the board to be tested through a corresponding MCIO connection line, wherein the slots at least include a first slot and a second slot, and N is a positive integer; inserting a first daughter board into the first slot to be electrically connected to the test motherboard, the first daughter board includes a complex programmable logic device, wherein the complex programmable logic device includes input / output signals, differential clocks and multiple serial communication test logic circuits suitable for the board to be tested; inserting a second daughter board into the second slot to be electrically connected to the test motherboard, the second daughter board includes a baseboard management controller; and when performing a PCIe Gen5 interface test, the baseboard management controller executes a test program to drive the complex programmable logic device to test the input / output signals, differential clocks and the serial communication.
[0008] The device and method disclosed in the present invention are as described above. The difference from the prior art is that the present invention electrically connects the test motherboard and the board to be tested to each other through N MCIO connectors and their corresponding connecting wires, so that the test motherboard receives the PCIe Gen5 differential signal, differential clock signal, input / output signal and I2C signal from the board to be tested, and then performs the test through the test logic circuit of the complex programmable logic device and the test program of the baseboard management controller.
[0009] Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the convenience and coverage of testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 FIG. 4 is a device block diagram of a PCIe Gen5 interface test device according to the present invention.
[0011] Figure 2 The present invention is a flowchart of a method for testing a PCIe Gen5 interface.
[0012] Figure 3 The figure is a schematic diagram of applying the present invention to test PCIe Gen5 differential signals.
[0013] Figure 4 It is a schematic diagram of applying the present invention to test differential clock.
[0014] Figure 5 The figure is a schematic diagram of applying the present invention to test out-of-band signals.
[0015] Description of reference numerals:
[0016] 100: Test motherboard
[0017] 101: PCIe switch
[0018] 102: Slot
[0019] 102a: First slot
[0020] 102b: Second slot
[0021] 103: MCIO connector
[0022] 104: MCIO cable
[0023] 110: First daughter board
[0024] 120: Second daughter board
[0025] 130: Board under test
[0026] 410: Frequency Buffer
[0027] 510: I2C master
[0028] 520: I2C slave port
[0029] 530: Foot position
[0030] Step 210: electrically connect a test motherboard and a unit under test (UUT), wherein the test motherboard includes a PCIe switch, a plurality of slots, and N MCIO (Mini Cool Edge IO) connectors, one end of each MCIO connector is connected to the PCIe switch, and the other end of each MCIO connector is connected to the UUT through a corresponding MCIO connection line, wherein the slots include at least a first slot and a second slot, and N is a positive integer.
[0031] Step 220: Insert the first daughter board into the first slot to electrically connect with the test motherboard, the first daughter board comprising a complex programmable logic device (CPLD), wherein the complex programmable logic device comprises an input / output (I / O) signal, a differential clock (REFCLK) and a plurality of serial communication test logic circuits suitable for the test board
[0032] Step 230: Insert a second daughter board into the second slot to electrically connect to the test motherboard, wherein the second daughter board includes a baseboard management controller (BMC).
[0033] Step 240: When performing the PCIe Gen5 interface test, the baseboard management controller executes a test program to drive the complex programmable logic device to test the input / output signal, the differential clock and the serial communication. DETAILED DESCRIPTION
[0034] The following will describe the implementation methods of the present invention in detail with reference to the accompanying drawings and embodiments, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.
[0035] Please read first Figure 1 , Figure 1The device block diagram of the PCIe Gen5 interface test device of the present invention includes: a test motherboard 100, a first daughterboard 110 and a second daughterboard 120. The test motherboard 100 includes: a PCIe switch 101, a plurality of slots 102 and N MCIO connectors 103, wherein N is a positive integer. In actual implementation, each MCIO connector 103 of the test motherboard 100 can support differential clock test (REFCLK test), out-of-band (Sideband) signal test, I2C function test and SPI / UART function test. It should be particularly noted that if the number of MCIO connectors of the board under test 130 exceeds the number of MCIO connectors 103 of the test motherboard 100, multiple test motherboards 100 can be used simultaneously for testing. For example, assuming that the board under test 130 has 16 MCIO connectors and the test motherboard 100 has only 8 MCIO connectors 103, two test motherboards 100 (such as Lightning devices) can be used simultaneously for testing. In other words, the 8 MCIO connectors 103 of the first test motherboard 100 and the 8 MCIO connectors 103 of the second test motherboard 100 are connected to the 16 MCIO connectors of the board under test 130, so that the two test motherboards 100 can complete the test at one time without having to be separated in order. In this way, the use of the test motherboard 100 can simplify the traditional PCIe interface test equipment, reduce the test cost, and improve the test coverage.
[0036] The PCIe switch 101 is used to expand and manage the connection of the PCIe bus, provide multi-channel connection and data exchange. In actual implementation, the PCIe switch 101 refers to a PCI Express (Peripheral Component Interconnect Express) switch, which is a high-speed data bus technology used to connect various hardware devices in a computer, such as graphics cards, network cards, storage devices, etc. The PCIe switch 101 allows multiple PCIe devices to connect and communicate.
[0037] The slot 102 at least includes a first slot 102a and a second slot 102b. In actual implementation, the present invention does not limit the type of the slot 102. As long as the slot 102 can provide the first daughter board 110 and the second daughter board 120 for insertion, so that the first daughter board 110 and the second daughter board 120 can be electrically connected to the test motherboard 100, all types of slots are within the scope of application of the present invention.
[0038] One end of each of the MCIO connectors 103 is connected to the PCIe switch 101, and the other end of each of the MCIO connectors 103 is connected to the PCIe interface of the test board 130 through the corresponding MCIO connection line 104. In actual implementation, the MCIO connection line 104 includes M channels for transmitting differential signals between the test motherboard 100 and the test board 130, and the complex programmable logic device tests the differential signal transmitted in each channel, wherein M is a positive integer, which will be explained later with reference to the accompanying drawings.
[0039] Next, in the first daughter board 110, it is inserted into the first slot 102a to be electrically connected to the test motherboard 100. The first daughter board 110 includes a complex programmable logic device, wherein the complex programmable logic device includes input / output signals, differential clocks and multiple serial communication test logic circuits suitable for the board 130 to be tested. In actual implementation, the serial communication may include an integrated bus circuit (Inter-Integrated Circuit, I2C), a serial peripheral interface (Serial Peripheral Interface, SPI) and a universal asynchronous receiver / transmitter (UART). The complex programmable logic device can complete the out-of-band signal test by testing the input / output signals and the serial communication. In addition, when the complex programmable logic device is testing the differential clock, the differential frequency of one of the MCIO connectors 103 can be used as the differential clock, and the differential frequencies of N-1 of the MCIO connectors 103 can be transmitted to the complex programmable logic device to detect the frequency of the differential clock.
[0040] In addition, in the part of the second daughter board 120, it is inserted into the second slot 102b to be electrically connected to the test motherboard 100. This second daughter board 120 includes a baseboard management controller for executing a test program, and the test program drives the complex programmable logic device to test the input / output signal, the differential clock and the serial communication. In addition, the second daughter board 120 can also be connected to various ports, such as RS232, USB, RJ45 or the like. In actual implementation, the baseboard management controller runs the OpenBMC system to allow integration with the factory business system process, and provides a Redfish application program interface to allow control and testing through a third-party system. For example, the third-party system connects to the second daughter board through the above-mentioned port for remote control and testing. The baseboard management controller is responsible for monitoring and managing various hardware information of the test motherboard 100, such as temperature, voltage, PCIe status, etc., and can provide remote system management functions, and the OpenBMC it runs is an open source embedded Linux system, that is, a Linux distribution version suitable for the baseboard management controller.
[0041] It should be particularly noted that, in actual implementation, the present invention can be partially or completely implemented based on hardware, for example, in addition to complex programmable logic devices, it can also be implemented by hardware components such as integrated circuit chips, system on chip (SoC), field programmable gate array (FPGA), etc. The test logic circuit can be written by combinational language instructions, instruction set architecture instructions, machine instructions, machine-related instructions, microinstructions, firmware instructions, or any combination of one or more programming languages, the programming language includes object-oriented programming languages, such as Common Lisp, Python, C++, Objective-C, Smalltalk, Delphi, Java, Swift, C#, Perl, Ruby and PHP, and conventional procedural programming languages, such as C language or similar programming languages.
[0042] See also Figure 2 , Figure 2The method flow chart of the PCIe Gen5 interface test method of the present invention includes the following steps: electrically connecting a test motherboard 100 and a test board 130 to each other, wherein the test motherboard 100 includes a PCIe switch 101, a plurality of slots 102, and N MCIO connectors 103, wherein one end of each MCIO connector 103 is connected to the PCIe switch 101, and the other end of each MCIO connector 103 is connected to the test board 130 via a corresponding MCIO connection line 104, wherein the slots 102 at least include a first slot 102a and a second slot 102b, and N is A positive integer (step 210); inserting the first daughter board 110 into the first slot 102a to electrically connect to the test motherboard 100, the first daughter board 110 includes a complex programmable logic device, wherein the complex programmable logic device includes input / output signals, differential clocks (REFCLK) and multiple serial communication test logic circuits suitable for the test board 130 (step 220); inserting the second daughter board 120 into the second slot 102b to electrically connect to the test motherboard 100, the second daughter board 120 includes a baseboard management controller (step 230); and when performing a PCIe Gen5 interface test, the baseboard management controller executes a test program to drive the complex programmable logic device to test the input / output signals, differential clocks and the serial communication (step 240). Through the above steps, the test motherboard 100 and the board under test 130 can be electrically connected to each other through N MCIO connectors 103 and their corresponding MCIO connection lines 104, so that the test motherboard 100 receives the PCIe Gen5 differential signal, differential clock signal, input / output signal and I2C signal from the board under test 130, and then performs testing through the test logic circuit of the complex programmable logic device and the test program of the baseboard management controller.
[0043] The following match Figures 3 to 5 The following description is given by way of example. Please refer to Figure 3 , Figure 3 The schematic diagram of the present invention for testing PCIe Gen5 differential signals is shown in FIG. 1 . In actual implementation, the PCIe signal can be realized by directly connecting the MCIO connector of the board to be tested 130 with the MCIO connector 103 of the test motherboard 100 through the MCIO connection line 104. In fact, the port width (also called the number of channels of the port) of x8 is preset, and different port width designs can be used for different test situations, such as x1, x2, x4, x8, x16, etc., where x1 represents a single channel; x2 represents a dual channel, x4 represents a quad channel, and so on. The wider the channel width, the higher the data transmission speed that can be supported.
[0044] like Figure 4 Indicated, Figure 4 The schematic diagram of the differential clock test of the present invention is shown in FIG. 1. Assuming that the board 130 to be tested has two CPUs (i.e., CPU0 and CPU1) and their corresponding frequency buffers 410, when the differential clock is to be tested, a set of differential clocks of one of the MCIO connectors 103 can be connected to the PCIe switch 101 of the test motherboard 100 to provide the PCIe differential clock, and the differential clocks of the remaining MCIO connectors 103 are connected to the CPLD so as to detect the frequency of the input clock through the frequency detection logic circuit on the CPLD.
[0045] like Figure 5 Indicated, Figure 5 The figure is a schematic diagram of applying the present invention to test out-of-band signals. In actual implementation, the out-of-band signal test may include out-of-band input / output signal test, I2C interconnection test, I2C / SPI / UART terminal test, etc. Taking the out-of-band input / output signal test as an example, it is assumed that the MCIO connector of the board to be tested 130 includes pins numbered A1 to A37 and B1 to B37, which include 8 groups of PCIe Gen5 differential signals, 2 groups of differential clock (REFCLK) signals, a number of input / output signals and power signals, and 3 groups of I2C signals. At this time, the out-of-band input / output signal pins, such as numbered A8, A9, A26, A27, B8 / B9, B10, B11, B12, B26 / B27, B28, and B29 / B30, etc., can be connected to the test motherboard 100 to read the power-on state for testing, and the remaining pins are connected to the first daughter board 110 to implement testing through input / output mode, voltage measurement mode, or analog I2C Slave device mode. For example, the pins numbered B8 / B9, B26 / B27, and B28 / B29 can be tested by analog I2C Slave device, and the remaining pins can be tested through input / output mode (i.e., I / O testing), and even the pins numbered A9 and B12 can be tested by voltage measurement mode in addition to input / output mode.
[0046] Next, taking the I2C interconnection test as an example, the CPLD of the first daughter board 110 is responsible for monitoring the start / stop status of the I2C bus, for example: the pin number B26 / B27 of each connector 530, and then dynamically switches the I2C interconnection relationship and automatically selects the I2C bus to communicate. A basic test connection logic is as follows: Figure 5As shown, 16 groups of I2C come from the same I2C master 510 (Master). Therefore, there is no need to implement independent testing for each I2C interface. It is only necessary to automatically switch the bus and notify the I2C slave 520 (Slave) which line of the I2C master 510 is currently connected. In other words, the CPLD is responsible for monitoring the start / stop status of the I2C bus, and then switching the corresponding bus to the I2C slave 520 (or terminal Slave), so that the I2C slave 520 can implement the corresponding response according to the selected line. It should be particularly noted that the specific implementation of the present invention is not limited to the above examples, and any similar I2C interconnection test does not deviate from the application scope of the present invention.
[0047] Next, taking the I2C / SPI / UART terminal test as an example, there are two specific implementation methods. The first is to implement a standard protocol, such as the Universal Backplane Management (UBM) protocol, which can be used to respond to basic protocol instructions. In this way, the relevant terminals need to be set up, and the corresponding response packet format is set according to the topology of the board under test 130. Another way is the copy mode, that is, at the beginning, by connecting the I2C of the test motherboard 100 to the traditional host line, at this time, the test motherboard 100 works in the monitoring mode, and the overall bus data can be acquired and stored in this mode. When testing, the test motherboard 100 will respond to the request of the board under test 130 according to the pre-acquired and stored data.
[0048] In summary, it can be seen that the difference between the present invention and the prior art lies in that the test motherboard 100 and the test board 130 are electrically connected to each other through N MCIO connectors 103 and their corresponding MCIO connecting lines 104, so that the test motherboard 100 receives the PCIe Gen5 differential signal, differential clock signal, input / output signal and I2C signal from the test board 130, and then the test is performed through the test logic circuit of the complex programmable logic device and the test program of the baseboard management controller. This technical means can solve the problems existing in the prior art, thereby achieving the technical effect of improving the convenience and coverage of the test.
[0049] Although the present invention is disclosed as above with the aforementioned embodiments, it is not intended to limit the present invention. Any technician in this field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be based on the scope defined by the claims attached to this specification.
Claims
1. A PCIe Gen5 interface test device, the device comprising: A test motherboard, the test motherboard comprising: PCIe switches are used to expand and manage PCIe bus connections, providing multi-channel connections and data exchange; A plurality of slots, the slots comprising at least a first slot and a second slot; and N MCIO connectors, one end of each MCIO connector is connected to the PCIe switch, and the other end of each MCIO connector is connected to the PCIe interface of the board to be tested through a corresponding MCIO connection line, in, N is a positive integer; A first daughter board is inserted into the first slot to be electrically connected to the test motherboard, the first daughter board comprises a complex programmable logic device, wherein the complex programmable logic device comprises an input / output signal, a differential clock and a plurality of serial communication test logic circuits suitable for the test board; as well as The second daughter board is inserted into the second slot to be electrically connected to the test motherboard. The second daughter board includes a baseboard management controller for executing a test program. The test program drives the complex programmable logic device to test input / output signals, differential clocks and the serial communication.
2. The PCIe Gen5 interface testing device according to claim 1, wherein the serial communication includes an integrated bus circuit, a serial peripheral interface and a universal asynchronous transceiver transmitter, and the complex programmable logic device completes out-of-band signal testing by testing input / output signals and the serial communication.
3. The PCIe Gen5 interface test device according to claim 1, wherein the MCIO connection line comprises M channels for transmitting differential signals between the test motherboard and the board under test, and the complex programmable logic device tests the differential signal transmitted in each of the channels, in, M is a positive integer.
4. The PCIe Gen5 interface testing device according to claim 1, wherein when testing the differential clock, the complex programmable logic device uses the differential frequency of one of the MCIO connectors as the differential clock, and transmits the differential frequencies of N-1 of the MCIO connectors to the complex programmable logic device to detect the frequency of the differential clock.
5. The PCIe Gen5 interface testing device according to claim 1, wherein the baseboard management controller runs an OpenBMC system to allow integration with factory business system processes, and provides a Redfish application programming interface to allow control and testing through a third-party system.
6. A PCIe Gen5 interface testing method, the steps of which are include: The test motherboard and the test board are electrically connected to each other, wherein the test motherboard comprises a PCIe switch, a plurality of slots and N MCIO connectors, one end of each MCIO connector is connected to the PCIe switch, and the other end of each MCIO connector is connected to the test board through a corresponding MCIO connection line, wherein the slots at least comprise a first slot and a second slot, and N is a positive integer; Inserting a first daughter board into the first slot to be electrically connected to the test motherboard, the first daughter board comprising a complex programmable logic device, wherein the complex programmable logic device comprises input / output signals, differential clocks and a plurality of serial communication test logic circuits applicable to the test board; Inserting a second daughter board into the second slot to be electrically connected to the test motherboard, the second daughter board comprising a baseboard management controller; and When performing a PCIe Gen5 interface test, the baseboard management controller executes a test program to drive the complex programmable logic device to test the input / output signal, the differential clock and the serial communication.
7. The PCIe Gen5 interface testing method according to claim 6, wherein the serial communication includes an integrated bus circuit, a serial peripheral interface and a universal asynchronous transceiver transmitter, and the complex programmable logic device completes the out-of-band signal test by testing the input / output signal and the serial communication.
8. The PCIe Gen5 interface testing method according to claim 6, wherein the MCIO connection line comprises M channels for transmitting differential signals between the test motherboard and the board under test, and the complex programmable logic device tests the differential signal transmitted in each of the channels, in, M is a positive integer.
9. The PCIe Gen5 interface testing method according to claim 6, wherein when testing the differential clock, the complex programmable logic device uses the differential frequency of one of the MCIO connectors as the differential clock, and transmits the differential frequencies of N-1 of the MCIO connectors to the complex programmable logic device to detect the frequency of the differential clock.
10. The PCIe Gen5 interface testing method of claim 6, wherein the baseboard management controller runs an OpenBMC system to allow integration with factory business system processes, and provides a Redfish application programming interface to allow control and testing through a third-party system.