Silicon optical device structure and manufacturing method thereof

Abstract

The invention discloses a silicon optical device structure and a manufacturing method thereof. The silicon optical device structure comprises a first semiconductor structure arranged on a substrate; the first dielectric layer is arranged on the substrate and covers the first semiconductor structure; the first window is arranged on the surface of the first dielectric layer, and the bottom surface of the first window is located on the first semiconductor structure; the second semiconductor structure is arranged in the first window and is in contact with the first semiconductor structure on the bottom surface of the first window; a second window is formed between the second semiconductor structure and the side wall of the first window, a third semiconductor structure is arranged in the second window, and the third semiconductor structure is in contact with the first semiconductor structure and the second semiconductor structure. According to the invention, a method compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process can be used, the integration of a high-quality silicon optical device is realized, and the performance of the device is improved while the process risk is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit technology, and in particular to a silicon optical device structure compatible with CMOS technology and a manufacturing method thereof. Background Art

[0002] Silicon-based optoelectronic technology focuses on nanoscale optoelectronic devices. With the help of the CMOS process platform and the use of SOI substrate, it realizes the conversion and processing of photoelectric signals in the same chip, and has excellent performance such as high bandwidth, low power consumption, anti-interference and high reliability. It has been applied to data centers, quantum computing, laser radar and biosensors and has broad development prospects. Silicon optical devices usually include passive devices and active devices. Passive devices are used to process optical signals, and active devices are used to convert photoelectric signals.

[0003] Due to the particularity of optical signals, although the silicon photonics process can use the CMOS platform to reduce costs, it still needs to add many special processes that are different from conventional CMOS. These special processes usually become difficulties in the development of silicon photonics processes. For example, photodetectors used in optical communication bands (such as O / C / L bands, etc.) are one of the difficulties of silicon photonics platform technology. Due to the limitations of silicon materials themselves, they cannot absorb light in the optical communication band, so it is impossible to directly use silicon materials to make some silicon photonic devices (such as optical receivers). It is usually necessary to switch to III-V materials or germanium materials. Among them, the lattice coefficients between III-V materials and silicon materials do not match, so it is difficult to use epitaxial processes to grow high-quality on silicon materials. Generally, only bonding processes can be used to bond III-V material devices to silicon substrates, which is difficult and costly. In comparison, germanium materials have a good absorption coefficient in the communication band, and the lattice coefficient is slightly different from that of silicon materials. The industry already has a relatively mature germanium epitaxial process on silicon, which can meet the needs of manufacturing germanium-based photodetectors.

[0004] However, there are still some process difficulties in the current germanium-based photodetector structure and process integration. For example, when the optical signal reaches the germanium-based photodetector through the silicon waveguide, an additional structure needs to be configured for optical mode matching to improve the response rate of the germanium-based photodetector. The current technical means usually add a polysilicon optical mode matching structure in the area where the silicon waveguide and the germanium-based photodetector intersect. The specific process plan includes, after forming structures such as silicon waveguides and silicon active devices on the top silicon layer of the SOI substrate, performing polysilicon and dielectric layer deposition and patterning processes to form a polysilicon optical mode matching structure, and forming a germanium epitaxial window on the silicon active device, removing the dielectric layer and polysilicon layer in the epitaxial window area, and stopping at the silicon active device structure; then performing a germanium epitaxial process in the epitaxial window to form a germanium-based photodetector structure. However, the above process scheme has the following problems: (1) When etching to form the epitaxial window, it is necessary to take into account the treatment of the polysilicon side wall and the surface of the silicon active device structure at the same time, otherwise it will affect the quality of the subsequent germanium epitaxy, making it difficult to adjust the process to take into account different processing requirements; (2) When performing the germanium epitaxial process, germanium will grow synchronously on the polysilicon side wall in the epitaxial window, thereby affecting the epitaxial quality of germanium; (3) Since there is a high correlation between the germanium epitaxial process and the epitaxial window size, it is usually necessary to fix the size of the epitaxial window; but since the performance of the germanium-based photodetector will also be affected by the size of the epitaxial window, it is also difficult to take into account both the process difficulty and the device performance at the same time. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a silicon optical device structure and a manufacturing method thereof.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a silicon optical device structure, comprising:

[0008] substrate;

[0009] a first semiconductor structure disposed on the substrate;

[0010] a first dielectric layer disposed on the substrate, wherein the first dielectric layer covers the first semiconductor structure;

[0011] A first window is provided on the surface of the first dielectric layer, wherein the bottom surface of the first window is located on the first semiconductor structure;

[0012] A second semiconductor structure disposed in the first window, the second semiconductor structure being in contact with the first semiconductor structure located on the bottom surface of the first window;

[0013] A second window is formed between the second semiconductor structure and the sidewall of the first window. A third semiconductor structure is disposed in the second window. The third semiconductor structure is in contact with the first semiconductor structure and the second semiconductor structure.

[0014] Further, the first semiconductor structure is provided with a first contact region of the first conductivity type and a second contact region of the second conductivity type, the third semiconductor structure is provided with a third contact region of the first conductivity type and a fourth contact region of the second conductivity type, the first contact region is connected to the third contact region, the second contact region is connected to the fourth contact region, and / or the first semiconductor structure forms an active device, the second semiconductor structure forms a light receiving part, and the third semiconductor structure forms an electrical lead-out part, and / or the second window and the third semiconductor structure therein are arranged around the second semiconductor structure.

[0015] Furthermore, a protective layer is provided on the surface of the first dielectric layer, and the protective layer covers the second semiconductor structure. A second dielectric layer is also provided on the surface of the first dielectric layer, and the second dielectric layer covers the protective layer and the third semiconductor structure. A conductive contact hole is provided in the second dielectric layer, and the conductive contact hole is connected to the third semiconductor structure.

[0016] Furthermore, the materials of the first semiconductor structure to the third semiconductor structure are different, and / or the material of the first semiconductor structure includes doped single crystal silicon, the material of the second semiconductor structure includes intrinsic germanium, and the material of the third semiconductor structure includes doped polycrystalline silicon.

[0017] Furthermore, the substrate comprises an SOI substrate, the SOI substrate comprises a substrate silicon layer, a buried oxide layer and a top silicon layer, the first semiconductor structure is formed on the top silicon layer, and the first dielectric layer covers the buried oxide layer and the first semiconductor structure.

[0018] The present invention also provides a method for manufacturing a silicon optical device structure, comprising:

[0019] providing a substrate;

[0020] forming a first semiconductor structure on the substrate;

[0021] forming a first dielectric layer on the surface of the substrate to cover the first semiconductor structure;

[0022] forming a first window on the surface of the first dielectric layer to expose the top surface of the first semiconductor structure below;

[0023] Filling the first window with a second semiconductor layer and patterning the layer to form a second semiconductor structure in the first window, and forming a second window between the second semiconductor structure and the sidewall of the first window to expose the top surface of the first semiconductor structure below;

[0024] A third semiconductor layer is filled in the second window and patterned to form a third semiconductor structure in the second window.

[0025] Furthermore, providing a substrate and forming a first semiconductor structure on the substrate specifically includes:

[0026] Providing an SOI substrate, wherein the SOI substrate comprises a substrate silicon layer, a buried oxide layer and a top silicon layer;

[0027] Using photolithography and etching processes to pattern the top silicon layer to form a top silicon layer pattern, exposing the surface of the buried oxide layer;

[0028] Forming a doped first contact region of a first conductivity type and a doped second contact region of a second conductivity type on both sides of the top silicon layer pattern, thereby forming a doped single crystal silicon first semiconductor structure on the surface of the buried oxide layer of the SOI substrate;

[0029] The step of forming a first dielectric layer on the surface of the substrate to cover the first semiconductor structure specifically includes:

[0030] A first dielectric layer is formed on the surface of the buried oxide layer to cover the first semiconductor structure.

[0031] Furthermore, forming a first window on the surface of the first dielectric layer to expose the top surface of the first semiconductor structure below specifically includes:

[0032] Using photolithography and etching processes, forming a first window on the surface of the first dielectric layer above the first semiconductor structure, so that the first window is located within the region of the first semiconductor structure and stops on the top surface of the first semiconductor structure;

[0033] The step of filling the first window with a second semiconductor layer and patterning the first window to form a second semiconductor structure, and forming a second window between the second semiconductor structure and the sidewall of the first window to expose the top surface of the first semiconductor structure below, specifically includes:

[0034] Using an epitaxial process, growing an intrinsic germanium second semiconductor layer on the top surface of the first semiconductor structure in the first window to fill the first window;

[0035] forming a protective layer on the surface of the first dielectric layer to cover the second semiconductor layer;

[0036] The second semiconductor layer is patterned by using photolithography and etching processes to form an intrinsic germanium second semiconductor structure in the first window, and the second semiconductor structure is contacted with the top surface of the first semiconductor structure between the first contact area and the second contact area, so that a second window surrounding the second semiconductor structure is formed between the second semiconductor structure and the sidewall of the first window, and the top surface of the first semiconductor structure below is exposed;

[0037] The step of filling the second window with a third semiconductor layer and patterning the second window to form a third semiconductor structure includes:

[0038] forming a third semiconductor layer of polysilicon on the surface of the protective layer, and filling the second window;

[0039] Removing the redundant third semiconductor layer on the surface of the protective layer, and making the top surface of the third semiconductor layer in the second window lower than the surface of the protective layer, thereby forming a patterned third semiconductor layer in the second window, and making the third semiconductor layer contact with the top surface of the first semiconductor structure and the side surface of the second semiconductor structure;

[0040] A doped third contact region of the first conductivity type and a doped fourth contact region of the second conductivity type are formed on the patterned third semiconductor layer, and the third contact region is connected to the first contact region, and the fourth contact region is connected to the second contact region, thereby forming a doped polysilicon third semiconductor structure surrounding the second semiconductor structure in the second window.

[0041] Furthermore, it also includes:

[0042] forming a second dielectric layer on the surface of the protective layer to cover the third semiconductor structure;

[0043] A conductive contact hole having a bottom portion connected to the third contact region and the fourth contact region on the top surface of the third semiconductor structure is formed on the surface of the second dielectric layer.

[0044] Further, a doped single crystal silicon active device is formed by forming the first contact region and the second contact region on the single crystal silicon first semiconductor structure; a germanium light receiving part is formed by forming the intrinsic germanium second semiconductor structure on the active device between the first contact region and the second contact region; an electrical lead-out part of the active device is formed by forming the third contact region and the fourth contact region on the polycrystalline silicon third semiconductor structure; and / or, a light receiving area of ​​the germanium light receiving part is adjusted by adjusting the relative size between the second window and the first window.

[0045] It can be seen from the above technical scheme that the present invention forms a first window as an epitaxial window on the first dielectric layer on the first semiconductor structure (silicon active device), forms a second semiconductor structure (germanium light receiving part) in the first window, and then forms a third semiconductor structure (including a polysilicon electrical lead-out part and a polysilicon optical mode matching structure for matching with the passive device) by patterning the second window formed between the second semiconductor structure and the first window, so it has the following advantages:

[0046] (1) When the first window serving as the epitaxial window is formed by an etching process, since the first window is formed in the first dielectric layer, only the surface treatment of the substrate silicon (first semiconductor structure) needs to be considered, thereby eliminating the problem of simultaneously considering the treatment of the polysilicon sidewalls in the epitaxial window, resulting in a significant reduction in the difficulty of the process.

[0047] (2) Since the germanium second semiconductor layer will not contact the polysilicon third semiconductor layer during epitaxial formation, defects in the germanium second semiconductor layer caused by the polysilicon third semiconductor layer during epitaxial growth are avoided, thereby reducing the process difficulty and improving device performance.

[0048] (3) While the polysilicon third semiconductor layer formation process is being carried out, the width of the second semiconductor structure serving as the germanium light receiving part can be adjusted by forming second windows of different sizes, thereby avoiding the adverse effects of the epitaxial window width on the germanium epitaxial process, thereby also reducing the process difficulty and improving device performance.

[0049] (4) By setting the conductive contact hole for lead-out on the polysilicon third semiconductor structure, the electric field distribution can overlap more with the silicon optical device (germanium photodetector) and be better distributed, so that the electron-hole pairs generated by light can be swept away by the electric field more quickly, thereby further improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of a silicon optical device structure according to a preferred embodiment of the present invention.

[0051] Figure 2-Figure 10 This is a flow chart of a method for manufacturing a silicon optical device structure according to a preferred embodiment of the present invention; wherein: Figure 8 A top view showing the relative positions of the polysilicon third semiconductor structure, the germanium second semiconductor structure and the conductive contact hole. Fig. 9 for Figure 8 AA section structure diagram, Fig.10 for Figure 8 Schematic diagram of the cross-sectional structure along the BB axis. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0053] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0054] refer to Figure 1 The silicon optical device structure of the present invention includes: a substrate 100, a first semiconductor structure 1031 disposed on the substrate 100, a second semiconductor structure 110 disposed on the first semiconductor structure 1031, a third semiconductor structure 107 disposed on the first semiconductor structure 1031 and located on the side of the second semiconductor structure 110, and a first dielectric layer 104 disposed on the substrate 100.

[0055] The first dielectric layer 104 covers the upper surface of the substrate 100 and surrounds the first semiconductor structure 1031. A first window 105 is provided on the upper surface of the first dielectric layer 104, and the bottom surface of the first window 105 is located on the upper surface of the first semiconductor structure 1031. The second semiconductor structure 110 is provided in the first window 105 and contacts the upper surface of the first semiconductor structure 1031 exposed on the bottom surface of the first window 105. A certain distance is maintained between the side surface of the second semiconductor structure 110 and the side wall of the first window 105, so that a second window 1051 is formed between the side surface of the second semiconductor structure 110 and the side wall of the first window 105. The third semiconductor structure 107 is provided in the second window 1051, and the third semiconductor structure 107 contacts the upper surface of the first semiconductor structure 1031 and the side surface of the second semiconductor structure 110.

[0056] refer to Figure 1 In some embodiments, the first semiconductor structure 1031 is provided with a first contact region 1032 of the first conductivity type and a second contact region 1033 of the second conductivity type. The third semiconductor structure 107 is provided with a third contact region 1071 of the first conductivity type and a fourth contact region 1072 of the second conductivity type. The first contact region 1032 is in contact with and connected to the third contact region 1071, and the second contact region 1033 is in contact with and connected to the fourth contact region 1072. Taking the first conductivity type as N type and the second conductivity type as P type as an example, the left side of the first semiconductor structure 1031 is provided with a first conductivity type medium-doped N type first contact region 1032, and the right side of the first semiconductor structure 1031 is provided with a second conductivity type medium-doped P type second contact region 1033; the third semiconductor structure 107 on the left side is provided with a first conductivity type heavily doped N++ type third contact region 1071, and the third semiconductor structure 107 on the right side is provided with a second conductivity type heavily doped P++ type fourth contact region 1072.

[0057] In some embodiments, the first semiconductor structure 1031 forms an active device of a silicon photonic device; the second semiconductor structure 110 forms a light receiving portion of the silicon photonic device; and the third semiconductor structure 107 forms an electrical lead-out portion of the silicon photonic device.

[0058] In some embodiments, the second window 1051 is disposed around the second semiconductor structure 110 .

[0059] Furthermore, the third semiconductor structure 107 disposed in the second window 1051 is continuously disposed around the second semiconductor structure 110 .

[0060] refer to Figure 1In some embodiments, a protection layer 109 is disposed on the upper surface of the first dielectric layer 104 , and the protection layer 109 also covers the upper surface of the second semiconductor structure 110 .

[0061] Furthermore, a second dielectric layer 106 is further provided on the upper surface of the first dielectric layer 104, and the second dielectric layer 106 also covers the protective layer 109 and the third semiconductor structure 107 (including the second semiconductor structure 110). A plurality of conductive contact holes 108 are provided in the second dielectric layer 106, the lower ends of the conductive contact holes 108 are respectively connected to the third contact region 1071 and the fourth contact region 1072 of the third semiconductor structure 107, and the upper ends of the conductive contact holes 108 are led out from the upper surface of the second dielectric layer 106.

[0062] In some embodiments, the upper surface of the third semiconductor structure 107 is not higher than the upper surface of the protective layer 109. For example, the upper surface of the third semiconductor structure 107 may be lower than the upper surface of the protective layer 109, and may be further lower than the upper surface (top surface) of the second semiconductor structure 110. That is, the upper surface of the third semiconductor structure 107 is lower than the top of the first window 105 (the second window 1051).

[0063] In some embodiments, the materials of the first semiconductor structure 1031 to the third semiconductor structure 107 are different. For example, the material of the first semiconductor structure 1031 includes doped single crystal silicon, the material of the second semiconductor structure 110 includes intrinsic germanium, and the material of the third semiconductor structure 107 includes doped polysilicon, but it is not limited thereto.

[0064] In some embodiments, the material of the first dielectric layer 104 and / or the material of the second dielectric layer 106 includes silicon dioxide or silicon oxynitride, or includes other low dielectric constant materials.

[0065] In some embodiments, the material of the protection layer 109 includes conventional dielectric layer materials such as silicon dioxide or silicon nitride.

[0066] In some embodiments, the substrate 100 includes an SOI substrate 100; the SOI substrate 100 includes a substrate silicon layer 101, a buried oxide layer 102, and a top silicon layer 103. The first semiconductor structure 1031 is formed on the top silicon layer 103, that is, the first semiconductor structure 1031 is formed by patterning the top silicon layer 103, so the first dielectric layer 104 can cover the buried oxide layer 102 and the first semiconductor structure 1031 at the same time.

[0067] The above silicon photonic device structure can be used to form a photodetector, such as a germanium-based photodetector, and can further form a silicon photonic light receiving device.

[0068] A method for manufacturing a silicon optical device structure of the present invention is further described in detail below through specific implementations and in conjunction with the accompanying drawings.

[0069] refer to Figure 2-Figure 10 The present invention provides a method for manufacturing a silicon optical device structure, which can be used to manufacture the above-mentioned Figure 1 A silicon optical device structure of the present invention may include the following steps:

[0070] Step S1: providing a substrate 100 .

[0071] like Figure 2 As shown, a silicon optical device structure of the present invention is manufactured using an SOI substrate 100. The SOI substrate 100 includes a substrate silicon layer 101, a buried oxide layer 102 and a top silicon layer 103 from bottom to top.

[0072] Step S2 : forming a first semiconductor structure 1031 on the substrate 100 .

[0073] like Figure 3 As shown, first, a CMOS-related process of a silicon-based active device is performed on the SOI substrate 100. Specifically, the process includes: patterning the top silicon layer 103 of the SOI substrate 100 by photolithography and etching processes to form a top silicon layer 103 pattern (a pattern of the first semiconductor structure 1031), exposing the upper surface of the buried oxide layer 102. After cleaning, an ion implantation process is used to form an N-type doped first contact region 1032 and a P-type doped second contact region 1033 on both sides of the top silicon layer 103 pattern. Thus, a doped single crystal silicon first semiconductor structure 1031 as a silicon optical active device is formed on the surface of the buried oxide layer 102 of the SOI substrate 100.

[0074] Step S3 : forming a first dielectric layer 104 on the surface of the substrate 100 to cover the first semiconductor structure 1031 .

[0075] like Figure 3 As shown, a dielectric deposition process is then used to form a first dielectric layer 104 such as silicon dioxide on the upper surface of the SOI substrate 100 , that is, the first dielectric layer 104 is formed on the upper surface of the buried oxide layer 102 , so that the first dielectric layer 104 covers the buried oxide layer 102 and the first semiconductor structure 1031 .

[0076] The deposition thickness of the first dielectric layer 104 is related to the design thickness of the silicon optical device structure (eg, germanium-based photodetector). For example, the thickness of the first dielectric layer 104 is

[0077] Step S4: forming a first window 105 on the surface of the first dielectric layer 104 to expose the top surface of the first semiconductor structure 1031 thereunder.

[0078] like Figure 4 As shown, then, a photolithography and etching process is used to etch downward on the upper surface of the first dielectric layer 104 to form a first window 105 as a germanium epitaxial window, and the first window 105 is located in an area within the first semiconductor structure 1031, and the bottom surface of the first window 105 stops on the upper surface of the first semiconductor structure 1031, exposing the top surface of the first semiconductor structure 1031 below.

[0079] The etching process may include a dry etching process; a dry-wetting process, or a pure wet process may also be used to achieve a better etching morphology and a good silicon surface state.

[0080] Step S5: Fill the first window 105 with a second semiconductor layer and perform patterning to form a second semiconductor structure 110 in the first window 105 and a second window 1051 between the second semiconductor structure 110 and the sidewall of the first window 105 to expose the top surface of the first semiconductor structure 1031 below.

[0081] like Figure 5 As shown, then, an epitaxial process is used to grow an intrinsic germanium second semiconductor layer 1101 on the top surface of the silicon first semiconductor structure 1031 in the first window 105 to fill the first window 105 .

[0082] Among them, the germanium epitaxial process includes the steps of surface pretreatment, low-temperature germanium epitaxy and high-temperature germanium epitaxy, and annealing is required after epitaxy.

[0083] Afterwards, a planarization process is used to planarize the surface of the formed germanium epitaxial second semiconductor layer 1101. For example, a chemical mechanical polishing method can be used to remove the excess germanium second semiconductor layer 1101 material outside the first window 105, so that the surface of the germanium second semiconductor layer 1101 is flat, thereby forming the germanium second semiconductor layer 1101 in the first window 105.

[0084] It is understandable that, when the germanium epitaxial morphology is well controlled, the above-mentioned planarization step may be omitted.

[0085] Next, a dielectric deposition process is used to form a silicon dioxide protective layer 109 on the upper surface of the first dielectric layer 104 to cover the germanium second semiconductor layer 1101. The thickness of the protective layer 109 is, for example, greater than

[0086] like Figure 6As shown, then, the second semiconductor layer 1101 is patterned by using photolithography and etching processes, and part of the second semiconductor layer 1101 material near the sidewall area of ​​the first window 105 is removed, and an intrinsic germanium second semiconductor structure 110 is formed in the first window 105, and the second semiconductor structure 110 is contacted with the top surface of the first semiconductor structure 1031 located between the first contact area 1032 and the second contact area 1033. Thus, a second window 1051 surrounding the second semiconductor structure 110 is formed between the side of the second semiconductor structure 110 and the sidewall of the first window 105, and the top surface of the first semiconductor structure 1031 below is exposed. The formed intrinsic germanium second semiconductor structure 110 can be used to form a germanium light receiving part.

[0087] The etching process may be a dry etching process; or a dry-wet etching process, or a pure wet etching process, to achieve a better etching morphology and a good surface state of the silicon first semiconductor structure 1031 .

[0088] By adjusting the relative size between the second window 1051 and the first window 105, that is, adjusting the critical dimension when etching the second semiconductor layer 1101, the light receiving area of ​​the formed germanium light receiving portion can be adjusted.

[0089] Step S6 : filling the second window 1051 with a third semiconductor layer and performing patterning to form a third semiconductor structure 107 in the second window 1051 .

[0090] like Figure 7 As shown, then, a deposition process is used to form a polysilicon third semiconductor layer on the upper surface of the protection layer 109 (the first dielectric layer 104 ) to fill the second window 1051 .

[0091] Then, a planarization process, for example, a chemical mechanical polishing method may be used to remove the redundant third semiconductor layer on the surface of the protective layer 109 outside the second window 1051, so that the third semiconductor layer has a flat surface, and the top surface of the third semiconductor layer in the second window 1051 is lower than the surface of the protective layer 109. The top of the third semiconductor layer in the second window 1051 is patterned by chemical mechanical polishing, so that a pattern of the third semiconductor layer with a flat upper surface (i.e., a pattern of the third semiconductor structure 107) is formed in the second window 1051, and the third semiconductor layer is in contact with the top surface of the first semiconductor structure 1031 and the side surface of the second semiconductor structure 110.

[0092] A silicon etch-back process may also be used to etch the top of the third semiconductor layer to form a pattern of the third semiconductor layer having a flat upper surface in the second window 1051 .

[0093] A top surface of the third semiconductor layer pattern may be lower than a top surface of the second semiconductor structure 110 , exposing a portion of a side surface of the second semiconductor structure 110 .

[0094] like Fig. 9 As shown, then, a photolithography process is used to define ion implantation regions on the patterned third semiconductor layer located on both sides of the second semiconductor structure 110, and an ion implantation process is used to form an N++-doped third contact region 1071 and a P++-doped fourth contact region 1072 on the third semiconductor layer located on both sides of the second semiconductor structure 110, and the third contact region 1071 is connected to the first contact region 1032, and the fourth contact region 1072 is connected to the second contact region 1033. Thus, a doped polysilicon third semiconductor structure 107 surrounding the second semiconductor structure 110 is formed in the second window 1051. By forming the third contact region 1071 and the fourth contact region 1072 on the polysilicon third semiconductor structure 107, they can be used as electrical lead-out portions of the silicon active device below (for example, as electrical lead-out portions of a germanium-based photodetector).

[0095] When the third contact region 1071 and the fourth contact region 1072 are formed by implantation, the doping ion concentration per unit volume is usually E19-E20 atoms / cm 3 Magnitude.

[0096] Furthermore, it also includes:

[0097] Step S7 : forming a conductive contact hole 108 on the third semiconductor structure 107 .

[0098] like Fig. 9 As shown, a dielectric deposition process is used to form a second dielectric layer 106 such as silicon dioxide on the upper surface of the protection layer 109 (the first dielectric layer 104 ), and the top surface of the third semiconductor structure 107 is covered.

[0099] Then, by using photolithography and etching processes, contact hole trenches are formed on the upper surface of the second dielectric layer 106 , the bottoms of which are respectively connected to the third contact region 1071 and the fourth contact region 1072 on the top surface of the third semiconductor structure 107 .

[0100] Next, the contact hole trench is filled with contact hole metal and other processes are performed to form a conductive contact hole 108 whose bottom is respectively connected to the third contact area 1071 and the fourth contact area 1072. The top view structure of the completed silicon optical device is as follows: Figure 8 , which shows the relative positions of the polysilicon third semiconductor structure 107 , the germanium second semiconductor structure 110 and the conductive contact hole 108 . Fig. 9 Shows Figure 8 The cross-sectional structure of the silicon photonic device in the AA direction. Fig.10 Shows Figure 8 Cross-sectional structure of silicon photonic device in the BB direction.

[0101] Conventional CMOS back-end processes may be used subsequently to further form a metal interconnection layer, which will not be described in detail.

[0102] The above method of the present invention can manufacture a germanium-based photodetector structure as a silicon photonic device, and can further form a silicon photonic light receiving device.

[0103] In summary, the present invention forms a first window 105 as a germanium epitaxial window on the first dielectric layer 104 on the first semiconductor structure 1031 as a silicon active device, and forms a second semiconductor structure 110 as a germanium light receiving part in the first window 105, and then forms a second window 1051 formed between the second semiconductor structure 110 and the first window 105 by patterning, and then forms a third semiconductor structure 107 including a polysilicon electrical lead-out part, which can significantly reduce the process difficulty and improve the germanium epitaxy quality; and the width of the germanium light receiving part can be adjusted by forming second windows 1051 of different sizes, thereby avoiding the adverse effects of the epitaxial window width on the germanium epitaxy process. The present invention can use a method compatible with the CMOS process to achieve the integration of high-quality germanium-based photodetection devices, while reducing process risks and improving device performance.

[0104] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A silicon optical device structure, It is characterized in that include: substrate; a first semiconductor structure disposed on the substrate; a first dielectric layer disposed on the substrate, wherein the first dielectric layer covers the first semiconductor structure; A first window is provided on the surface of the first dielectric layer, wherein the bottom surface of the first window is located on the first semiconductor structure; A second semiconductor structure disposed in the first window, the second semiconductor structure being in contact with the first semiconductor structure located on the bottom surface of the first window; A second window is formed between the second semiconductor structure and the sidewall of the first window. A third semiconductor structure is disposed in the second window. The third semiconductor structure is in contact with the first semiconductor structure and the second semiconductor structure.

2. The silicon photonic device structure according to claim 1, It is characterized in that The first semiconductor structure is provided with a first contact region of a first conductivity type and a second contact region of a second conductivity type, the third semiconductor structure is provided with a third contact region of the first conductivity type and a fourth contact region of the second conductivity type, the first contact region is connected to the third contact region, the second contact region is connected to the fourth contact region, and / or the first semiconductor structure forms an active device, the second semiconductor structure forms a light receiving part, and the third semiconductor structure forms an electrical lead-out part, and / or the second window and the third semiconductor structure therein are arranged around the second semiconductor structure.

3. The silicon photonic device structure according to claim 1, It is characterized in that A protective layer is provided on the surface of the first dielectric layer, and the protective layer covers the second semiconductor structure. A second dielectric layer is also provided on the surface of the first dielectric layer, and the second dielectric layer covers the protective layer and the third semiconductor structure. A conductive contact hole is provided in the second dielectric layer, and the conductive contact hole is connected to the third semiconductor structure.

4. The silicon photonic device structure according to claim 1, It is characterized in that The materials of the first semiconductor structure to the third semiconductor structure are different from each other, and / or the material of the first semiconductor structure includes doped single crystal silicon, the material of the second semiconductor structure includes intrinsic germanium, and the material of the third semiconductor structure includes doped polycrystalline silicon.

5. The silicon photonic device structure according to claim 1, It is characterized in that The substrate comprises an SOI substrate, which comprises a substrate silicon layer, a buried oxide layer and a top silicon layer. The first semiconductor structure is formed on the top silicon layer, and the first dielectric layer covers the buried oxide layer and the first semiconductor structure.

6. A method for manufacturing a silicon optical device structure, It is characterized in that include: providing a substrate; forming a first semiconductor structure on the substrate; forming a first dielectric layer on the surface of the substrate to cover the first semiconductor structure; forming a first window on the surface of the first dielectric layer to expose the top surface of the first semiconductor structure below; Filling the first window with a second semiconductor layer and patterning the layer to form a second semiconductor structure in the first window, and forming a second window between the second semiconductor structure and the sidewall of the first window to expose the top surface of the first semiconductor structure below; A third semiconductor layer is filled in the second window and patterned to form a third semiconductor structure in the second window.

7. The method for manufacturing a silicon optical device structure according to claim 6, It is characterized in that The providing of a substrate and forming a first semiconductor structure on the substrate specifically includes: Providing an SOI substrate, wherein the SOI substrate comprises a substrate silicon layer, a buried oxide layer and a top silicon layer; Using photolithography and etching processes to pattern the top silicon layer to form a top silicon layer pattern, exposing the surface of the buried oxide layer; Forming a doped first contact region of a first conductivity type and a doped second contact region of a second conductivity type on both sides of the top silicon layer pattern, thereby forming a doped single crystal silicon first semiconductor structure on the surface of the buried oxide layer of the SOI substrate; The step of forming a first dielectric layer on the surface of the substrate to cover the first semiconductor structure specifically includes: A first dielectric layer is formed on the surface of the buried oxide layer to cover the first semiconductor structure.

8. The method for manufacturing a silicon optical device structure according to claim 7, It is characterized in that The step of forming a first window on the surface of the first dielectric layer to expose the top surface of the first semiconductor structure below specifically includes: Using photolithography and etching processes, forming a first window on the surface of the first dielectric layer above the first semiconductor structure, so that the first window is located within the region of the first semiconductor structure and stops on the top surface of the first semiconductor structure; The step of filling the first window with a second semiconductor layer and patterning the first window to form a second semiconductor structure, and forming a second window between the second semiconductor structure and the sidewall of the first window to expose the top surface of the first semiconductor structure below, specifically includes: Using an epitaxial process, growing an intrinsic germanium second semiconductor layer on the top surface of the first semiconductor structure in the first window to fill the first window; forming a protective layer on the surface of the first dielectric layer to cover the second semiconductor layer; The second semiconductor layer is patterned by using photolithography and etching processes to form an intrinsic germanium second semiconductor structure in the first window, and the second semiconductor structure is contacted with the top surface of the first semiconductor structure between the first contact area and the second contact area, so that a second window surrounding the second semiconductor structure is formed between the second semiconductor structure and the sidewall of the first window, and the top surface of the first semiconductor structure below is exposed; The step of filling the second window with a third semiconductor layer and patterning the second window to form a third semiconductor structure includes: forming a third semiconductor layer of polysilicon on the surface of the protective layer, and filling the second window; Removing the redundant third semiconductor layer on the surface of the protective layer, and making the top surface of the third semiconductor layer in the second window lower than the surface of the protective layer, thereby forming a patterned third semiconductor layer in the second window, and making the third semiconductor layer contact with the top surface of the first semiconductor structure and the side surface of the second semiconductor structure; A doped third contact region of the first conductivity type and a doped fourth contact region of the second conductivity type are formed on the patterned third semiconductor layer, and the third contact region is connected to the first contact region, and the fourth contact region is connected to the second contact region, thereby forming a doped polysilicon third semiconductor structure surrounding the second semiconductor structure in the second window.

9. The method for manufacturing a silicon optical device structure according to claim 8, It is characterized in that Also includes: forming a second dielectric layer on the surface of the protective layer to cover the third semiconductor structure; A conductive contact hole having a bottom portion connected to the third contact region and the fourth contact region on the top surface of the third semiconductor structure is formed on the surface of the second dielectric layer.

10. The method for manufacturing a silicon photonic device structure according to claim 9, It is characterized in that The first contact region and the second contact region are formed on the first single crystal silicon semiconductor structure to form a doped single crystal silicon active device; the intrinsic germanium second semiconductor structure is formed on the active device between the first contact region and the second contact region to form a germanium light receiving portion; Forming the third contact region and the fourth contact region on the polysilicon third semiconductor structure to form an electrical lead-out portion of the active device; And / or, by adjusting the relative size between the second window and the first window, the light receiving area of ​​the germanium light receiving part is adjusted.

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