Network packet processing device and network packet processing method

Abstract

The invention discloses a network packet processing apparatus and a network packet processing method. The network packet processing device comprises a first memory, a second memory, a direct memory access controller and a network processor. The access delay of the second memory is lower than the access delay of the first memory. The direct memory access controller is used for writing a network packet into the first memory and writing a part of packet content in the network packet into the second memory. The network processor is configured to read the partial packet content from the second memory and perform packet preprocessing of the network packet according to the partial packet content.

Description

Technical Field

[0001] The present invention relates to network packet processing, and more particularly to a network packet processing device and a network packet processing method that utilizes a memory with lower access delay to store partial packet content to improve the packet preprocessing performance of a network processor. Background Art

[0002] A network processor (NPU) is a processor specifically used for network packet processing, and has some special features and architectures to accelerate the processing efficiency of network packets. For example, for packet forwarding, the network processor can perform packet preprocessing to determine the matching forwarding rules. The network chip can then use the matching forwarding rules to send the network packets received by a network connection port out of the network connection port that meets the forwarding rules. For traditional embedded devices with limited resources, dynamic random access memory (DRAM) is generally used to store a large number of network packets. Therefore, when the network processor performs packet preprocessing, it is necessary to read the packet data from the dynamic random access memory. However, the dynamic random access memory has a very high access latency. For example, each read takes at least 150 nanoseconds. Since the packet preprocessing performance of the network processor is limited by the high access latency of the dynamic random access memory, the overall packet forwarding processing efficiency is affected. Summary of the invention

[0003] One of the objectives of the present invention is to provide a network packet processing device and a network packet processing method that utilize a memory with lower access latency to store partial packet content to improve the packet pre-processing performance of a network processor.

[0004] In one embodiment of the present invention, a network packet processing device is disclosed. The network packet processing device includes a first memory, a second memory, a direct memory access controller, and a network processor. The access delay of the second memory is lower than the access delay of the first memory. The direct memory access controller is used to write a network packet to the first memory, and write a portion of the packet content in the network packet to the second memory. The network processor is used to read the portion of the packet content from the second memory, and perform packet preprocessing of the network packet according to the portion of the packet content.

[0005] In one embodiment of the present invention, a network packet processing method is disclosed. The network packet processing method comprises: writing a network packet to a first memory through direct memory access; writing a portion of packet content in the network packet to a second memory through direct memory access, wherein the access delay of the second memory is lower than the access delay of the first memory; and reading the portion of packet content from the second memory, and performing packet preprocessing of the network packet according to the portion of packet content.

[0006] Compared to reading the data required by the packet preprocessing circuit from a memory with a higher access delay, the present invention reads the data required by the packet preprocessing circuit from a memory with a lower access delay, which can greatly improve the packet preprocessing performance of the packet preprocessing circuit, thereby improving the performance of subsequent network chips in packet forwarding. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of a network packet processing device according to an embodiment of the present invention.

[0008] Figure 2 A schematic diagram of an address sniffing configuration according to an embodiment of the present invention.

[0009] Figure 3 The data structure of the ring buffer is maintained by an embodiment of the present invention. Figure 1 A schematic diagram of the sniff list is shown.

[0010] Figure 4 FIG. 4 is a schematic diagram of memory synchronization according to an embodiment of the present invention.

[0011] Figure 5 The figure is a flow chart of a network packet processing method according to an embodiment of the present invention.

[0012] Figure 6 For an embodiment of the present invention, Figure 1 FIG. 1 is a schematic diagram showing a network packet processing device performing packet preprocessing to improve packet forwarding efficiency.

[0013]

Explanation of symbols

[0014] 100: Network packet processing device

[0015] 102, 104: Memory

[0016] 103: Bus

[0017] 106: Direct Memory Access Controller

[0018] 108: Network Processor

[0019] 109: Sniff List

[0020] 110: Address sniffing circuit

[0021] 112: memory synchronization circuit

[0022] 111: Entry

[0023] 114: Packet preprocessing circuit

[0024] 302: Ring buffer

[0025] 304: Data Structure

[0026] 306: Packet Descriptor

[0027] 602: Network chip

[0028] PKT, P1, P2, P3, P4: Package

[0029] PH, H1, H2, H3, H4: Partial package content

[0030] addr1, addr2, addr3, addr(n-2), addr(n-1), addrn, addr(n+1), addrN, BUF_ADDR: memory address

[0031] IDX_R, IDX_W, HW_IDX, SW_IDX: index value

[0032] PKT_INFO: package related information

[0033] PKT_LEN: Packet length

[0034] FSB_1, FSB_2, FSB_3, FSB_N-1, FSB_N: storage blocks

[0035] S500, S502, S504, S506, S508, S510, S512, S514, S516: Steps DETAILED DESCRIPTION

[0036] Certain words are used in the specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the criterion for distinction. The "include" and "comprising" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the term "coupled" or "coupled" herein includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0037] Figure 1Schematic diagram of a network packet processing device according to an embodiment of the present invention. For example, the network packet processing device 100 can be applied to a network device, such as a gateway. As shown in the figure, the network packet processing device 100 can include memories 102, 104, a direct memory access (DMA) controller 106, and a network processor 108. The memory 102 and the memory 104 adopt different architectures and have different access delays. In this embodiment, the access delay of the memory 104 is lower than the access delay of the memory 102. For example, the memory 102 is a dynamic random access memory, and the memory 104 is a static random access memory (SRAM). However, the present invention is not limited to this. The network processor 108 can be a RISC-V processor and has a packet preprocessing circuit 114 to support the packet preprocessing function. For example, the packet preprocessing function can be applied to the application scenario of packet forwarding. However, the present invention is not limited to this. The direct memory access controller 106 can access (read and write) the memories 102 and 104 directly through the bus 103 without the intervention of the processor. In this embodiment, compared with the memory 102, the memory 104 has a higher cost, so the capacity of the memory 102 is greater than the capacity of the memory 104, so the direct memory access controller 106 will write a network packet PKT (such as a TCP packet) completely to the memory 102. In addition, compared with the memory 102, the memory 104 has a lower access delay (i.e., a higher access speed), so the direct memory access controller 106 will also write a portion of the packet content PH in the network packet PKT to the memory 104. When the packet preprocessing function is applied to the application scenario of packet forwarding, the portion of the packet content PH will include the header of the network packet PKT, and the length of the portion of the packet content PH can be set according to the actual application requirements, for example, the portion of the packet content PH will be 32 bytes of data in the network packet PKT.

[0038] The network processor 108 (especially the packet preprocessing circuit 114 of the network processor 108) can read part of the packet content PH from the memory 104, and perform packet preprocessing (e.g., preprocessing of packet forwarding) of the network packet PKT according to the part of the packet content PH. Compared with reading the data required by the packet preprocessing circuit 114 from the memory 102 with a higher access delay, the present invention reads the data required by the packet preprocessing circuit 114 from the memory 104 with a lower access delay, which can greatly improve the packet preprocessing performance of the packet preprocessing circuit 114, thereby improving the performance of the subsequent network chip in packet forwarding. The operation details of the network packet processing device 100 of the present invention will be described in detail below.

[0039] In this embodiment, the direct memory access controller 106 includes an address sniffing circuit 110 and a memory synchronization circuit 112. The address sniffing circuit 110 configures a memory address to be monitored. For example, the sniffing list 109 can record N memory addresses addr1, addr2, ..., addrn, ..., addrN at most. The address sniffing circuit 110 reads the memory address to be monitored (for example, addr1) from the sniffing list 109 through an index value IDX_R. In addition, when the direct memory access controller 106 performs direct memory access on the memory 102, the address sniffing circuit 110 also monitors at least one write address that the direct memory access controller 106 wants to write into the memory 102, and when the memory address to be monitored hits the at least one write address, the memory synchronization circuit 112 is triggered to write the partial packet content PH into the memory 104. In this embodiment, before the network packet PKT is transmitted to the memory 102, the memory synchronization circuit 112 will first transmit the partial packet content PH to the memory 104. In this way, it can be ensured that after the network packet PKT is written to the memory 102, the memory 104 will have the partial packet content PH in the network packet PKT. In other words, the same partial packet content PH will be synchronously stored in the memories 102 and 104.

[0040] In addition to supporting the packet preprocessing function, the network processor 108 is further used to establish and maintain the aforementioned sniff list 109. For example, the sniff list 109 can be stored in the memory 102. The sniff list 109 can have a fixed length and is arranged as a plurality of entries 111, which are respectively used to record a plurality of memory addresses addr1-addrN in the memory 102 that can be used by a plurality of network packets. The network processor 108 will first use a preset value (e.g., 0x0) to initialize all entries 111 in the sniff list 109 (e.g., addr1=0x0, addr2=0x0, ..., addrN=0x0) and set the index value IDX_W to an initial value (e.g., IDX_W=1). After that, the network processor 108 (especially the packet preprocessing circuit 114 of the network processor 108) will fill the memory address in the memory 102 that can be used for the network packet into the sniff list 109 based on the index value IDX_W, and update the index value IDX_W accordingly (e.g., IDX_W=IDX_W+1). In other words, the index value IDX_W is used to indicate which entry 111 in the sniff list 109 can currently be filled with a new memory address to be monitored.

[0041] In addition, the index value IDX_R is used to indicate which entry 111 in the sniff list 109 can currently be read by the address sniffing circuit 110 to configure the memory address to be monitored by the address sniffing circuit 110. When at least one write address to be written by the direct memory access controller 106 to the memory 102 hits the memory address to be monitored currently configured by the address sniffing circuit 110 (for example, the memory address to be monitored falls within the memory address range to be written by the direct memory access burst (DMA burst)), the address sniffing circuit 110 will update the index value IDX_R (for example, IDX_R=IDX_R+1) so as to read the next memory address to be monitored from the sniff list 109 to replace the current memory address to be monitored.

[0042] Figure 2 Schematic diagram of the address sniffing configuration of an embodiment of the present invention. Since the direct memory access controller 106 generally uses the direct memory access burst mode to access the memory 102, the memory address to be monitored configured by the address sniffing circuit 111 needs to be aligned with the direct memory access burst size (DMA burst size). For example, the offset between two memory addresses to be monitored will be an integer multiple of the direct memory access burst size. For example, assuming that the direct memory access burst size is 128 bytes, the memory address to be monitored can be set to 0x80, 0x100, 0x180, etc., respectively aligned with the direct memory access burst size of 128 bytes. Figure 2 As shown, the packet preprocessing circuit 114 writes multiple memory addresses in the memory 102 for storing network packets into the entries 111 in the sniffing list 109 one by one. When the current index value IDX_W=n, the address sniffing circuit 110 has recorded addr1=0x0880, addr2=0x1080, addr3=0x1880, ..., addr(n-2)=0x4880, addr(n-1)=0x6080. At this time, the packet preprocessing circuit 114 writes the new memory address 0x7880 into the entry indicated by the index value IDX_W=n (i.e., addrn=0x7880), and updates the index value IDX_W to n+1. If the next new memory address is 0x8080, 0x8080 will be written into the entry indicated by the current index value IDX_W=n+1 (i.e., addr(n+1)=0x8080).

[0043] When the current index value IDX_R=1, the address sniffing circuit 110 will read the entry indicated by the index value IDX_R=1, obtain the memory address set by the packet preprocessing circuit 114 in the sniffing list 109 (i.e., addr1=0x0880) as the current memory address to be monitored, and update the index value IDX_R to 2. When a new memory address to be monitored needs to be set subsequently, the address sniffing circuit 110 reads the memory address set by the packet preprocessing circuit 114 from the entry indicated by the index value IDX_R=2 (i.e., addr1=0x1080) as the memory address to be monitored.

[0044] In some embodiments of the present invention, the network processor 108 (especially the packet preprocessing circuit 114 of the network processor 108) writes to the sniff list 109 through a ring buffer data structure, and the address sniffing circuit 110 reads the sniff list 109 through the data structure of the ring buffer. Figure 3 The data structure of the ring buffer is maintained by an embodiment of the present invention. Figure 1 Schematic diagram of the sniffing list 109 shown. In the process of receiving network packets, the memory 102 not only stores the network packets, but also allocates a storage space as a circular buffer 302 to record the description information of the network packets, that is, the data structure 304 of the circular buffer 302 is used to record the corresponding multiple packet descriptors (packet descriptors) 306 of the multiple network packets, each packet descriptor 306 is used to describe the memory address BUF_ADDR (that is, the write address of the memory 102) allocated to the direct memory access of the corresponding network packet in the memory 102, the packet related information PKT_INFO and the packet length PKT_LEN, wherein the write address BUF_ADDR is the starting address (also the starting address of the header), which can be used as the memory address to be monitored by the address sniffing circuit 110, therefore, the aforementioned sniffing list 109 can be implemented by the write addresses BUF_ADDR of the multiple network packets recorded in the data structure 304 of the circular buffer 302. The circular buffer 302 is maintained by two index values ​​HW_IDX and SW_IDX, wherein the index value HW_IDX is controlled by hardware and is used to indicate the buffer position in the circular buffer 302 corresponding to the currently received network packet, which can be used as the aforementioned index value IDX_R. In addition, the index value SW_IDX is written by software and is used to indicate the buffer position in the circular buffer 302 that stores the memory address currently to be filled by the network processor 108 (especially the packet pre-processing circuit 114 of the network processor 108), which can be used as the aforementioned index value IDX_W.

[0045] When the address sniffing circuit 110 compares the memory address and detects a monitoring hit, the address sniffing circuit 110 triggers the memory synchronization circuit 112 to write the packet content (such as the header) required for packet preprocessing into the memory 104. Figure 4 Schematic diagram of memory synchronization of one embodiment of the present invention. The memory synchronization circuit 112 will only transmit the partial packet content of interest (such as the header) directly to the memory 104. In one embodiment, the storage space of the memory 104 can be pre-divided into multiple storage blocks FSB_1, FSB_2, FSB_3, ..., FSB_N-1, FSB_N, which are respectively used to store multiple partial packet contents corresponding to multiple network packets. The storage blocks FSB_1~FSB_N can have a fixed length. In addition, the total number of storage blocks FSB_1~FSB_N can be equal to the total number of entries in the sniff list 109, that is, the storage blocks in the memory 104 and the entries in the sniff list 109 will be one-to-one. In this way, it can be ensured that the memory address to be monitored by the address sniffing and the partial packet content stored in the memory 104 (such as the header) are one-to-one. As Figure 4 As shown, when a packet is written to the memory (labeled as DRAM in the figure) 102 via direct memory access, the memory synchronization circuit 112 ensures that part of the packet content (such as the header) in the packet is synchronously stored in the storage block in the memory (labeled as SRAM in the figure) 104.

[0046] Figure 5 The flowchart of the network packet processing method of one embodiment of the present invention is shown in FIG. Figure 5 In step S502, the network processor 108 initializes the address sniffing circuit 110. In step S504, the network processor 108 initializes the ring buffer 302 for storing packet descriptors. Since the sniffing list 109 can be maintained by the packet descriptors recorded in the ring buffer 302, the initialization of the ring buffer 302 is also the initialization of the sniffing list 109. In step S506, the direct memory access controller 106 (especially the address sniffing circuit 110 of the direct memory access controller 106) reads the memory address to be monitored from the ring buffer 302 (especially the sniffing list 109 maintained by the ring buffer 302). When the network connection port receives a packet (step S500), the direct memory access controller 106 performs direct memory access on the memory 102 to write the packet into the memory 102. At this time, the address sniffing circuit 110 detects whether at least one write address that the direct memory access controller 106 wants to write into the memory 102 hits the current memory address to be monitored (step S508).

[0047] When the comparison of the memory address indicates a monitoring hit, the address sniffing circuit 110 triggers the memory synchronization circuit 112 to write part of the packet content (e.g., header) to the memory 104. In step S514, the network processor 108 (especially the packet preprocessing circuit 114 of the network processor 108) reads part of the packet content (e.g., header) from the memory 104 to perform packet preprocessing. In step S516, when the packet in the memory 102 is forwarded, the storage space originally occupied by the packet can be released for use by a new packet received by the network connection port. Therefore, the network processor 108 (especially the packet preprocessing circuit 114 of the network processor 108) can fill the new memory address into the ring buffer 302, that is, fill the new memory address into the sniffing list 109 maintained by the ring buffer 302 as the memory address to be monitored later.

[0048] Figure 6 For an embodiment of the present invention, Figure 1 The schematic diagram of the network packet processing device 100 shown in the figure is to perform packet preprocessing to improve packet forwarding performance. Compared with reading the data required by the packet preprocessing circuit 114 from the memory (labeled as DRAM) 102 with higher access delay, the present invention reads the data required by the packet preprocessing circuit 114 from the memory (labeled as SRAM) 104 with lower access delay, which can greatly improve the packet preprocessing performance of the packet preprocessing circuit 114, thereby improving the performance of the subsequent network chip (labeled as NET-IC) 602 in packet forwarding. Figure 6 As shown, when the network device (e.g., a gateway) receives network packets P1, P2, P3, and P4 in sequence, the direct memory access controller (labeled as DMA in the figure) 106 will write the network packets P1, P2, P3, and P4 to the memory 102 in sequence. In addition, with the assistance of the address sniffing circuit 110 and the memory synchronization circuit 112, the partial packet contents (e.g., headers) H1, H2, H3, and H4 of the network packets P1, P2, P3, and P4 will also be written to the memory 102 in sequence. The network processor (labeled as RISC-V) 108 can quickly read the partial packet contents (e.g., headers) H1, H2, H3, and H4 from the memory 102 to perform packet preprocessing of the corresponding network packets P1, P2, P3, and P4, such as determining the forwarding rules of the network packets P1, P2, P3, and P4. According to the forwarding rules obtained by packet preprocessing, the network chip (labeled as NET-IC) 602 performs packet forwarding processing, and reads network packets P1, P2, P3, P4 from the memory 102 through the direct memory access controller 106 and sends them out through the designated network connection port.

[0049] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A network packet processing device, comprising: a first memory; a second memory, wherein an access delay of the second memory is lower than an access delay of the first memory; A direct memory access controller, used for writing the network packet into the first memory, and writing a portion of the packet content in the network packet into the second memory; and The network processor is used for reading the partial packet content from the second memory and performing packet preprocessing of the network packet according to the partial packet content. 2 . The network packet processing device as claimed in claim 1 , wherein the partial packet content comprises a header of the network packet. 3 . The network packet processing device as claimed in claim 1 , wherein the first memory is a dynamic random access memory, and the second memory is a static random access memory.

4. The network packet processing device as claimed in claim 1, wherein the direct memory access controller comprises: memory synchronization circuit; and The address sniffing circuit is used to configure the memory address to be monitored, monitor at least one write address that the direct memory access controller wants to write to the first memory, and trigger the memory synchronization circuit to write the partial packet content to the second memory when the memory address to be monitored hits the at least one write address. 5 . The network packet processing device as claimed in claim 4 , wherein before the network packet is transmitted to the first memory, the memory synchronization circuit first transmits the partial packet content to the second memory.

6. The network packet processing device as claimed in claim 4, wherein when the memory address to be monitored hits the at least one write address, the address sniffing circuit is further used to configure another memory address to be monitored to replace the memory address to be monitored.

7. A network packet processing device as described in claim 4, wherein the network processor is further used to establish and maintain a sniff list; the sniff list has multiple entries, which are respectively used to record multiple memory addresses in the first memory that can be used by multiple network packets; and the address sniffing circuit is further used to obtain the memory address to be monitored from the sniff list.

8. The network packet processing device as claimed in claim 7, wherein the network processor writes to the sniff list through the data structure of the ring buffer, and the address sniffing circuit reads the sniff list through the data structure of the ring buffer.

9. The network packet processing device as claimed in claim 8, wherein the data structure of the ring buffer is used to record a plurality of packet descriptors corresponding to the plurality of network packets, and the sniffing list is maintained by the plurality of packet descriptors.

10. A network packet processing device as described in claim 7, wherein the second memory has a storage space; the storage space is divided into a plurality of storage blocks, respectively used to store a plurality of partial packet contents corresponding to a plurality of network packets; and the total number of entries in the sniffing list is equal to the total number of storage blocks of the storage space.

11. A network packet processing method, comprising: Writing the network packet to the first memory via direct memory access; Writing a portion of the packet content in the network packet to a second memory through direct memory access, wherein an access delay of the second memory is lower than an access delay of the first memory; and The partial packet content is read from the second memory, and packet preprocessing of the network packet is performed according to the partial packet content.

12. The network packet processing method as claimed in claim 11, wherein the partial packet content includes a header of the network packet. 13 . The network packet processing method as claimed in claim 11 , wherein the first memory is a dynamic random access memory, and the second memory is a static random access memory.

14. The network packet processing method of claim 11, wherein the step of writing the portion of the packet content in the network packet to the second memory through direct memory access comprises: Configure the memory address to be monitored; monitoring at least one write address to be written by the direct memory access controller to the first memory; and When the address of the memory to be monitored hits the at least one write address, the partial packet content is written into the second memory. 15 . The network packet processing method as claimed in claim 14 , wherein before the network packet is transmitted to the first memory, the partial packet content is first transmitted to the second memory.

16. The network packet processing method of claim 14, wherein the step of writing the portion of the packet content in the network packet to the second memory through direct memory access further comprises: When the memory address to be monitored hits the at least one write address, another memory address to be monitored is configured to replace the memory address to be monitored.

17. The network packet processing method according to claim 14, further comprising: Build and maintain sniff lists; The sniffing list has a plurality of entries, which are respectively used to record a plurality of memory addresses in the first memory that can be used by a plurality of network packets; and the memory address to be monitored is obtained from the sniffing list.

18. The network packet processing method according to claim 17, further comprising: The sniff list is written to and read from via a ring buffer data structure.

19. The network packet processing method as claimed in claim 18, wherein the data structure of the ring buffer is used to record a plurality of packet descriptors corresponding to the plurality of network packets, and the sniff list is maintained by the plurality of packet descriptors.

20. A network packet processing method as described in claim 17, wherein the second memory has a storage space; the storage space is divided into multiple storage blocks, which are used to store corresponding multiple partial packet contents of multiple network packets respectively; and the total number of entries in the sniffing list is equal to the total number of storage blocks of the storage space.

Images