Digital integrated circuit optimization method and system

Abstract

The invention relates to the technical field of integrated circuit optimization, in particular to a digital integrated circuit optimization method and system. The method comprises the following steps: acquiring an original data set of the integrated circuit; performing circuit function demand analysis on the integrated circuit original data set to generate circuit optimization demand data; carrying out heterogeneous feasibility test on the circuit optimization demand data by utilizing a process-design combined embedding algorithm, and generating a circuit digital integration preprocessing data set; constructing a digital integrated circuit optimization model by using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; therefore, through the digital integration optimization process of the integrated circuit, the problem of insufficient precision of a traditional optimization method in process adaptation and time sequence analysis is solved, and the feasibility and comprehensive performance of circuit optimization are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit optimization, and in particular to a digital integrated circuit optimization method and system. Background Art

[0002] Traditional digital integrated circuit optimization methods mainly rely on static design and optimization models. These methods often show certain limitations when dealing with complex timing problems, parasitic parameters, and cross-domain physical field interactions. At the same time, traditional circuit optimization methods usually ignore the impact of process fluctuations and environmental changes, and fail to effectively integrate these factors for comprehensive optimization, thus affecting the reliability of the final design. In addition, existing circuit optimization systems usually lack effective prediction and management of the aging process of circuit components. Although some design schemes have taken into account the basic aging characteristics of components, in actual use, due to the dynamic changes of circuits in complex environments, the decay mode of components becomes more complex, resulting in the inability of traditional design methods to comprehensively and accurately evaluate and prevent potential failure risks. Therefore, the lack of a systematic aging simulation and evaluation mechanism cannot effectively extend the service life of integrated circuits. In addition, the current technology also has problems with the setting of circuit optimization thresholds. Traditional methods rely on preset optimization thresholds for model comparison. This static optimization strategy fails to fully consider the real-time dynamic changes of actual circuits during operation, resulting in poor accuracy and adaptability when processing large-scale integrated circuits. Summary of the invention

[0003] Based on this, it is necessary to provide a digital integrated circuit optimization method and system to solve at least one of the above technical problems.

[0004] To achieve the above object, a digital integrated circuit optimization method is provided, the method comprising the following steps:

[0005] Step S1: obtaining an original data set of integrated circuits; performing circuit function requirement analysis on the original data set of integrated circuits to generate circuit optimization requirement data; performing heterogeneous feasibility testing on the circuit optimization requirement data using a process-design joint embedding algorithm to generate a circuit digital integration preprocessing data set;

[0006] Step S2: constructing a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; predicting parasitic parameters of the initial integrated circuit optimization model, and injecting a timing analysis engine mechanism optimization to obtain a digital integrated circuit optimization model;

[0007] Step S3: performing optimization simulation test on the digital integrated circuit optimization model to generate digital integrated circuit model optimization data; performing comparative analysis on the digital integrated circuit model optimization data to obtain a preliminary report on digital integrated circuit optimization;

[0008] Step S4: Evaluate the effect of the optimization results based on the preliminary report on the digital integrated circuit optimization and generate a final report on the digital integrated circuit optimization.

[0009] The beneficial effect of the present invention is that by acquiring the original data set of the integrated circuit and performing functional requirement analysis on it, the circuit optimization requirement data is generated, which lays a data foundation for the subsequent optimization work. The heterogeneous feasibility test is carried out by using the process-design joint embedding algorithm, which not only ensures the feasibility of the circuit design under the process conditions, but also provides more accurate input data for further optimization by generating the circuit digital integration preprocessing data set. The circuit digital integration preprocessing data set is used to construct a digital integrated circuit optimization model. In this process, the performance of the circuit model is effectively improved by injecting the parasitic parameter prediction and timing analysis engine mechanism, and the potential problems in timing and power consumption are reduced, so as to obtain a more accurate and feasible circuit optimization model. By optimizing the optimization model and performing simulation tests, not only the actual performance of the model is verified, but also the preliminary report of digital integrated circuit optimization is obtained by comparing and analyzing the optimization data. This process further confirms the effectiveness of the optimization through multi-level data comparison. Through the effect evaluation based on the preliminary optimization report, the final report of digital integrated circuit optimization is generated. The complete evaluation system provides circuit designers with comprehensive feedback on the optimization results, and further guides subsequent design decisions. Through this series of links, the present invention ensures the smoothness of data flow and the accuracy of optimization results, improves the overall efficiency and quality of circuit design, and is particularly important in meeting complex process requirements and optimizing design performance. Therefore, the present invention solves the problem of insufficient accuracy of traditional optimization methods in process adaptation and timing analysis through the digital integrated optimization process of integrated circuits, and improves the feasibility and comprehensive performance of circuit optimization.

[0010] Preferably, step S1 comprises the following steps:

[0011] Step S11: Acquire the integrated circuit original data set;

[0012] Step S12: Cleaning the original data set of the integrated circuit to obtain original cleaned data of the circuit;

[0013] Step S13: performing circuit function requirement analysis on the original circuit cleaning data to generate circuit optimization requirement data;

[0014] Step S14: using a process-design joint embedding algorithm to perform hyperbolic space netlist alignment on the circuit optimization requirement data to generate circuit hyperbolic space alignment data;

[0015] Step S15: Perform heterogeneous feasibility test on the circuit hyperbolic space alignment data, and package the data set to generate a circuit digital integration preprocessing data set.

[0016] The present invention provides a basic data source for subsequent processing and analysis by acquiring the original data set of integrated circuits. In step S12, the original data set of the circuit is cleaned, noise and redundant information are eliminated, and the original cleaned data of the circuit is obtained. This process significantly improves the data quality at the data level and ensures the accuracy of subsequent analysis. By performing circuit function requirement analysis on the original cleaned data of the circuit and generating circuit optimization requirement data, this link provides a clear direction and basis for optimization, thereby ensuring the pertinence and effectiveness of the optimization work. The hyperbolic space netlist is aligned using the process-design joint embedding algorithm to generate circuit hyperbolic space alignment data. This process not only optimizes the spatial layout of the circuit design, but also ensures the compatibility of multiple design parameters in a unified coordinate system, avoiding optimization deviations caused by improper coordinate or space matching during the design process. By performing heterogeneous feasibility tests on the circuit hyperbolic space alignment data and packaging the data set, a circuit digital integration preprocessing data set is generated, providing accurate and efficient input data for subsequent circuit design and optimization. By optimizing this series of steps, the present invention eliminates the problems of difficulty in integrating multi-source data, insufficient data cleaning, inaccurate spatial alignment, etc. in traditional integrated circuit design at the data level, ensures the efficiency and reliability of the data processing process, and thus significantly improves the quality and performance of integrated circuit design.

[0017] Preferably, step S13 comprises the following steps:

[0018] Step S131: acquiring original circuit cleaning data, wherein the original circuit cleaning data includes circuit component cleaning data and circuit transport cleaning data;

[0019] Step S132: performing circuit component parameter design analysis on the circuit component cleaning data to generate circuit component parameter analysis data;

[0020] Step S133: performing a power transmission path structure analysis on the circuit transmission cleaning data to generate circuit power transmission path structure data;

[0021] Step S134: Utilize the circuit component parameter analysis data to perform circuit function requirement analysis on the circuit power transmission path structure data, and generate circuit optimization requirement data.

[0022] The present invention obtains the original circuit cleaning data, including circuit element cleaning data and circuit transmission cleaning data, to provide a clean and accurate data basis for further processing, thereby ensuring the data quality in the design process. The circuit element cleaning data is subjected to circuit element parameter design analysis to generate circuit component parameter analysis data. This process conducts in-depth mining of the key parameters of the circuit elements, so that the functional characteristics and optimization requirements of each element are fully analyzed, providing accurate data information for subsequent optimization. The circuit transmission cleaning data is subjected to a transmission path structure analysis to generate circuit transmission path structure data. This analysis optimizes the path layout in the circuit design by comprehensively deconstructing the transmission path in the circuit, thereby providing the necessary structural information for the efficient realization of the circuit function. The circuit component parameter analysis data is integrated with the circuit transmission path structure data, and a circuit function requirement analysis is performed to generate circuit optimization requirement data. This analysis not only integrates the requirements of components and transmission paths, but also ensures that the subsequent circuit optimization work can accurately match the design goals through a comprehensive understanding of the functional requirements. Through this series of precise data processing and analysis, the present invention fundamentally solves the problem of independent processing of various types of data and lack of systematic integration in traditional circuit design, improves the compatibility and optimization potential of various data in circuit design, and provides data guarantee for efficient integrated circuit optimization.

[0023] Preferably, step S2 comprises the following steps:

[0024] Step S21: obtaining circuit RC parasitic parameters and real-time circuit timing data, wherein the circuit RC parasitic parameters include RC interconnect resistance parameter data and RC proximity effect coupling capacitance data;

[0025] Step S22: constructing a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model;

[0026] Step S23: using the RC interconnect resistance parameter data to perform thermal-electrical-mechanical coupling correction on the initial integrated circuit optimization model to generate a digital integrated circuit multi-physics field correction model;

[0027] Step S24: using RC proximity effect coupling capacitance data to perform adversarial robustness enhancement processing on the digital integrated circuit multi-physics field correction model to generate a digital integrated circuit anti-disturbance model;

[0028] Step S25: dynamically recalibrate the critical path of the digital integrated circuit anti-disturbance model to generate a digital integrated circuit recalibration path; perform clock domain awareness constraints on the digital integrated circuit recalibration path to generate digital integrated circuit clock constraint rules; adjust the digital circuit closure priority of the digital integrated circuit recalibration path based on the digital integrated circuit clock constraint rules and real-time circuit timing data to obtain a digital integrated circuit optimization model.

[0029] The present invention obtains circuit RC parasitic parameters and real-time circuit timing data, wherein RC interconnection resistance parameter data and RC proximity effect coupling capacitance data provide basic data for subsequent multi-physical field optimization, ensuring that the resistance and capacitance effects in the circuit design can be accurately reflected in the model. The digital integrated circuit optimization model is constructed using the circuit digital integration preprocessing data set, and an initial integrated circuit optimization model is generated, laying a solid foundation for subsequent optimization work. The initial integrated circuit optimization model is corrected for thermal-electric-mechanical coupling using RC interconnection resistance parameter data, and multi-dimensional coupling optimization from thermal effect, current distribution to mechanical properties is performed to ensure the stability and reliability of the circuit under different working conditions, and a multi-physical field correction model for digital integrated circuits is generated. By using RC proximity effect coupling capacitance data, the multi-physical field correction model is enhanced for antagonistic robustness, and an anti-disturbance model for digital integrated circuits is generated. In this process, the enhancement of anti-disturbance capability enables the circuit to effectively resist external environmental changes and internal design deviations, thereby improving the robustness and stability of the circuit. By dynamically recalibrating the key paths of the digital integrated circuit anti-disturbance model, performing clock domain perception constraints, and adjusting the closure priority in combination with real-time circuit timing data, the precise control and efficient operation of the circuit timing are ensured, and finally the digital integrated circuit optimization model is obtained. The entire process overcomes the problems of imperfect multi-physical field coupling and insufficient timing optimization in traditional circuit design through the effective integration and optimization of multi-source data, ensuring the efficient operation and optimization accuracy of circuit design in complex environments.

[0030] Preferably, step S23 includes the following steps:

[0031] Step S231: extracting current density and temperature gradient from the initial integrated circuit optimization model using RC interconnect resistance parameter data, and generating integrated digital circuit current density data and integrated digital circuit temperature gradient data;

[0032] Step S232: dividing the integrated digital circuit current density data and the integrated digital circuit temperature gradient data into power consumption regions to generate digital integrated circuit power consumption regions;

[0033] Step S233: constructing an electric-thermal coupling equation for the power consumption area of ​​the digital integrated circuit to generate an electric-thermal coupling equation for the digital integrated circuit; constructing a thermal-mechanical coupling equation for the power consumption area of ​​the digital integrated circuit to generate a thermal-mechanical coupling equation for the digital integrated circuit;

[0034] Step S234: Perform nonlinear parameter cross-iteration optimization on the initial integrated circuit optimization model using the digital integrated circuit electrical-thermal coupling equation and the digital integrated circuit thermal-mechanical coupling equation to generate a digital integrated circuit multi-physical field correction model.

[0035] The present invention extracts current density and temperature gradient data by using RC interconnection resistance parameter data, which provides accurate basic data for subsequent power consumption analysis and thermal effect modeling. The current density data reveals the distribution characteristics of the current in the circuit, while the temperature gradient data provides key information for thermal effect analysis, thereby laying a data foundation for the thermal management and current distribution optimization of the circuit. By dividing the power consumption area of ​​the current density data and temperature gradient data of the integrated digital circuit, the power consumption area of ​​the digital integrated circuit is generated. This process can help identify the areas with higher power consumption in the circuit, provide accurate target areas for subsequent optimization, and ensure that high power consumption areas can be effectively identified during the design process to reduce energy loss. By constructing the electric-thermal coupling equation and the thermal-mechanical coupling equation, the power consumption area of ​​the digital integrated circuit is refined and modeled, so that the thermal effect and mechanical response of the circuit can be more accurately coupled and analyzed, so that the influence of the temperature change of the circuit in actual operation on its mechanical stability can be better evaluated, and the thermal management and mechanical structure design of the circuit can be optimized. By performing nonlinear parameter cross-iteration optimization on the electric-thermal coupling equation and the thermal-mechanical coupling equation, a multi-physics field correction model for digital integrated circuits is obtained. This model accurately reflects the comprehensive behavior of the circuit in a multi-dimensional environment through cross-coupling processing of multiple physical fields, and improves the overall robustness and stability of the design. Through this series of optimization steps, the present invention solves the optimization problems of circuits in multiple fields such as current, temperature, and mechanics from a data level, enhances the global considerations and multi-physics field coordination of circuit design, and enables it to better cope with performance requirements in complex environments in practical applications.

[0036] Preferably, step S24 includes the following steps:

[0037] Step S241: using RC proximity effect coupling capacitance data to perform process fluctuation range perturbation on the digital integrated circuit multi-physics field correction model to generate digital integrated circuit process range perturbation data;

[0038] Step S242: using the RC proximity effect coupling capacitance data to perform temperature fluctuation range perturbation on the digital integrated circuit multi-physics field correction model to generate digital integrated circuit temperature range perturbation data;

[0039] Step S243: aligning the digital integrated circuit process range disturbance data and the digital integrated circuit temperature range disturbance data by model node topology to generate digital integrated circuit physical rule disturbance data;

[0040] Step S244: construct physical constraint adversarial samples for the physical rule disturbance data of the digital integrated circuit, and use clock tree robustness training to generate a digital integrated circuit anti-disturbance model.

[0041] The present invention uses RC proximity effect coupling capacitor data to perform process fluctuation range perturbation on the digital integrated circuit multi-physics field correction model, and generates digital integrated circuit process range perturbation data. This process can simulate the impact of process fluctuation on circuit design, and provide quantized perturbation data for potential process errors in circuit design, thereby ensuring the fault tolerance and stability of circuit design. The temperature fluctuation range perturbation of the digital integrated circuit multi-physics field correction model is performed using RC proximity effect coupling capacitor data, and digital integrated circuit temperature range perturbation data is generated. This operation takes into account the impact of temperature fluctuation on circuit performance, and can effectively predict the performance changes of the circuit under different working environment temperatures, ensuring the stability and reliability of the circuit under extreme environmental conditions. The process range perturbation data and the temperature range perturbation data are further aligned with the model node topology, and the digital integrated circuit physical rule perturbation data is generated. Through topological alignment, this process integrates multiple perturbation data into a unified circuit node model, thereby optimizing the design matching degree under different physical environments, and providing accurate data support for further optimization. Physical constraint adversarial sample construction is performed on the physical rule perturbation data, and clock tree robustness training is used to generate a digital integrated circuit anti-disturbance model. Through adversarial sample training, the model enables the circuit to effectively cope with process fluctuations, temperature fluctuations and other uncertain factors, improving the robustness and anti-interference ability of the circuit design. Throughout the process, the generation and optimization of disturbance data ensure that digital integrated circuits can still maintain high performance and high stability under complex and changeable working conditions, thus solving the problems of poor adaptability to environmental factors and insufficient anti-interference in traditional circuit design.

[0042] Preferably, step S3 comprises the following steps:

[0043] Step S31: obtaining initial integrated circuit data;

[0044] Step S32: performing optimization simulation test on the digital integrated circuit optimization model to generate digital integrated circuit model optimization data;

[0045] Step S33: using a preset circuit optimization threshold to compare and analyze the digital integrated circuit model optimization data and the initial integrated circuit data, and generating a preliminary digital integrated circuit optimization report.

[0046] The present invention provides a basis for subsequent optimization by obtaining initial integrated circuit data, ensures that the initial parameters of each component, connection and functional module in the circuit design are fully mastered, and provides original information support for the implementation of optimization. By optimizing the digital integrated circuit optimization model and performing simulation tests, digital integrated circuit model optimization data is generated. In this process, the actual working state of the simulated circuit is simulated by simulation tests, and the influence of different optimization strategies on the circuit performance is evaluated, thereby generating detailed model optimization data. The data not only includes the working parameters of the circuit, but also covers the performance changes presented by the circuit after optimization, providing a data basis for further analysis and improvement of subsequent optimization. By comparing and analyzing the digital integrated circuit model optimization data with the initial integrated circuit data, and using a preset circuit optimization threshold, a preliminary report on digital integrated circuit optimization is generated. Through this comparative analysis, the performance improvement of the circuit after optimization compared to the initial state can be clearly identified, ensuring that the optimization measures have higher performance and efficiency while meeting the design requirements. Through comparison and analysis at the data level, the effect of the optimization process is quantified and further verified, making the entire optimization process more transparent and controllable, and being able to effectively identify potential optimization bottlenecks. On the whole, the present invention not only provides a theoretical basis and data support for circuit optimization through systematic optimization simulation testing and data comparison, but also significantly improves the overall performance and optimization efficiency of circuit design, and solves the problems of insufficient precision and complex tuning in the traditional optimization process.

[0047] Preferably, step S32 includes the following steps:

[0048] Step S321: when the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is less than or equal to the preset circuit optimization threshold, the digital integrated circuit model optimization data is detected for abnormal fluctuation range, and potential optimization nodes are marked to generate digital integrated circuit potential optimization node data; the digital integrated circuit potential optimization node data is processed by neural differential dynamic clearing to obtain digital integrated circuit model optimization data;

[0049] Step S322: When the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is greater than a preset circuit optimization threshold, the immediate digital integrated circuit optimization operation is stopped.

[0050] The present invention first detects the abnormal fluctuation range of the optimization data when the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is less than or equal to the preset circuit optimization threshold. This detection step can timely identify the potential abnormal fluctuations in the circuit design by analyzing the data fluctuations in the optimization process, thereby preventing the unstable factors or performance degradation caused by the optimization process. On this basis, the system marks the potential optimization nodes, which are the parts that have problems or need further adjustment in the optimization process, and provides targeted optimization directions. The neural differential dynamic clearing process is performed on the potential optimization node data of the digital integrated circuit. Through this process, irrelevant or redundant information in the optimization node is cleared, thereby retaining more accurate optimization data, so that the optimization data finally obtained is more in line with the actual needs of the circuit, and the accuracy and reliability of the optimization effect are improved. When the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is greater than the preset circuit optimization threshold, the system automatically stops the optimization operation. This mechanism effectively avoids the waste of resources and over-adjustment of circuit performance caused by over-optimization, ensures the efficiency and rationality of the optimization process, and ensures that the circuit optimization does not exceed the established design goals, thereby improving the effectiveness of the overall optimization and the rational use of resources. Through these data-driven steps, the present invention effectively solves the problems of inaccurate identification of optimization nodes, over-optimization or under-optimization in traditional circuit optimization, and significantly improves the accuracy, efficiency and robustness of circuit optimization.

[0051] Preferably, step S32 includes the following steps:

[0052] Step S41: acquiring digital integrated circuit component historical data, wherein the digital integrated circuit component historical data includes circuit component maintenance historical data and circuit component service life historical data;

[0053] Step S42: performing hotspot clustering and vulnerable area identification on the circuit component maintenance history data to generate circuit component vulnerable areas; performing regional optimization comparative analysis on the circuit component vulnerable areas and the preliminary digital integrated circuit optimization report to generate digital integrated circuit maintenance comparative data;

[0054] Step S43: Perform digital twin aging simulation on the historical data of the service life of circuit components to generate circuit component aging simulation data; perform risk probability assessment on the circuit component aging simulation data and the preliminary report on digital integrated circuit optimization to generate digital integrated circuit aging assessment data;

[0055] Step S44: Evaluate the optimization effect of the digital integrated circuit maintenance comparison data and the digital integrated circuit aging assessment data to generate a final report on the digital integrated circuit optimization.

[0056] The present invention provides a rich data basis for subsequent analysis by acquiring historical data of digital integrated circuit components, including historical data of circuit component maintenance and historical data of circuit component service life. By performing hot spot clustering analysis on the historical data of circuit component maintenance, the vulnerable areas of the circuit components are identified. This process can accurately locate the vulnerable parts of the circuit, and generate maintenance comparison data by comparing and analyzing with the preliminary report of digital integrated circuit optimization, providing data support for subsequent maintenance and optimization. Digital twin aging simulation is performed using the historical data of the service life of the circuit components to simulate the aging process of the components and generate corresponding simulation data. By performing risk probability assessment on the aging simulation data and the preliminary report of optimization, the aging assessment data of the circuit components is further obtained. This process can foresee the impact of component aging on circuit performance in advance and provide a prediction basis for subsequent maintenance and replacement. Finally, the digital integrated circuit maintenance comparison data and aging assessment data are subjected to comprehensive optimization result effect evaluation to generate a final optimization report. Through this series of steps, the data is continuously refined and improved in the interaction and feedback at different levels, and the accuracy, efficiency and long-term performance reliability of the overall circuit optimization process are finally improved. Through data-driven all-round analysis, the present invention provides a more accurate and scientific solution for circuit maintenance and aging prediction, significantly improving the stability and economy of integrated circuits in long-term use.

[0057] In this specification, a digital integrated circuit optimization system is provided, which is used to perform the above-mentioned digital integrated circuit optimization method. The digital integrated circuit optimization system includes:

[0058] The data integration and demand analysis module is used to obtain the original data set of integrated circuits; perform circuit function demand analysis on the original data set of integrated circuits to generate circuit optimization demand data; use the process-design joint embedding algorithm to perform heterogeneous feasibility tests on the circuit optimization demand data to generate a circuit digital integration preprocessing data set;

[0059] The model building and optimization module is used to build a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; perform parasitic parameter prediction on the initial integrated circuit optimization model, and inject the timing analysis engine mechanism optimization to obtain a digital integrated circuit optimization model;

[0060] The optimization simulation and comparative analysis module is used to perform optimization simulation tests on the digital integrated circuit optimization model and generate digital integrated circuit model optimization data; perform comparative analysis on the digital integrated circuit model optimization data and obtain a preliminary report on the digital integrated circuit optimization;

[0061] The effect evaluation and report generation module is used to evaluate the effect of optimization results based on the preliminary report of digital integrated circuit optimization and generate the final report of digital integrated circuit optimization.

[0062] The beneficial effect of the present invention is that by acquiring the original data set of the integrated circuit and performing functional requirement analysis on it, the circuit optimization requirement data is generated, which lays a data foundation for the subsequent optimization work. The heterogeneous feasibility test is carried out by using the process-design joint embedding algorithm, which not only ensures the feasibility of the circuit design under the process conditions, but also provides more accurate input data for further optimization by generating the circuit digital integration preprocessing data set. The circuit digital integration preprocessing data set is used to construct a digital integrated circuit optimization model. In this process, the performance of the circuit model is effectively improved by injecting the parasitic parameter prediction and timing analysis engine mechanism, and the potential problems in timing and power consumption are reduced, so as to obtain a more accurate and feasible circuit optimization model. By optimizing the optimization model and performing simulation tests, not only the actual performance of the model is verified, but also the preliminary report of digital integrated circuit optimization is obtained by comparing and analyzing the optimization data. This process further confirms the effectiveness of the optimization through multi-level data comparison. Through the effect evaluation based on the preliminary optimization report, the final report of digital integrated circuit optimization is generated. The complete evaluation system provides circuit designers with comprehensive feedback on the optimization results, and further guides subsequent design decisions. Through this series of links, the present invention ensures the smoothness of data flow and the accuracy of optimization results, improves the overall efficiency and quality of circuit design, and is particularly important in meeting complex process requirements and optimizing design performance. Therefore, the present invention solves the problem of insufficient accuracy of traditional optimization methods in process adaptation and timing analysis through the digital integrated optimization process of integrated circuits, and improves the feasibility and comprehensive performance of circuit optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram of a process flow of a digital integrated circuit optimization method;

[0064] Figure 2 for Figure 1 Detailed implementation steps of step S2 in the flowchart;

[0065] Figure 3 for Figure 1 Detailed implementation steps of step S3 in FIG.

[0066] Figure 4 for Figure 1 Detailed implementation steps of step S4 in FIG.

[0067] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0068] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0069] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0070] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0071] To achieve this, please refer to Figures 1 to 4 , a digital integrated circuit optimization method, the method comprising the following steps:

[0072] Step S1: obtaining an original data set of integrated circuits; performing circuit function requirement analysis on the original data set of integrated circuits to generate circuit optimization requirement data; performing heterogeneous feasibility testing on the circuit optimization requirement data using a process-design joint embedding algorithm to generate a circuit digital integration preprocessing data set;

[0073] Step S2: constructing a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; predicting parasitic parameters of the initial integrated circuit optimization model, and injecting a timing analysis engine mechanism optimization to obtain a digital integrated circuit optimization model;

[0074] Step S3: performing optimization simulation test on the digital integrated circuit optimization model to generate digital integrated circuit model optimization data; performing comparative analysis on the digital integrated circuit model optimization data to obtain a preliminary report on digital integrated circuit optimization;

[0075] Step S4: Evaluate the effect of the optimization results based on the preliminary report on the digital integrated circuit optimization and generate a final report on the digital integrated circuit optimization.

[0076] The beneficial effect of the present invention is that by acquiring the original data set of the integrated circuit and performing functional requirement analysis on it, the circuit optimization requirement data is generated, which lays a data foundation for the subsequent optimization work. The heterogeneous feasibility test is carried out by using the process-design joint embedding algorithm, which not only ensures the feasibility of the circuit design under the process conditions, but also provides more accurate input data for further optimization by generating the circuit digital integration preprocessing data set. The circuit digital integration preprocessing data set is used to construct a digital integrated circuit optimization model. In this process, the performance of the circuit model is effectively improved by injecting the parasitic parameter prediction and timing analysis engine mechanism, and the potential problems in timing and power consumption are reduced, so as to obtain a more accurate and feasible circuit optimization model. By optimizing the optimization model and performing simulation tests, not only the actual performance of the model is verified, but also the preliminary report of digital integrated circuit optimization is obtained by comparing and analyzing the optimization data. This process further confirms the effectiveness of the optimization through multi-level data comparison. Through the effect evaluation based on the preliminary optimization report, the final report of digital integrated circuit optimization is generated. The complete evaluation system provides circuit designers with comprehensive feedback on the optimization results, and further guides subsequent design decisions. Through this series of links, the present invention ensures the smoothness of data flow and the accuracy of optimization results, improves the overall efficiency and quality of circuit design, and is particularly important in meeting complex process requirements and optimizing design performance. Therefore, the present invention solves the problem of insufficient accuracy of traditional optimization methods in process adaptation and timing analysis through the digital integrated optimization process of integrated circuits, and improves the feasibility and comprehensive performance of circuit optimization.

[0077] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a schematic diagram of a step flow chart of a digital integrated circuit optimization method of the present invention. In this example, the digital integrated circuit optimization method includes the following steps:

[0078] Step S1: obtaining an original data set of integrated circuits; performing circuit function requirement analysis on the original data set of integrated circuits to generate circuit optimization requirement data; performing heterogeneous feasibility testing on the circuit optimization requirement data using a process-design joint embedding algorithm to generate a circuit digital integration preprocessing data set;

[0079] In the embodiment of the present invention, by acquiring the original data set of the integrated circuit, comprehensive data collection is performed for the design and functional requirements of the integrated circuit, and these data include but are not limited to the structural parameters, electrical characteristics, process requirements and other information of the circuit. By analyzing the circuit functional requirements of these original data, the target to be optimized in the circuit system can be identified and converted into circuit optimization demand data. The key to this step is to use advanced data mining and analysis technology to extract features closely related to circuit function optimization from the original circuit data, and generate specific optimization demand data. This process not only relies on big data technology, but also needs to accurately define the functional requirements in combination with domain knowledge. In the next step, the process-design joint embedding algorithm is used to process the circuit optimization demand data so as to find the optimal balance between complex circuit design and process constraints. The role of the process-design joint embedding algorithm is to highly couple the circuit design requirements and the manufacturing process requirements, and on this basis, perform heterogeneous feasibility tests to ensure that the optimization scheme is feasible under different process conditions. At the data level, this algorithm embeds the design parameters and process parameters into the same data space for joint optimization, thereby achieving efficient matching and verification in multiple dimensions, avoiding the influence of the constraints of a single process or design on the optimization results. Through this technical means, it is possible to effectively screen out optimization solutions that are feasible in the actual manufacturing process, and generate a circuit digital integration preprocessing data set to provide strong data support for the subsequent circuit optimization process.

[0080] Step S2: constructing a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; predicting parasitic parameters of the initial integrated circuit optimization model, and injecting a timing analysis engine mechanism optimization to obtain a digital integrated circuit optimization model;

[0081] In the embodiment of the present invention, a preliminary circuit optimization model is constructed by an algorithm model. The model reflects the association between circuit design and optimization requirements, and provides a preliminary framework for subsequent optimization. The construction process of the initial integrated circuit optimization model relies on a variety of technical means such as machine learning and numerical optimization. These methods establish an optimal solution approximation in the design space by training and fitting existing data. After obtaining the preliminary optimization model, the next key step is to predict the parasitic parameters in the model. Parasitic parameters such as parasitic resistance and capacitance have an important impact on circuit performance in integrated circuit design, so accurately predicting these parasitic parameters is the key to optimizing circuit performance. By analyzing factors such as circuit layout, component parameters and working environment, and using regression analysis and numerical simulation technology in machine learning, parasitic parameters can be accurately predicted. At this time, the influence of all parasitic effects is incorporated into the optimization model, further improving the accuracy of the model. In the model optimization process, injecting a timing analysis engine mechanism is an important link. The timing analysis engine can analyze based on the timing characteristics of the circuit such as the operating frequency and delay, and perform timing optimization in the model. By dynamically adjusting the timing delay of each node in the circuit, the timing analysis engine can effectively eliminate the performance degradation caused by the delay and ensure the stability and reliability of the circuit under high-frequency working conditions. Ultimately, through parasitic parameter prediction and timing analysis optimization, the digital integrated circuit optimization model obtained is more accurate, can better meet design requirements and adapt to actual process limitations, and lay a solid data foundation for further optimization of circuit design.

[0082] Step S3: performing optimization simulation test on the digital integrated circuit optimization model to generate digital integrated circuit model optimization data; performing comparative analysis on the digital integrated circuit model optimization data to obtain a preliminary report on digital integrated circuit optimization;

[0083] In the embodiment of the present invention, the effectiveness of the performance and design parameters of the optimization model preliminarily constructed is verified by system simulation. The simulation test relies on efficient numerical calculation and simulation technology, such as time domain simulation, frequency domain simulation and multi-physics field coupling simulation. By introducing fine electrical characteristic models, thermal models and mechanical models, the simulation can comprehensively evaluate the response of the circuit under different working conditions, such as power consumption, delay, thermal effect, signal integrity, etc. This process mainly uses numerical simulation software platforms (such as Cadence, Synopsys, etc.) for simulation analysis to obtain key performance indicators (KPIs) related to the optimization target, thereby generating digital integrated circuit model optimization data. Secondly, based on the obtained simulation results, the digital integrated circuit model optimization data is compared and analyzed, mainly by comparing the simulation optimization results with the initial design requirements, so as to evaluate whether the optimized circuit design reaches the expected performance target. The data comparison and analysis methods include statistical analysis, error evaluation and sensitivity analysis, etc., by comparing the deviation between the simulation test data and the target value, quantifying the optimization effect, and identifying the advantages and disadvantages of the model. Further, based on the results of the comparative analysis, a preliminary report on the optimization of the digital integrated circuit is generated.

[0084] Step S4: Evaluate the effect of the optimization results based on the preliminary report on the digital integrated circuit optimization and generate a final report on the digital integrated circuit optimization.

[0085] In an embodiment of the present invention, an in-depth effect evaluation is performed on each data index in the preliminary optimization report, so as to quantitatively analyze the overall effect of circuit optimization. This process first requires comparing the various optimization parameters and performance indicators (such as power consumption, delay, signal integrity, thermal effect, etc.) contained in the preliminary report with the preset optimization target, and evaluating the impact of various design decisions on the overall performance of the circuit during the optimization process through statistical methods and error analysis. At the data processing level, this evaluation work is usually achieved by establishing a multi-dimensional performance evaluation model, which includes but is not limited to linear regression analysis, sensitivity analysis, Monte Carlo simulation, sensitivity evaluation and other methods to quantify the contribution of various indicators to the overall performance of the circuit. By comparing the performance of different optimization schemes, data evaluation can reveal which optimization strategies are effective and which strategies fail to achieve the expected results, and further optimize the solution. This step also includes a comprehensive evaluation of the reliability, stability and scalability of the circuit design to ensure that the design not only performs well under the current constraints, but also can adapt to future process changes and environmental changes. Finally, based on these data analysis results, a final report on the optimization of digital integrated circuits is generated.

[0086] Preferably, step S1 comprises the following steps:

[0087] Step S11: Acquire the integrated circuit original data set;

[0088] Step S12: Cleaning the original data set of the integrated circuit to obtain original cleaned data of the circuit;

[0089] Step S13: performing circuit function requirement analysis on the original circuit cleaning data to generate circuit optimization requirement data;

[0090] Step S14: using a process-design joint embedding algorithm to perform hyperbolic space netlist alignment on the circuit optimization requirement data to generate circuit hyperbolic space alignment data;

[0091] Step S15: Perform heterogeneous feasibility test on the circuit hyperbolic space alignment data, and package the data set to generate a circuit digital integration preprocessing data set.

[0092] In the embodiment of the present invention, by acquiring the original data set of the integrated circuit, the various circuit parameters, design data, functional requirements and process information contained therein are systematically sorted. Then, the original data of the circuit is cleaned, mainly using technical means such as outlier detection, missing data filling, noise filtering, etc., to eliminate interference factors and ensure the accuracy and consistency of the data. The cleaned data is used for subsequent circuit functional requirements analysis. In this process, rule-based reasoning or data-driven models (such as decision trees, regression analysis, etc.) are usually used to extract the performance requirements and optimization goals of the circuit from the cleaned data to generate circuit optimization requirements data. The circuit optimization requirements data is aligned in hyperbolic space using a process-design joint embedding algorithm. This process maps design data of different sources, formats or attributes into a unified mathematical space, and usually uses geometric or topological methods to spatially embed the design drawings of the circuit, thereby reducing the distance error between data through the characteristics of the hyperbolic space, and ensuring data consistency and alignment between different design levels or models. The generated circuit hyperbolic space alignment data further supports heterogeneous feasibility testing. This link verifies whether the optimization requirements can be achieved under multiple design and process conditions by calculating the similarity between different data sources.

[0093] Preferably, step S13 includes the following steps:

[0094] Step S131: acquiring original circuit cleaning data, wherein the original circuit cleaning data includes circuit component cleaning data and circuit transport cleaning data;

[0095] Step S132: performing circuit component parameter design analysis on the circuit component cleaning data to generate circuit component parameter analysis data;

[0096] Step S133: performing a power transmission path structure analysis on the circuit transmission cleaning data to generate circuit power transmission path structure data;

[0097] Step S134: Utilize the circuit component parameter analysis data to perform circuit function requirement analysis on the circuit power transmission path structure data, and generate circuit optimization requirement data.

[0098] In an embodiment of the present invention, by obtaining the original cleaning data of the circuit, the data includes circuit element cleaning data and circuit transmission cleaning data. The circuit element cleaning data mainly includes parameter information of various components in the circuit (such as resistance, capacitance, inductance, etc.), while the circuit transmission cleaning data is the path information of the circuit connection part, including the transmission path of the electrical signal, power loss, and impedance change. By collecting these cleaned original data, accurate and consistent basic data can be provided for the subsequent analysis of the circuit. Subsequently, the circuit element cleaning data is subjected to circuit element parameter design analysis, usually using parametric modeling technology and engineering optimization methods (such as design space exploration, sensitivity analysis, etc.), and the design parameters of the circuit elements (such as rated current, load conditions, etc.) are deeply analyzed to generate circuit component parameter analysis data, which provide detailed guidance for the actual working conditions, performance and optimization direction of the components. The transmission path structure analysis of the circuit transmission cleaning data is mainly carried out through topological analysis, path optimization algorithm and network analysis technology to identify the key transmission paths, power flow directions and bottleneck areas in the circuit. This process not only considers the circuit connection at the physical level, but also factors such as signal transmission delay, power consumption, and noise. Through these analyses, circuit transmission path structure data is generated to further reveal the efficiency and stability of current transmission within the circuit. Finally, circuit component parameter analysis data and circuit transmission path structure data are used to perform circuit functional requirements analysis. Model-based analysis (such as circuit simulation or multi-objective optimization methods) is usually used to evaluate the functional performance of each part of the circuit under actual working conditions, thereby generating circuit optimization requirements data.

[0099] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes:

[0100] Step S21: obtaining circuit RC parasitic parameters and real-time circuit timing data, wherein the circuit RC parasitic parameters include RC interconnect resistance parameter data and RC proximity effect coupling capacitance data;

[0101] Step S22: constructing a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model;

[0102] Step S23: using the RC interconnect resistance parameter data to perform thermal-electrical-mechanical coupling correction on the initial integrated circuit optimization model to generate a digital integrated circuit multi-physics field correction model;

[0103] Step S24: using RC proximity effect coupling capacitance data to perform adversarial robustness enhancement processing on the digital integrated circuit multi-physics field correction model to generate a digital integrated circuit anti-disturbance model;

[0104] Step S25: dynamically recalibrate the critical path of the digital integrated circuit anti-disturbance model to generate a digital integrated circuit recalibration path; perform clock domain awareness constraints on the digital integrated circuit recalibration path to generate digital integrated circuit clock constraint rules; adjust the digital circuit closure priority of the digital integrated circuit recalibration path based on the digital integrated circuit clock constraint rules and real-time circuit timing data to obtain a digital integrated circuit optimization model.

[0105] In an embodiment of the present invention, by obtaining the circuit RC parasitic parameters and real-time circuit timing data, the basic data includes RC interconnect resistance parameters and RC proximity effect coupling capacitance data. RC parasitic parameters directly affect the signal transmission characteristics of the circuit, especially signal delay, power consumption and current distribution, and real-time circuit timing data provides dynamic behavior information of the circuit under operation. These data provide a crucial basis for subsequent optimization work and can reflect the response and performance of the circuit in actual use. By using the circuit digital integration preprocessing data set to construct a digital integrated circuit optimization model, various functional requirements and performance indicators of the integrated circuit are modeled with the help of advanced algorithms (such as machine learning, data mining, etc.), and an initial integrated circuit optimization model is generated. The initial integrated circuit optimization model is corrected for thermal-electric-mechanical coupling using RC interconnect resistance parameter data. The key technical means of this step lies in multi-physics field simulation. By combining thermal effects, electrical effects and mechanical effects into a unified correction framework, the comprehensive performance of the circuit under actual working conditions can be accurately evaluated. This multi-physics field coupling correction method effectively improves the accuracy and reliability of the circuit model, enabling it to adapt to more complex working environments. RC proximity effect coupling capacitance data is used to enhance the adversarial robustness of the multi-physics field correction model of digital integrated circuits. This process usually introduces perturbation data and adopts adversarial training methods to enhance the fault tolerance of the circuit model to various external perturbations and noises, ensuring that the circuit can operate stably in different environments. Focusing on further improving the optimization model of digital integrated circuits, firstly, the key paths in the perturbation model are re-evaluated and adjusted through the key path dynamic recalibration technology to optimize the signal transmission path, reduce latency and improve power efficiency. Then, the perception constraints of the clock domain are optimized. In this process, the closure priority is adjusted using real-time circuit timing data to ensure the synchronization of the clock signal and the accuracy of the circuit timing.

[0106] Preferably, step S23 includes the following steps:

[0107] Step S231: extracting current density and temperature gradient from the initial integrated circuit optimization model using RC interconnect resistance parameter data, and generating integrated digital circuit current density data and integrated digital circuit temperature gradient data;

[0108] Step S232: dividing the integrated digital circuit current density data and the integrated digital circuit temperature gradient data into power consumption regions to generate digital integrated circuit power consumption regions;

[0109] Step S233: constructing an electric-thermal coupling equation for the power consumption area of ​​the digital integrated circuit to generate an electric-thermal coupling equation for the digital integrated circuit; constructing a thermal-mechanical coupling equation for the power consumption area of ​​the digital integrated circuit to generate a thermal-mechanical coupling equation for the digital integrated circuit;

[0110] Step S234: Perform nonlinear parameter cross-iteration optimization on the initial integrated circuit optimization model using the digital integrated circuit electrical-thermal coupling equation and the digital integrated circuit thermal-mechanical coupling equation to generate a digital integrated circuit multi-physical field correction model.

[0111] In an embodiment of the present invention, the current density and temperature gradient data in the initial integrated circuit optimization model are extracted using RC interconnect resistance parameter data. RC interconnect resistance parameters are key physical parameters in circuit design, which directly affect the distribution and transmission efficiency of current. By extracting current density and temperature gradient data, the current flow characteristics and heat conduction characteristics of the circuit in the working state can be obtained, and these data provide a basis for subsequent power consumption analysis and thermal management. The current density data reflects the spatial distribution of the current in the circuit, while the temperature gradient reveals the distribution of thermal effects caused by current flow and power consumption in the circuit. The current density data and the temperature gradient data are divided into power consumption areas to generate digital integrated circuit power consumption areas. The division of power consumption areas is based on the spatial variation of current density and temperature gradient. By analyzing these data, the areas of heat concentration and energy loss in the circuit can be determined, and then these areas can be optimized to achieve energy efficiency improvement. This technical means uses data mining and spatial analysis algorithms to make the identification of power consumption areas more accurate, thereby providing a basis for subsequent thermal management and optimization. By constructing electrical-thermal coupling equations and thermal-mechanical coupling equations, a deeper level of physical modeling of the power consumption area of ​​the digital integrated circuit is performed. The electro-thermal coupling equation describes the interaction between current flow and thermal effects, while the thermal-mechanical coupling equation further considers the impact of thermal effects on the mechanical behavior of the circuit. By establishing these two types of coupling equations, the multi-physics field behavior of the circuit in actual operation can be simulated and predicted more accurately, thereby enhancing the adaptability and accuracy of the model to actual environmental changes. The construction of these equations usually relies on high-order numerical methods, such as finite element analysis and multi-physics field simulation technology. The electro-thermal coupling equation and the thermal-mechanical coupling equation are applied to the initial integrated circuit optimization model, and nonlinear parameter cross-iteration optimization is performed. The optimization process is carried out in a multiple-iteration manner, and each iteration optimizes the circuit design parameters under the influence of current density, temperature gradient, and thermal-mechanical coupling effects to make the model optimal in terms of thermal management, power consumption, and mechanical response. This optimization process uses advanced algorithms (such as adaptive optimization, genetic algorithms, etc.) to effectively handle multi-variable, multi-constrained nonlinear problems, thereby realizing multi-physics field correction of digital integrated circuits, ensuring that the optimized circuit not only has excellent electrical performance, but also can operate stably under thermal and mechanical loads.

[0112] Preferably, step S24 includes the following steps:

[0113] Step S241: using RC proximity effect coupling capacitance data to perform process fluctuation range perturbation on the digital integrated circuit multi-physics field correction model to generate digital integrated circuit process range perturbation data;

[0114] Step S242: using the RC proximity effect coupling capacitance data to perform temperature fluctuation range perturbation on the digital integrated circuit multi-physics field correction model to generate digital integrated circuit temperature range perturbation data;

[0115] Step S243: aligning the digital integrated circuit process range disturbance data and the digital integrated circuit temperature range disturbance data by model node topology to generate digital integrated circuit physical rule disturbance data;

[0116] Step S244: construct physical constraint adversarial samples for the physical rule disturbance data of the digital integrated circuit, and use clock tree robustness training to generate a digital integrated circuit anti-disturbance model.

[0117] In an embodiment of the present invention, the RC proximity effect coupling capacitor data is used to perturb the process fluctuation and temperature fluctuation range of the digital integrated circuit multi-physics field correction model. The RC proximity effect coupling capacitor data reflects the interaction between the interconnect resistance and capacitance in the circuit, and these effects usually affect the stability and performance of the circuit. By introducing process fluctuations and temperature fluctuations in the multi-physics field correction model, the impact of manufacturing processes and temperature changes in the actual working environment on circuit performance can be simulated. These perturbation data provide important inputs for subsequent optimization and robustness analysis, helping to evaluate the performance of the circuit under various conditions. The process range perturbation data and the temperature range perturbation data are topologically aligned with the model nodes to generate digital integrated circuit physical rule perturbation data. This process is to precisely match the space and topological structure of the perturbation data to ensure that the changes in physical parameters can be accurately reflected between the nodes of the circuit model. The topological alignment technology ensures that the perturbation data can be consistent with the actual layout of the circuit by accurately matching the geometric position and physical characteristics of each component in the circuit model, avoiding distortion of the analysis results due to inconsistent data. The physical rule perturbation data further describes the diversity and uncertainty of the circuit in different physical environments based on the consideration of actual manufacturing and environmental factors. The physical constraint adversarial sample construction technology is used for processing, and the digital integrated circuit anti-disturbance model is generated in combination with clock tree robustness training. Physical constraint adversarial sample construction is to introduce challenging perturbation samples into the circuit model to approximate the performance of the circuit under extreme conditions. These adversarial samples can not only test the fault tolerance of the circuit, but also reveal potential weaknesses in the circuit design. Clock tree robustness training improves the overall stability of the circuit by optimizing the robustness of the clock signal transmission process. By training the clock tree structure, the synchronization and accuracy of the clock signal can be guaranteed under different disturbance conditions, thereby ensuring the efficient operation of the circuit. Ultimately, the anti-disturbance model can effectively improve the robustness of the circuit in the face of external disturbances (such as process fluctuations, temperature changes, etc.), ensuring its reliability and stability in practical applications.

[0118] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes:

[0119] Step S31: obtaining initial integrated circuit data;

[0120] Step S32: performing optimization simulation test on the digital integrated circuit optimization model to generate digital integrated circuit model optimization data;

[0121] Step S33: using a preset circuit optimization threshold to compare and analyze the digital integrated circuit model optimization data and the initial integrated circuit data, and generating a preliminary digital integrated circuit optimization report.

[0122] In the embodiment of the present invention, by obtaining the initial integrated circuit data, the foundation for the entire optimization process is laid. The initial integrated circuit data generally includes the basic design parameters, process specifications and functional requirements of the circuit, which provide a reference for the construction of the subsequent optimization model. The digital integrated circuit optimization model is optimized and simulated, and the optimization model is multi-dimensionally simulated and analyzed based on the initial integrated circuit data through computer-aided design (CAD) and simulation tools. This process generally includes multi-physics field simulations such as timing analysis, power consumption analysis, and thermal effect analysis, which aim to verify the performance of the circuit under actual working conditions and identify potential bottlenecks or deficiencies. The digital integrated circuit model optimization data obtained by simulation reflects the various performance improvements of the circuit under the optimized design, especially the improvement in function and efficiency. The digital integrated circuit model optimization data is compared and analyzed with the initial integrated circuit data, and a preliminary report on the optimization of the digital integrated circuit is generated in combination with a preset circuit optimization threshold. The optimization threshold is generally set by the design standard or process requirement, mainly for indicators such as power consumption, delay, and area of ​​the circuit. In the comparative analysis process, the effectiveness of the optimization result is evaluated by quantitative comparative indicators (such as reduced power consumption, shortened delay, etc.). Ultimately, the optimization preliminary report generated based on these data analyses not only outlines the improvements made during the optimization process, but also provides suggestions or directions for further optimization, helping the design team to further refine the circuit design.

[0123] Preferably, step S32 includes the following steps:

[0124] Step S321: when the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is less than or equal to the preset circuit optimization threshold, the digital integrated circuit model optimization data is detected for abnormal fluctuation range, and potential optimization nodes are marked to generate digital integrated circuit potential optimization node data; the digital integrated circuit potential optimization node data is processed by neural differential dynamic clearing to obtain digital integrated circuit model optimization data;

[0125] Step S322: When the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is greater than a preset circuit optimization threshold, the immediate digital integrated circuit optimization operation is stopped.

[0126] In the embodiment of the present invention, the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is compared, and it is determined whether the ratio is less than or equal to the preset circuit optimization threshold. The calculation of this ratio is based on the difference between the model optimization data and the initial data, reflecting the significance of the optimization effect. If the ratio is small, it means that the performance improvement during the optimization process is not significant, and there will be potential anomalies or fluctuations. Therefore, it is necessary to further detect the abnormal fluctuation range. At this time, the fluctuation detection algorithm identifies the abnormal fluctuation range by comparing the continuous optimization data changes. Through this process, it is possible to find out the potential abnormal or unstable factors in the data and form potential optimization node data. Further, these potential optimization node data are processed by neural differential dynamic clearing, and the dynamic characteristics of these nodes are analyzed by the neural network method, and these abnormal data points are removed or adjusted to obtain smoother and more accurate optimization data. This clearing process can effectively reduce data fluctuations caused by noise or local disturbances, thereby optimizing the accuracy of the overall circuit model. Based on another situation of the ratio, when the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is greater than the preset circuit optimization threshold, the optimization process is determined to have reached the expected optimization goal, and then the optimization operation is stopped. The decision-making mechanism in this process is based on the comparison between the ratio and the threshold, which reflects the degree of achievement of the optimization goal and avoids unnecessary over-optimization, thereby saving resources and improving efficiency.

[0127] As an example of the present invention, refer to Figure 4 As shown, in this example, step S4 includes:

[0128] Step S41: acquiring digital integrated circuit component historical data, wherein the digital integrated circuit component historical data includes circuit component maintenance historical data and circuit component service life historical data;

[0129] Step S42: performing hotspot clustering and vulnerable area identification on the circuit component maintenance history data to generate circuit component vulnerable areas; performing regional optimization comparative analysis on the circuit component vulnerable areas and the preliminary digital integrated circuit optimization report to generate digital integrated circuit maintenance comparative data;

[0130] Step S43: Perform digital twin aging simulation on the historical data of the service life of circuit components to generate circuit component aging simulation data; perform risk probability assessment on the circuit component aging simulation data and the preliminary report on digital integrated circuit optimization to generate digital integrated circuit aging assessment data;

[0131] Step S44: Evaluate the optimization effect of the digital integrated circuit maintenance comparison data and the digital integrated circuit aging assessment data to generate a final report on the digital integrated circuit optimization.

[0132] In an embodiment of the present invention, the acquired digital integrated circuit component historical data includes maintenance history data and service life history data of the circuit components. These data provide a basis for subsequent identification of vulnerable areas and aging simulation, wherein the maintenance history data records the failure and maintenance of the components, and the service life history data provides information on the attenuation and performance changes of the components during use. By analyzing these historical data, potential vulnerable areas and risk points can be identified. The hotspot clustering analysis method is used to cluster the maintenance history data of the circuit components to identify high-risk areas or vulnerable areas with frequent failures in the circuit. These vulnerable areas can generate digital integrated circuit maintenance comparison data by comparing and analyzing with the preliminary report of digital integrated circuit optimization, providing support for subsequent optimization and maintenance decisions. The service life history data of the circuit components is modeled and simulated to simulate the aging process of the components in the actual working environment. Through the digital twin technology, the physical decay characteristics of the components over time can be accurately simulated, thereby generating aging simulation data of the circuit components. On this basis, by performing risk probability assessment with the preliminary optimization report, the aging assessment data of the digital integrated circuit is obtained to assess the performance degradation and failure risks caused by different components during the aging process. Finally, a final report on the optimization of digital integrated circuits is generated by comprehensively evaluating the maintenance comparison data and aging assessment data.

[0133] In this specification, a digital integrated circuit optimization system is provided, which is used to perform the above-mentioned digital integrated circuit optimization method. The digital integrated circuit optimization system includes:

[0134] The data integration and demand analysis module is used to obtain the original data set of integrated circuits; perform circuit function demand analysis on the original data set of integrated circuits to generate circuit optimization demand data; use the process-design joint embedding algorithm to perform heterogeneous feasibility tests on the circuit optimization demand data to generate a circuit digital integration preprocessing data set;

[0135] The model building and optimization module is used to build a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; perform parasitic parameter prediction on the initial integrated circuit optimization model, and inject the timing analysis engine mechanism optimization to obtain a digital integrated circuit optimization model;

[0136] The optimization simulation and comparative analysis module is used to perform optimization simulation tests on the digital integrated circuit optimization model and generate digital integrated circuit model optimization data; perform comparative analysis on the digital integrated circuit model optimization data and obtain a preliminary report on the digital integrated circuit optimization;

[0137] The effect evaluation and report generation module is used to evaluate the effect of optimization results based on the preliminary report of digital integrated circuit optimization and generate the final report of digital integrated circuit optimization.

[0138] The beneficial effect of the present invention is that by acquiring the original data set of the integrated circuit and performing functional requirement analysis on it, the circuit optimization requirement data is generated, which lays a data foundation for the subsequent optimization work. The heterogeneous feasibility test is carried out by using the process-design joint embedding algorithm, which not only ensures the feasibility of the circuit design under the process conditions, but also provides more accurate input data for further optimization by generating the circuit digital integration preprocessing data set. The circuit digital integration preprocessing data set is used to construct a digital integrated circuit optimization model. In this process, the performance of the circuit model is effectively improved by injecting the parasitic parameter prediction and timing analysis engine mechanism, and the potential problems in timing and power consumption are reduced, so as to obtain a more accurate and feasible circuit optimization model. By optimizing the optimization model and performing simulation tests, not only the actual performance of the model is verified, but also the preliminary report of digital integrated circuit optimization is obtained by comparing and analyzing the optimization data. This process further confirms the effectiveness of the optimization through multi-level data comparison. Through the effect evaluation based on the preliminary optimization report, the final report of digital integrated circuit optimization is generated. The complete evaluation system provides circuit designers with comprehensive feedback on the optimization results, and further guides subsequent design decisions. Through this series of links, the present invention ensures the smoothness of data flow and the accuracy of optimization results, improves the overall efficiency and quality of circuit design, and is particularly important in meeting complex process requirements and optimizing design performance. Therefore, the present invention solves the problem of insufficient accuracy of traditional optimization methods in process adaptation and timing analysis through the digital integrated optimization process of integrated circuits, and improves the feasibility and comprehensive performance of circuit optimization.

[0139] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0140] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A digital integrated circuit optimization method, characterized in that: The following steps are involved: Step S1: obtaining an original data set of an integrated circuit; performing circuit function requirement analysis on the original data set of the integrated circuit to generate circuit optimization requirement data; Use the process-design joint embedding algorithm to perform heterogeneous feasibility tests on circuit optimization demand data and generate circuit digital integration preprocessing data sets; Step S2: constructing a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; predicting parasitic parameters of the initial integrated circuit optimization model, and injecting a timing analysis engine mechanism optimization to obtain a digital integrated circuit optimization model; Step S3: performing optimization simulation test on the digital integrated circuit optimization model to generate digital integrated circuit model optimization data; performing comparative analysis on the digital integrated circuit model optimization data to obtain a preliminary report on digital integrated circuit optimization; Step S4: Evaluate the effect of the optimization results based on the preliminary report on the digital integrated circuit optimization and generate a final report on the digital integrated circuit optimization.

2. The digital integrated circuit optimization method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: Acquire the integrated circuit original data set; Step S12: Cleaning the original data set of the integrated circuit to obtain original cleaned data of the circuit; Step S13: performing circuit function requirement analysis on the original circuit cleaning data to generate circuit optimization requirement data; Step S14: using a process-design joint embedding algorithm to perform hyperbolic space netlist alignment on the circuit optimization requirement data to generate circuit hyperbolic space alignment data; Step S15: Perform heterogeneous feasibility test on the circuit hyperbolic space alignment data, and package the data set to generate a circuit digital integration preprocessing data set.

3. The digital integrated circuit optimization method according to claim 2, characterized in that: Step S13 includes the following steps: Step S131: acquiring original circuit cleaning data, wherein the original circuit cleaning data includes circuit component cleaning data and circuit transport cleaning data; Step S132: performing circuit component parameter design analysis on the circuit component cleaning data to generate circuit component parameter analysis data; Step S133: performing a power transmission path structure analysis on the circuit transmission cleaning data to generate circuit power transmission path structure data; Step S134: Utilize the circuit component parameter analysis data to perform circuit function requirement analysis on the circuit power transmission path structure data, and generate circuit optimization requirement data.

4. The digital integrated circuit optimization method according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: obtaining circuit RC parasitic parameters and real-time circuit timing data, wherein the circuit RC parasitic parameters include RC interconnect resistance parameter data and RC proximity effect coupling capacitance data; Step S22: constructing a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; Step S23: using the RC interconnect resistance parameter data to perform thermal-electrical-mechanical coupling correction on the initial integrated circuit optimization model to generate a digital integrated circuit multi-physics field correction model; Step S24: using RC proximity effect coupling capacitance data to perform adversarial robustness enhancement processing on the digital integrated circuit multi-physics field correction model to generate a digital integrated circuit anti-disturbance model; Step S25: dynamically recalibrate the critical path of the digital integrated circuit anti-disturbance model to generate a digital integrated circuit recalibration path; perform clock domain awareness constraints on the digital integrated circuit recalibration path to generate digital integrated circuit clock constraint rules; adjust the digital circuit closure priority of the digital integrated circuit recalibration path based on the digital integrated circuit clock constraint rules and real-time circuit timing data to obtain a digital integrated circuit optimization model.

5. The digital integrated circuit optimization method according to claim 4, characterized in that: Step S23 includes the following steps: Step S231: extracting current density and temperature gradient from the initial integrated circuit optimization model using RC interconnect resistance parameter data, and generating integrated digital circuit current density data and integrated digital circuit temperature gradient data; Step S232: dividing the integrated digital circuit current density data and the integrated digital circuit temperature gradient data into power consumption regions to generate digital integrated circuit power consumption regions; Step S233: constructing an electric-thermal coupling equation for the power consumption area of ​​the digital integrated circuit to generate an electric-thermal coupling equation for the digital integrated circuit; constructing a thermal-mechanical coupling equation for the power consumption area of ​​the digital integrated circuit to generate a thermal-mechanical coupling equation for the digital integrated circuit; Step S234: Perform nonlinear parameter cross-iteration optimization on the initial integrated circuit optimization model using the digital integrated circuit electrical-thermal coupling equation and the digital integrated circuit thermal-mechanical coupling equation to generate a digital integrated circuit multi-physical field correction model.

6. The digital integrated circuit optimization method according to claim 4, characterized in that: Step S24 includes the following steps: Step S241: using RC proximity effect coupling capacitance data to perform process fluctuation range perturbation on the digital integrated circuit multi-physics field correction model to generate digital integrated circuit process range perturbation data; Step S242: using the RC proximity effect coupling capacitance data to perform temperature fluctuation range perturbation on the digital integrated circuit multi-physics field correction model to generate digital integrated circuit temperature range perturbation data; Step S243: aligning the digital integrated circuit process range disturbance data and the digital integrated circuit temperature range disturbance data by model node topology to generate digital integrated circuit physical rule disturbance data; Step S244: construct physical constraint adversarial samples for the physical rule disturbance data of the digital integrated circuit, and use clock tree robustness training to generate a digital integrated circuit anti-disturbance model.

7. The digital integrated circuit optimization method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: obtaining initial integrated circuit data; Step S32: performing optimization simulation test on the digital integrated circuit optimization model to generate digital integrated circuit model optimization data; Step S33: using a preset circuit optimization threshold to compare and analyze the digital integrated circuit model optimization data and the initial integrated circuit data, and generating a preliminary digital integrated circuit optimization report.

8. The digital integrated circuit optimization method according to claim 7, characterized in that: Step S32 includes the following steps: Step S321: when the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is less than or equal to the preset circuit optimization threshold, the digital integrated circuit model optimization data is detected for abnormal fluctuation range, and potential optimization nodes are marked to generate digital integrated circuit potential optimization node data; the digital integrated circuit potential optimization node data is processed by neural differential dynamic clearing to obtain digital integrated circuit model optimization data; Step S322: When the ratio of the digital integrated circuit model optimization data to the initial integrated circuit data is greater than a preset circuit optimization threshold, the immediate digital integrated circuit optimization operation is stopped.

9. The digital integrated circuit optimization method according to claim 7, characterized in that: Step S4 includes the following steps: Step S41: acquiring digital integrated circuit component historical data, wherein the digital integrated circuit component historical data includes circuit component maintenance historical data and circuit component service life historical data; Step S42: performing hotspot clustering and vulnerable area identification on the circuit component maintenance history data to generate circuit component vulnerable areas; performing regional optimization comparative analysis on the circuit component vulnerable areas and the preliminary digital integrated circuit optimization report to generate digital integrated circuit maintenance comparative data; Step S43: Perform digital twin aging simulation on the historical data of the service life of circuit components to generate circuit component aging simulation data; perform risk probability assessment on the circuit component aging simulation data and the preliminary report on digital integrated circuit optimization to generate digital integrated circuit aging assessment data; Step S44: Evaluate the optimization effect of the digital integrated circuit maintenance comparison data and the digital integrated circuit aging assessment data to generate a final report on the digital integrated circuit optimization.

10. A digital integrated circuit optimization system, characterized in that: For executing the digital integrated circuit optimization method as claimed in claim 1, the digital integrated circuit optimization system comprises: The data integration and demand analysis module is used to obtain the original data set of integrated circuits; perform circuit function demand analysis on the original data set of integrated circuits to generate circuit optimization demand data; use the process-design joint embedding algorithm to perform heterogeneous feasibility tests on the circuit optimization demand data to generate a circuit digital integration preprocessing data set; The model building and optimization module is used to build a digital integrated circuit optimization model using the circuit digital integration preprocessing data set to generate an initial integrated circuit optimization model; perform parasitic parameter prediction on the initial integrated circuit optimization model, and inject the timing analysis engine mechanism optimization to obtain a digital integrated circuit optimization model; The optimization simulation and comparative analysis module is used to perform optimization simulation tests on the digital integrated circuit optimization model and generate digital integrated circuit model optimization data; perform comparative analysis on the digital integrated circuit model optimization data and obtain a preliminary report on the digital integrated circuit optimization; The effect evaluation and report generation module is used to evaluate the effect of optimization results based on the preliminary report of digital integrated circuit optimization and generate the final report of digital integrated circuit optimization.

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