Test method and system for chip simulation model

Abstract

The invention relates to the technical field of chip simulation testing, in particular to a testing method and system for a chip simulation model. The method comprises the following steps: acquiring chip design data and carrying out rated load analysis on a circuit node element to obtain node load data; then, carrying out high-frequency and high-voltage simulation on the load data based on the chip simulation model, and identifying a packaging stress cycle decay gradient; then, on the basis of the packaging stress decay gradient, carrier migration efficiency decay is calculated, and chip performance loss is quantified; and finally, performing failure mode generalization processing according to the performance loss data, collecting test results, generating a chip performance failure mode report, and feeding back the chip performance failure mode report to the terminal. According to the invention, the chip simulation test technology is optimized, so that the chip simulation test technology is more perfect.

Description

Technical Field

[0001] The present invention relates to the technical field of chip simulation testing, and in particular to a testing method and system for a chip simulation model. Background Art

[0002] The chip simulation model can simulate the performance of the chip in different working environments, load conditions and aging processes without actual hardware testing. By accurately simulating the working state of each circuit node inside the chip, the simulation model can predict the performance degradation and failure mode of the chip, providing a scientific basis for design optimization and fault prevention. In this process, the simulation model not only needs to consider the behavior at the circuit level, but also needs to model the physical level, including complex phenomena such as packaging stress, thermal management, and carrier migration efficiency. These factors have an important impact on the long-term performance of the chip, especially under high-frequency and high-voltage working conditions, any slight change will lead to serious degradation of chip performance or even failure. In addition, with the increasing size of chips, the previous single failure mode test method often requires a large amount of experimental data and time, which greatly increases the cost and cycle of chip testing. The simulation method can predict the performance changes of the chip under various workloads in advance through accurate models and algorithms, so as to quickly evaluate the advantages and disadvantages of different design schemes, reduce the number of experiments, and reduce development costs and time consumption. Therefore, the test method of the chip simulation model is not only a key tool to improve design efficiency, but also an effective means to ensure that the chip works stably under high-voltage and high-frequency environments. However, a traditional chip simulation model testing method has the problems of low accuracy in quantitative analysis of chip performance degradation and large error in test result precision loss. Summary of the invention

[0003] Based on this, it is necessary to provide a chip simulation model testing method and system to solve at least one of the above technical problems.

[0004] To achieve the above object, a chip simulation model testing method is provided, the method comprising the following steps:

[0005] Step S1: Obtain chip design data; perform circuit node component rated load analysis based on the chip design data to obtain node component rated load data;

[0006] Step S2: Based on the chip simulation model, a high-frequency and high-voltage load state simulation is performed on the rated load data of the node element to obtain chip load state time series segmented data; a package stress cycle decay gradient is identified on the chip load state time series segmented data to obtain a package stress cycle decay gradient;

[0007] Step S3: performing carrier migration efficiency decay calculation based on the package stress cycle decay gradient to obtain carrier migration efficiency decay data; performing chip performance degradation quantification according to the carrier migration efficiency degradation data to obtain chip performance degradation quantification data;

[0008] Step S4: perform failure mode generalization processing based on the chip performance degradation quantification data to obtain performance degradation failure mode generalization data; collect test results based on the performance degradation failure mode generalization data to obtain a chip performance failure mode result report, and feed back the chip performance failure mode result report to the terminal.

[0009] The present invention firstly obtains chip design data, and can accurately grasp each circuit node of the chip and its corresponding component parameters. These data lay the foundation for subsequent circuit load analysis and ensure the accuracy of subsequent analysis. By performing rated load analysis of node components, the load bearing capacity of each component under different working conditions can be quantified, thereby identifying high-load areas, providing data support for subsequent high-frequency and high-voltage load simulations, avoiding overload or design defects, and optimizing circuit design in advance. By using a chip simulation model to simulate the high-frequency and high-voltage load state of the rated load data of the circuit node components, the chip can be stress-tested in a virtual environment, simulating the behavior of the chip under extreme working conditions, and predicting the location and timing of stress concentration. This step can identify potential failure points of the chip under high load. By identifying the gradient of package stress cycle decay, the distribution and evolution of stress in the package structure can be quantified, which helps to optimize the package design, extend the service life of the chip, and provide a basis for subsequent performance degradation prediction. The gradient of package stress cycle decay directly affects the electron migration efficiency inside the chip. Therefore, using this gradient to calculate the carrier migration efficiency decay can effectively evaluate the decay of the carrier transmission capacity of the chip over time under long-term high-frequency and high-voltage conditions. By quantifying the decay of carrier migration efficiency, it is possible to predict the performance degradation trend of the chip in actual work and identify the performance degradation caused by stress and aging in advance. This provides data support for long-term reliability evaluation of the chip, optimizing chip design, and selecting appropriate materials and manufacturing processes. By generalizing the failure mode of the chip performance degradation quantification data, different failure modes can be identified and summarized in multiple different working environments, and the failure mechanism of the chip under various working conditions can be obtained. This step not only helps to discover hardware defects, but also provides a comprehensive model for chip fault prediction and provides improvement directions for chip design. By generalizing the performance degradation failure mode, the stability of the chip in various application scenarios can be ensured, and a reliable basis can be provided for subsequent testing and performance verification. Therefore, the present invention optimizes a traditional chip simulation model testing method, solves the problems of low precision of quantitative analysis of chip performance degradation and large error in test result precision loss in the traditional chip simulation model testing method, improves the precision of quantitative analysis of chip performance degradation and reduces the error in test result precision loss.

[0010] Preferably, step S1 comprises the following steps:

[0011] Step S11: Obtain chip design data;

[0012] Step S12: extracting the circuit layout of the chip design data to obtain chip circuit layout data;

[0013] Step S13: classify and mark the circuit node components of the chip circuit layout data to obtain circuit node component classification mark data;

[0014] Step S14: performing circuit node component rated load analysis on the circuit node component classification labeling data based on the chip design data to obtain node component rated load data.

[0015] The present invention obtains chip design data, which is the basis of the entire analysis process. By accurately collecting and organizing chip design data, it is ensured that there is a reliable data source for subsequent analysis. These design data usually include circuit structure, functions and parameters of each component, wiring mode, etc., covering the basic working principle and layout of the chip. In practical applications, accurate data acquisition lays a solid foundation for subsequent analysis and optimization, reduces errors, and improves the accuracy and efficiency of subsequent work. The circuit layout extraction step helps to convert the specific circuit elements and layout forms in the design data into clear and operable circuit structure information. By performing circuit layout extraction on chip design data, important information such as the connection relationship between each circuit node and the distribution position of the components can be obtained. This process not only provides detailed circuit structure data for subsequent load analysis, but also helps to identify high-density areas or hot spots of the circuit, providing support for circuit optimization and fault prediction. Classification and marking of node components on chip circuit layout data helps to systematically and structuredly manage the components in the circuit. By classifying and marking each circuit node and component, different types of components (such as transistors, resistors, capacitors, etc.) and their functions and relationships in the circuit can be accurately distinguished. This process can help to conduct a more detailed analysis of the characteristics of different components in subsequent load analysis, thereby optimizing the design and avoiding potential failures caused by differences in loads of different components. After completing the classification and labeling of circuit node components, performing rated load analysis on them is a key step in further optimizing chip performance. By analyzing the rated loads of circuit node components, the maximum bearing capacity, energy consumption, power distribution, etc. of each node and component under normal working conditions can be clarified. This analysis result helps to discover high-load areas, identify potential bottlenecks or overload risks in circuit design, and avoid circuit failures or component failures caused by overload, thereby laying the foundation for the stability, reliability and long-term use of the chip.

[0016] Preferably, step S2 comprises the following steps:

[0017] Step S21: Based on the chip simulation model, a high-frequency and high-voltage load state simulation is performed on the rated load data of the node element to obtain the high-frequency and high-voltage load state data of the chip; wherein the high-frequency and high-voltage refer to: high voltage and high frequency;

[0018] Step S22: performing time-series segmentation processing on the chip high-frequency and high-voltage load state data to obtain chip load state time-series segmented data;

[0019] Step S23: performing resonance range widening analysis on the chip load state time series segmented data to obtain resonance range widening data;

[0020] Step S24: performing package stress cycle decay gradient identification on the chip load state time series segmented data according to the resonance range widening data to obtain the package stress cycle decay gradient.

[0021] The present invention simulates the high-frequency and high-voltage load state of the node element rated load data by using a chip simulation model, and can simulate its working performance in a high-voltage and high-frequency environment without actually manufacturing the chip. High voltage and high-frequency load states are usually the extreme working conditions encountered by chips in high-speed computing or high-speed communication. Through simulation, the behavior of the chip under these conditions can be predicted in advance, including problems such as excessive power consumption, overheating, and signal distortion. This step can discover potential weaknesses in circuit design, help optimize circuit layout and component selection, and reduce risks in practical applications. The load of the chip under a high-frequency and high-voltage load state is usually variable, with periodic fluctuations or sudden load changes. By performing time-series segmentation processing on the high-frequency and high-voltage load state data, the load fluctuation can be divided into multiple meaningful time periods, and the load characteristics of each time period can be analyzed separately. This processing can help accurately identify the load change trend of the chip under different working cycles, and then reveal the performance bottleneck and potential failure risk of the chip in different time periods. This step provides more detailed data support for subsequent stress analysis and failure mode prediction, which helps to achieve optimized design and efficient operation of the chip. Resonance is a common phenomenon in circuit design, especially under high-frequency and high-voltage load conditions, resonance will occur in the circuit, resulting in instability of current and voltage. The resonance range widening analysis of the timing segmented data helps to understand the frequency response characteristics of the chip under different load conditions. By identifying and widening the resonance range, the resonance frequency points generated under high-frequency loads can be effectively identified, as well as the impact of these frequencies on circuit stability and chip life. This analysis can help designers optimize circuit layout, reduce the negative impact of resonance on chip performance, and improve the stability and reliability of the chip under high-frequency working conditions. Package stress cycle decay is an important failure mechanism in the long-term operation of the chip. Especially under high-frequency and high-voltage loads, the chip's packaging materials and internal structures will suffer frequent stress cycles, leading to fatigue and performance degradation of the packaging materials. Based on the resonance range widening data, the package stress cycle decay gradient can be further identified, the distribution of stress in the packaging structure can be quantified, and the decay trend of the packaging material can be predicted. Through this step, the long-term impact of package stress on chip performance can be evaluated, providing data support for optimizing package design, selecting appropriate materials, and improving chip durability. At the same time, this process helps ensure that the chip can operate stably for a long time in actual applications and reduce failures caused by package failure.

[0022] Preferably, the present invention further provides a chip simulation model testing system, which is used to execute the chip simulation model testing method as described above, and the chip simulation model testing system comprises:

[0023] The component rated load analysis module is used to obtain chip design data; based on the chip design data, the circuit node component rated load analysis is performed to obtain the node component rated load data;

[0024] The package stress cycle decay identification module is used to simulate the high-frequency and high-voltage load state of the node element rated load data based on the chip simulation model to obtain the chip load state time series segmented data; the package stress cycle decay gradient is identified on the chip load state time series segmented data to obtain the package stress cycle decay gradient;

[0025] The performance degradation quantification module is used to perform carrier migration efficiency degradation calculation based on the package stress cycle decay gradient to obtain carrier migration efficiency degradation data; and to quantify chip performance degradation based on the carrier migration efficiency degradation data to obtain chip performance degradation quantification data;

[0026] The test result collection and feedback module is used to generalize the failure mode according to the chip performance degradation quantification data to obtain the performance degradation failure mode generalization data; collect test results based on the performance degradation failure mode generalization data to obtain the chip performance failure mode result report, and feed back the chip performance failure mode result report to the terminal.

[0027] The beneficial effects of the present invention are that, firstly, by acquiring chip design data, each circuit node of the chip and its corresponding component parameters can be accurately grasped. These data lay the foundation for subsequent circuit load analysis and ensure the accuracy of subsequent analysis. By performing rated load analysis of node components, the load bearing capacity of each component under different working conditions can be quantified, thereby identifying high-load areas, providing data support for subsequent high-frequency and high-voltage load simulations, avoiding overload or design defects, and optimizing circuit design in advance. By using a chip simulation model to simulate the high-frequency and high-voltage load state of the rated load data of the circuit node components, the chip can be stress-tested in a virtual environment, simulating the behavior of the chip under extreme working conditions, and predicting the location and timing of stress concentration. This step can identify potential failure points of the chip under high load. By identifying the gradient of the package stress cycle decay, the distribution and evolution of stress in the package structure can be quantified, which helps to optimize the package design, extend the service life of the chip, and provide a basis for subsequent performance degradation prediction. The package stress cycle decay gradient directly affects the electron migration efficiency inside the chip. Therefore, using this gradient to calculate the carrier migration efficiency decay can effectively evaluate the decay of the carrier transmission capacity of the chip over time under long-term high-frequency and high-voltage conditions. By quantifying the carrier migration efficiency decay, it is possible to predict the performance degradation trend of the chip in actual work and identify the performance degradation caused by stress and aging in advance. This provides data support for long-term reliability evaluation of the chip, optimizing chip design, and selecting appropriate materials and manufacturing processes. By generalizing the failure mode of the chip performance degradation quantification data, different failure modes can be identified and summarized in multiple different working environments, and the failure mechanism of the chip under various working conditions can be obtained. This step not only helps to discover hardware defects, but also provides a comprehensive model for chip fault prediction and provides improvement directions for chip design. By generalizing the performance degradation failure mode, the stability of the chip in various application scenarios can be ensured, and a reliable basis can be provided for subsequent testing and performance verification. Therefore, the present invention optimizes a traditional chip simulation model testing method, solves the problems of low precision of quantitative analysis of chip performance degradation and large error in test result precision loss in the traditional chip simulation model testing method, improves the precision of quantitative analysis of chip performance degradation and reduces the error in test result precision loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the steps of a chip simulation model testing method;

[0029] Figure 2 for Figure 1 Detailed implementation steps of step S2 in the flowchart;

[0030] Figure 3 for Figure 1 Detailed implementation steps of step S3 in FIG. DETAILED DESCRIPTION

[0031] The technical method of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0033] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0034] To achieve this, please refer to Figures 1 to 3 , a chip simulation model testing method, the method comprising the following steps:

[0035] Step S1: Obtain chip design data; perform circuit node component rated load analysis based on the chip design data to obtain node component rated load data;

[0036] Step S2: Based on the chip simulation model, a high-frequency and high-voltage load state simulation is performed on the rated load data of the node element to obtain chip load state time series segmented data; a package stress cycle decay gradient is identified on the chip load state time series segmented data to obtain a package stress cycle decay gradient;

[0037] Step S3: performing carrier migration efficiency decay calculation based on the package stress cycle decay gradient to obtain carrier migration efficiency decay data; performing chip performance degradation quantification according to the carrier migration efficiency degradation data to obtain chip performance degradation quantification data;

[0038] Step S4: perform failure mode generalization processing based on the chip performance degradation quantification data to obtain performance degradation failure mode generalization data; collect test results based on the performance degradation failure mode generalization data to obtain a chip performance failure mode result report, and feed back the chip performance failure mode result report to the terminal.

[0039] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a schematic diagram of a step flow chart of a chip simulation model testing method of the present invention. In this example, the chip simulation model testing method includes the following steps:

[0040] Step S1: Obtain chip design data; perform circuit node component rated load analysis based on the chip design data to obtain node component rated load data;

[0041] In the embodiment of the present invention, it is first necessary to obtain the design data of the chip, which includes but is not limited to circuit schematics, layout diagrams and process information. The design data is usually stored in digital format and imported and parsed by standard EDA tools (such as Cadence or Synopsys). Based on these design data, the rated load analysis of circuit node components is performed. The main goal of the rated load analysis of circuit node components is to identify the load borne by each circuit node to evaluate the load-bearing capacity of the component under normal working conditions. During the specific implementation, it is first necessary to parse the circuit design diagram and extract the connection relationship between each circuit node and component. Then, according to the current, voltage, power and other parameters in the circuit, the maximum current and power on each circuit node are calculated by Kirchhoff's law and Ohm's law. Then, by comparing with the rated parameters of the circuit element (such as resistance, capacitance, inductance, withstand voltage, etc.), it is determined whether it exceeds the rated load range of the component, and finally the node element rated load data is obtained.

[0042] Step S2: Based on the chip simulation model, a high-frequency and high-voltage load state simulation is performed on the rated load data of the node element to obtain chip load state time series segmented data; a package stress cycle decay gradient is identified on the chip load state time series segmented data to obtain a package stress cycle decay gradient;

[0043] In an embodiment of the present invention, a simulation model based on a chip is used to simulate the high-frequency and high-voltage load state of the rated load data of the node element. The simulation model uses finite element analysis (FEA) and time domain simulation methods to simulate the response behavior of each node element of the chip under high-frequency (such as GHz range) and high-voltage (such as above 10V) working conditions. First, it is necessary to use a dedicated simulation software (such as Ansys or COMSOL) to perform time domain simulation on the chip circuit, input the rated load data of the node element, and obtain the dynamic response of each node under high-frequency and high-voltage conditions through the simulation solver. Through the time-series segmented analysis of these simulation results, the different stages of the load state are identified to form the chip load state time-series segmented data. Then, the package stress cycle decay gradient is identified according to the chip load state time-series segmented data. The package stress cycle decay gradient refers to the fatigue damage degree caused by thermal expansion and mechanical stress changes of the chip packaging material under the action of long-term high-frequency and high-voltage load. This part is processed by thermal-mechanical coupling analysis, and multi-physics field simulation technology is used to simulate the stress changes of the package. First, the stress change law is determined by analyzing the interaction between the thermal cycle and mechanical cycle of the chip packaging material. Then, according to the stress variation data, the corresponding mathematical model (such as the Manson-Coffin criterion) is used to calculate the cyclic decay gradient of the package stress, thereby obtaining the package stress cyclic decay data.

[0044] Step S3: performing carrier migration efficiency decay calculation based on the package stress cycle decay gradient to obtain carrier migration efficiency decay data; performing chip performance degradation quantification according to the carrier migration efficiency degradation data to obtain chip performance degradation quantification data;

[0045] In an embodiment of the present invention, the decay of carrier migration efficiency is derived by the package stress cycle decay gradient data obtained in the previous step. The calculation of the decay of carrier migration efficiency adopts a model based on mobility change. High-frequency and high-voltage loads can cause the carrier mobility in semiconductor materials to decrease, and this change can be achieved through physical modeling and statistical regression analysis. Specifically, based on stress decay data, the carrier mobility model (such as Arrhenius model or Wertheim model) in materials science is used to quantify the decrease in mobility. Afterwards, the chip performance degradation is quantified based on the decay data of carrier migration efficiency. The performance degradation quantification of the chip refers to adjusting the performance indicators of the chip such as current, frequency response, power consumption, etc. through the decayed mobility. The quantification method uses a semi-empirical model, combined with the working parameters of the chip (such as current, voltage, frequency, etc.), to calculate the degradation of the overall performance of the chip. This process obtains the degradation ratio and the final performance degradation quantification data by comparing the circuit behavior before and after the decay.

[0046] Step S4: perform failure mode generalization processing based on the chip performance degradation quantification data to obtain performance degradation failure mode generalization data; collect test results based on the performance degradation failure mode generalization data to obtain a chip performance failure mode result report, and feed back the chip performance failure mode result report to the terminal.

[0047] In an embodiment of the present invention, the failure mode is generalized according to the chip performance impairment quantification data, and a test result report is finally generated. First, the performance impairment quantification data is normalized. The purpose of normalization is to eliminate the dimensional differences between different test data so that the data can be uniformly compared. By standardizing the performance impairment data, a normalized data set is obtained, which provides a basis for the subsequent generalization of failure modes. Then, based on these normalized data, data mining techniques (such as cluster analysis, principal component analysis, etc.) are used to generalize the performance impairment failure mode. At this time, the big data analysis method used can help identify the potential failure modes of the chip under different load conditions. According to the generalization results of these failure modes, the test results are further collected, and the collected data includes the failure type, the failure cause, and the performance change of the chip after failure. Finally, a detailed "chip performance failure mode result report" is generated through an automated report generation tool (such as Matlab or Python script), which records the performance impairment of the chip under different test conditions, and feeds the results back to the terminal system for subsequent analysis and decision-making.

[0048] Preferably, step S1 comprises the following steps:

[0049] Step S11: Obtain chip design data;

[0050] Step S12: extracting the circuit layout of the chip design data to obtain chip circuit layout data;

[0051] Step S13: classify and mark the circuit node components of the chip circuit layout data to obtain circuit node component classification mark data;

[0052] Step S14: performing circuit node component rated load analysis on the circuit node component classification labeling data based on the chip design data to obtain node component rated load data.

[0053] In an embodiment of the present invention, obtaining chip design data is the first step of the chip simulation model testing method. This step involves extracting design data from the chip design platform, which generally includes circuit schematics, layout diagrams, manufacturing process information, and electrical parameters. The acquisition method of these data is carried out through standardized design formats (such as GDSII files, DEF files, SPICE netlists, etc.). The design data includes information such as the position, size, material properties, and connection relationship of each circuit element (such as transistors, resistors, capacitors, etc.). At this time, the chip design file is directly read by calling a design tool (such as Cadence Virtuoso or Synopsys IC Compiler). It should be noted that the accuracy and completeness of the design data are the basis for subsequent analysis. Therefore, when acquiring data, it must be ensured that there are no omissions or errors in the design file, and the format and version of the data must be compatible with the simulation software. The acquired data will be used for subsequent layout extraction and load analysis. Based on the design data obtained in step S11, the circuit layout is extracted. In this step, it is first necessary to extract the position, size, adjacent relationship, and electrical connection information of each circuit element in the chip. This process is usually carried out by utilizing the physical layer information in the design data to extract the circuit layout data of the chip. During the specific implementation, the layout data (such as GDSII file format) in the design file is first parsed to extract the geometric shape, size and specific layout position of each component on the chip. Then, according to the electrical connection information, the connection relationship between each component is determined to obtain the topological structure of the circuit. In order to ensure the accuracy of the circuit layout, physical verification is also required, such as checking whether the spacing between components meets the process requirements to avoid circuit short circuit or excessive parasitic effects. After the extraction is completed, the chip circuit layout data is generated and used for subsequent node component classification marking and load analysis. Based on the circuit layout data obtained in step S12, the circuit node components in the chip are classified and marked. The purpose of this step is to classify each component in the circuit according to function, physical properties and electrical characteristics for subsequent load analysis. In the specific implementation process, the categories of each component in the circuit (such as transistors, resistors, capacitors, inductors, etc.) are first identified by parsing the chip circuit layout data. In the classification and marking process, it is necessary to group according to the function, position and other electrical properties of the circuit components. For example, all components used for signal processing can be classified as signal channel categories, and all components used for power distribution can be classified as power supply categories. For each component, its working status, power consumption, thermal characteristics, etc. are marked to generate classified labeling data for each circuit node component. In addition, the connection relationship between components, such as input, output, and feedback loop, needs to be marked, which is very important for subsequent load analysis. The classified labeling data provides the necessary information for subsequent load analysis and ensures that the analysis of each component can be performed based on its specific function and location.By classifying and marking data of circuit node elements, rated load analysis of node elements is performed, and rated load data of each node element is finally obtained. Rated load analysis is a key step in evaluating power consumption, heat generation and current carrying capacity of circuit elements during operation. During specific implementation, first, the type and working state of each circuit node and element are identified according to the classified marking data obtained in step S13. Then, the power consumption and current transmission of each node are calculated by using the electrical parameters (such as voltage, current, power, thermal resistance, etc.) of the circuit elements, combined with the working conditions of the circuit (such as input signal frequency, power, etc.), applying basic circuit theories such as Kirchhoff's law, Ohm's law and current-voltage relationship. For example, for a transistor element, its rated power consumption can be obtained by calculating its input voltage and current, combined with the working model of the transistor (such as SPICE model). In the calculation process, the influence of temperature effect and material properties on current and power also need to be considered. For resistor elements, Ohm's law is used to calculate the current and voltage passing through it, so as to determine the power consumption. For capacitor elements, its power consumption and parasitic current can be calculated according to its voltage and frequency response. Through these circuit analysis methods, the rated load data of each node component can be obtained, including its maximum current, voltage and power, etc. Ultimately, these data will provide the basis for subsequent high-frequency and high-voltage load simulation.

[0054] Preferably, step S2 comprises the following steps:

[0055] Step S21: Based on the chip simulation model, a high-frequency and high-voltage load state simulation is performed on the rated load data of the node element to obtain the high-frequency and high-voltage load state data of the chip; wherein the high-frequency and high-voltage refer to: high voltage and high frequency;

[0056] Step S22: performing time-series segmentation processing on the chip high-frequency and high-voltage load state data to obtain chip load state time-series segmented data;

[0057] Step S23: performing resonance range widening analysis on the chip load state time series segmented data to obtain resonance range widening data;

[0058] Step S24: performing package stress cycle decay gradient identification on the chip load state time series segmented data according to the resonance range widening data to obtain the package stress cycle decay gradient.

[0059] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes:

[0060] Step S21: Based on the chip simulation model, a high-frequency and high-voltage load state simulation is performed on the rated load data of the node element to obtain the high-frequency and high-voltage load state data of the chip; wherein the high-frequency and high-voltage refer to: high voltage and high frequency;

[0061] In an embodiment of the present invention, a simulation model based on a chip is used to simulate the high-frequency and high-voltage load state of the rated load data of the node element. The key to high-frequency and high-voltage load simulation is to accurately capture the behavior of the chip under extreme working conditions, especially for high voltage (e.g., more than 10V) and high frequency (e.g., GHz level) working conditions. In the specific implementation process, the rated load data of the node element obtained in steps S1 and S2 need to be first imported into the simulation model. The simulation model needs to include all the basic components of the circuit and be able to handle the electrical behavior under high-frequency and high-voltage conditions. In the simulation process, the operating frequency and voltage value of the circuit are first set, and the response of the chip under these working conditions is simulated by applying the frequency domain analysis method. For each node, an analytical method (e.g., Fourier transform) is used to calculate the change of the signal under high-frequency conditions. High-frequency signals will produce parasitic capacitance and inductance effects, which will affect the overall behavior of the circuit, so it is necessary to simulate these effects through accurate electromagnetic field simulation. In the case of high voltage, it is necessary to consider the nonlinear response of the current and the breakdown voltage effect, which will affect the current and power consumption of the circuit elements. Therefore, during simulation, nonlinear circuit models (such as SPICE models) will be used to accurately calculate the voltage-current characteristics, especially for nonlinear components such as transistors and diodes. Ultimately, through the above simulation, the electrical response data of each node under high frequency and high voltage can be obtained. These data will be used to analyze the stability and reliability of the chip under extreme conditions and provide a basis for subsequent timing segmentation processing.

[0062] Step S22: performing time-series segmentation processing on the chip high-frequency and high-voltage load state data to obtain chip load state time-series segmented data;

[0063] In an embodiment of the present invention, the goal is to perform time-series segmentation processing on the state data of the chip under high-frequency and high-voltage load to obtain the time-series segmentation data of the chip load state. The data generated by the high-frequency and high-voltage load state simulation is usually a time domain signal, which is expressed as a time series and contains the electrical parameters (such as voltage, current, power, etc.) of the chip response at different time points. However, in order to more effectively analyze the performance of the chip under extreme working conditions, these data must be processed by time-series segmentation. In specific implementation, the entire time-series signal is first divided into several continuous time periods. The electrical characteristics in each time period should be relatively stable and have obvious characteristics different from other time periods. The principle of time-series segmentation is usually divided according to the rate of change and fluctuation amplitude of the signal. For example, if the voltage fluctuation amplitude exceeds the set threshold, the segment data is considered to be a new time segment. Common methods for time-series segmentation processing include peak detection, slope analysis, and threshold judgment. Based on these methods, the data in each time segment can be analyzed and processed independently. In addition, in the process of time-series segmentation, the periodicity and harmonic characteristics of the signal also need to be considered. In particular, in high-frequency signals, there will be multiple harmonic components. Therefore, it is necessary to use frequency domain analysis tools such as Fourier transform to perform spectrum analysis on each time segment, extract the main frequency components, and use them as the basis for time segment division. Through these processing steps, the obtained time segment data can more accurately reflect the behavior of the chip under different loads.

[0064] Step S23: performing resonance range widening analysis on the chip load state time series segmented data to obtain resonance range widening data;

[0065] In an embodiment of the present invention, the resonance range widening analysis is performed on the chip load state time series segmented data to obtain the resonance range widening data. Under the high-frequency load state, some circuit nodes in the chip will produce resonance phenomenon, especially under the excitation of high voltage and high frequency, the resonance frequency of the circuit element will change. In order to capture these changes, the resonance range widening analysis must be performed on the time series segmented data. In this step, firstly, a spectrum analysis is performed on each time series segment to determine the main frequency components of the signal. Fourier transform or other frequency domain analysis methods are used to extract the frequency components in the time series segment, including the main frequency and the harmonic frequency. Next, the resonant frequency is identified by analyzing the changes in each frequency component. Due to the presence of high-frequency signals, the originally stable resonant frequency will be affected by changes in temperature, voltage and current, and frequency drift will occur. Therefore, the goal of the widening analysis is to identify the range of these frequency drifts. The amplitude of the change in the resonant frequency is quantified by calculating statistical indicators such as the standard deviation of the frequency change and the root mean square (RMS) value. Especially under high-frequency and high-voltage conditions, the amplitude of the frequency drift will change with time, so it is necessary to continuously analyze the time series to obtain the range of the resonant frequency change of each time series. Finally, these data are combined to obtain resonance range broadening data, which provide a basis for subsequent packaging stress cycle decay analysis.

[0066] Step S24: performing package stress cycle decay gradient identification on the chip load state time series segmented data according to the resonance range widening data to obtain the package stress cycle decay gradient.

[0067] In an embodiment of the present invention, based on the resonance range widening data, the chip load state time series segmented data is used to identify the package stress cyclic decay gradient. The package stress cyclic decay gradient refers to the process in which the material performance gradually decays due to the cumulative effect of factors such as thermal expansion and mechanical stress under high-frequency and high-voltage working conditions. The package stress cyclic decay will affect the long-term stability and reliability of the chip, so it must be accurately identified in the chip simulation under high-frequency and high-voltage load. In implementation, first, based on the resonance range widening data obtained in step S23, combined with the changes in temperature and current in the circuit, the thermal-mechanical coupling model is used to analyze the stress distribution of the chip package. Under high-frequency and high-voltage conditions, due to changes in frequency and voltage, the packaging material will experience temperature fluctuations, and these fluctuations will cause stress changes inside the package. By analyzing the stress distribution under different frequency bands and different load states, the amplitude and periodicity of the stress change are determined. In order to identify the cyclic decay gradient of the package stress, a coupling analysis method of mechanics and thermodynamics is used, considering the mutual influence of thermal cycles and mechanical cycles. A multidimensional analysis model of cyclic stress (such as Poisson's ratio, thermal expansion coefficient, etc.) is used for analysis to identify the periodic changes and decay rate of stress decay. Specifically, the stress decay curve can be obtained by fitting the stress data of each time segment, and the package stress cycle decay gradient data can be obtained by calculating the slope change of the stress decay curve. Ultimately, these data will be used for subsequent carrier migration efficiency decay analysis.

[0068] Preferably, step S23 includes the following steps:

[0069] Step S231: performing time-series segmented electromagnetic field intensity analysis on the chip load state time-series segmented data to obtain time-series segmented electromagnetic field intensity data;

[0070] Step S232: performing resonance frequency coupling based on the time-series segmented electromagnetic field intensity data to obtain the time-series segmented resonance frequency;

[0071] Step S233: analyzing the time-varying characteristics of the time-series segmented resonant frequency to obtain time-varying characteristic resonant frequency data;

[0072] Step S234: calculating the wavelength expansion amplitude difference according to the time-varying characteristic resonant frequency data to obtain the resonant frequency wavelength expansion amplitude difference;

[0073] Step S235: performing resonance range widening analysis based on the resonance frequency wavelength expansion amplitude difference to obtain resonance range widening data.

[0074] In an embodiment of the present invention, electromagnetic field intensity analysis is performed on the chip load state time series segmented data to obtain time series segmented electromagnetic field intensity data. Electromagnetic field intensity analysis is to evaluate the electromagnetic effect of the chip under high-frequency working state, especially the distribution of current signals, the intensity of electromagnetic radiation and the influence of electromagnetic interference. The first step of this process is to further refine the distribution of electric field and magnetic field intensity in each time series segment according to the time series segmented data obtained in the aforementioned step S22. In actual operation, it is first necessary to model the electrical signal in each time series segment through time domain analysis. For each time series segment, the distribution of electric field and magnetic field is calculated by numerical solution method using electromagnetic field model based on Faraday's law and Ampere's law. This is usually achieved by finite element analysis (FEA) or boundary element method (BEM), which can effectively simulate the behavior of complex electromagnetic fields. For each time point in the time series segmented data, the corresponding electric field intensity and magnetic field intensity are calculated to obtain the electromagnetic field intensity data of each time series segment. Especially in the high-frequency working state, the propagation characteristics of electromagnetic waves change significantly, so it is necessary to analyze the high-frequency components in the signal in detail. The time domain signal is converted into a frequency domain signal by using a fast Fourier transform (FFT), and the high-frequency component in the signal is extracted, and the electromagnetic field strength of these frequency components is calculated in combination with the electromagnetic field model. In this way, the obtained time-series segmented electromagnetic field strength data can accurately reflect the changes in the electromagnetic environment inside the chip under high-frequency load conditions. Resonant frequency coupling is performed based on the time-series segmented electromagnetic field strength data to obtain the time-series segmented resonant frequency. The main purpose of the resonant frequency coupling analysis is to identify the resonance phenomenon existing in the circuit and determine the coupling relationship between the electromagnetic wave and the circuit element. This analysis step is of great significance for revealing the behavior of the chip under high-frequency conditions, because the frequency response directly affects the stability and reliability of the circuit. First, based on the electromagnetic field strength data obtained in step S231, the response of different frequency components in the circuit can be identified by frequency domain analysis. Using the resonance theory model, the coupling analysis is performed in combination with the electromagnetic field strength data. Specifically, the mutual influence between circuit elements can be calculated by the coupling matrix method to determine the resonant frequency when the electromagnetic wave propagates in the circuit. In the coupling analysis process, the impedance matching of the circuit and the electromagnetic interaction of each node need to be considered, especially under high-frequency conditions, the parasitic capacitance and inductance effects in the circuit will have an important influence on the resonant frequency. During the calculation, the electromagnetic field intensity data is first converted into frequency domain data through Fourier transform to obtain each frequency component. Then, according to the resonance characteristics of the circuit, the current and voltage response of the circuit at different frequencies are analyzed. The resonant frequency of the circuit is calculated through a mathematical model to obtain the resonant frequency data of each timing segment. These data are used to further analyze the impact of the resonance phenomenon on chip performance and provide a basis for subsequent time-varying characteristics analysis. The time-varying characteristics of the timing segmented resonant frequency are analyzed to obtain the time-varying characteristics resonant frequency data.The purpose of time-varying characteristic analysis is to study the variation of the resonant frequency of the chip over time when it works for a long time. Since high-frequency signals are affected by external conditions (such as temperature changes, current fluctuations, etc.), the resonant frequency in the chip also changes, so time-varying characteristic analysis is crucial for evaluating the long-term stability of the chip. During implementation, it is first necessary to perform a time series analysis on the resonant frequency data obtained in step S232. Through the time series analysis method, the frequency data is smoothed using the sliding window technology, and the trend analysis of the frequency change is performed. Common analysis methods include moving average method, exponential smoothing method, etc., which can effectively remove short-term fluctuations and highlight long-term change trends. Next, it is necessary to apply a time-frequency analysis method (such as wavelet transform or short-time Fourier transform) to further analyze the resonant frequency. Wavelet transform can help identify non-stationary features in frequency changes, thereby revealing the details of the resonant frequency changes at a specific time point. Through these analyses, a resonant frequency curve that varies with time can be obtained, which reflects the dynamic change characteristics of the frequency of the chip during operation. The wavelength extension amplitude difference is calculated based on the time-varying characteristic resonant frequency data to obtain the resonant frequency wavelength extension amplitude difference. The main purpose of this step is to quantify the wavelength expansion effect of the chip under high-frequency conditions, especially at different resonant frequencies, the wavelength change in the chip will cause additional stress or performance degradation. First, the wavelength of each time segment can be calculated through the relationship between wavelength and frequency. The relationship between wavelength and frequency is λ = c / f, where λ is the wavelength, c is the speed of light, and f is the frequency. In this step, the wavelength corresponding to each frequency point is calculated according to the time-varying characteristic resonant frequency data. Then, the wavelength expansion amplitude difference is obtained by calculating the wavelength difference in each time segment. This difference reflects the wavelength change amplitude caused by frequency change during the operation of the chip. By further analyzing the wavelength expansion amplitude difference, the potential impact of frequency change on circuit behavior can be identified, especially electromagnetic interference, signal attenuation and other problems caused by wavelength expansion under high-frequency and high-voltage loads. These data can be used as an important indicator for chip stability analysis. The resonance range widening analysis is performed based on the resonance frequency wavelength expansion amplitude difference to obtain the resonance range widening data. The purpose of this step is to evaluate the resonant frequency range of the chip under different load conditions, especially the changes in the resonance range caused by frequency drift and wavelength expansion in high-frequency working conditions. During the implementation process, it is first necessary to combine the wavelength expansion amplitude difference data and use the frequency broadening model for analysis. This model takes into account the electromagnetic coupling effect inside the chip and the influence of the external environment, and simulates the impact of different frequency components on the overall resonance range. By calculating the range of change of the resonance frequency, the degree of broadening of the resonance range is obtained. This analysis usually uses a multivariate regression model, using the existing time-varying resonance frequency data and wavelength expansion amplitude difference data to fit the relationship between the resonance range and these variables.Through this analysis, the stability and performance changes of the chip under high-frequency and high-voltage working conditions can be determined, and the resonance range widening data can be obtained. These data are of great reference value for subsequent packaging stress cycle decay analysis.

[0075] Preferably, step S25 comprises the following steps:

[0076] Step S251: performing time series variation heat increment analysis on the chip load state time series segmented data to obtain time series variation heat increment data;

[0077] Step S252: performing a heat flow cycle heteroscedasticity simulation based on the time-series heat increment data to obtain heat flow cycle heteroscedasticity data;

[0078] Step S253: performing heat distribution local imbalance calculation on the heat flow cycle heteroscedasticity data according to the resonance range widening data to obtain heat distribution local imbalance data;

[0079] Step S254: performing local temperature gradient anomaly analysis on the local imbalance data of thermal distribution to obtain local gradient anomaly data of thermal distribution;

[0080] Step S255: performing package stress cyclic decay gradient identification according to the local gradient anomaly data of the thermal distribution to obtain the package stress cyclic decay gradient.

[0081] In an embodiment of the present invention, the chip load state time series segmented data is subjected to time series change heat increment analysis, thereby obtaining time series change heat increment data. The core goal of heat increment analysis is to evaluate the temperature change of the chip due to factors such as power consumption, conduction and radiation during the load state change process. First, it is necessary to calculate the power consumption in each time series segment according to the circuit layout and load state of the chip, combined with the time series data of current and voltage. The power consumption data can be calculated by the electrical characteristics of resistance, inductance and capacitance, and the heat generated in the circuit can be estimated according to the instantaneous values ​​of current and voltage. The heat increment is further estimated according to factors such as the working environment and heat dissipation mode of the chip. The numerical simulation method based on the heat conduction equation can be used to calculate the heat increment. In order to realize the time series change heat increment analysis, the time series data of the chip load state is matched with its corresponding power consumption to obtain the heat increment in each time series segment. On this basis, a thermal model (such as a thermoelectric effect model) is used to calculate the temperature change and determine the temperature increment in each time series segment. Finally, the obtained time series change heat increment data reflects the temperature change of the chip in each working stage. Through these data, the thermal response characteristics of the chip when the load changes can be judged, and data support can be provided for subsequent heat flow simulation. Based on the time-varying heat increment data, the heat flow cycle heteroscedasticity simulation is performed to obtain the heat flow cycle heteroscedasticity data. The heat flow cycle heteroscedasticity analysis is to evaluate the thermal stress and strain caused by local temperature differences in the chip during the thermal cycle. First, the time-varying heat increment data obtained in step S251 needs to be converted into heat flow data, and the conduction and flow of heat in each time segment are calculated. In this process, the heat conduction equation is needed to describe the heat transfer behavior in the chip. The size of the heat flow is related to the geometric structure, material properties (such as thermal conductivity) and temperature gradient of the chip. In order to accurately simulate the change of heat flow, the finite difference method (FDM) or finite element method (FEM) can be used to numerically simulate the heat conduction process inside the chip to calculate the heat flow changes in each time segment. On the basis of the heat flow simulation, the heteroscedasticity characteristics of the heat flow of the chip during the thermal cycle are simulated by cyclic loading. Specifically, the heteroscedasticity data of the heat flow are obtained by comparing the heat flow changes in different regions. This data reflects the local temperature fluctuations of the chip under thermal cycles, especially during the heat exchange process between the chip surface and the packaging material, changes in heat flow will cause temperature non-uniformity. Through the heat flow cycle heteroscedasticity simulation, the asymmetry of the heat flow change can be obtained, and the thermal stress distribution of the chip under different loads can be further understood, providing a basis for subsequent temperature gradient analysis and packaging stress analysis. According to the resonance range broadening data, the heat flow cycle heteroscedasticity data is used to calculate the local imbalance of thermal distribution to obtain the local imbalance data of thermal distribution. The core of this step is to analyze the local temperature imbalance caused by uneven heat flow at different frequencies and loads of the chip, thereby causing potential risks.First, according to the resonance range widening data obtained in step S235, the influence of the resonance phenomenon on the heat flow distribution during the chip operation is identified. In particular, under high-frequency and high-voltage conditions, the heat conduction and dissipation in different areas of the chip will be different, resulting in uneven temperature distribution. Using the heat flow heteroscedasticity data, the heat distribution of the chip in this state can be evaluated, and the heat distribution can be calculated by thermodynamic equations. In a specific implementation, by partitioning different areas of the chip, the temperature change trend and heat flow response of each area are analyzed. The temperature difference of different parts can be calculated using the heat balance equation, and then it can be determined which areas will have thermal imbalance. The heat transfer of each area is simulated using the heat conduction equation, and the heat flow difference between different areas is calculated to obtain the local imbalance data of the heat distribution. The analysis results help to identify the risk of overheating of the chip under high load conditions, especially the temperature imbalance problem in the chip packaging area. Through this process, the thermal stability of the chip under extreme working conditions can be predicted, and a reference can be provided for optimizing the thermal management design. The local temperature gradient anomaly analysis of the local imbalance data of the heat distribution is performed to obtain the local gradient anomaly data of the heat distribution. The purpose of the local temperature gradient anomaly analysis is to detect whether there are abnormal changes in the temperature gradients of different regions inside the chip, so as to identify potential thermal stress concentration areas. In this step, it is necessary to first use the local imbalance data of thermal distribution to analyze the temperature gradients of each region. The temperature gradient refers to the rate of change of temperature within a unit distance, which reflects the concentration of heat flow. Under high-frequency load conditions, the temperature gradient inside the chip changes dramatically due to the action of local heat sources. This change is often accompanied by the concentration of thermal stress, leading to fatigue and failure of the packaging material. In specific implementation, by performing local heat flow simulation on the local imbalance data of thermal distribution, the temperature change rate of each region is calculated to obtain the temperature gradient of each region. The local temperature gradient is analyzed using the differential method to identify those areas with abnormal temperature gradients. Especially in the contact surface, packaging interface and high-power working area of ​​the chip, these areas are often high-incidence areas of temperature gradient anomalies. The obtained local gradient anomaly data of thermal distribution can provide important information for the thermal management design of the chip, help evaluate whether the chip will have stress problems caused by excessive temperature gradients during operation, and provide a basis for subsequent packaging stress cycle analysis. The package stress cyclic decay gradient is identified based on the local gradient anomaly data of thermal distribution, so as to obtain the package stress cyclic decay gradient. The core goal of this step is to analyze the package stress changes caused by the abnormal temperature gradient during the thermal load change of the chip, and then identify the fatigue decay of the packaging material. First, the thermal stress caused by temperature difference is identified through the local gradient anomaly data of thermal distribution combined with the thermal stress model. Specifically, the distribution of thermal stress in the packaging material is calculated using the thermal expansion coefficient and the elastic modulus of the material. Especially in areas with abnormal temperature gradients, the thermal stress in these areas will increase significantly, resulting in stress concentration in the packaging material.The finite element analysis (FEA) method is used to simulate the distribution of thermal stress and further identify the cyclic changes of thermal stress during the packaging process. Through the timing analysis of the package stress, the decay mode of the stress can be identified and the package stress cyclic decay gradient can be obtained. This gradient reflects the degree of performance degradation of the package structure due to changes in stress and temperature after the package material has undergone multiple thermal cycles. Finally, the reliability of the chip package can be predicted and its service life under high-frequency and high-voltage load conditions can be evaluated through the package stress cyclic decay gradient data. These data are of great guiding significance for the subsequent chip design and testing process.

[0082] Preferably, step S255 includes the following steps:

[0083] Conduct neighborhood thermal stress concentration differentiation analysis on the local gradient anomaly data of thermal distribution to obtain neighborhood thermal stress concentration difference data;

[0084] Obtain chip component packaging design data;

[0085] Based on the neighborhood thermal stress concentration difference data, the continuous entropy value fluctuation analysis is carried out to obtain the thermal stress continuous entropy value fluctuation data;

[0086] According to the continuous entropy value fluctuation data of thermal stress, the thermal deformation stress conversion calculation of the packaging material is performed on the chip component packaging design data to obtain the material thermal deformation stress conversion data;

[0087] The package stress cyclic decay gradient is identified based on the material thermal deformation stress conversion data to obtain the package stress cyclic decay gradient.

[0088] In an embodiment of the present invention, the local thermal stress concentration difference analysis of the local gradient anomaly data of the thermal distribution is performed to identify the local thermal stress concentration area caused by the temperature gradient anomaly in the chip package. The core goal of this step is to quantify the difference in thermal stress distribution and evaluate the degree of thermal stress concentration in each region, so as to provide data support for the design and selection of packaging materials. First, the temperature gradient changes in different regions of the chip surface and its packaging structure are analyzed using the local gradient anomaly data of the thermal distribution. In this step, a differentiation method is used to evaluate the distribution of thermal stress, especially focusing on the temperature gradient changes on the chip surface, interface and contact layer. By calculating the deviation of the temperature gradient in different regions and combining the thermal expansion coefficient, the concentration of thermal stress in certain regions can be identified. For each neighborhood region, the degree of thermal stress differentiation is calculated using a differentiation analysis technique (such as a local difference coefficient method) based on the temperature gradient anomaly value. This process involves performing a difference calculation on the local temperature gradient, and then evaluating the concentration of thermal stress in the adjacent regions. These analysis results can help identify the areas in the package that are most prone to stress concentration and determine the thermal stress concentration difference data. The packaging design data of the chip element is obtained to further evaluate the propagation and transformation of stress in the chip packaging structure. Chip package design data includes information such as package geometry, selected package material properties, package interface materials, thermal conductivity, expansion coefficient of package materials, etc. The process of obtaining package design data usually depends on package drawings and material specifications generated during chip design. These data provide the necessary geometric and physical property basis for subsequent stress analysis. For example, by obtaining package design drawings, the specific size, shape, material type and specification of the package structure, as well as parameters such as thermal conductivity and elastic modulus of different materials can be obtained. In addition, package design data should also include thermal management solutions, heat dissipation structures, thermal expansion coefficient matching solutions, etc. used in the packaging process, which are essential for thermal stress analysis. Package design data can be extracted and organized through CAD software or chip design tools to provide detailed physical properties and design details. Based on the neighborhood thermal stress concentration difference data, a continuous entropy fluctuation analysis is performed to obtain the continuous entropy fluctuation data of thermal stress. The purpose of entropy fluctuation analysis is to evaluate the complexity and uncertainty of thermal stress changes caused by thermal stress concentration in chip packaging. First, based on the neighborhood thermal stress concentration difference data, the information entropy method is used to analyze the fluctuation of thermal stress. Information entropy is used to quantify the degree of chaos and uncertainty of the system state. In thermal stress analysis, entropy fluctuation analysis can describe the degree of change in temperature and thermal stress between different regions, especially in the case of periodic thermal cycles, the volatility of thermal stress will affect the long-term performance of packaging materials. Specifically, by performing time series analysis on thermal stress difference data, the entropy value of thermal stress change can be calculated.On this basis, through the fluctuation calculation, the persistence characteristics of thermal stress fluctuations, that is, the continuous entropy value fluctuation data of thermal stress, are obtained. This data reflects the nonlinear change characteristics of thermal stress. Especially under high frequency and high voltage loads, the chip packaging structure will be subjected to frequent thermal shocks, which will lead to fatigue and failure of the packaging material. According to the continuous entropy value fluctuation data of thermal stress, combined with the chip component packaging design data, the thermal deformation stress of the packaging material is converted and calculated to obtain the material thermal deformation stress conversion data. The purpose of this process is to evaluate the deformation behavior of the packaging material under the influence of thermal stress fluctuations, and then quantify the thermal deformation and stress response of the material. First, based on the continuous entropy value fluctuation data of thermal stress, the thermodynamic model is used to calculate the thermal deformation of the packaging material under different temperature fluctuation conditions. The thermal deformation stress conversion calculation generally depends on the thermal expansion coefficient, elastic modulus and temperature dependence of the material. By analyzing the response of the packaging material under different temperature fields, the material deformation caused by thermal stress in each area can be obtained. In the specific implementation, based on the entropy value fluctuation data, the stress-strain relationship is used to calculate the material thermal deformation, and combined with the material properties in the packaging design data, the thermal deformation stress conversion is completed. The conversion calculation not only considers the linear expansion effect of the material, but also needs to consider the nonlinear effect and temperature dependence. Through the thermal deformation stress conversion, the deformation and stress distribution of the packaging material under the action of thermal stress can be obtained, and the thermal deformation stress conversion data of the material can be obtained. Based on the thermal deformation stress conversion data of the material, the packaging stress cyclic decay gradient is identified to obtain the packaging stress cyclic decay gradient. The core of this process is to identify the performance degradation of the packaging material caused by thermal stress fluctuations and cumulative effects in multiple thermal cycles by analyzing the thermal deformation stress conversion data. First, according to the thermal deformation stress conversion data of the material, the thermal cycle simulation method is used to model the thermal stress evolution process generated by the packaging material after multiple thermal cycles. By simulating the stress response within different temperature change ranges, the fatigue decay degree of the material under multiple thermal stresses is calculated. This process usually uses the cyclic loading method to simulate the performance of the material in repeated thermal cycles, and analyzes the cyclic decay caused by thermal stress based on the fatigue life model of the packaging material. The gradient of thermal stress decay is identified through continuous loading and unloading of thermal stress. This process helps to identify the reliability and durability of the packaging material and predict the impact of packaging stress on the long-term stability of the chip. Ultimately, by identifying the cyclic decay gradient of package stress, the service life of the chip package can be evaluated, especially the stability under long-term high-frequency and high-voltage load conditions, providing theoretical support for chip design and packaging optimization.

[0089] Preferably, step S3 comprises the following steps:

[0090] Step S31: performing cycle number influence weight analysis on the package stress cycle decay gradient to obtain the stress decay cycle number influence weight;

[0091] Step S32: identifying the voltage drift level of the package stress cycle decay gradient according to the influence weight of the stress decay cycle number, and obtaining voltage drift level data;

[0092] Step S33: performing carrier migration efficiency decay calculation based on the voltage drift level data and the package stress cycle decay gradient to obtain carrier migration efficiency decay data;

[0093] Step S34: quantifying chip performance degradation according to the voltage drift level data and the carrier migration efficiency degradation data to obtain chip performance degradation quantification data.

[0094] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes:

[0095] Step S31: performing cycle number influence weight analysis on the package stress cycle decay gradient to obtain the stress decay cycle number influence weight;

[0096] In an embodiment of the present invention, by analyzing the package stress cycle decay gradient, the influence weight of different cycle numbers on stress decay is identified, thereby evaluating the influence of thermal stress cycles on packaging materials. First, by quantitatively analyzing the periodic changes of package stress, the contribution of each thermal cycle to stress and its decay trend are calculated. In this process, the package stress cycle decay gradient data is first segmented to identify the stress levels corresponding to different cycle numbers. According to temperature fluctuations and thermal expansion characteristics, different cycle numbers are weighted for analysis. Specifically, according to the number and amplitude of thermal cycles, the weighted average method is used to calculate the influence of stress decay in each round of thermal cycles. The weight distribution is based on the number and periodic characteristics of thermal cycles. The early cycle often has a greater impact on the material, and as time goes by, the increase in the number of cycles gradually decreases the impact of stress decay. Therefore, when performing weight analysis on different cycle numbers, it is necessary to weight according to the amplitude of stress decay to obtain the influence weight of the number of stress decay cycles. For example, by weighted averaging thermal stress data of multiple different cycle numbers, the difference in the influence of initial and long-term thermal cycles on package stress is identified. This data can help further analyze package durability and performance degradation.

[0097] Step S32: identifying the voltage drift level of the package stress cycle decay gradient according to the influence weight of the stress decay cycle number, and obtaining voltage drift level data;

[0098] In an embodiment of the present invention, based on the weight of the number of stress decay cycles, the voltage drift level of the package stress cycle decay gradient is identified, and then the voltage drift level data is obtained. Voltage drift refers to the voltage change of the chip during operation due to the effect of the package stress, which is usually accompanied by the thermal expansion or contraction of the package material, causing the change of the circuit parameters and affecting the stability of the chip. First, according to the weight data of the number of stress decay cycles obtained in step S31, the voltage drift caused by the package stress decay under different stress cycles is analyzed. The relationship between the package stress change and the voltage drift is established using a mathematical model, and the voltage drift formula is usually used: ΔV=f(ΔE,T,π); wherein ΔV represents the voltage change, ΔE represents the stress change of the material, T represents the temperature change, and π represents the strain of the material. According to this model, the voltage drift caused by the stress change under different cycles is calculated, and it is divided into different drift levels according to the amplitude of the voltage drift. Through the division of the voltage drift level, the voltage stability of the chip after long-term operation, especially under the influence of multiple thermal cycles, can be determined. This process not only quantifies the size of the voltage drift, but also requires dividing the levels by voltage offset and response time, such as: slight drift, medium drift, severe drift, etc.

[0099] Step S33: performing carrier migration efficiency decay calculation based on the voltage drift level data and the package stress cycle decay gradient to obtain carrier migration efficiency decay data;

[0100] In an embodiment of the present invention, a carrier migration efficiency decay calculation is performed based on the voltage drift level data and the package stress cycle decay gradient to obtain the carrier migration efficiency decay data. Carrier migration efficiency refers to the migration ability of carriers (such as electrons, holes, etc.) in a chip under the action of an electric field, which is usually closely related to factors such as material quality, temperature, and stress. First, a mathematical model of carrier migration efficiency is established in combination with the voltage drift level and the package stress cycle decay gradient. In this process, the migration efficiency of carriers is affected by thermal stress. As the packaging material expands and contracts thermally, the defects and stress distribution inside the material will affect the migration ability of carriers. Specifically, the change in carrier migration efficiency can be characterized by the following formula: Where F represents the carrier migration efficiency, F 0 is the initial value of the carrier migration efficiency, E a is the activation energy, K Bis the Boltzmann constant, T is the temperature, β is the thermal stress coefficient, and a is the stress value of the packaging material. This formula, combined with the voltage drift level data, calculates the degree of degradation of carrier migration efficiency under different thermal stresses. This calculation can not only quantify the degradation of carrier migration efficiency, but also reflect the impact of long-term voltage drift and stress cycles on carrier migration ability, providing basic data for the subsequent quantification of chip performance degradation.

[0101] Step S34: quantifying chip performance degradation according to the voltage drift level data and the carrier migration efficiency degradation data to obtain chip performance degradation quantification data.

[0102] In an embodiment of the present invention, the degree of chip performance degradation is quantified based on the voltage drift level data and the carrier migration efficiency degradation data, thereby obtaining the chip performance degradation quantitative data. The performance degradation of the chip is mainly reflected in the decline in its computing power, power consumption, response speed, etc. By quantifying the voltage drift and the carrier migration efficiency degradation, the performance degradation of the chip during long-term operation can be accurately evaluated. First, based on the voltage drift level data and the carrier migration efficiency degradation data, the weighted average method is used to combine the influence of the two to obtain the quantitative data of the overall performance degradation of the chip. Voltage drift affects the voltage stability of the chip, and the degradation of the carrier migration efficiency directly affects the operating frequency and energy consumption of the chip. The combined effect of the two determines the overall performance of the chip.

[0103] Preferably, step S33 includes the following steps:

[0104] Step S331: performing benchmark processing on the voltage drift level data to obtain standardized voltage drift level data;

[0105] Step S332: performing a multivariate regression analysis of the decay factor according to the standardized voltage drift level data and the package stress cycle decay gradient to obtain the multivariate regression data of the decay factor;

[0106] Step S333: performing carrier migration efficiency decay prediction based on decay factor multivariate regression data to obtain carrier migration efficiency decay prediction data;

[0107] Step S334: quantifying the deviation range of the carrier migration performance degradation prediction data to obtain the performance degradation deviation quantification range;

[0108] Step S335: performing carrier migration performance degradation calculation based on the performance degradation deviation quantization range to obtain carrier migration performance degradation data.

[0109] In an embodiment of the present invention, the voltage drift level data is benchmarked, and the original voltage drift level data is converted into standardized data for subsequent analysis and comparison. Benchmarking is to convert data into a dimensionless standard form. A commonly used method is zero mean unit variance processing to ensure that the data is comparable under different scales and magnitudes. In this process, the voltage drift level data is first obtained. Usually, these data are recorded based on the voltage drift situation under different working conditions of the chip, and the values ​​are affected by various factors such as the chip working environment, usage time, and stress cycle. In order to avoid the influence of these factors, the mean and standard deviation of the voltage drift level data are first calculated, and then the original data is standardized, and the data is converted into standardized voltage drift level data using the following formula. Through this processing, the voltage drift level data is converted into standardized data with zero mean and unit variance, which can avoid the influence between different dimensions, making the subsequent regression analysis more accurate and reliable. Through the multivariate regression analysis of the decay factor, a relationship model between the standardized voltage drift level data and the package stress cycle decay gradient is established, thereby obtaining the regression data of the decay factor. Regression analysis can reveal the degree of influence of different factors on chip performance degradation. First, the standardized voltage drift level data and the package stress cycle decay gradient data are selected as independent variables, which are used as inputs, and the chip performance degradation factor is used as the dependent variable. Using the multivariate regression model, combined with the known data set, the multivariate regression model can solve the regression coefficient by the least squares method. The least squares method optimizes the regression coefficient by minimizing the square difference between the predicted value and the actual value, thereby obtaining the optimal regression relationship. After obtaining the regression coefficient, the specific impact of voltage drift and package stress cycle on chip performance degradation can be further analyzed to obtain the multivariate regression data of the degradation factor. This data reveals the contribution of each variable to performance degradation and provides a basis for subsequent analysis. Based on the multivariate regression data of the degradation factor, the carrier migration efficiency degradation is predicted to obtain the carrier migration efficiency degradation prediction data. The carrier migration efficiency degradation reflects the change of the migration efficiency of carriers (electrons, holes, etc.) inside the chip over time. This performance degradation directly affects the working speed and power consumption of the chip. In this process, the regression data of the decay factor obtained in step S332 is first used to combine it with the carrier migration model of the chip to predict the decay of the carrier migration performance. This decay can be described by the mathematical model of the carrier migration performance, and the predicted data of the decay of the carrier migration performance over time is calculated by substituting the regression data of the decay factor. This data can provide a basis for the long-term reliability analysis and performance decay evaluation of the chip. The deviation range of the carrier migration performance decay prediction data is quantified, and the variation range of the carrier migration performance decay is further quantified to more accurately predict the long-term performance changes of the chip.First, by analyzing the predicted data of carrier migration performance decay, the statistical characteristics of the data such as the maximum value, minimum value, mean value and standard deviation are calculated. Then, these statistical characteristics are used to define the deviation range of performance decay, and the fluctuation range of performance decay is obtained by quantifying the deviation range, so as to further quantify the decay degree of carrier migration performance under different working conditions, and provide more refined quantitative data for chip reliability assessment. Based on the performance decay deviation quantification range obtained in step S334, the carrier migration performance decay calculation is performed, and finally the carrier migration performance decay data is obtained. The calculation process simulates the actual change of carrier migration performance decay according to the known deviation range. First, according to the deviation range of performance decay, the Monte Carlo method or other random process simulation method is used for simulation. By generating multiple random samples, the carrier migration performance decay under different conditions is simulated to obtain multiple decay data points. Through statistical analysis of these data points, the final data of carrier migration performance decay can be obtained. For example, the final carrier migration performance decay data can be obtained by calculating the mean and standard deviation of the decay data. This step can accurately predict the changing trend of carrier migration efficiency, provide detailed information on future chip performance degradation, and provide an important basis for chip design optimization and reliability improvement.

[0110] Preferably, step S4 comprises the following steps:

[0111] Step S41: normalizing the chip performance impairment quantified data to obtain chip performance impairment normalized data;

[0112] Step S42: performing failure mode generalization processing according to chip performance degradation normalization data to obtain performance degradation failure mode generalization data;

[0113] Step S43: collecting test results based on the performance degradation failure mode generalization data, obtaining a chip performance failure mode result report, and feeding back the chip performance failure mode result report to the terminal.

[0114] In an embodiment of the present invention, the quantitative data of chip performance degradation is normalized so as to convert data of different dimensions or ranges into a unified standard, eliminate the influence caused by the difference in data scale, and ensure the fairness and consistency of subsequent analysis. Normalization scales the data to a fixed range, usually the interval [0,1], to facilitate the comparison and analysis of different types of loss data. First, the quantitative data of chip performance degradation are obtained. These data reflect the performance degradation of the chip under different usage cycles and working conditions, and are usually obtained through multiple tests and calculations. When normalizing these data, it is first necessary to calculate the minimum and maximum values ​​of the data. The main purpose of this step is to ensure that the range of all chip performance degradation data is between [0,1], thereby eliminating the influence of different dimensions and scales on subsequent analysis, so that various types of data are evaluated and compared under the same standard. After normalization, the obtained chip performance degradation normalized data can be used for subsequent failure mode analysis and prediction analysis, thereby providing a basis for chip design optimization and reliability evaluation. According to the normalized chip performance impairment data, the failure mode is generalized, and the performance impairment mode of a specific chip under specific conditions is deduced into a more universal failure mode, providing a theoretical basis for the long-term reliability prediction and design improvement of the chip. In this process, the performance impairment data of different chips are first collected. The data covers multiple factors such as the use cycle, workload, and environmental conditions of different chips. Based on these data, a failure mode generalization model suitable for different chips and different usage scenarios is constructed. The specific failure mode generalization processing can be achieved through statistical analysis methods, clustering algorithms, or machine learning models. First, the chip performance impairment data is clustered through clustering analysis, and data points with similar performance impairment characteristics are classified into the same category. Commonly used clustering algorithms include K-means clustering, DBSCAN clustering, etc. According to the clustering results, different types of chip failure modes can be revealed, and a weight or influence coefficient can be assigned to each failure mode. In addition, failure mode generalization can also be achieved through data dimensionality reduction and principal component analysis (PCA). PCA can reduce high-dimensional data to low-dimensional space, making the representation of failure modes more concise and clear. For example, through the PCA method, the principal components of chip performance degradation can be found, and the failure modes can be summarized and concluded based on these principal components. In this way, a large amount of performance data can be converted into more representative and widely applicable failure modes, and performance degradation failure mode generalization data can be obtained. Based on the performance degradation failure mode generalization data obtained in step S42, the test results are collected and a chip performance failure mode result report is generated, so as to realize the performance prediction and evaluation of the chip under different working environments and usage conditions, and finally the report is fed back to the terminal for chip quality control and design improvement. First, based on the failure mode generalization data, multiple typical test scenarios and workloads are selected to conduct actual tests on the chip.In each test scenario, the chip's operating status is monitored, its performance degradation is recorded, and the failure mode of the chip is analyzed in combination with the failure mode generalization data. For example, under the conditions of high temperature, high pressure, and long-term continuous operation, the chip will experience different performance degradation processes. For each situation, relevant performance data is collected. Test data can be collected in real time through automated test equipment or sensors. The data collection process includes recording chip parameters such as current, voltage, temperature, frequency, and chip performance indicators such as working efficiency, power consumption, and delay. The test results are analyzed based on the failure mode generalization data to confirm whether the chip decays according to the expected failure mode and determine its life and reliability. After the test results are collected, a chip performance failure mode result report is generated. The report content includes the chip's failure mode type, the impact of various failure modes, the trend of chip performance degradation, etc. By statistically analyzing the test results, the performance stability and reliability of the chip under different working environments can be evaluated, potential weak links or design defects can be identified, and a basis for chip improvement and optimization can be provided. Finally, the performance failure mode result report will be transmitted to the terminal through the corresponding feedback mechanism so that designers, engineers or manufacturers can further verify and adjust the chip. In actual applications, the terminal device will optimize the chip design, manufacturing process and working environment based on the information in the report, thereby improving the overall performance and reliability of the chip. Through this series of operations, the prediction and evaluation of chip performance failure modes can be completed, and the necessary data support can be provided for subsequent chip development and optimization.

[0115] Preferably, the present invention further provides a chip simulation model testing system, which is used to execute the chip simulation model testing method as described above, and the chip simulation model testing system comprises:

[0116] The component rated load analysis module is used to obtain chip design data; based on the chip design data, the circuit node component rated load analysis is performed to obtain the node component rated load data;

[0117] The package stress cycle decay identification module is used to simulate the high-frequency and high-voltage load state of the node element rated load data based on the chip simulation model to obtain the chip load state time series segmented data; the package stress cycle decay gradient is identified on the chip load state time series segmented data to obtain the package stress cycle decay gradient;

[0118] The performance degradation quantification module is used to perform carrier migration efficiency degradation calculation based on the package stress cycle decay gradient to obtain carrier migration efficiency degradation data; and to quantify chip performance degradation based on the carrier migration efficiency degradation data to obtain chip performance degradation quantification data;

[0119] The test result collection and feedback module is used to generalize the failure mode according to the chip performance degradation quantification data to obtain the performance degradation failure mode generalization data; collect test results based on the performance degradation failure mode generalization data to obtain the chip performance failure mode result report, and feed back the chip performance failure mode result report to the terminal.

[0120] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0121] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A chip simulation model testing method, characterized in that: The following steps are involved: Step S1: Obtain chip design data; Perform circuit node component rated load analysis based on chip design data to obtain node component rated load data; Step S2: Based on the chip simulation model, a high-frequency and high-voltage load state simulation is performed on the rated load data of the node element to obtain chip load state time series segmented data; Performing package stress cycle decay gradient identification on chip load state time series segmented data to obtain package stress cycle decay gradient; Step S3: performing carrier migration efficiency decay calculation based on the packaging stress cycle decay gradient to obtain carrier migration efficiency decay data; Quantify the chip performance degradation according to the carrier migration efficiency degradation data to obtain the chip performance degradation quantitative data; Step S4: performing failure mode generalization processing according to the chip performance degradation quantification data to obtain performance degradation failure mode generalization data; The test results are collected based on the generalized data of the performance degradation failure mode, a chip performance failure mode result report is obtained, and the chip performance failure mode result report is fed back to the terminal.

2. The chip simulation model testing method according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: Obtain chip design data; Step S12: extracting the circuit layout of the chip design data to obtain chip circuit layout data; Step S13: classify and mark the circuit node components of the chip circuit layout data to obtain circuit node component classification mark data; Step S14: performing circuit node component rated load analysis on the circuit node component classification labeling data based on the chip design data to obtain node component rated load data.

3. The chip simulation model testing method according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: Based on the chip simulation model, a high-frequency and high-voltage load state simulation is performed on the rated load data of the node element to obtain the high-frequency and high-voltage load state data of the chip; wherein the high-frequency and high-voltage refer to: high voltage and high frequency; Step S22: performing time-series segmentation processing on the chip high-frequency and high-voltage load state data to obtain chip load state time-series segmented data; Step S23: performing resonance range widening analysis on the chip load state time series segmented data to obtain resonance range widening data; Step S24: performing package stress cycle decay gradient identification on the chip load state time series segmented data according to the resonance range widening data to obtain the package stress cycle decay gradient.

4. The chip simulation model testing method according to claim 3, characterized in that: Step S23 includes the following steps: Step S231: performing time-series segmented electromagnetic field intensity analysis on the chip load state time-series segmented data to obtain time-series segmented electromagnetic field intensity data; Step S232: performing resonance frequency coupling based on the time-series segmented electromagnetic field intensity data to obtain the time-series segmented resonance frequency; Step S233: analyzing the time-varying characteristics of the time-series segmented resonant frequency to obtain time-varying characteristic resonant frequency data; Step S234: calculating the wavelength expansion amplitude difference according to the time-varying characteristic resonant frequency data to obtain the resonant frequency wavelength expansion amplitude difference; Step S235: performing resonance range widening analysis based on the resonance frequency wavelength expansion amplitude difference to obtain resonance range widening data.

5. The chip simulation model testing method according to claim 3, characterized in that: Step S25 includes the following steps: Step S251: performing time series variation heat increment analysis on the chip load state time series segmented data to obtain time series variation heat increment data; Step S252: performing a heat flow cycle heteroscedasticity simulation based on the time-series heat increment data to obtain heat flow cycle heteroscedasticity data; Step S253: performing heat distribution local imbalance calculation on the heat flow cycle heteroscedasticity data according to the resonance range widening data to obtain heat distribution local imbalance data; Step S254: performing local temperature gradient anomaly analysis on the local imbalance data of thermal distribution to obtain local gradient anomaly data of thermal distribution; Step S255: performing package stress cyclic decay gradient identification according to the local gradient anomaly data of the thermal distribution to obtain the package stress cyclic decay gradient.

6. The chip simulation model testing method according to claim 5, characterized in that: Step S255 includes the following steps: Conduct neighborhood thermal stress concentration differentiation analysis on the local gradient anomaly data of thermal distribution to obtain neighborhood thermal stress concentration difference data; Obtain chip component packaging design data; Based on the neighborhood thermal stress concentration difference data, the continuous entropy value fluctuation analysis is carried out to obtain the thermal stress continuous entropy value fluctuation data; According to the continuous entropy value fluctuation data of thermal stress, the thermal deformation stress conversion calculation of the packaging material is performed on the chip component packaging design data to obtain the material thermal deformation stress conversion data; The package stress cyclic decay gradient is identified based on the material thermal deformation stress conversion data to obtain the package stress cyclic decay gradient.

7. The chip simulation model testing method according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: performing cycle number influence weight analysis on the package stress cycle decay gradient to obtain the stress decay cycle number influence weight; Step S32: identifying the voltage drift level of the package stress cycle decay gradient according to the influence weight of the stress decay cycle number, and obtaining voltage drift level data; Step S33: performing carrier migration efficiency decay calculation based on the voltage drift level data and the package stress cycle decay gradient to obtain carrier migration efficiency decay data; Step S34: quantifying chip performance degradation according to the voltage drift level data and the carrier migration efficiency degradation data to obtain chip performance degradation quantification data.

8. The chip simulation model testing method according to claim 7, characterized in that: Step S33 includes the following steps: Step S331: performing benchmark processing on the voltage drift level data to obtain standardized voltage drift level data; Step S332: performing a multivariate regression analysis of the decay factor according to the standardized voltage drift level data and the package stress cycle decay gradient to obtain the multivariate regression data of the decay factor; Step S333: performing carrier migration efficiency decay prediction based on decay factor multivariate regression data to obtain carrier migration efficiency decay prediction data; Step S334: quantifying the deviation range of the carrier migration performance degradation prediction data to obtain the performance degradation deviation quantification range; Step S335: performing carrier migration performance degradation calculation based on the performance degradation deviation quantization range to obtain carrier migration performance degradation data.

9. The chip simulation model testing method according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: normalizing the chip performance impairment quantified data to obtain chip performance impairment normalized data; Step S42: performing failure mode generalization processing according to chip performance degradation normalization data to obtain performance degradation failure mode generalization data; Step S43: collecting test results based on the performance degradation failure mode generalization data, obtaining a chip performance failure mode result report, and feeding back the chip performance failure mode result report to the terminal.

10. A chip simulation model testing system, characterized in that: A chip simulation model testing method according to claim 1, wherein the chip simulation model testing system comprises: The component rated load analysis module is used to obtain chip design data; based on the chip design data, the circuit node component rated load analysis is performed to obtain the node component rated load data; The package stress cycle decay identification module is used to simulate the high-frequency and high-voltage load state of the node element rated load data based on the chip simulation model to obtain the chip load state time series segmented data; the package stress cycle decay gradient is identified on the chip load state time series segmented data to obtain the package stress cycle decay gradient; The performance degradation quantification module is used to perform carrier migration efficiency degradation calculation based on the package stress cycle decay gradient to obtain carrier migration efficiency degradation data; and to quantify chip performance degradation based on the carrier migration efficiency degradation data to obtain chip performance degradation quantification data; The test result collection and feedback module is used to generalize the failure mode according to the chip performance degradation quantification data to obtain the performance degradation failure mode generalization data; collect test results based on the performance degradation failure mode generalization data to obtain the chip performance failure mode result report, and feed back the chip performance failure mode result report to the terminal.

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