Image data processing chip, electronic device, and image data processing method

Abstract

The invention discloses an image data processing chip, electronic equipment and an image data processing method, and relates to the technical field of image data processing device.The image data processing chip comprises a first display link used for reading first source data from a memory of the electronic equipment, converting the first source data into first image data and sending the first image data to a second display link; the first image data is matched with display parameters of a first display screen of the electronic equipment and used for driving the first display screen to display a first image; the write-back branch is used for writing the first image data back to the memory when the electronic equipment is in the first display mode; and the second display link is used for reading the first image data from the memory in the first display mode, and driving a second display screen of the electronic equipment to display the first image based on the first image data.

Description

Technical Field

[0001] The present application relates to the technical field of image data processing equipment, and in particular to an image data processing chip, an electronic device, and an image data processing method. Background Art

[0002] At present, in order to meet users' multi-screen display needs, electronic devices such as smart phones, laptops, multimedia conferencing systems, and vehicle-mounted central control devices require image data processing chips that can simultaneously control multiple (at least two) display screens for image display.

[0003] When the image data processing chip in the prior art controls multiple display screens to display images simultaneously, the amount of data processed is large, resulting in high power consumption. Summary of the invention

[0004] In view of the above problems, the present application provides an image data processing chip, an electronic device and an image data processing method to achieve the purpose of reducing the amount of data processing when multiple display screens display images simultaneously. The specific scheme is as follows:

[0005] The first aspect of the present application provides an image data processing chip, comprising:

[0006] A first display link, the first display link is used to read first source data from a memory of the electronic device, convert the first source data into first image data, the first image data matches a display parameter of a first display screen of the electronic device, and is used to drive the first display screen to display a first image;

[0007] A write-back branch, the write-back branch is used to write the first image data back to the memory when the electronic device is in the first display mode;

[0008] The second display link is used in the first display mode to read the first image data from the memory, and drive the second display screen of the electronic device to display the first image based on the first image data.

[0009] Optionally, in the above-mentioned image data processing chip, the image data processing chip further includes: a switching branch, the switching branch being used to construct a data processing path matching display parameters of the second display screen based on the second display link in the first display mode.

[0010] Optionally, in the above-mentioned image data processing chip, the second display link includes a data reading module, a display processing module and a timing control module which are sequentially connected between the memory and the second display screen;

[0011] In the second display link, the data reading module is used to select to read the first image data from the memory or read the second source data different from the first source data according to the display mode of the electronic device; the display processing module includes a plurality of display processing units sequentially connected between the data reading module and the timing control module, and the display processing unit is used to process the data input by the data reading module; the timing control module is used to perform timing matching between the image data input by the display processing module or the switching branch and the second display screen based on the display parameters of the second display screen;

[0012] Wherein, for the display processing module in the second display link, if it is in the first display mode, the switching branch can bypass at least part of the display processing units in the display processing module.

[0013] Optionally, in the above-mentioned image data processing chip, the switching branch is used to bypass all display processing units in the display processing module in the first display mode;

[0014] Or, the plurality of display processing units include a target display processing unit connected to the timing control module;

[0015] The target display processing unit is used to match the image parameters of the input data with the display parameters of the second display screen;

[0016] The switching branch is used to bypass other display processing units between the data reading module and the target display processing unit in the first display mode.

[0017] Optionally, in the above-mentioned image data processing chip, the electronic device further includes a second display mode, in which the images displayed on the first display screen and the second display screen are different, and the write-back branch is in a disabled state;

[0018] The switch branch is used to disconnect in the second display mode so that the entire path of the second display link is connected between the memory and the second display screen.

[0019] Optionally, in the above-mentioned image data processing chip, if in the second display mode, the second display link is used to read second source data different from the first source data from the memory, convert the second source data into second image data matching the display parameters of the second display screen, and drive the second display screen to display a second image having different content from the first image based on the second image data.

[0020] Optionally, in the above-mentioned image data processing chip, the image data processing chip includes:

[0021] Multiple parallel data reading channels for reading data from the memory;

[0022] A plurality of first display processing channels connected to the data reading channels in a one-to-one correspondence, and used for preprocessing the data input by the corresponding data reading channels;

[0023] A display processing component connected to each of the first display processing channels, and configured to perform layer overlay on input of the first display processing channel;

[0024] Two second display processing channels respectively connected to the display processing component, used to match image parameters of data input by the display processing component with display parameters of the first display screen and the second display screen respectively;

[0025] Part of the plurality of data reading channels and part of the first display processing channel are configured as a first display link, and part of the plurality of data reading channels and part of the first display processing channel are configured as a second display link;

[0026] The input end of the write-back branch is connected to the input end and the output end of each second display processing channel respectively, and is used for selecting the image data to be written back;

[0027] The output ends of multiple data reading channels and the input ends and output ends of each second display processing channel are connected to a switching branch, and the switching branch is used to build a data processing path matching the display parameters of the second display screen based on the second display link in the first display mode.

[0028] A second aspect of the present application provides an electronic device, including:

[0029] Memory;

[0030] An image data processing chip connected to a memory includes: a first display link, the first display link is used to read first source data from a memory of an electronic device, convert the first source data into first image data, the first image data matches display parameters of a first display screen of the electronic device, and is used to drive the first display screen to display a first image; a write-back branch, the write-back branch is used to write the first image data back to the memory when the electronic device is in a first display mode; and a second display link, in the first display mode, the second display link is used to read the first image data from the memory, and drive a second display screen of the electronic device to display the first image based on the first image data.

[0031] A third aspect of the present application provides an image data processing method, comprising:

[0032] Reading first source data from the memory, converting the first source data into first image data, the first image data being adapted to display parameters of the first display screen, and being used to drive the first display screen to display the first image;

[0033] If the electronic device is in the first display mode, after the image data is written back to the memory, the first image data is read from the memory, and the second display screen of the electronic device is driven to display the first image based on the first image data.

[0034] A fourth aspect of the present application provides another electronic device, including an image data processing chip;

[0035] The image data processing chip is used to read the first source data from the memory, convert the first source data into first image data, the first image data is adapted to the display parameters of the first display screen, and is used to drive the first display screen to display the first image; if the electronic device is in the first display mode, the image data processing chip is also used to write the image data back to the memory, read the first image data from the memory, and drive the second display screen of the electronic device to display the first image based on the first image data.

[0036] By means of the above technical solution, in the technical solution of the present application, the image data processing chip can read the first source data from the memory through the first display link, convert the first source data into the first image data matching the display parameters of the first display screen, and drive the first display screen to display the image through the first image data. In the first display mode, the image data processing chip can also write the first image data back to the memory through the write-back branch, so that the second display link can read the first image data from the memory, and drive the second display screen to display the first image based on the first image data. In this way, when the second display screen and the first display screen need to display the same image, in the first display mode, the second display link can directly read the first image data converted by the data processing of the first display link from the storage device, so that the second display link can at least save the data processing process of converting the source data into the image data, thereby reducing the data processing amount of the second display link, and further reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0038] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0039] Figure 1 A schematic diagram of the principle of an image data processing chip in an electronic device controlling two display screens to display images;

[0040] Figure 2 A schematic diagram of the structure of an image data processing chip provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the structure of another image data processing chip provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the structure of another image data processing chip provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the structure of another image data processing chip provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram showing the principle of the image data processing chip controlling the first display screen and the second display screen to display images;

[0045] Figure 7 An equivalent circuit diagram of an image data processing chip provided in an embodiment of the present application;

[0046] Figure 8 Based on Figure 7 The equivalent circuit shown is constructed Figure 4 The schematic diagram of the principle of the image data processing chip shown;

[0047] Fig. 9 Based on Figure 7 The equivalent circuit shown is constructed Figure 5 The schematic diagram of the principle of the image data processing chip shown;

[0048] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0049] Fig.11 A schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

[0050] Fig.12A flowchart of an image data processing method provided in an embodiment of the present application.

[0051] Reference numerals:

[0052] 100-memory; 101-image data processing chip; 102-first display screen; 103-second display screen; 104-first display link; 105-second display link; 106-data reading module; 107-display processing module; 108-timing control module; 109-preprocessing unit; 110-synthesis unit; 111-post-processing unit; 112-write back branch; 113-switching branch; 114-data reading channel; 115-first display processing channel; 116-display processing component; 117-second display processing channel; 118-first multiplexer; 119-second multiplexer; 120-third multiplexer. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0054] At present, when it is necessary to control multiple display screens to display images at the same time, the image data processing chip needs to configure independent display links for each display screen. Taking an electronic device with two display screens as an example, the principle of its image data processing chip controlling the two display screens to display images can be as follows: Figure 1 shown.

[0055] refer to Figure 1 , Figure 1 The electronic device includes: a memory 100; an image data processing chip 101 connected to the memory 100; and a first display screen 102 and a second display screen 103 respectively connected to the image data processing chip 101.

[0056] The image data processing chip 101 includes: a first display link 104 and a second display link 105. The first display screen 102 is connected to the memory 100 via the first display link 104. The second display screen 103 is connected to the memory 100 via the second display link 105.

[0057] The first display link 104 and the second display link 105 both include a data reading module 106 , a display processing module 107 and a timing control module 108 which are connected in sequence.

[0058] In the first display link 104, the data reading module 106, the display processing module 107 and the timing control module 108 are sequentially connected between the memory 100 and the first display screen 102. In the second display link 105, the data reading module 106, the display processing module 107 and the timing control module 108 are sequentially connected between the memory 100 and the second display screen 103.

[0059] In the same display link, the display processing module 107 includes a plurality of display processing units connected in sequence, and the plurality of display processing units at least include a pre-processing unit 109 (Pre-processing, referred to as pre) connected in sequence between the data reading module 106 and the timing control module 108, a synthesis unit 110 (composer, referred to as cmps) and a post-processing unit 111 (Post-processing, referred to as post).

[0060] Optionally, the memory 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM for short). The timing control module 108 includes a display timing generator (Display Timing Generator, or Display Timing Gen).

[0061] The first display screen 102 and the second display screen 103 are from different manufacturers and / or different models, resulting in differences in display parameters of the two display screens. When the two display screens are displayed simultaneously, the resolutions and refresh rates of the two display screens require different clock frequencies and output different timings. If the first display screen 102 and the second display screen 103 use the same display link, it will cause a mismatch between the data processing clock frequency and the display timing, which will lead to data loss and failure to display normally.

[0062] In view of this, an easy-to-think-of design is Figure 1As shown, an independent display link is configured for the first display screen 102 and the second display screen 103 in the image data processing chip 101. In this way, the first display screen 102 can sequentially realize system reading, data processing and output timing signals through the data reading module 106, the display processing module 107 and the timing control module 108 in the first display link 104; the second display screen 103 can sequentially realize data reading, data processing and timing output through the data reading module 106, the display processing module 107 and the timing control module 108 in the second display link 105. In the same display link, the data reading module 106 is used for data reading to read source data from the memory 100; the display processing module 107 is used for processing data to convert the source data obtained from the data reading module 106 into image data; the timing control module 108 is used for outputting timing signals to perform timing matching of the image data obtained from the display processing module 107 and the display parameters of the connected display screen, so that the display screen can display based on the image data matched with the timing.

[0063] exist Figure 1 In the illustrated manner, when the display contents of the first display screen 102 and the second display screen 103 are the same (i.e., the two display screens display the same image), the image data processing chip 101 still needs to read data, process data, and output timing signals in sequence through the first display link 104 and the second display link 105, i.e., each display link needs to read the source data of the same layer, which increases the system data bandwidth and power consumption, and each display link needs to perform approximately the same data processing and layer superposition on the read layer source data, resulting in a large amount of data processing for the image data processing chip 101 and a large power consumption.

[0064] In a display scenario with multiple layers superimposed, the power consumption problem caused by layer processing is more prominent. This is because in this scenario, each display link needs to read all layer data, which increases the bandwidth requirements and reading power consumption of the system. For example, the first display link 104 needs to read four layers of source data, and the second display link 105 also needs to read the four layers of source data. The bandwidth from the memory 100 to the display layer needs to support 8 layers of data reading, and both display links need to perform the same data processing flow in the display processing module 107. For scenarios where two display screens need to display the same content, the data processing power consumption of the display processing module 107 in one display link is wasted. Among them, the display scenario with superimposed layers includes a display screen that needs to display multiple layers in the same frame image, such as a display desktop of a display screen including multiple unused application windows.

[0065] In order to solve the above problems, an embodiment of the present application provides an image data processing chip, including:

[0066] A first display link, the first display link is used to read first source data from a memory of the electronic device, convert the first source data into first image data, the first image data matches a display parameter of a first display screen of the electronic device, and is used to drive the first display screen to display a first image;

[0067] A write-back branch, the write-back branch is used to write the first image data back to the memory when the electronic device is in the first display mode;

[0068] The second display link is used in the first display mode to read the first image data from the memory, and drive the second display screen of the electronic device to display the first image based on the first image data.

[0069] In an embodiment of the present application, the image data processing chip can read the first source data from the memory through the first display link, convert the first source data into the first image data matching the display parameters of the first display screen, and drive the first display screen to display the image through the first image data. In the first display mode, the image data processing chip can also write the first image data back to the memory through the write-back branch, so that the second display link can read the first image data from the memory, and drive the second display screen to display the first image based on the first image data. In this way, when the second display screen and the first display screen need to display the same image, in the first display mode, the second display link can directly read the first image data converted by the data processing of the first display link from the storage device, so that the second display link can at least save the data processing process of converting the source data into the image data, thereby reducing the data processing amount of the second display link, and further reducing power consumption.

[0070] It should be noted that in the embodiment of the present application, the image data processing chip is used to connect two display screens. It is easy to know that in the embodiment of the present application, the image data processing chip can be used to connect at least two display screens, and the number of connected display screens is not limited to two. The image data processing chip can also be connected to 3, 4 or more display screens.

[0071] At least one second display link may be configured in the image data processing chip. When the image data processing chip is connected to more than two display screens, multiple second display links may be configured in the image data processing chip, each second display link being used to connect to a corresponding separate second display screen.

[0072] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0073] refer to Figure 2 , Figure 2This is a schematic diagram of the structure of an image data processing chip provided in an embodiment of the present application. The image data processing chip 101 is used in an electronic device. The image data processing chip 101 includes:

[0074] A first display link 104, the first display link 104 is used to read first source data from the memory 100 of the electronic device, convert the first source data into first image data, the first image data matches the display parameters of the first display screen 102 of the electronic device, and is used to drive the first display screen 102 to display the first image;

[0075] A write-back branch 112, the write-back branch 112 is used to write the first image data back to the memory 100 when the electronic device is in the first display mode;

[0076] The second display link 105 is used in the first display mode to read the first image data from the memory 100 and drive the second display screen 103 of the electronic device to display the first image based on the first image data.

[0077] In the first display mode, the first display screen 102 and the second display screen 103 display the same content, and both display the first image. Figure 2 In the drawings of the subsequent embodiments, the dotted arrows represent the data transmission path in which the first image data is transmitted to the memory 100 via the write-back branch 112 and the second display link 105 reads the first image data from the memory 100 .

[0078] exist Figure 2 In the illustrated manner, the image data processing chip 101 can read the first source data from the memory 100 via the first display link 104, convert the first source data into first image data matching the display parameters of the first display screen 102, and drive the first display screen 102 to display an image via the first image data.

[0079] In the first display mode, the image data processing chip 101 can also write the first image data back to the memory 100 through the write-back branch 112, so that the second display link 105 can read the first image data from the memory 100, and drive the second display screen 103 to display the first image based on the first image data. In this way, when the second display screen 103 and the first display screen 102 need to display the same image, in the first display mode, the second display link 105 can directly read the first image data converted by the data processing of the first display link 104 from the memory 100, so that the second display link 105 can at least save the data processing process of converting the source data into the image data, thereby reducing the data processing amount of the second display link 105, and further reducing the power consumption.

[0080] refer to Figure 3, Figure 3 This is a schematic diagram of the structure of another image data processing chip provided in an embodiment of the present application. Based on the above implementation, Figure 3 The image data processing chip 101 further includes a switching branch 113 , which is used to construct a data processing path matching the display parameters of the second display screen 103 based on the second display link 105 in the first display mode.

[0081] Optionally, the switching branch 113 may bypass part of the second display link 105 to reduce the data processing flow in the second display link 105, thereby reducing the data processing amount, thereby reducing power consumption. Since the second display screen 103 and the first display screen 102 display the same content in the first display mode, and both display the same image, the second display link 105 may be bypassed through the switching branch 113, and the second display link 105 may directly use the first image data output by the first display link 104, thereby saving the data processing flow in the second display link 105 that is repeated with the first display link 104, reducing the data processing flow in the second display link 105, thereby reducing the data processing amount.

[0082] refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of another image data processing chip provided in an embodiment of the present application. Based on the above implementation, the second display link 105 includes a data reading module 106, a display processing module 107 and a timing control module 108 which are sequentially connected between the memory 100 and the second display screen 103.

[0083] In the second display link 105, the data reading module 106 is used to select to read the first image data from the memory 100 or to read the second source data different from the first source data according to the display mode of the electronic device; the display processing module 107 includes a plurality of display processing units sequentially connected between the data reading module 106 and the timing control module 108, and the display processing unit is used to process the data input by the data reading module 106; the timing control module 108 is used to perform timing matching between the image data input by the display processing module 107 or the switching branch 113 and the second display screen 103 based on the display parameters of the second display screen 103.

[0084] Among them, for the display processing module 107 in the second display link 105, if it is in the first display mode, the switching branch 113 can bypass at least part of the display processing units in the display processing module 107, so as to save the data processing flow of the bypassed display processing units in the first display mode, thereby reducing the data processing amount of the second display link 105 and reducing power consumption.

[0085] Optionally, the first display link 104 and the second display link 105 have the same module structure, that is, both include a data reading module 106, a display processing module 107 and a timing control module 108 connected in sequence, and the display processing module 107 in the two display links at least includes a pre-processing unit 109, a synthesis unit 110 and a post-processing unit 111 connected in sequence between the data reading module 106 and the timing control module 108. In the same display link, the data reading module 106 is used to read data from the memory 100; the display processing module 107 is used to perform data processing on the input data; and the timing control module 108 is used to perform timing matching on the input data.

[0086] In the first display link 104, the data reading module 106 is used for data reading to read the first source data from the memory 100; the display processing module 107 is used for processing data to convert the first source data obtained from the data reading module 106 into first image data; the timing control module 108 is used for outputting a timing signal to perform timing matching between the first image data obtained from the display processing module 107 and the display parameters of the connected first display screen 102, so that the first display screen 102 can display the first image based on the timing matched image data.

[0087] If in the first display mode, since the second display screen 103 and the first display screen 102 display the same content, both display the first image. For the second display link 105, the first image data written back to the memory 100 through the write-back branch 112 can be directly read from the memory 100, and the display processing module 107 can be directly bypassed as a whole through the switching branch 113, and the first image data is directly sent to the timing control module 108 through the switching branch 113. The first image data is matched with the display parameters of the second display screen 103 through the timing control module 108, so that the second display screen 103 can display the first image based on the timing-matched first image data.

[0088] Optionally, the electronic device further includes a second display mode, in which the first display screen 102 and the second display screen 103 display different images, and the write-back branch 112 is in a non-enabled state, the write-back branch 112 in the non-enabled state is in a closed state, and the first image data is no longer written back to the memory 100 through the write-back branch 112. The switch branch 113 is used to disconnect in the second display mode so that the entire path of the second display link 105 is connected between the memory 100 and the second display screen 103. In the second display mode, the second display link 105 can be connected as a whole between the memory 100 and the second display screen 103 to form a path, and can independently perform source data conversion and data processing, so that the second display screen 103 and the first display screen 102 can display different content, and when the first display screen 102 displays the first image, the second display screen 103 can display a second image different from the first image.

[0089] If in the second display mode, the second display link 105 is used to read second source data different from the first source data from the memory 100, convert the second source data into second image data matching the display parameters of the second display screen 103, and drive the second display screen 103 to display a second image having different content from the first image based on the second image data.

[0090] When the electronic device is in the second display mode, for the first display link 104, the first source data can be obtained from the memory 100 based on its own data reading module 106, the first source data can be converted into first image data through its own display processing module 107, and the first image data can be time-matched with the display parameters of the first display screen 102 through its own timing control module 108, so that the first display screen 102 can display the first image based on the timing-matched first image data; for the second display link 105, the second source data can be obtained from the memory 100 based on its own data reading module 106, the second source data can be converted into second image data through its own display processing module 107, and the second image data can be time-matched with the display parameters of the second display screen 103 through its own timing control module 108, so that the second display screen 103 can display the second image based on the timing-matched second image data.

[0091] In one embodiment, if Figure 4As shown, for the first display link 104, the input end of the write-back branch 112 is connected to the output end of the display processing module 107; correspondingly, for the second display link 105, the input end of the switch branch 113 is connected to the input end of the display processing module 107, and the output end of the switch branch 113 is connected to the output end of the display processing module 107. The switch branch 113 is used to bypass all display processing units in the display processing module 107 in the first display mode. For the display processing module 107 in the second display link 105, the switch branch 113 is connected to the input end and the output end of the display processing module 107, so that in the first display mode, the switch branch 113 can bypass the entire display processing module 107 of the second display link 105, that is, bypass all display processing units in the display processing module 107.

[0092] refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of another image data processing chip provided in an embodiment of the present application. Based on the above implementation mode, in this method, for the second display link 105, the multiple display processing units of the display processing module 107 include a target display processing unit connected to the timing control module; the target display processing unit is used to match the image parameters of the input data with the display parameters of the second display screen 103; wherein the switching branch 113 is used to bypass other display processing units between the data reading module 106 and the target display processing unit in the first display mode.

[0093] Figure 5 In the illustrated manner, for the first display link 104, the input end of the write-back branch 112 is connected to the input end of the target display processing unit in the display processing module 107; correspondingly, for the second display link 105, the input end of the switching branch 113 is connected to the input end of the target display processing unit, and other display processing units between the data reading module 106 and the target display processing unit can be bypassed by the switching branch 113 to save the data processing flow of these other display processing units, thereby reducing the data processing amount in the second display link 105 and reducing power consumption.

[0094] Optionally, for the second display link 105, the multiple display processing units in the display processing module 107 include at least a pre-processing unit 109, a synthesis unit 110 and a post-processing unit 111 which are sequentially connected between the data reading module 106 and the timing control module 108. For the second display link 105, the target display processing unit may be the post-processing unit 111, Figure 5The method shown can bypass the pre-processing unit 109 and the synthesis unit 110 in the display processing module 107, and the switching branch 113 can directly send the first image data obtained by the data reading module 106 to the post-processing unit 111, thereby saving the data processing flow of the pre-processing unit 109 and the synthesis unit 110.

[0095] For the display processing module 107, the pre-processing unit 109 can be used to decode the input data, convert the format and perform layer scaling and other operations; the synthesis unit 110 can be used to perform layer overlay and other operations on the input data; the post-processing unit 111 is used to perform operations such as adaptive scaling of image data and screen size and color gamut adjustment.

[0096] In the first display mode, Figure 5 The illustrated approach enables both the first display link 104 and the second display link 105 to undergo data processing procedures of a separate post-processing unit 111 , and enables the two display links to perform processing procedures adapted to the resolution and color gamut characteristics of the display screens to which they are connected.

[0097] Taking dual-screen display as an example, simulation data shows that based on Figure 4 The solution shown can reduce the power consumption of data reading and data processing by 35%. Figure 5 The solution shown can reduce the power consumption of data reading and data processing by 25%.

[0098] It should be noted that the data transmission path from the memory 100 to the display screen ( Figure 1-Figure 5 The display link inputs and outputs data from left to right, that is, the left side of each module or unit in the display link is the input end, and the right side is the output end.

[0099] In the first display mode, the switching branch 113 constructs a data processing path matching the display parameters of the second display screen 103 based on at least the data reading module 106 and the timing control module 108 in the second display link 105, such as Figure 4 As shown, the data reading module 106, the switching branch 113 and the timing control module 108 constitute a data processing path, or as shown in FIG. Figure 5 As shown, the data reading module 106, the switching branch 113, the target display processing unit (which may be the post-processing unit 111) and the timing control module 108 constitute a data processing path. In this way, the image data provided to the second display screen 103 can be matched with the display parameter timing of the second display screen 103, so that the data processing clock frequency required by the display system can be matched with the display timing of the second display screen 103, thereby avoiding data loss due to timing mismatch, and avoiding problems such as failure to display or display errors due to data loss.

[0100] In the embodiment of the present application, the first image data is image data after data processing by the display processing module 107 of the first display link 104. The first image data written back to the memory 100 is at least processed by the layer overlay of the display processing module 107. If the first image includes multiple layers, the first image data in the display processing module 107 of the first display link 104 is image data after the layer overlay, that is, the write-back branch 112 writes the first image data after the layer overlay back to the memory 100.

[0101] Based on this, in the first display mode, if the first image includes multiple layers, the first display link 104 only needs to read all layer source data, process each layer in turn and superimpose the layers, and then send the formed first image data to the first display screen 102 to drive the first display screen 102 to display the first image, and at the same time, write the first image data after the layer superposition processing back to the memory 100 through the write-back branch 112. What is written back to the memory 100 by the write-back branch 112 is the first image data after the layer superposition, which is equivalent to the single-layer data, and the bandwidth is much smaller than the read bandwidth of multiple layers.

[0102] In the first display mode, after the first image data processed by the first display link 104 is written back to the memory 100 through the write-back branch 112, the second display link 105 can directly read the first image data processed by the first display link 104 from the memory, which can reduce the bandwidth and power consumption of the second display link 105. In this way, the first display link 104 only needs to read the source data of each layer, and perform data processing and layer superposition on each layer. The second display link 105 does not need to perform these data processing processes, and can directly read the first image data processed by the first display link 104. When the display contents of the second display screen 103 and the first display screen 102 are the same, the data processing process of the display processing module 107 in the second display link 105 can be saved, thereby reducing the bandwidth and power consumption of the second display link 105.

[0103] Based on the above description, it can be known that in the embodiment of the present application, the write-back branch 112 writes back the first image data after the layers are superimposed through the first display link 104, which is the write-back of the single-layer image data, and the write-back bandwidth is much smaller than the read bandwidth of multiple layers. Moreover, the power consumption of the write-back operation is much smaller than the data processing power consumption of the display processing module 107 in the second display link 105, which can save the bandwidth and power consumption of reading the multi-layer source data in the second display link 105, and can also reduce the data processing flow and power consumption of the display processing module 107 in the second display link 105.

[0104] for Figure 4 and Figure 5 In the manner shown, the product of the resolution and refresh rate of the first display screen 102 and the second display screen 103 can be different. If the first display screen 102 can be set to have a larger product of the resolution and refresh rate, the two display screens can have the same resolution and different refresh rates, and the first display screen 102 has a higher refresh rate. In this case, the display timing of the two display screens can be as follows: Figure 6 shown.

[0105] refer to Figure 6 , Figure 6 The schematic diagram is a principle diagram of the image data processing chip controlling the first display screen and the second display screen to display images. The timing control module 108 in the first display link 104 is set as the first timing control module, and the timing control module 108 in the second display link 105 is set as the second timing control module. In the first display mode, the first timing control module controls the first display screen 102 to display the first image after timing matching the first image data, and the second timing control module controls the second display screen 103 to display the first image after timing matching the written back first image data.

[0106] Since the refresh rate of the second display screen 103 is relatively low, in the timing direction ( Figure 6 As shown by the arrow in the implementation diagram, the second display screen 103 does not have time to display the partial image frame written back to the memory 100, such as Figure 6 As shown, under the same timing, when the first display screen 102 displays four frames of images from F0 to F3, the second display screen 103 can only display three frames of images from f0 to f2 due to the limitation of its own refresh frequency.

[0107] In the embodiment of the present application, since the second display link 105 reads the first image data written back to the memory 100 , the second display screen 103 has a delay relative to the first display screen 102 , and the second display screen 103 can be used as a secondary screen to copy the display content of the first display screen 102 .

[0108] In other embodiments, the resolution and refresh rate of the first display screen 102 and the second display screen 103 may be different or the same.

[0109] refer to Figure 7 , Figure 7An equivalent circuit diagram of an image data processing chip provided in an embodiment of the present application, based on the above-mentioned implementation mode, the image data processing chip 101 includes: a plurality of parallel data reading channels 114, the data reading channel 114 is used to read data from the memory 100; a plurality of first display processing channels 115 connected to the data reading channels 114 in a one-to-one correspondence, the first display processing channels 115 are used to pre-process the data input by the corresponding data reading channels 114; a display processing component 116 connected to each of the first display processing channels 115, the display processing component 116 is used to perform layer overlay on the input of the first display processing channel 115; two second display processing channels 117 respectively connected to the display processing components 116, the second display processing channels 117 are used to match the image parameters of the data input by the display processing component 116 with the display parameters of the first display screen 102 and the second display screen 103 respectively.

[0110] Part of the multiple data reading channels 114 and part of the first display processing channel 115 are configured as the first display link 104 , and part of the multiple data reading channels 114 and part of the first display processing channel 115 are configured as the second display link 105 .

[0111] A portion of the plurality of data reading channels 114 (the number of the data reading channels 114 is set to A) is configured as the data reading module 106 in the first display link 104, and another portion (the number of the data reading channels 114 is set to B) is configured as the data reading module 106 in the second display link 105, A+B≤C. Wherein, C is the total number of the data reading channels 114, C can be 10 or other positive integers greater than 1, A, B and C can be set according to requirements, and the embodiment of the present application does not limit this.

[0112] A portion of the plurality of first display processing channels 115 (the number of the first display processing channels 115 is set to E) is configured as the pre-processing unit 109 in the first display link 104, and another portion (the number of the first display processing channels 115 is set to F) is configured as the second display link 105, E+F≤D. Wherein, D is the total number of the first display processing channels 115, D can be 10 or other positive integers greater than 1, D, E and F can be set according to requirements, and this embodiment of the present application does not limit this.

[0113] The input end of the write-back branch 112 is connected to the input end and the output end of each second display processing channel 117 respectively, and is used to select the image data to be written back. Figure 7 As shown, the write-back branch 112 can be connected to the input end and the output end of each second display processing channel 117 through the first multiplexer 118, respectively.

[0114] The display processing component 116 may serve as a synthesis unit 110 , and the first display link 104 and the second display link 105 may share the same synthesis unit 110 .

[0115] One second display processing channel 117 serves as the post-processing unit 111 of the first display link 104, and another second display processing channel 117 serves as the post-processing unit 111 of the second display link 105. The two second display processing channels 117 are respectively connected to a timing control module 108.

[0116] The output ends of the plurality of data reading channels 114 and the input ends and output ends of each second display processing channel 117 are connected to the switching branch 113, and the switching branch 113 is used to construct a data processing path matching the display parameters of the second display screen 103 based on the second display link 105 in the first display mode. The switching branch 113 includes a second multiplexer 119 and a third multiplexer 120. The output ends of each data reading channel 114 can be respectively connected to the input ends of each second display processing channel 117 through the second multiplexer 119. The output ends of each data reading channel 114 can be respectively connected to the output ends of each second display processing channel 117 through the third multiplexer 120.

[0117] Compared with the active area and power consumption of the image data processing chip, the area introduced by the multiplexer is smaller and the power consumption is lower, which can be ignored.

[0118] refer to Figure 8 , Figure 8 Based on Figure 7 The equivalent circuit shown is constructed Figure 4 The schematic diagram of the image data processing chip shown in the figure. Figure 7 and Figure 8 As shown, if Figure 7 In the embodiment, the first multiplexer 118 is connected to the output end of each second display processing channel 117, and the input end of each second display processing channel 117 is disconnected, then the write-back branch 112 can write the output data of the second display processing channel 117 back to the memory 100. Correspondingly, the second multiplexer 119 is disconnected from the input end of each second display processing channel 117, and the third multiplexer 120 is connected to the output end of each second display processing channel 117. At this time, the following structure can be constructed: Figure 4 The image data processing chip shown.

[0119] refer to Fig. 9 , Fig. 9 Based on Figure 7 The equivalent circuit shown is constructed Figure 5 The schematic diagram of the image data processing chip shown in the figure. Figure 7 and Fig. 9 As shown, if Figure 7 In the embodiment, the first multiplexer 118 is disconnected from the output end of each second display processing channel 117, and is connected to the input end of each second display processing channel 117, then the write-back branch 112 can write the input data of the second display processing channel 117 back to the memory 100. Correspondingly, the second multiplexer 119 is connected to the input end of each second display processing channel 117, and the third multiplexer 120 is disconnected from the output end of each second display processing channel 117. At this time, the following structure can be constructed: Figure 4 The image data processing chip shown.

[0120] in, Figure 8 and Fig. 9 In the diagram, × indicates a circuit break. Figure 8 and Fig. 9 In the embodiment, the first two data reading channels 114, the first two first display processing channels 115 and the first second display processing channel 117 are used to construct the first display link 104, and the last data reading channel 114, the last first display processing channel 115 and the second second display processing channel 117 are used to construct the second display link 105.

[0121] The image data processing chip 101 can control the connection state of each multiplexer based on the control instruction to select the connection state of the write-back branch 112 and the switch branch 113. Figure 4 or Figure 5 Perform data write-back and construct a data processing path corresponding to the second display link 105 .

[0122] In the embodiment of the present application, the reading of all layer source data, the processing of each layer data and the layer overlay operation can be performed only in the first display link 104. The first image data obtained by the first display link 104 can be sent to the first display screen 102 through its own timing control module 108, and the first image data can also be written back to the memory 100 through the write-back branch 112. The first image data written back to the memory 100 can be used for reading by the second display link 105 to reduce the data processing flow and power consumption of the second display link 105. The write-back branch 112 writes back the single-layer data after the layer overlay is performed by the first display link 104. Compared with the amount read in by the first display link 104, the amount of data written back by the write-back branch 112 can be reduced to more than one third.

[0123] In the first display mode, the second display link 105 can bypass part of the display processing unit by switching the branch 113 to construct a simplified data processing path connected to a low-resolution or low-refresh-rate display screen. In this mode, the second display link 105 can directly read the first image data written back to the memory 100, without reading the source data of each layer, and without performing layer overlay operations, which can reduce the amount of processing and power consumption. The second display link 105 only needs to read the image data (first image data) after layer overlay by the first display link 104, which is equivalent to reading a single layer of data after fusion and overlay, which can save data reading bandwidth and power consumption, and can also save power consumption of data processing of each layer and layer overlay operations.

[0124] Based on the image data processing chip 101 provided in the above embodiment, another embodiment of the present application further provides an electronic device, the structure of which is as follows: Fig.10 shown.

[0125] refer to Fig.10 , Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, the electronic device shown includes: a memory 100; an image data processing chip 101 connected to the memory 100. The image data processing chip 101 includes: a first display link 104, the first display link 104 is used to read the first source data from the memory 100 of the electronic device, convert the first source data into first image data, the first image data matches the display parameters of the first display screen 102 of the electronic device, and is used to drive the first display screen 102 to display the first image; a write-back branch 112, the write-back branch 112 is used to write the first image data back to the memory 100 when the electronic device is in the first display mode; a second display link 105, in the first display mode, the second display link 105 is used to read the first image data from the memory 100, and drive the second display screen 103 of the electronic device to display the first image based on the first image data.

[0126] exist Fig.10 In the illustrated embodiment, the electronic device does not include a display screen, and the electronic device is provided with an interface for connecting the display screen, so that the first display link 104 and the second display link 105 are connected to the first display screen 102 and the second display screen 103 respectively.

[0127] In the embodiment of the present application, the electronic device can also be Figure 2-Figure 5 As shown in either manner, a first display screen 102 and a second display screen 103 are included.

[0128] Based on the image data processing chip 101 provided in the above embodiment, another embodiment of the present application further provides an electronic device, the structure of which is as follows: Fig.11 shown.

[0129] refer to Fig.11 , Fig.11 A structural schematic diagram of another electronic device provided for an embodiment of the present application, the electronic device shown includes: an image data processing chip 101; the image data processing chip 101 is used to read first source data from a memory 100, convert the first source data into first image data, the first image data is adapted to display parameters of a first display screen 102, and is used to drive the first display screen 102 to display a first image; if the electronic device is in a first display mode, the image data processing chip 101 is also used to write the image data back to the memory 100, read the first image data from the memory 100, and drive the second display screen 103 of the electronic device to display the first image based on the first image data.

[0130] exist Fig.11 In the illustrated manner, the electronic device at least includes an image data processing chip 101. Optionally, the electronic device may be a DPU (Data Processing Unit). The electronic device may not include a display screen and a memory 100. The electronic device may be provided with a first interface for connecting to a display screen, so that the first display link 104 and the second display link 105 are connected to the first display screen 102 and the second display screen 103 respectively; the electronic device may also be provided with a second interface for connecting to the memory 100, so that the input end of each display link is connected to the memory 100.

[0131] Based on the image data processing chip 101 and the electronic device provided in the above embodiments, another embodiment of the present application further provides an image data processing method. Fig.12 shown.

[0132] refer to Fig.12 , Fig.12 A flowchart of an image data processing method provided in an embodiment of the present application, the method comprising:

[0133] Step S11: read the first source data from the memory 100, convert the first source data into first image data, the first image data is adapted to the display parameters of the first display screen 102, and is used to drive the first display screen 102 to display the first image.

[0134] Step S12: if the electronic device is in the first display mode, after writing the image data back to the memory 100, the first image data is read from the memory 100, and based on the first image data, the second display screen 103 of the electronic device is driven to display the first image.

[0135] The image data processing chip 101 includes a plurality of display links, each of which is used to connect a display screen. The image data processing method further includes: before reading the first source data, selecting one of the plurality of display links as the first display link 104, and using the other display links as the second display link 105. Thus, as described above, in the first display mode, the first source data can be read through the first display link and converted into the first image data, and the second display link can directly read the first image data written back to the memory 100, thereby reducing the data processing flow and power consumption in the second display link.

[0136] In the first display mode, the image data processing chip 101 can select one of the display links as the first display link 104, use the first display link 104 as the main display data processing path, and the other display links are all second display links 105. The first display screen 102 can be determined according to the product of the resolution and refresh rate of the display screen, the display link connected to the determined first display screen 102 is determined as the first display link 104, and the other display links are determined as the second display link 105. The product of the resolution and refresh rate of the first display screen is not less than the product of the resolution and refresh rate of the other display screens.

[0137] The image data processing method also includes: determining the working mode of the electronic device; if it is determined that the electronic device is in the first display mode, executing step S12; if the electronic device is in the second working mode, not executing the write back operation of the first image data, reading second source data different from the first source data from the memory 100, converting the second source data into second image data, the second image data is adapted to the display parameters of the second display screen 103, and is used to drive the second display screen 103 to display the second image.

[0138] In the embodiment of the present application, the above-mentioned image data processing method can be executed by the image data processing chip 101, and the implementation principle can refer to the description of the relevant implementation method of the image data processing chip 101.

[0139] The embodiments of the image data processing method and electronic device provided in the present application have the same or similar technical effects as the embodiment of the image data processing chip 101. To avoid repetition, they will not be described in detail in the embodiments of the present application.

[0140] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0141] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0142] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0143] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0144] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An image data processing chip, comprising: A first display link, wherein the first display link is used to read first source data from a memory of the electronic device, convert the first source data into first image data, wherein the first image data matches a display parameter of a first display screen of the electronic device, and is used to drive the first display screen to display a first image; a write-back branch, the write-back branch being used to write the first image data back to the memory when the electronic device is in a first display mode; A second display link, in the first display mode, the second display link is used to read the first image data from the memory, and drive the second display screen of the electronic device to display the first image based on the first image data.

2. The image data processing chip according to claim 1, further comprising: A switching branch, wherein the switching branch is used to construct a data processing path matching the display parameters of the second display screen based on the second display link in the first display mode.

3. The image data processing chip according to claim 2, wherein the second display link comprises a data reading module, a display processing module and a timing control module which are sequentially connected between the memory and the second display screen; In the second display link, the data reading module is used to select to read the first image data from the memory or read the second source data different from the first source data according to the display mode of the electronic device; the display processing module includes a plurality of display processing units sequentially connected between the data reading module and the timing control module, and the display processing unit is used to process the data input by the data reading module; the timing control module is used to perform timing matching between the image data input by the display processing module or the switching branch and the second display screen based on the display parameters of the second display screen; in, For the display processing module in the second display link, if it is in the first display mode, the switching branch can bypass at least part of the display processing units in the display processing module.

4. The image data processing chip according to claim 3, wherein the switching branch is used to bypass all the display processing units in the display processing module in the first display mode; Or, the plurality of display processing units include a target display processing unit connected to the timing control module; The target display processing unit is used to match the image parameters of the input data with the display parameters of the second display screen; in, The switching branch is used to bypass other display processing units between the data reading module and the target display processing unit in the first display mode.

5. The image data processing chip according to claim 2, wherein the electronic device further comprises a second display mode, in which the first display screen and the second display screen display different images, and the write-back branch is in a disabled state; The switching branch is used to disconnect in the second display mode so that the entire path of the second display link is connected between the memory and the second display screen.

6. The image data processing chip according to claim 5, if in the second display mode, the second display link is used to read second source data different from the first source data from the memory, convert the second source data into second image data matching the display parameters of the second display screen, and drive the second display screen to display a second image having different content from the first image based on the second image data.

7. The image data processing chip according to any one of claims 1 to 6, comprising: A plurality of parallel data reading channels for reading data from the memory; A plurality of first display processing channels connected to the data reading channels in a one-to-one correspondence, and used for preprocessing the data input by the corresponding data reading channels; A display processing component connected to each of the first display processing channels, used for overlaying layers on inputs input by the first display processing channels; two second display processing channels respectively connected to the display processing components, used to match image parameters of data input by the display processing components with display parameters of the first display screen and the second display screen respectively; Part of the plurality of data reading channels and part of the first display processing channel are used to be configured as the first display link, and part of the plurality of data reading channels and part of the first display processing channel are used to be configured as the second display link; The input end of the write-back branch is connected to the input end and the output end of each of the second display processing channels respectively, and is used for selecting the image data to be written back; The output ends of the multiple data reading channels and the input ends and output ends of each of the second display processing channels are connected to a switching branch, and the switching branch is used to construct a data processing path matching the display parameters of the second display screen based on the second display link in the first display mode.

8. An electronic device comprising: Memory; The image data processing chip connected to the memory includes: a first display link, the first display link is used to read first source data from the memory of the electronic device, convert the first source data into first image data, the first image data matches the display parameters of the first display screen of the electronic device, and is used to drive the first display screen to display the first image; a write-back branch, the write-back branch is used to write the first image data back to the memory when the electronic device is in the first display mode; a second display link, in the first display mode, the second display link is used to read the first image data from the memory, and drive the second display screen of the electronic device to display the first image based on the first image data.

9. A method for processing image data, comprising: Reading first source data from a memory, converting the first source data into first image data, the first image data being adapted to display parameters of a first display screen, and being used to drive the first display screen to display a first image; If the electronic device is in the first display mode, after writing the image data back to the memory, the first image data is read from the memory, and based on the first image data, the second display screen of the electronic device is driven to display the first image.

10. An electronic device comprising an image data processing chip; The image data processing chip is used to read the first source data from the memory, convert the first source data into first image data, the first image data is adapted to the display parameters of the first display screen, and is used to drive the first display screen to display the first image; if the electronic device is in the first display mode, the image data processing chip is also used to write the image data back to the memory, read the first image data from the memory, and drive the second display screen of the electronic device to display the first image based on the first image data.

Images