Display device

Abstract

The display device includes: a pixel unit; a data driving unit; and a data distribution unit including a first switch connecting the first data output line to the first data line according to a first control signal, a second switch connecting the first data output line to the second data line according to a second control signal, a third switch connecting the first data output line to the second data line, and a fourth switch connecting the second data output line to the third data line according to a second control signal. A third switch connecting the second data output line to a third data line according to a third control signal, and a fourth switch connecting the second data output line to a fourth data line according to a fourth control signal; and a control circuit in which the first control signal has the same phase as that of the third control signal and the second control signal has the same phase as that of the fourth control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0174836 filed on December 5, 2023 and Korean Patent Application No. 10-2024-0056768 filed on April 29, 2024 and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments relate to a display device. Background Art

[0004] In the display device, a plurality of gate lines, a plurality of data lines, and a plurality of pixels located at intersections of the gate lines and the data lines are provided. Summary of the invention

[0005] In order to apply a data signal to each of the plurality of data lines, a data driver needs to be provided with data output lines of a number corresponding to the number of data lines, and since a plurality of integrated circuits are required, there is a disadvantage in that manufacturing costs increase.

[0006] Embodiments include a display device having a reduced number of data output lines in a data driving unit. Embodiments include a display device having an improved control signal conversion rate. However, these objects are merely examples, and the scope of the embodiments is not limited thereto.

[0007] Additional features will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the embodiments presented in the disclosure.

[0008] In an embodiment of the present disclosure, a display device includes: a pixel unit including a first data line, a second data line, a third data line and a fourth data line; a data driving unit outputting a data signal through a data output line; a data distribution unit including a first switch, a second switch, a third switch and a fourth switch, wherein the first switch connects a first data output line among the data output lines to the first data line according to a first control signal, the second switch connects the first data output line to the second data line according to a second control signal, the third switch connects a second data output line among the data output lines to the third data line according to a third control signal, and the fourth switch connects the second data output line to the fourth data line according to a fourth control signal; and a control circuit including: a first power supply circuit outputting a first control signal; a second power supply circuit outputting a second control signal; a third power supply circuit outputting a third control signal; and a fourth power supply circuit outputting a fourth control signal, wherein the first control signal has a phase identical to that of the third control signal, and the second control signal has a phase identical to that of the fourth control signal.

[0009] In an embodiment, the second data line and the first data line may be spaced apart from each other with two columns interposed therebetween, and the fourth data line and the third data line may be spaced apart from each other with two columns interposed therebetween.

[0010] In an embodiment, the display device may further include: a first control signal line connecting the first switch and the first power supply circuit to each other; a second control signal line connecting the second switch and the second power supply circuit to each other; a third control signal line connecting the third switch and the third power supply circuit to each other; and a fourth control signal line connecting the fourth switch and the fourth power supply circuit to each other.

[0011] In an embodiment, the display device may further include: a first power output line, connecting the first power circuit and the first control signal line to each other; a second power output line, connecting the second power circuit and the second control signal line to each other; a third power output line, connecting the third power circuit and the third control signal line to each other; and a fourth power output line, connecting the fourth power circuit and the fourth control signal line to each other.

[0012] In an embodiment, the display device may further include: a first bridge wire connecting the first power circuit and the first control signal line to each other; a second bridge wire connecting the second power circuit and the second control signal line to each other; a third bridge wire connecting the third power circuit and the third control signal line to each other; and a fourth bridge wire connecting the fourth power circuit and the fourth control signal line to each other.

[0013] In an embodiment, the display device may further include: a first power output line connecting the first power circuit and the first bridge line to each other; a second power output line connecting the second power circuit and the second bridge line to each other; a third power output line connecting the third power circuit and the third bridge line to each other; and a fourth power output line connecting the fourth power circuit and the fourth bridge line to each other.

[0014] In an embodiment, the display device may further include: a first bridge connection line, connecting the first bridge line and the first control signal line to each other; a second bridge connection line, connecting the second bridge line and the second control signal line to each other; a third bridge connection line, connecting the third bridge line and the third control signal line to each other; and a fourth bridge connection line, connecting the fourth bridge line and the fourth control signal line to each other.

[0015] In an embodiment, the number of each of the first to fourth bridge connection lines may be greater than the number of each of the first to fourth power output lines.

[0016] In an embodiment, each of the first to fourth control signal lines and the first to fourth bridge lines may extend in a first direction, and each of the first to fourth bridge connection lines may extend in a second direction crossing the first direction.

[0017] In an embodiment, the pixel unit may further include a first pixel, a second pixel, a third pixel, and a fourth pixel arranged in the same row, the first data line may be connected to one of the sub-pixels of the first pixel, the second data line may be connected to one of the sub-pixels of the second pixel, the third data line may be connected to one of the sub-pixels of the third pixel, and the fourth data line may be connected to one of the sub-pixels of the fourth pixel.

[0018] In an embodiment, a sub-pixel of the first pixel's sub-pixels connected to the first data line and a sub-pixel of the second pixel's sub-pixels connected to the second data line can emit light of the same color, and a sub-pixel of the third pixel's sub-pixels connected to the third data line and a sub-pixel of the fourth pixel's sub-pixels connected to the fourth data line can emit light of the same color.

[0019] In an embodiment, the pixel unit may further include: a fifth data line, between the first data line and the second data line; a sixth data line, between the second data line and the third data line; a seventh data line, between the third data line and the fourth data line; and an eighth data line, and the data distribution unit may further include a fifth switch, a sixth switch, a seventh switch and an eighth switch, wherein the fifth switch connects the third data output line among the data output lines to the fifth data line according to the first control signal, the sixth switch connects the third data output line to the sixth data line according to the second control signal, the seventh switch connects the fourth data output line among the data output lines to the seventh data line according to the third control signal, and the eighth switch connects the fourth data output line to the eighth data line according to the fourth control signal.

[0020] In an embodiment, the first switch and the fifth switch may be connected to the first power supply circuit via a first control signal line, the second switch and the sixth switch may be connected to the second power supply circuit via a second control signal line, the third switch and the seventh switch may be connected to the third power supply circuit via a third control signal line, and the fourth switch and the eighth switch may be connected to the fourth power supply circuit via a fourth control signal line.

[0021] In an embodiment of the present disclosure, a display device includes: a first data line, a second data line, a third data line and a fourth data line, which are respectively connected to sub-pixels; a data output line, which is connected to a data driving unit that outputs a data signal; a first switch transistor, a second switch transistor, a third switch transistor and a fourth switch transistor, which are respectively connected to the first to fourth data lines; and a first control signal line, a second control signal line, a third control signal line and a fourth control signal line, which are arranged between the data output line and the first to fourth switch transistors in a plan view and extend in a first direction, wherein each of the first to fourth switch transistors includes: a semiconductor layer; a first gate line and a second gate line, which are arranged on the semiconductor layer and extend in a second direction intersecting the first direction; a first electrode and a second electrode, which are arranged on the first gate line and the second gate line and extend in the second direction and are respectively connected to opposite ends of the semiconductor layer; and a third electrode, which is arranged between the first electrode and the second electrode.

[0022] In an embodiment, the first electrode and the second electrode of each of the first and second switching transistors may be connected to a first data output line among the data output lines, and the first electrode and the second electrode of each of the third and fourth switching transistors may be connected to a second data output line among the data output lines.

[0023] In an embodiment, the third electrode of the first switching transistor can be connected to the first data line, the third electrode of the second switching transistor can be connected to the second data line, the third electrode of the third switching transistor can be connected to the third data line, and the third electrode of the fourth switching transistor can be connected to the fourth data line.

[0024] In an embodiment, the first and second gate lines of the first switching transistor can be connected to the first control signal line, the first and second gate lines of the second switching transistor can be connected to the second control signal line, the first and second gate lines of the third switching transistor can be connected to the third control signal line, and the first and second gate lines of the fourth switching transistor can be connected to the fourth control signal line.

[0025] In an embodiment, the display device may further include: a first bridge line, a second bridge line, a third bridge line and a fourth bridge line, which extend in the first direction and are arranged between the first to fourth control signal lines and the control circuit in a plan view; and a first bridge connection line connecting the first bridge line and the first control signal line to each other, a second bridge connection line connecting the second bridge line and the second control signal line to each other, a third bridge connection line connecting the third bridge line and the third control signal line to each other, and a fourth bridge connection line connecting the fourth bridge line and the fourth control signal line to each other, the first bridge connection line, the second bridge connection line, the third bridge connection line and the fourth bridge connection line extending in the second direction.

[0026] In an embodiment, the first control signal line may transmit a first control signal to the first switching transistor, the second control signal line may transmit a second control signal to the second switching transistor, the third control signal line may transmit a third control signal to the third switching transistor, and the fourth control signal line may transmit a fourth control signal to the fourth switching transistor, the first control signal may have a phase that is the same as a phase of the third control signal, and the second control signal may have a phase that is the same as a phase of the fourth control signal.

[0027] In an embodiment, the semiconductor layer may include an oxide-based semiconductor material.

[0028] In an embodiment of the present disclosure, a display device includes: a pixel unit including a first data line, a second data line, a third data line and a fourth data line; a data driving unit outputting a data signal through a data output line; a data distribution unit connecting a first data output line among the data output lines to a second data line, and connecting a second data output line among the data output lines to a fourth data line, the data distribution unit including: a first switch connecting the first data output line to the first data line according to a first control signal; and a second switch connecting the second data output line to the third data line according to a second control signal; and a control circuit including: a first power supply circuit outputting a first control signal; and a second power supply circuit outputting a second control signal, wherein the first control signal has the same phase as that of the second control signal.

[0029] In an embodiment, the second data line and the first data line may be disposed spaced apart from each other with two columns interposed therebetween, and the fourth data line and the third data line may be disposed spaced apart from each other with two columns interposed therebetween.

[0030] In an embodiment, the display device may further include: a first control signal line connecting the first switch and the first power circuit to each other; and a second control signal line connecting the second switch and the second power circuit to each other.

[0031] In an embodiment, the display device may further include: a first power output line connecting the first power circuit and the first control signal line to each other; and a second power output line connecting the second power circuit and the second control signal line to each other.

[0032] In an embodiment, the display device may further include: a first bridge line connecting the first power circuit and the first control signal line to each other; and a second bridge line connecting the second power circuit and the second control signal line to each other.

[0033] In an embodiment, the display device may further include: a first power output line connecting the first power circuit and the first bridge line to each other; and a second power output line connecting the second power circuit and the second bridge line to each other.

[0034] In an embodiment, the display device may further include: a first bridge connection line connecting the first bridge line and the first control signal line to each other; and a second bridge connection line connecting the second bridge line and the second control signal line to each other.

[0035] In an embodiment, the number of the first bridge connection lines may be greater than the number of the first power output lines, and the number of the second bridge connection lines may be greater than the number of the second power output lines.

[0036] In an embodiment, the first control signal line, the second control signal line, the first bridge line, and the second bridge line may extend in a first direction, and the first bridge connection line and the second bridge connection line may extend in a second direction crossing the first direction.

[0037] In an embodiment, the pixel unit may further include a first pixel, a second pixel, a third pixel, and a fourth pixel arranged in the same row, the first data line may be connected to one of the sub-pixels of the first pixel, the second data line may be connected to one of the sub-pixels of the second pixel, the third data line may be connected to one of the sub-pixels of the third pixel, and the fourth data line may be connected to one of the sub-pixels of the fourth pixel.

[0038] In an embodiment, a sub-pixel of the first pixel's sub-pixels connected to the first data line and a sub-pixel of the second pixel's sub-pixels connected to the second data line can emit light of the same color, and a sub-pixel of the third pixel's sub-pixels connected to the third data line and a sub-pixel of the fourth pixel's sub-pixels connected to the fourth data line can emit light of the same color.

[0039] In an embodiment of the present disclosure, a display device includes: a first data line, a second data line, a third data line and a fourth data line, which are respectively connected to sub-pixels; a first data output line, connecting a data driving unit with the first data line and the second data line; a second data output line, connecting the data driving unit with the third data line and the fourth data line; a first switching transistor, connected between the first data line and the first data output line; a second switching transistor, connected between the third data line and the second data output line; and a first control signal line and a second control signal line, which are arranged between the first data output line and the first switching transistor and between the second data output line and the second switching transistor in a plan view and extend in a first direction, wherein each of the first switching transistor and the second switching transistor includes: a semiconductor layer; a first gate line and a second gate line, which are arranged on the semiconductor layer and extend in a second direction intersecting the first direction; a first electrode and a second electrode, which are arranged on the first gate line and the second gate line and are respectively connected to opposite ends of the semiconductor layer; and a third electrode, which is arranged between the first electrode and the second electrode.

[0040] In an embodiment, the first electrode and the second electrode of the first switching transistor can be connected to the first data output line, the first electrode and the second electrode of the second switching transistor can be connected to the second data output line, the second data line can be connected to the first data output line, and the fourth data line can be connected to the second data output line.

[0041] In an embodiment, the third electrode of the first switch transistor may be connected to the first data line, and the third electrode of the second switch transistor may be connected to the third data line.

[0042] In an embodiment, the first gate line and the second gate line of the first switch transistor may be connected to the first control signal line, and the first gate line and the second gate line of the second switch transistor may be connected to the second control signal line.

[0043] In an embodiment, the display device may further include: a first bridge line and a second bridge line, which extend in the first direction and are arranged between the control circuit and the first control signal line and the second control signal line in a plan view; and a first bridge connection line connecting the first bridge line and the first control signal line to each other and a second bridge connection line connecting the second bridge line and the second control signal line to each other, the first bridge connection line and the second bridge connection line extending in the second direction.

[0044] The first control signal line may transmit a first control signal to the first switching transistor, and the second control signal line may transmit a second control signal to the second switching transistor, and the first control signal and the second control signal may have the same phase.

[0045] In an embodiment, the semiconductor layer may include an oxide-based semiconductor material.

[0046] In an embodiment of the present disclosure, a display device includes: a pixel unit including 2N data lines, N being a natural number satisfying 2≤N; a data driving unit outputting a data signal through a first data output line and a second data output line; a data distribution unit connecting the first data output line to an Nth data line among the 2N data lines, and connecting the second data output line to a 2Nth data line among the 2N data lines, the data distribution unit including: N-1 switches connecting the first data output line to each of N-1 data lines among the 2N data lines; and N-1 switches connecting the second data output line to each of the remaining N-1 data lines among the 2N data lines; and a control circuit outputting 2N-2 control signals for controlling each of the switches, wherein the i-th control signal (1≤i≤N-1, where i is a natural number) has the same phase as that of the N+i-th control signal.

[0047] Other features and advantages in addition to those described above will become apparent from the following drawings, claims, and detailed description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and other features and advantages of illustrative embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0049] Figure 1 is a perspective view schematically illustrating an embodiment of a display device;

[0050] Figure 2 is a diagram schematically illustrating an embodiment of a display device;

[0051] Figure 3A and Figure 3B are equivalent circuit diagrams each schematically illustrating an embodiment of a sub-pixel;

[0052] Figure 4A and Figure 4B are cross-sectional views each schematically illustrating an embodiment of a region of a display device;

[0053] Figure 5 is a diagram for describing an embodiment of a sub-demultiplexer;

[0054] Figure 6 is a diagram schematically illustrating an embodiment of a display device;

[0055] Figure 7 Is used to describe Figure 6 A timing diagram of the operation of the display device shown in ;

[0056] Figure 8 is a diagram schematically illustrating an embodiment of a display device;

[0057] Fig. 9 is a layout diagram schematically illustrating an embodiment of a data distribution unit;

[0058] Fig.10 It is a schematic diagram Fig. 9 A cross-sectional view of a cross section of the display device shown in taken along line AA';

[0059] Fig.11 is a diagram schematically illustrating an embodiment of a display device;

[0060] Fig.12 is a layout diagram schematically illustrating an embodiment of a data distribution unit;

[0061] Fig.13A and Fig. 13B is a graph showing a control signal of a display device according to a comparative example and a control signal of a display device according to an embodiment;

[0062] Fig.14 is a diagram for describing an embodiment of a sub-demultiplexer;

[0063] Fig.15 is a diagram schematically illustrating an embodiment of a display device;

[0064] Fig.16 Is used to describe Fig.15 A timing diagram of the operation of the display device shown in ;

[0065] Fig.17 is a diagram schematically illustrating an embodiment of a display device;

[0066] Fig.18 is a layout diagram schematically illustrating an embodiment of a data distribution unit;

[0067] Fig.19 is a diagram schematically illustrating an embodiment of a display device;

[0068] Fig. 20 is a layout diagram schematically illustrating an embodiment of a data distribution unit;

[0069] Fig.21 is a diagram for describing an embodiment of a sub-demultiplexer; and

[0070] Fig. 22 is a diagram schematically illustrating an embodiment of a display device. DETAILED DESCRIPTION

[0071] Now will refer to each embodiment in detail, these embodiments are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements from time to time. In this regard, the illustrated embodiments can have different forms, and should not be construed as being limited to the description set forth herein. Accordingly, each embodiment is only described below by reference to the accompanying drawings to explain the features described. As used in this article, the term "and / or" includes any and all combinations of one or more of the listed associated items. Throughout this disclosure, the statement "at least one of a, b and c" represents only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variations.

[0072] Since the present disclosure allows for various modifications and numerous embodiments, illustrative embodiments will be illustrated in the drawings and described in the written description. Hereinafter, the effects and features of the present disclosure and methods for achieving them will be more fully described with reference to the attached drawings in which various embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0073] It should be understood that although terms such as “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms and these terms are only used to distinguish one element from another.

[0074] In the following embodiments, expressions used in the singular include expressions in the plural unless they have obviously different meanings in the context.

[0075] In the following embodiments, terms such as “comprising,” “including,” or “having” mean the presence of features or elements described in the present specification, and do not exclude the possibility of adding one or more other features or elements.

[0076] In the following embodiments, when a component such as a film, a region or an element is disposed above or on another component, this refers not only to a case where the component is directly above the other component but also to a case where other films, regions or elements are located therebetween.

[0077] For the convenience of description, the size of the elements in the drawings may be exaggerated or reduced. For example, for the convenience of description, the size and thickness of each element shown in the drawings are arbitrarily shown, and therefore the embodiments are not necessarily limited to the contents shown.

[0078] Herein, when a line extends in the first direction or the second direction, this means not only extending in a straight line but also extending in a zigzag shape or a curved line in the first direction or the second direction.

[0079] Herein, “in a plan view” means when the target portion is viewed from above, and “in a cross-sectional view” means when a cross section of the target portion is vertically cut and viewed from the side.

[0080] Herein, when a first element “overlaps” a second element, it means that the first element is disposed above or below the second element.

[0081] Herein, when X and Y are connected, this may include a case where X and Y are electrically connected, a case where X and Y are functionally connected, and a case where X and Y are directly connected. Here, X and Y may be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Accordingly, the above is not limited to a specific connection relationship (e.g., a connection relationship shown in the drawings or described in the detailed description), and may also include a connection relationship other than the connection relationship shown in the drawings or described in the detailed description.

[0082] When X and Y are electrically connected, this may include a case where one or more elements capable of making an electrical connection between X and Y (eg, switches, transistors, capacitive elements, inductors, resistor elements, diodes, etc.) are connected between X and Y.

[0083] In the following embodiments, "on" used in conjunction with the state of an element may refer to the activated state of an element, and "off" may refer to the deactivated state of an element. "On" used in conjunction with a signal received by an element may refer to a signal that activates an element, and "off" may refer to a signal that deactivates an element. A device may be activated by a high level voltage or a low level voltage. For example, a p-channel transistor is activated by a low level voltage, and an n-channel transistor is activated by a high level voltage. Accordingly, it should be understood that the "on" voltage of a p-channel transistor (p-type transistor) and an n-channel transistor (n-type transistor) is an opposite (low to high) voltage level.

[0084] Terms such as "unit" used herein are intended to mean a hardware component that performs a predetermined function. For example, the hardware component may include a circuit such as a field programmable gate array ("FPGA") or an application specific integrated circuit ("ASIC").

[0085] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0086] Figure 1 is a perspective view schematically illustrating an embodiment of the display device 10 .

[0087] refer to Figure 1 , the display device 10 may include a display area DA in which an image is displayed and a peripheral area PA disposed around the display area DA. The display device 10 may provide an image by light emitted from a plurality of pixels arranged in the display area DA. The peripheral area PA is an area disposed around the display area DA, and may be a non-display area in which no pixels are disposed. The display area DA may be completely surrounded by the peripheral area PA. In the peripheral area PA, various lines for transmitting electrical signals to be applied to the display area DA and pads to which a printed circuit board or a driver integrated circuit ("IC") chip is attached may be disposed.

[0088] The display device 10 according to the embodiment is a device for displaying a moving image or a still image, and can be used as a display screen of various products such as a television, a laptop computer, a monitor, a billboard or an Internet of Things ("IoT") device, and a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player ("PMP"), a navigation device, and an ultra-mobile PC ("UMPC"). In addition, the display device 10 in the embodiment can be used as a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head-mounted display ("HMD"). In addition, the display device 10 in the embodiment can be used as a display of a vehicle dashboard, a central information display ("CID") set on the central instrument panel or dashboard of the vehicle, a car interior mirror display replacing a vehicle side mirror, or as a display arranged on the back of the front seat of the vehicle for entertainment of the rear seats. In addition, the display device 10 can be a flexible, rollable, foldable or retractable device.

[0089] Figure 2 is a diagram schematically illustrating an embodiment of the display device 10 .

[0090] refer to Figure 2 The display device 10 may include a pixel unit 110 , a gate driving unit 130 , a data driving unit 150 , a data distribution unit 170 , a control circuit 180 , and a control unit 190 .

[0091] The pixel unit 110 in which a plurality of sub-pixels Ps are arranged may be provided in the display area DA (refer to Figure 1 The gate driving unit 130, the data driving unit 150, the data distribution unit 170, the control circuit 180, and the control unit 190 may be provided in the peripheral area PA (refer to Figure 1 )middle.

[0092] Each of the plurality of pixels Ps can be connected to a corresponding gate line among a plurality of gate lines GL1 to GLn and a corresponding data line among a plurality of data lines DL1 to DLm. Here, n and m can be natural numbers greater than 0. The gate lines GL1 to GLn can each extend in a first direction (e.g., the x direction of the row direction) and can be connected to the sub-pixels Ps in the same row. Each of the gate lines GL1 to GLn can transmit a gate signal to the sub-pixel Ps. The data lines DL1 to DLm can each extend in a second direction (e.g., the y direction of the column direction) and can be connected to the sub-pixels Ps in the same column.

[0093] The gate drive unit 130 may be connected to a plurality of gate lines GL1 to GLn, and may generate a gate signal in response to a gate drive control signal GCS from a control unit 190, and sequentially supply the generated gate signal to the gate lines GL1 to GLn. When the gate signal is sequentially supplied to the gate lines GL1 to GLn, the sub-pixel Ps may be selected row by row. Each of the data lines DL1 to DLm may transmit a data signal to the sub-pixel Ps of the selected row. The gate lines GL1 to GLn may be connected to the gates of the transistors included in the sub-pixel Ps. The gate signal may be a gate control signal for controlling the conduction and cut-off of the transistors connected to the gate lines. The gate signal may be a square wave signal in which a turn-on voltage that may turn on the transistor and a cut-off voltage that may cut off the transistor are repeated.

[0094] The data driving unit 150 may be connected to the plurality of data output lines OL1 to OLm / i, and the plurality of data output lines OL1 to OLm / i may be connected to the plurality of data lines DL1 to DLm via the data distribution unit 170. The data driving unit 150 may convert the image signal into a data signal in the form of voltage or current in response to the data driving control signal DCS received from the control unit 190. The data driving unit 150 may supply the data signal to the data distribution unit 170 via the data output lines OL1 to OLm / i.

[0095] The control circuit 180 may be connected to a plurality of power output lines POL, and the plurality of power output lines POL may be connected to the data distribution unit 170. The control circuit 180 may supply a control signal of the sub-demultiplexer DMX to the data distribution unit 170 via the power output line POL in response to a distribution control signal CS received from the control unit 190.

[0096] The data distribution unit 170 may be connected between a plurality of data output lines OL1 to OLm / i and a plurality of data lines DL1 to DLm. The data distribution unit 170 may include m / i (where i is a natural number greater than 2) sub-demultiplexers DMX including a plurality of switches. In other words, the data distribution unit 170 may have the same number of sub-demultiplexers DMX as the number of data output lines OL1 to OLm / i. One end of the sub-demultiplexer DMX may be connected to a corresponding data output line among the plurality of data output lines OL1 to OLm / i. In addition, the opposite end of the sub-demultiplexer DMX may be connected to i data lines. The sub-demultiplexer DMX may supply the data signal supplied from the corresponding data output line to the i data lines. By using the sub-demultiplexer DMX, fewer data output lines OL1 to OLm / i than the number of data lines DL1 to DLm are required, and therefore, the number of data output lines OL1 to OLm / i connected to the data driving unit 150 is reduced, thereby reducing manufacturing costs. The sub-demultiplexer DMX may include a plurality of switches each connected to a corresponding data output line and respectively connected to i data lines. In an embodiment, i may be 2.

[0097] The control unit 190 may generate a data drive control signal DCS and a gate drive control signal GCS in response to a synchronization signal supplied from the outside. The control unit 190 may output the data drive control signal DCS to the data drive unit 150, and output the gate drive control signal GCS to the gate drive unit 130. The control unit 190 may output a distribution control signal CS to the control circuit 180, and the control circuit 180 may output a control signal of the sub-demultiplexer DMX in response to the distribution control signal CS. The data distribution unit 170 may selectively connect the data output lines OL1 to OLm / i to the data lines DL1 to DLm in response to the control signal of the sub-demultiplexer DMX.

[0098] The gate driving unit 130, the data distribution unit 170, and the control unit 190 may be directly formed on the substrate. The data driving unit 150 and the control circuit 180 may be disposed on a flexible printed circuit board ("FPCB") electrically connected to a pad disposed on one side of the substrate. In another embodiment, the data driving unit 150 and the control circuit 180 may be directly disposed on the substrate in a chip on glass ("COG") or chip on plastic ("COP") method.

[0099] When the display device 10 is an organic light-emitting display device, a first power supply voltage ELVDD and a second power supply voltage ELVSS may be supplied to the sub-pixels Ps of the display device 10. The first power supply voltage ELVDD may be a high-level voltage supplied to a first electrode (pixel electrode or anode electrode) of a display element (light-emitting element) included in each sub-pixel Ps. The second power supply voltage ELVSS may be a low-level voltage supplied to a second electrode (counter electrode or cathode electrode) of a display element included in each sub-pixel Ps. The first power supply voltage ELVDD and the second power supply voltage ELVSS may be driving voltages for causing a plurality of sub-pixels Ps to emit light.

[0100] Hereinafter, in the embodiment, an organic light emitting display device is described in the embodiment of a display device (also referred to as a display device) 10, but the display device according to the embodiment is not limited thereto. In another embodiment, the display device 10 of the embodiment may be an inorganic light emitting display device (or an inorganic electroluminescent ("EL") display device) or a quantum dot light emitting display device.

[0101] Figure 3A and Figure 3B 1 and 2 are equivalent circuit diagrams each schematically illustrating an embodiment of a sub-pixel Ps.

[0102] refer to Figure 3A , the sub-pixel Ps may include an organic light emitting diode OLED and a sub-pixel circuit PC connected to the organic light emitting diode OLED. The sub-pixel circuit PC may include first to sixth transistors T1 to T6, a first capacitor C1, and a second capacitor C2. The first transistor T1 may be a driving transistor that outputs a driving current Id corresponding to a data signal Vdata, and the second to sixth transistors T2 to T6 may be switching transistors that are turned on or off in response to a gate-source voltage or a gate voltage.

[0103] The first transistor T1 to the sixth transistor T6 may be implemented as a thin film transistor. The first terminal and the second terminal of each of the first transistor T1 to the sixth transistor T6 may be a source or a drain, and the second terminal and the first terminal may not be the same terminal. In an embodiment, for example, when the first terminal is a source, the second terminal may be a drain.

[0104] The sub-pixel circuit PC can be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, a fourth gate line EML transmitting a fourth gate signal EM, a fifth gate line EMBL transmitting a fifth gate signal EMB, and a data line DL transmitting a data signal Vdata.

[0105] In addition, the sub-pixel circuit PC may be connected to a driving voltage line PL transmitting a first power voltage ELVDD, a reference voltage line VL1 transmitting a reference voltage VREF, and a first initialization voltage line VL2 transmitting a first initialization voltage Vint.

[0106] In an embodiment, the first to sixth transistors T1 to T6 may be provided as n-channel metal oxide semiconductor field effect transistors ("n-type MOSFET" or "NMOS"). In another embodiment, some of the first to sixth transistors T1 to T6 may be provided as NMOS, and the remaining transistors may be provided as p-channel MOSFET ("PMOS"). In an embodiment, the fifth transistor T5 and the sixth transistor T6 may be provided as PMOS, and the first to fourth transistors T1 to T4 may be provided as NMOS. In another embodiment, for example, the first to sixth transistors T1 to T6 may be provided as PMOS.

[0107] In an embodiment, the first to sixth transistors T1 to T6 may be oxide semiconductor transistors including oxide semiconductor materials. In an embodiment, for example, the oxide semiconductor material may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce) and zinc (Zn). The oxide semiconductor material may be In-Ga-Zn-O ("IGZO"), In-Sn-Zn-O ("ITZO") or In-Ga-Sn-Zn-O ("IGTZO").

[0108] Because oxide semiconductor transistors have relatively high carrier mobility and relatively low leakage current, the voltage drop is not obvious even when the display device is driven for a long time. Therefore, oxide semiconductor transistors can achieve low-frequency driving. In addition, when oxide semiconductor transistors are used, there is no need to form a crystallization process by excimer laser annealing ("ELA") of a low-temperature polycrystalline silicon ("LTPS") semiconductor transistor, and therefore, the manufacturing cost of the display device can be reduced.

[0109] In another embodiment, some of the first to sixth transistors T1 to T6 may be oxide semiconductor transistors, and the remaining transistors may be silicon semiconductor transistors including silicon-based semiconductor materials. In another embodiment, the first to sixth transistors T1 to T6 may be silicon semiconductor transistors. The silicon-based semiconductor material may be polycrystalline silicon or amorphous silicon.

[0110] The first transistor T1 may include a first terminal connected to the driving voltage line PL via a fifth transistor T5, a second terminal connected to the second node N2, a first gate connected to the first node N1, and a second gate connected to the second node N2. The first transistor T1 may receive the data signal Vdata in response to a switching operation of the second transistor T2 and provide a driving current Id to the organic light emitting diode OLED.

[0111] The second transistor T2 (data write transistor) may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 may be turned on in response to a first gate signal GW received via the first gate line GWL, and may perform a switching operation for transmitting a data signal Vdata received via the data line DL to the first node N1.

[0112] The third transistor T3 (first initialization transistor) may include a gate connected to the third gate line GRL, a first terminal connected to the reference voltage line VL1, and a second terminal connected to the first node N1. The third transistor T3 may be turned on in response to a third gate signal GR received via the third gate line GRL, and may transmit a reference voltage VREF received via the reference voltage line VL1 and initialize the first node N1.

[0113] The fourth transistor T4 (second initialization transistor) may include a gate connected to the second gate line GIL, a first terminal connected to the first initialization voltage line VL2, and a second terminal connected to the third node N3. The fourth transistor T4 may be turned on in response to the second gate signal GI received via the second gate line GIL, and may transmit the first initialization voltage Vint received via the first initialization voltage line VL2 to the third node N3 and initialize the pixel electrode of the organic light emitting diode OLED.

[0114] The fifth transistor T5 (first emission control transistor) may include a gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The sixth transistor T6 (second emission control transistor) may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The fifth transistor T5 may be turned on in response to a fourth gate signal EM received via the fourth gate line EML, and the sixth transistor T6 may be turned on in response to a fifth gate signal EMB received via the fifth gate line EMBL, so that the driving current Id may flow through the organic light emitting diode OLED.

[0115] In another embodiment, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 can be connected to the same gate line (emission control signal line). In this case, the fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously by the same gate signal (emission control signal).

[0116] The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The first capacitor C1, which is a storage capacitor, may store a voltage corresponding to a threshold voltage of the first transistor T1 and the data signal Vdata.

[0117] The second capacitor C2 may include a first electrode connected to the driving voltage line PL and a second electrode connected to the second node N2. In an embodiment, the capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2. Figure 3A In the embodiment, the first electrode of the second capacitor C2 is connected to the driving voltage line PL. However, the present disclosure is not limited thereto. In an embodiment, for example, the first electrode of the second capacitor C2 may be connected to a reference voltage line VL1 transmitting a reference voltage VREF or a first initialization voltage line VL2 transmitting a first initialization voltage Vint.

[0118] The organic light emitting diode OLED may include a pixel electrode connected to the third node N3 and an opposing electrode (eg, a cathode electrode) facing the pixel electrode, and the opposing electrode may receive the second power voltage ELVSS. The opposing electrode may be a common electrode shared by a plurality of sub-pixels Ps.

[0119] refer to Figure 3B , the sub-pixel circuit PC may include first to seventh transistors T1 to T7 , a first capacitor C1 , and a second capacitor C2 .

[0120] The sub-pixel circuit PC can be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, a fourth gate line EML transmitting a fourth gate signal EM, a fifth gate line EMBL transmitting a fifth gate signal EMB, and a data line DL transmitting a data signal Vdata.

[0121] Furthermore, the subpixel circuit PC may be connected to a driving voltage line PL transmitting a first power voltage ELVDD, a reference voltage line VL1 applying a reference voltage VREF, a first initialization voltage line VL2 transmitting a first initialization voltage Vint, and a second initialization voltage line VL3 transmitting a second initialization voltage Vaint.

[0122] The first transistor T1 may include a first terminal connected to the driving voltage line PL via a fifth transistor T5, a second terminal connected to the second node N2, a first gate connected to the first node N1, and a second gate connected to the second node N2. The first transistor T1 may receive the data signal Vdata in response to a switching operation of the second transistor T2 and supply a driving current Id to the organic light emitting diode OLED.

[0123] The second transistor T2 (data write transistor) may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 may be turned on in response to a first gate signal GW received via the first gate line GWL, and may perform a switching operation for transmitting a data signal Vdata received via the data line DL to the first node N1.

[0124] The third transistor T3 (first initialization transistor) may include a gate connected to the third gate line GRL, a first terminal connected to the reference voltage line VL1, and a second terminal connected to the first node N1. The third transistor T3 may be turned on in response to a third gate signal GR received via the third gate line GRL, and may transmit a reference voltage VREF received via the reference voltage line VL1 and initialize the first node N1.

[0125] The fourth transistor T4 (second initialization transistor) may include a gate connected to the second gate line GIL, a first terminal connected to the first initialization voltage line VL2, and a second terminal connected to the second node N2. The fourth transistor T4 may be turned on in response to a second gate signal GI received via the second gate line GIL, and may transmit a first initialization voltage Vint received via the first initialization voltage line VL2 to the second node N2, and initialize the second node N2.

[0126] The fifth transistor T5 (first emission control transistor) may include a gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The sixth transistor T6 (second emission control transistor) may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The fifth transistor T5 may be turned on in response to a fourth gate signal EM received via the fourth gate line EML, and the sixth transistor T6 may be turned on in response to a fifth gate signal EMB received via the fifth gate line EMBL, so that the driving current Id may flow through the organic light emitting diode OLED.

[0127] In another embodiment, the gate of the fifth transistor T5 and the gate of the sixth transistor T6 can be connected to the same gate line (emission control signal line). In this case, the fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously by the same gate signal (emission control signal).

[0128] The seventh transistor T7 (third initialization transistor) may include a gate connected to the second gate line GIL, a first terminal connected to the second initialization voltage line VL3, and a second terminal connected to the third node N3. The seventh transistor T7 may be turned on in response to the second gate signal GI received via the second gate line GIL, and may transmit the second initialization voltage Vaint received via the second initialization voltage line VL3 to the third node N3 and initialize the pixel electrode of the organic light emitting diode OLED.

[0129] exist Figure 3B In the embodiment, the first terminal of the fourth transistor T4 and the first terminal of the seventh transistor T7 are respectively connected to different voltage lines. However, the present disclosure is not limited thereto. In an embodiment, the first terminal of the fourth transistor T4 and the first terminal of the seventh transistor T7 may be connected to the same voltage line, and the same initialization voltage may be transmitted to the second node N2 and the third node N3.

[0130] The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The first capacitor C1, which is a storage capacitor, may store a voltage corresponding to a threshold voltage of the first transistor T1 and the data signal Vdata.

[0131] The second capacitor C2 may include a first electrode connected to the driving voltage line PL and a second electrode connected to the second node N2. In an embodiment, the capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2. Figure 3B In the embodiment, the first electrode of the second capacitor C2 is connected to the driving voltage line PL. However, the present disclosure is not limited thereto. In an embodiment, for example, the first electrode of the second capacitor C2 may be connected to a reference voltage line VL1 transmitting a reference voltage VREF, a first initialization voltage line VL2 transmitting a first initialization voltage Vint, or a second initialization voltage line VL3 transmitting a second initialization voltage Vaint.

[0132] The organic light emitting diode OLED may include a pixel electrode connected to the third node N3 and an opposing electrode facing the pixel electrode, and the opposing electrode may receive the second power voltage ELVSS. The opposing electrode may be a common electrode shared by a plurality of sub-pixels Ps.

[0133] Figure 4A and Figure 4Bare cross-sectional views each schematically illustrating an example of a region of the display device 10 .

[0134] refer to Figure 4A and Figure 4B The display device 10 may include a sub-pixel Ps (refer to Figure 2 ). The sub-pixel Ps may include a sub-pixel circuit PC (refer to Figure 3A ) and an organic light emitting diode OLED electrically connected to the sub-pixel circuit PC. The sub-pixel circuit PC may include a thin film transistor and a capacitor. Figure 4A and Figure 4B The first thin film transistor TFT1 shown in FIG. 1 may correspond to the first transistor T1 (refer to Figure 3A ), and the second thin film transistor TFT2 may correspond to the sixth transistor T6 (reference Figure 3A ).

[0135] The display device 10 may include a substrate 100. The substrate 100 may include an area corresponding to a display area DA and a peripheral area PA (refer to FIG. Figure 1 Herein, when the substrate 100 includes the display area DA and the peripheral area PA, this means that the substrate 100 includes an area corresponding to the display area DA and an area corresponding to the peripheral area PA.

[0136] The substrate 100 may include a glass material, a ceramic material, a metal material, or a material having a flexible or bendable property. When the substrate 100 has a flexible or bendable property, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0137] The substrate 100 may have a single layer structure or a multi-layer structure. In an embodiment, the substrate 100 may have a multi-layer structure in which an inorganic layer is located between base layers including the polymer resin described above.

[0138] The barrier layer 101 may be disposed on the substrate 100. The barrier layer 101 may prevent or minimize impurities from penetrating into the sub-pixel circuit PC from the substrate 100, etc. The barrier layer 101 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic and inorganic compound, and may have a single-layer or multi-layer structure of an inorganic material and / or an organic material.

[0139] The third electrode C13 of the first capacitor C1 and the first electrode C21 of the second capacitor C2 may be disposed on the barrier layer 101. In an embodiment, the first electrode C21 of the second capacitor C2 may be connected to the driving voltage line PL. The third electrode C13 of the first capacitor C1 and the first electrode C21 of the second capacitor C2 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include one or more layers.

[0140] The first buffer layer 111 may be disposed on the third electrode C13 of the first capacitor C1 and the first electrode C21 of the second capacitor C2. The first buffer layer 111 may include an inorganic material such as oxide or nitride, an organic material, or an organic and inorganic compound, and may have a single layer or multilayer structure of an inorganic material and / or an organic material.

[0141] The second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, and the first lower gate electrode G12 of the first thin film transistor TFT1 may be disposed on the first buffer layer 111. In an embodiment, the second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, and the first lower gate electrode G12 of the first thin film transistor TFT1 may be integrally provided as a single body.

[0142] The second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, and the first lower gate electrode G12 of the first thin film transistor TFT1 may include Mo, Al, Cu, Ti, or the like, and may include one or more layers.

[0143] In a plan view, the second electrode C22 of the second capacitor C2 may overlap the first electrode C21 of the second capacitor C2 to form the second capacitor C2.

[0144] The second buffer layer 112 may be disposed on the second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, and the first lower gate electrode G12 of the first thin film transistor TFT1. The second buffer layer 112 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic and inorganic compound, and may have a single-layer or multi-layer structure of an inorganic material and / or an organic material.

[0145] The first semiconductor layer of the first thin film transistor TFT1 and the second semiconductor layer of the second thin film transistor TFT2 may be disposed on the second buffer layer 112. In an embodiment, the first semiconductor layer and the second semiconductor layer may include an oxide semiconductor material. In an embodiment, for example, the oxide semiconductor material may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), Al, cesium (Cs), cerium (Ce), and zinc (Zn). The oxide semiconductor material may be IGZO, ITZO, or IGTZO.

[0146] Each of the first semiconductor layer and the second semiconductor layer may include a channel region and a source region and a drain region respectively disposed on opposite sides of the channel region. In an embodiment, for example, the first semiconductor layer may include a first source region S1 and a first drain region D1 of a first thin film transistor TFT1, and the second semiconductor layer may include a second source region S2 and a second drain region D2 of a second thin film transistor TFT2.

[0147] The first upper gate electrode G11 and the first lower gate electrode G12 of the first thin film transistor TFT1 may overlap the channel region of the first semiconductor layer. The second gate electrode G2 of the second thin film transistor TFT2 may overlap the channel region of the second semiconductor layer.

[0148] The gate insulating layer 113 may be disposed on the first semiconductor layer and the second semiconductor layer. The gate insulating layer 113 may include an inorganic insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. Figure 4A and Figure 4B As shown in , the gate insulating layer 113 may be patterned to have a shape corresponding to a conductive layer disposed on the gate insulating layer 113 .

[0149] The first upper gate electrode G11 of the first thin film transistor TFT1, the second gate electrode G2 of the second thin film transistor TFT2, and the first electrode C11 of the first capacitor C1 may be disposed on the gate insulating layer 113. Each of the first upper gate electrode G11 of the first thin film transistor TFT1, the second gate electrode G2 of the second thin film transistor TFT2, and the first electrode C11 of the first capacitor C1 may include Mo, Al, Cu, Ti, or the like, and may include one or more layers.

[0150] In a plan view, the first electrode C11 of the first capacitor C1 may overlap with the second electrode C12 and the third electrode C13 of the first capacitor C1 to form the first capacitor C1. In an embodiment, the first electrode C11 of the first capacitor C1 may be connected in contact with the third electrode C13 of the first capacitor C1 through a contact hole passing through the first buffer layer 111, the second buffer layer 112, and the gate insulating layer 113.

[0151] The interlayer insulating layer 114 may be disposed on the first upper gate electrode G11 of the first thin film transistor TFT1, the second gate electrode G2 of the second thin film transistor TFT2, and the first electrode C11 of the first capacitor C1. The interlayer insulating layer 114 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic and inorganic compound, and may have a single-layer or multi-layer structure of an inorganic material and / or an organic material.

[0152] The first connection electrode 134, the second connection electrode 136, and the data line DL may be disposed on the interlayer insulating layer 114. The first connection electrode 134 may be connected to the first source region S1 of the first thin film transistor TFT1, the second drain region D2 of the second thin film transistor TFT2, the second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, and the first lower gate electrode G12 of the first thin film transistor TFT1 via a contact hole. The second connection electrode 136 may be connected to the second source region S2 of the second thin film transistor TFT2 through a contact hole passing through the interlayer insulating layer 114.

[0153] The first connection electrode 134, the second connection electrode 136 and the data line DL may include a conductive material including Mo, Al, Cu or Ti, etc., and may include one or more layers including the materials described above. In an embodiment, for example, the first connection electrode 134, the second connection electrode 136 and the data line DL may have a multilayer of Ti / Al / Ti.

[0154] The first organic insulating layer 115 may be disposed on the first connection electrode 134, the second connection electrode 136, and the data line DL. In an embodiment, the first organic insulating layer 115 may include an organic insulating material such as a general polymer (e.g., poly(methyl methacrylate) ("PMMA") or polystyrene ("PS")), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and any combination thereof.

[0155] The third connection electrode 142 and the driving voltage line PL may be disposed on the first organic insulating layer 115. The third connection electrode 142 may be connected to the second connection electrode 136 through a contact hole passing through the first organic insulating layer 115. The third connection electrode 142 and the driving voltage line PL may include a conductive material including Mo, Al, Cu, or Ti, etc., and may include or consist of one or more layers including the materials described above. In an embodiment, for example, the third connection electrode 142 and the driving voltage line PL may have a multilayer of Ti / Al / Ti.

[0156] exist Figure 4A and Figure 4B In the embodiment, the data line DL and the driving voltage line PL are arranged in different layers. However, in another embodiment, the data line DL and the driving voltage line PL may be arranged in the same layer. In an embodiment, for example, the data line DL may be arranged between the first organic insulating layer 115 and the second organic insulating layer 116.

[0157] The second organic insulating layer 116 may be disposed on the third connection electrode 142 and the driving voltage line PL. The second organic insulating layer 116 may include an organic material. In an embodiment, for example, the second organic insulating layer 116 may include an organic insulating material such as a general polymer (e.g., PMMA or PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and any combination thereof.

[0158] The organic light emitting diode OLED may be disposed on the second organic insulating layer 116. The organic light emitting diode OLED may include a pixel electrode 210, an emission layer 220, and an opposing electrode 230.

[0159] The pixel electrode 210 may be disposed on the second organic insulating layer 116. The pixel electrode 210 may be connected to the third connection electrode 142 through a contact hole passing through the second organic insulating layer 116. The pixel electrode 210 may be connected to the second source region S2 of the second thin film transistor TFT2 through the third connection electrode 142 and the second connection electrode 136.

[0160] The pixel electrode 210 may include a reflective film comprising silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or any combination thereof. In an alternative embodiment, the pixel electrode 210 may further include a conductive oxide layer located above and / or below the reflective film described above. The conductive oxide layer may include indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, indium gallium oxide and / or aluminum zinc oxide. In an embodiment, the pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0161] The bank layer 119 may be disposed on the pixel electrode 210. An opening 119OP may be defined in the bank layer 119 to expose at least a portion of the pixel electrode 210. A central portion of the pixel electrode 210 may be exposed through the opening 119OP defined in the bank layer 119. The bank layer 119 may prevent arcing, etc., from occurring at an edge of the pixel electrode 210 by increasing a distance between the edge of the pixel electrode 210 and the counter electrode 230 located above the pixel electrode 210. The opening 119OP may define an emission region of the organic light emitting diode OLED.

[0162] The bank layer 119 may include an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane ("HMDSO"), or phenolic resin. The bank layer 119 may be formed by spin coating or the like.

[0163] In an embodiment, the bank layer 119 may include a light-blocking material and may be provided in black. The light-blocking material may include carbon black, carbon nanotubes, a resin or paste containing a black dye, metal particles such as Ni, Al, Mo, and any alloy thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride), etc. When the bank layer 119 includes a light-blocking material, reflection of a metal element disposed below the bank layer 119 may be reduced.

[0164] A spacer (not shown) may be formed on the bank layer 119. The spacer may be formed together with the bank layer 119 in the same process, or may be separately formed in a separate process.

[0165] The emission layer 220 may include an organic material including or consisting of a fluorescent or phosphorescent material emitting red, green, blue or white light, or may be composed of the above-mentioned organic material. The emission layer 220 may be a low molecular weight organic material or a polymer organic material, and functional layers such as a hole transport layer, a hole injection layer, an electron transport layer and an electron injection layer may be further selectively disposed below and above the emission layer 220.

[0166] The emission layer 220 may have a patterned shape corresponding to the pixel electrode 210. A functional layer such as a hole transport layer may be integrally provided across a plurality of pixel electrodes 210.

[0167] The counter electrode 230 may be disposed on the emission layer 220. The counter electrode 230 may include a conductive material having a relatively low work function. In an embodiment, for example, the counter electrode 230 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or any alloy thereof. In an alternative embodiment, the counter electrode 230 may further include an indium tin oxide ("ITO"), indium zinc oxide ("IZO"), ZnO, or indium oxide (In) on the (semi) transparent layer including the materials described above. 2 O 3 In an embodiment, the counter electrode 230 may be integrally provided as a single body across a plurality of pixel electrodes 210 to cover the entire display area DA.

[0168] Figure 5 is a diagram for describing an embodiment of a sub-demultiplexer DMX.

[0169] refer to Figure 5 , the sub-demultiplexer DMX may selectively connect the kth data output line OLk to the ith data line DLi and the i+3th data line DLi+3. The sub-demultiplexer DMX may include a first switch SW1 and a second switch SW2.

[0170] The i-th data line DLi and the i+3-th data line DLi+3 may be data lines arranged to be spaced apart from each other with two columns interposed therebetween. In an embodiment, for example, the i+1-th data line and the i+2-th data line may be arranged between the i-th data line DLi and the i+3-th data line DLi+3. The i-th data line DLi may be connected to a sub-pixel in the i-th column (e.g., labeled by M1), and the i+3-th data line DLi+3 may be connected to a sub-pixel in the i+3-th column (e.g., labeled by M4).

[0171] The first switch SW1 may be provided between the kth data output line OLk and the ith data line DLi. The first switch SW1 may connect the kth data output line OLk to the ith data line DLi through the first control signal CLA and may apply the data signal DATA applied via the kth data output line OLk to the ith data line DLi.

[0172] The second switch SW2 may be provided between the kth data output line OLk and the i+3th data line DLi+3. The second switch SW2 may connect the kth data output line OLk to the i+3th data line DLi+3 through the second control signal CLB, and may apply the data signal DATA applied via the kth data output line OLk to the i+3th data line DLi+3.

[0173] From the control circuit 180 (reference Figure 2 ) The control signal CCS of the sub-demultiplexer DMX outputted by the control circuit may include a first control signal CLA and a second control signal CLB. The first control signal CLA and the second control signal CLB may be applied alternately at different timings without overlapping.

[0174] In an embodiment, sub-pixels connected to the i-th data line DLi and the i+3-th data line DLi+3 may emit light of the same color. In this regard, Figure 5 It is shown that the sub-pixels connected to the i-th data line DLi and the i+3-th data line DLi+3 are red sub-pixels PR that emit red light. However, the present disclosure is not limited to this. The connection between the data lines and the sub-pixels may be modified in various ways. In another embodiment, the sub-pixels connected to the i-th data line DLi may include sub-pixels that emit light of a first color and sub-pixels that emit light of a second color different from the first color, and the sub-pixels connected to the i+3-th data line DLi+3 may include sub-pixels that emit light of the first color and sub-pixels that emit light of the second color, and the sub-pixels connected to the i+1-th data line and the i+4-th data line may be sub-pixels that emit light of a third color different from the first color and the second color.

[0175] exist Figure 5 , a red sub-pixel PR connected to an n-1th gate line GLn-1 disposed in an n-1th row and an nth gate line GLn disposed in an nth row is shown. Figure 5 The gate lines GLn-1 and GLn shown in FIG. 4 may be Figure 2 The gate lines (eg, GL1, GL2, ..., GLn) shown in Figure 3A and Figure 3B The first gate line GWL is shown in FIG.

[0176] Figure 6 is a diagram schematically illustrating an embodiment of a display device. Figure 7 Is used to describe Figure 6 0 is a timing diagram of the operation of the display device shown in .

[0177] refer to Figure 6, the data distribution unit 170 may include a first demultiplexer DMX1 and a second demultiplexer DMX2, and the pixel unit 110 may include a plurality of pixels PX. The pixel PX may include a red sub-pixel PR, a green sub-pixel PG, and a blue sub-pixel PB. The above description of the sub-pixel Ps may be applicable to any one of the red sub-pixel PR, the green sub-pixel PG, and the blue sub-pixel PB.

[0178] In the pixel unit 110, the columns in which the red sub-pixels PR are arranged in the second direction (e.g., the y-axis direction), the columns in which the green sub-pixels PG are arranged in the second direction (e.g., the y-axis direction), and the columns in which the blue sub-pixels PB are arranged in the second direction (e.g., the y-axis direction) may be alternately repeated in the first direction (e.g., the x-axis direction).

[0179] In an embodiment, for example, in the first row, the first pixel, the second pixel, the third pixel and the fourth pixel may be arranged sequentially in a first direction (e.g., the x-axis direction), the first pixel may include three sub-pixels PR11, PG11 and PB11 in the first to third columns, the second pixel may include three sub-pixels PR12, PG12 and PB12 in the fourth to sixth columns, the third pixel may include three sub-pixels PR13, PG13 and PB13 in the seventh to ninth columns, and the fourth pixel may include three sub-pixels PR14, PG14 and PB14 in the tenth to twelfth columns.

[0180] A plurality of data lines DL1, DL2, . . . , DL12 and a plurality of gate lines GLn-3, GLn-2, ​​GLn-1, and GLn may be arranged in the pixel unit 110. The plurality of gate lines GLn-3, GLn-2, ​​GLn-1, and GLn may be Figure 2 The gate lines (eg, GL1, GL2, ..., GLn) shown in Figure 3A and Figure 3B The first gate line GWL is shown in FIG.

[0181] A gate line may be connected to sub-pixels arranged in the same row. A data line may be connected to sub-pixels arranged in the same column. A sub-pixel connected to the i-th data line DLi and a sub-pixel connected to the i+3-th data line DLi+3 may be sub-pixels emitting light of the same color. For ease of description, Figure 6 Only twelve data lines DL1, DL2, ..., and DL12, four gate lines GLn-3, GLn-2, ​​GLn-1, and GLn, and six data output lines OL1, OL2, ..., and OL6 are shown. However, the number of data lines, the number of gate lines, and the number of data output lines may be greater.

[0182] The first demultiplexer DMX1 may selectively connect the data output lines OL1, OL2, and OL3 belonging to the first group GR1 to the first to sixth data lines DL1, DL2, ..., and DL6, and the second demultiplexer DMX2 may selectively connect the data output lines OL4, OL5, and OL6 belonging to the second group GR2 to the seventh to twelfth data lines DL7, DL8, ..., and DL12.

[0183] Each of the first demultiplexer DMX1 and the second demultiplexer DMX2 may include a plurality of sub-demultiplexers DMX (refer to Figure 5 ). One sub-demultiplexer DMX may selectively connect one data output line to a pair of data lines. The pair of data lines connected to one sub-demultiplexer DMX may be arranged to be spaced apart from each other with two columns interposed therebetween.

[0184] In an embodiment, for example, a pair of data lines connected to the first data output line OL1 belonging to the first group GR1 may be a first data line DL1 and a fourth data line DL4. The first data line DL1 may be connected to a red sub-pixel PR11 of a first pixel, and the fourth data line DL4 may be connected to a red sub-pixel PR12 of a second pixel.

[0185] A pair of data lines connected to the fourth data output line OL4 belonging to the second group GR2 may be seventh and tenth data lines DL7 and DL10. The seventh data line DL7 may be connected to the red subpixel PR13 of the third pixel, and the tenth data line DL10 may be connected to the red subpixel PR14 of the fourth pixel.

[0186] The first demultiplexer DMX1 may include a first switch SW1 and a second switch SW2. Each of the first switches SW1 may be provided between the first data output line OL1 and the first data line DL1, between the second data output line OL2 and the second data line DL2, and between the third data output line OL3 and the third data line DL3. The first switch SW1 may be turned on by a first control signal CLA1, and may connect the first data output line OL1 to the first data line DL1, the second data output line OL2 to the second data line DL2, and the third data output line OL3 to the third data line DL3.

[0187] Each of the second switches SW2 may be provided between the first data output line OL1 and the fourth data line DL4, between the second data output line OL2 and the fifth data line DL5, and between the third data output line OL3 and the sixth data line DL6. The second switch SW2 may be turned on by the second control signal CLB1, and may connect the first data output line OL1 to the fourth data line DL4, the second data output line OL2 to the fifth data line DL5, and the third data output line OL3 to the sixth data line DL6.

[0188] The first data signal DATA applied to the first data output line OL1 <1> The first sub-data signal R applied to the red sub-pixel PR and the second data signal DATA applied to the second data output line OL2 may be included. <2> The second sub-data signal G applied to the green sub-pixel PG and the third data signal DATA applied to the third data output line OL3 may be included. <3> A third sub-data signal B applied to the blue sub-pixel PB may be included.

[0189] The second demultiplexer DMX2 may include a third switch SW3 and a fourth switch SW4. Each of the third switches SW3 may be provided between the fourth data output line OL4 and the seventh data line DL7, between the fifth data output line OL5 and the eighth data line DL8, and between the sixth data output line OL6 and the ninth data line DL9. The third switch SW3 may be turned on by the third control signal CLA2, and may connect the fourth data output line OL4 to the seventh data line DL7, the fifth data output line OL5 to the eighth data line DL8, and the sixth data output line OL6 to the ninth data line DL9.

[0190] Each of the fourth switches SW4 may be provided between the fourth data output line OL4 and the tenth data line DL10, between the fifth data output line OL5 and the eleventh data line DL11, and between the sixth data output line OL6 and the twelfth data line DL12. The fourth switch SW4 may be turned on according to the fourth control signal CLB2, and may connect the fourth data output line OL4 to the tenth data line DL10, the fifth data output line OL5 to the eleventh data line DL11, and the sixth data output line OL6 to the twelfth data line DL12.

[0191] The fourth data signal DATA applied to the fourth data output line OL4 <4> The first sub-data signal R applied to the red sub-pixel PR, the fifth data signal DATA applied to the fifth data output line OL5, <5> The second sub-data signal G applied to the green sub-pixel PG and the sixth data signal DATA applied to the sixth data output line OL6 may be included. <6> A third sub-data signal B applied to the blue sub-pixel PB may be included.

[0192] Figure 7 The data driving unit 150 (refer to Figure 2 ) The order of data signals applied to sub-pixels through data output lines. Hereinafter, when supplying or outputting any signal is described without separate mention, this may mean the on-voltage of the supply signal.

[0193] refer to Figure 7 , the first control signal CLA1, the second control signal CLB1, the third control signal CLA2 and the fourth control signal CLB2 can be obtained from the control circuit 180 (reference Figure 2 ) through the power output line POL (reference Figure 2 ) is supplied to the first demultiplexer DMX1 (reference Figure 6 ) and the second demultiplexer DMX2 (reference Figure 6 ).

[0194] The first control signal CLA1, the second control signal CLB1, the third control signal CLA2, and the fourth control signal CLB2 may be square wave signals in which a turn-on voltage that may turn on the first to fourth switches SW1, SW2, SW3, and SW4 and a turn-off voltage that may turn off the first to fourth switches SW1, SW2, SW3, and SW4 are repeated. In an embodiment, the turn-on voltage of the first control signal CLA1, the second control signal CLB1, the third control signal CLA2, and the fourth control signal CLB2 may be a high level voltage (a first level voltage), and the turn-off voltage of the first control signal CLA1, the second control signal CLB1, the third control signal CLA2, and the fourth control signal CLB2 may be a low level voltage (a second level voltage).

[0195] The first control signal CLA1 and the second control signal CLB1 may have the same waveform, but may be signals with offset phases. The third control signal CLA2 and the fourth control signal CLB2 may have the same waveform, but may be signals with offset phases. In an embodiment, for example, the timing at which the voltage levels of the first control signal CLA1 and the second control signal CLB1 are inverted may be the same. The period during which the on-voltage of the first control signal CLA1 is maintained (hereinafter, also referred to as the "on-voltage period") may overlap with the period during which the off-voltage of the second control signal CLB1 is maintained (hereinafter, also referred to as the "off-voltage period"), and the off-voltage period of the first control signal CLA1 may overlap with the on-voltage period of the second control signal CLB1.

[0196] The first control signal CLA1 and the third control signal CLA2 may have the same phase, and the second control signal CLB1 and the fourth control signal CLB2 may have the same phase. In an embodiment, for example, the on-voltage period of the first control signal CLA1 may overlap with the on-voltage period of the third control signal CLA2, and the off-voltage period of the first control signal CLA1 may overlap with the off-voltage period of the third control signal CLA2. The on-voltage period of the second control signal CLB1 may overlap with the on-voltage period of the fourth control signal CLB2, and the off-voltage period of the second control signal CLB1 may overlap with the off-voltage period of the fourth control signal CLB2.

[0197] In other words, the first and third switches SW1 and SW3 may be turned on or off simultaneously by the first and third control signals CLA1 and CLA2 , and the second and fourth switches SW2 and SW4 may be turned on or off simultaneously by the second and fourth control signals CLB1 and CLB2 .

[0198] During one frame, the gate signals Gn-3, Gn-2, Gn-1, and Gn-2 may be transmitted from the gate driving unit 130 (reference Figure 2 ) is sequentially supplied through gate lines GLn-3, GLn-2, ​​GLn-1 and GLn. Gate signals Gn-3, Gn-2, Gn-1 and Gn may be gate control signals for controlling the conduction and cut-off of a data write transistor (e.g., a second transistor T2). Gate signals Gn-3, Gn-2, Gn-1 and Gn may be supplied with a turn-on voltage for turning on the data write transistor and a cut-off voltage for cutting off the data write transistor. In an embodiment, the turn-on voltage of gate signals Gn-3, Gn-2, Gn-1 and Gn may be a high level voltage (a first level voltage), and the cut-off voltage of gate signals Gn-3, Gn-2, Gn-1 and Gn may be a low level voltage (a second level voltage).

[0199] The on-voltage period of the gate signals Gn-3, Gn-2, Gn-1, and Gn-2 may also be referred to as a line period LT. The line period LT may be a period of time during which the display device 10 (refer to FIG. 1 ) Figure 1 ) for a row (a line) of sub-pixels Ps (reference Figure 2 )The time required for writing the data signal DATA. In an embodiment, the line time period LT may be about 2H. The line time period LT may include a first sub-line time period LT1 and a second sub-line time period LT2 following the first sub-line time period LT1. Each of the first sub-line time period LT1 and the second sub-line time period LT2 may be about 1H. For each of the sub-line time periods LT1 and LT2, the turn-on voltage of the first control signal CLA1 and the turn-on voltage of the second control signal CLB1 may be alternately supplied to the first demultiplexer DMX1, and the turn-on voltage of the third control signal CLA2 and the turn-on voltage of the fourth control signal CLB2 may be alternately supplied to the second demultiplexer DMX2.

[0200] During the first sub-line time period LT1 of the line time period of the row to which the gate signal is supplied (hereinafter referred to as the "current line time period"), the first control signal CLA1 and the third control signal CLA2 may be supplied with a turn-on voltage, and then the first control signal CLA1 and the third control signal CLA2 may transition to a turn-off voltage and the second control signal CLB1 and the fourth control signal CLB2 may be supplied with a turn-on voltage. Similarly, during the second sub-line time period LT2, the first control signal CLA1 and the third control signal CLA2 may be supplied with a turn-on voltage, and then the first control signal CLA1 and the third control signal CLA2 may transition to a turn-off voltage and the second control signal CLB1 and the fourth control signal CLB2 may be supplied with a turn-on voltage. During the second sub-line time period LT2 of the current line time period, the data signal DATA corresponding to the sub-pixel Ps of the row to which the gate signal having the turn-on voltage is supplied may be written.

[0201] The data driving unit 150 (reference Figure 2 ) can be synchronized with the control signals CLA1, CLB1, CLA2 and CLB2, and can supply the data signal DATA to each data output line.

[0202] In an embodiment, for example, when the n-3rd gate signal Gn-3 is supplied to the n-3rd gate line GLn-3 during the line period LT, the sub-pixels PR11, PG11, PB11, PR12, ..., PB14 connected to the n-3rd gate line GLn-3 may be selected, and the data driving unit 150 may drive the data signal DATA <1> ,DATA <2> ,…,DATA <6> Output to data output lines OL1, OL2, ..., OL6.

[0203] In each of the sub-line time periods LT1 and LT2, the first control signal CLA1 and the third control signal CLA2 may be supplied with a turn-on voltage, and then the second control signal CLB1 and the fourth control signal CLB2 may be supplied with a turn-on voltage. The sub-data signal supplied during the first sub-line time period LT1 may be a sub-data signal of a previous line time period corresponding to a row (previous line) to which a previous gate signal is supplied.

[0204] During the second sub-line time period LT2, the first control signal CLA1 may be supplied to the first switch SW1 of the first demultiplexer DMX1 at an on voltage, and the third control signal CLA2 may be supplied to the third switch SW3 of the second demultiplexer DMX2 at an on voltage. Accordingly, the sub-data signals R11, G11, B11, R13, G13, and B13 of the current line time period may be supplied to the sub-pixels PR11, PG11, PB11, PR12, ..., PB14 connected to the n-3th gate line GLn-3, the sub-pixels PR11, PG11, and PB11 connected to the data lines DL1, DL2, and DL3 to which the first switch SW1 is connected, and the sub-pixels PR13, PG13, and PB13 connected to the data lines DL7, DL8, and DL9 to which the third switch SW3 is connected.

[0205] Thereafter, the second control signal CLB1 may be supplied to the second switch SW2 of the first demultiplexer DMX1 at an on voltage, and the fourth control signal CLB2 may be supplied to the fourth switch SW4 of the second demultiplexer DMX2 at an on voltage. Accordingly, the sub-data signals R12, G12, B12, R14, G14, and B14 may be supplied to the sub-pixels PR12, PG12, and PB12 connected to the data lines DL4, DL5, and DL6 to which the second switch SW2 is connected, and the sub-pixels PR14, PG14, and PB14 connected to the data lines DL10, DL11, and DL12 to which the fourth switch SW4 is connected, among the sub-pixels PR11, PG11, PB11, PR12, ..., PB14 connected to the n-3 th gate line GLn-3.

[0206] The sub-data signal of the previous line period written to the sub-pixel Ps during the first sub-line period LT1 may be overwritten by the sub-data signal of the current line period written to the sub-pixel Ps during the second sub-line period LT2 .

[0207] Similarly, when the n-2 th gate signal Gn-2 is supplied to the n-2 th gate line GLn-2 during the line period LT, the sub-pixels PR21, PG21, PB21, PR22, ..., PB24 connected to the n-2 th gate line GLn-2 may be selected, and the data driving unit 150 may drive the data signal DATA <1> ,DATA <2> ,…,DATA <6> Output to data output lines OL1, OL2, ..., OL6.

[0208] The first sub-line period LT1 of the n-2 th gate signal Gn-2 may overlap with the second sub-line period LT2 of the n-3 th gate signal Gn-3. During the first sub-line period LT1 of the n-2 th gate signal Gn-2, the first control signal CLA1 may be supplied to the first switch SW1 of the first demultiplexer DMX1 with a turn-on voltage, and the third control signal CLA2 may be supplied to the third switch SW3 of the second demultiplexer DMX2 with a turn-on voltage. Accordingly, the sub-data signals R11, G11, B11, R13, G13 and B13 of the previous line time period can be supplied to the sub-pixels PR21, PG21, PB21, PR22, ..., PB24 connected to the n-2th gate line GLn-2, ​​the sub-pixels PR21, PG21 and PB21 connected to the data lines DL1, DL2 and DL3 to which the first switch SW1 is connected, and the sub-pixels PR23, PG23 and PB23 connected to the data lines DL7, DL8 and DL9 to which the third switch SW3 is connected.

[0209] Thereafter, the second control signal CLB1 may be supplied to the second switch SW2 of the first demultiplexer DMX1, and the fourth control signal CLB2 may be supplied to the fourth switch SW4 of the second demultiplexer DMX2. Accordingly, the sub-data signals R12, G12, B12, R14, G14, and B14 of the previous line period may be supplied to the sub-pixels PR21, PG21, PB21, PR22, ..., PB24 connected to the data lines DL4, DL5, and DL6 to which the second switch SW2 is connected, and the sub-pixels PR24, PG24, and PB24 connected to the data lines DL10, DL11, and DL12 to which the fourth switch SW4 is connected.

[0210] During the second sub-line period LT2 of the n-2 th gate signal Gn-2, the first control signal CLA1 may be supplied to the first switch SW1 of the first demultiplexer DMX1, and the third control signal CLA2 may be supplied to the third switch SW3 of the second demultiplexer DMX2. Accordingly, the sub-data signals R21, G21, B21, R23, G23, and B23 of the current line period may be supplied to the sub-pixels PR21, PG21, PB21, PR22, ..., PB24 connected to the n-2 th gate line GLn-2, ​​the sub-pixels PR21, PG21, and PB21 connected to the data lines DL1, DL2, and DL3 to which the first switch SW1 is connected, and the sub-pixels PR23, PG23, and PB23 connected to the data lines DL7, DL8, and DL9 to which the third switch SW3 is connected.

[0211] Thereafter, the second control signal CLB1 may be supplied to the second switch SW2 of the first demultiplexer DMX1, and the fourth control signal CLB2 may be supplied to the fourth switch SW4 of the second demultiplexer DMX2. Accordingly, the sub-data signals R22, G22, B22, R24, G24, and B24 of the current line period may be supplied to the sub-pixels PR21, PG21, PB21, PR22, ..., PB24 connected to the n-2 gate line GLn-2, ​​the sub-pixels PR22, PG22, and PB22 connected to the data lines DL4, DL5, and DL6 to which the second switch SW2 is connected, and the sub-pixels PR24, PG24, and PB24 connected to the data lines DL10, DL11, and DL12 to which the fourth switch SW4 is connected.

[0212] In this manner, the data driving unit 150 may write data to all pixels PX during a single line period LT.

[0213] Figure 8 is a diagram schematically illustrating an embodiment of the display device 10 .

[0214] refer to Figure 8 , the display device 10 may include a pixel unit 110, a data distribution unit 170, a data driving circuit DIC, and power supply circuits PIC1, PIC2, ​​PIC3, and PIC4. The data driving circuit DIC may be included in Figure 2 In the data driving unit 150 shown in FIG. 1 , the power supply circuits PIC1, PIC2, ​​PIC3, and PIC4 may be included. Figure 2 In the control circuit 180 shown in .

[0215] The pixel unit 110 may include a data line DL and a plurality of sub-pixels Ps. Each of the plurality of sub-pixels Ps may be connected to a corresponding data line among the plurality of data lines DL. The data line DL may extend from the pixel unit 110 in a second direction (e.g., y-axis direction) and may be connected to the data distribution unit 170.

[0216] The data distribution unit 170 may be connected between a plurality of data output lines and a plurality of data lines DL. For ease of description, Figure 8 The data output line is omitted. The data distribution unit 170 may include a plurality of sub-demultiplexers DMX each including two switches. Figure 5 As described, the sub-demultiplexer DMX can selectively connect one data output line to a pair of data lines according to the control signals CLA1, CLB1, CLA2, and CLB2.

[0217] The data distribution unit 170 may be connected to the data driving circuit DIC through a plurality of data output lines. As the display device 10 becomes larger, one display device 10 may have a plurality of data driving circuits DIC. The data driving circuits DIC may be arranged spaced apart from each other in a first direction (e.g., an x-axis direction). A plurality of power supply circuits PIC1, PIC2, ​​PIC3, and PIC4 may be arranged between the data driving circuits DIC.

[0218] The power circuits PIC1, PIC2, ​​PIC3, and PIC4 may include a first power circuit PIC1 supplying a first control signal CLA1, a second power circuit PIC2 supplying a second control signal CLB1, a third power circuit PIC3 supplying a third control signal CLA2, and a fourth power circuit PIC4 supplying a fourth control signal CLB2. In an embodiment, the power circuits PIC1, PIC2, ​​PIC3, and PIC4 may be power management ICs.

[0219] The control signal lines CSL1, CSL2, CSL3, and CSL4 extending in a first direction (eg, an x-axis direction) may be arranged between the power supply circuits PIC1, PIC2, ​​PIC3, and PIC4 and the data distribution unit 170. The first control signal line CSL1 may switch the first switch SW1 (reference Figure 6 ) is connected to the first power supply circuit PIC1, and the second control signal line CSL2 can connect the second switch SW2 (reference Figure 6 ) is connected to the second power supply circuit PIC2, ​​and the third control signal line CSL3 can switch the third switch SW3 (reference Figure 6 ) is connected to the third power supply circuit PIC3, and the fourth control signal line CSL4 can connect the fourth switch SW4 (reference Figure 6 ) is connected to the fourth power supply circuit PIC4.

[0220] In an embodiment, for example, the display device 10 may include a first power output line POL1, a second power output line POL2, a third power output line POL3, and a fourth power output line POL4. The first control signal line CSL1 may be connected to the first power circuit PIC1 through the first power output line POL1, the second control signal line CSL2 may be connected to the second power circuit PIC2 through the second power output line POL2, the third control signal line CSL3 may be connected to the third power circuit PIC3 through the third power output line POL3, and the fourth control signal line CSL4 may be connected to the fourth power circuit PIC4 through the fourth power output line POL4.

[0221] The first control signal CLA1 supplied from the first power circuit PIC1 and the third control signal CLA2 supplied from the third power circuit PIC3 may have the same waveform and the same phase, and the second control signal CLB1 supplied from the second power circuit PIC2 and the fourth control signal CLB2 supplied from the fourth power circuit PIC4 may have the same waveform and the same phase. Each of the control signal lines CSL1, CSL2, CSL3, and CSL4 may be connected to the data distribution unit 170 through the control gate line SGL.

[0222] By dividing the control signal having the same waveform and the same phase into two control signal lines and applying the control signal, the capacitance of each line can be halved. Therefore, the load of each of the power supply circuits PIC1, PIC2, ​​PIC3 and PIC4 can be reduced, and the conversion rate of the control signals CLA1, CLB1, CLA2 and CLB2 can be improved.

[0223] Specifically, when the switch included in the sub-demultiplexer DMX is an oxide thin film transistor, the thin film transistor has a relatively large channel capacitance, and therefore, when the display device has only two control signals as in the prior art, the allowable current range of the power supply circuit may be exceeded. In an embodiment, four control signal lines CSL1, CSL2, CSL3, and CSL4 are provided so that the data distribution unit 170 can be driven within the allowable current range of the power supply circuits PIC1, PIC2, ​​PIC3, and PIC4.

[0224] Fig. 9 is a layout diagram schematically illustrating an embodiment of the data distribution unit 170 . Fig.10 It is a schematic diagram Fig. 9 0 is a cross-sectional view of the display device shown in taken along line AA′.

[0225] refer to Fig. 9, the data distribution unit 170 may include a plurality of switch transistors STR. Each of the switch transistors STR may be any one of a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4.

[0226] The control signal lines CSL1, CSL2, CSL3, and CSL4 extending in the first direction (e.g., the x-axis direction) may be disposed between the data distribution unit 170 and the data output lines OL1, OL2, ..., OL6. In other words, the control signal lines CSL1, CSL2, CSL3, and CSL4 extending in the first direction (e.g., the x-axis direction) may be disposed between the data output lines OL1, OL2, ..., OL6 and the first, second, third, and fourth switches SW1, SW2, SW3, and SW4.

[0227] The first control signal line CSL1 may be connected to the first power supply circuit PIC1 (refer to Figure 8 ), the second control signal line CSL2 can be connected to the second power supply circuit PIC2 (reference Figure 8 ), the third control signal line CSL3 can be connected to the third power supply circuit PIC3 (reference Figure 8 ), and the fourth control signal line CSL4 can be connected to the fourth power supply circuit PIC4 (reference Figure 8 ).

[0228] Each of the switch transistors STR may include a first terminal connected to a corresponding data line among the data lines DL1, DL2, ..., DL12, a second terminal connected to a corresponding connection line among the connection lines CL1, CL2, ..., CL12, and a gate connected to a corresponding control signal line among the control signal lines CSL1, CSL2, CSL3, and CSL4. In an embodiment, each of the switch transistors STR may include a semiconductor layer Act, a first electrode SD1, a second electrode SD2, a first control gate line SGL1, a second control gate line SGL2, and a third electrode SD3.

[0229] The semiconductor layer Act may include an oxide-based semiconductor material. The oxide-based semiconductor material may include an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn. The oxide-based semiconductor material may be IGZO, ITZO, or IGTZO.

[0230] The first electrode SD1 and the second electrode SD2 may be respectively disposed at opposite ends of the semiconductor layer Act. The first electrode SD1 and the second electrode SD2 may extend in the second direction (e.g., the y-axis direction), and may be arranged to be substantially parallel and spaced apart in the first direction (e.g., the x-axis direction). In an embodiment, the first electrode SD1 and the second electrode SD2 may be connected to each other at one end of the switching transistor STR, and may be integrally provided as a monomer. The first electrode SD1 and the second electrode SD2 may be connected to corresponding connection lines among the connection lines CL1, CL2, ..., CL12 at one end of the switching transistor STR.

[0231] The third electrode SD3 may be disposed between the first electrode SD1 and the second electrode SD2. The third electrode SD3 may pass through the center of the semiconductor layer Act and extend in the second direction (e.g., the y-axis direction). The third electrode SD3 may be connected to a corresponding data line among the data lines DL1, DL2, ..., DL12 at the opposite end of the switching transistor STR.

[0232] The first control gate line SGL1 may be disposed between the first electrode SD1 and the third electrode SD3, and the second control gate line SGL2 may be disposed between the third electrode SD3 and the second electrode SD2. Each of the first control gate line SGL1 and the second control gate line SGL2 may be Figure 8 Each of the first control gate line SGL1 and the second control gate line SGL2 may extend in a second direction (eg, y-axis direction) and may be connected to a corresponding control signal line among the control signal lines CSL1, CSL2, CSL3, and CSL4.

[0233] Each of the data output lines OL1, OL2, ..., OL6 may be connected to a pair of connection lines. A pair of connection lines connected to one data output line may be arranged to be spaced apart from each other with two columns interposed therebetween. In an embodiment, for example, the first data output line OL1 may be connected to the first connection line CL1 and the fourth connection line CL4, the second data output line OL2 may be connected to the second connection line CL2 and the fifth connection line CL5, the third data output line OL3 may be connected to the third connection line CL3 and the sixth connection line CL6, the fourth data output line OL4 may be connected to the seventh connection line CL7 and the tenth connection line CL10, the fifth data output line OL5 may be connected to the eighth connection line CL8 and the eleventh connection line CL11, and the sixth data output line OL6 may be connected to the ninth connection line CL9 and the twelfth connection line CL12.

[0234] The connection lines CL1, CL2, ..., CL12 may correspond one to one with the data lines DL1, DL2, ..., DL12. One switch transistor STR may be provided between each of the connection lines CL1, CL2, ..., CL12 and the corresponding data line.

[0235] The first control gate line SGL1 and the second control gate line SGL2 of each of the switching transistor STR between the first connection line CL1 and the first data line DL1, the switching transistor STR between the second connection line CL2 and the second data line DL2, and the switching transistor STR between the third connection line CL3 and the third data line DL3 can be connected to the first control signal line CSL1. The first control gate line SGL1 and the second control gate line SGL2 of each of the switching transistor STR between the fourth connection line CL4 and the fourth data line DL4, the switching transistor STR between the fifth connection line CL5 and the fifth data line DL5, and the switching transistor STR between the sixth connection line CL6 and the sixth data line DL6 can be connected to the second control signal line CSL2.

[0236] The first control gate line SGL1 and the second control gate line SGL2 of each of the switching transistor STR between the seventh connection line CL7 and the seventh data line DL7, the switching transistor STR between the eighth connection line CL8 and the eighth data line DL8, and the switching transistor STR between the ninth connection line CL9 and the ninth data line DL9 can be connected to the third control signal line CSL3. The first control gate line SGL1 and the second control gate line SGL2 of each of the switching transistor STR between the tenth connection line CL10 and the tenth data line DL10, the switching transistor STR between the eleventh connection line CL11 and the eleventh data line DL11, and the switching transistor STR between the twelfth connection line CL12 and the twelfth data line DL12 can be connected to the fourth control signal line CSL4.

[0237] In other words, the first control signal line CSL1 can transmit the first control signal CLA1 to the switching transistor STR between the first connection line CL1 and the first data line DL1, the switching transistor STR between the second connection line CL2 and the second data line DL2, and the switching transistor STR between the third connection line CL3 and the third data line DL3, and the second control signal line CSL2 can transmit the second control signal CLB1 to the switching transistor STR between the fourth connection line CL4 and the fourth data line DL4, the switching transistor STR between the fifth connection line CL5 and the fifth data line DL5, and the switching transistor STR between the sixth connection line CL6 and the sixth data line DL6.

[0238] The third control signal line CSL3 can transmit the third control signal CLA2 to the switching transistor STR between the seventh connection line CL7 and the seventh data line DL7, the switching transistor STR between the eighth connection line CL8 and the eighth data line DL8, and the switching transistor STR between the ninth connection line CL9 and the ninth data line DL9, and the fourth control signal line CSL4 can transmit the fourth control signal CLB2 to the switching transistor STR between the tenth connection line CL10 and the tenth data line DL10, the switching transistor STR between the eleventh connection line CL11 and the eleventh data line DL11, and the switching transistor STR between the twelfth connection line CL12 and the twelfth data line DL12.

[0239] As described above, by dividing the control signal having the same waveform and the same phase to two different control signal lines and applying the control signals, the capacitance of each line can be halved.

[0240] refer to Fig.10 , the display device 10 may include a substrate 100 .

[0241] The switching transistor STR, the first control signal line CSL1 , and the first connection line CL1 may be disposed in the peripheral area PA. Fig.10 The switch transistor STR shown in FIG. 1 may be a switch transistor STR between the first connection line CL1 and the first data line DL1 . This may be applied to other switch transistors STR having the same or similar structure.

[0242] The barrier layer 101, the first buffer layer 111, and the second buffer layer 112 may be sequentially stacked on the substrate 100. The semiconductor layer Act of the switching transistor STR may be disposed on the second buffer layer 112.

[0243] The gate insulating layer 113 may be disposed on the second buffer layer 112 and the semiconductor layer Act. The first connection line CL1, the first control gate line SGL1, and the second control gate line SGL2 may be disposed on the gate insulating layer 113 to be spaced apart from each other. The first control gate line SGL1 and the second control gate line SGL2 may be disposed on the semiconductor layer Act, and the gate insulating layer 113 may be disposed between the semiconductor layer Act and the first control gate line SGL1 and the second control gate line SGL2. The gate insulating layer 113 may be patterned to have a shape corresponding to a conductive layer disposed on the gate insulating layer 113.

[0244] In a plan view, the semiconductor layer Act overlapping the first control gate line SGL1 and the second control gate line SGL2 may be used as a channel region. The impurity region may be arranged so that the channel region of the semiconductor layer is located therebetween. Each of the impurity regions may be a source region or a drain region. In an embodiment, each of the first connection line CL1, the first control gate line SGL1, and the second control gate line SGL2 may include Mo, Al, Cu, or Ti, etc., and may have one or more layers. The first connection line CL1, the first control gate line SGL1, and the second control gate line SGL2 may overlap with Figure 4A The first upper gate electrode G11 of the first thin film transistor TFT1 shown in FIG. 1 is disposed in the same layer.

[0245] The interlayer insulating layer 114 may be disposed on the first connection line CL1, the first control gate line SGL1, and the second control gate line SGL2. The first control signal line CSL1, the first electrode SD1, the second electrode SD2, and the third electrode SD3 may be disposed on the interlayer insulating layer 114. The first electrode SD1 and the second electrode SD2 may be disposed on the first control gate line SGL1 and the second control gate line SGL2 with the interlayer insulating layer 114 therebetween.

[0246] The first control signal line CSL1, the first electrode SD1, the second electrode SD2, and the third electrode SD3 may include a conductive material including Mo, Al, Cu, or Ti, etc., and may include or consist of one or more layers including the materials described above. In an embodiment, the first control signal line CSL1, the first electrode SD1, the second electrode SD2, and the third electrode SD3 may be connected to Figure 4A and Figure 4B The first connection electrodes 134 shown in FIG. 1 are arranged in the same layer.

[0247] The first control signal line CSL1 may be connected to the first control gate line SGL1 through a contact hole passing through the interlayer insulating layer 114. Fig.10 Although not shown in the drawings, the first control signal line CSL1 may be connected to the second control gate line SGL2 through a contact hole passing through the interlayer insulating layer 114 .

[0248] The first electrode SD1 and the second electrode SD2 may be connected to opposite ends of the semiconductor layer Act, respectively. The first electrode SD1 may be connected to the first connection line CL1 and one end of the semiconductor layer Act through a contact hole passing through the interlayer insulating layer 114. The second electrode SD2 may be connected to the first connection line CL1 and the opposite end of the semiconductor layer Act through a contact hole passing through the interlayer insulating layer 114. The first electrode SD1 and the second electrode SD2 may be integrally provided as a single body.

[0249] The third electrode SD3 may be disposed between the first electrode SD1 and the second electrode SD2. Fig. 9 As shown in , the third electrode SD3 may be connected to the first data line DL1.

[0250] The switch transistor STR can be turned on or off depending on the first control signal CLA1 transmitted from the first control signal line CSL1 to the first control gate line SGL1 and the second control gate line SGL2. When the switch transistor STR is turned on, the data signal output to the first data output line OL1 can be transmitted from the first connection line CL1 to the first data line DL1 through the switch transistor STR.

[0251] Fig.11 is a diagram schematically illustrating an embodiment of the display device 10. Although Fig.11 and Figure 8 Similar, but different in that, in the former, the display device 10 further includes bridge lines BL1, BL2, BL3 and BL4 between the control signal lines CSL1, CSL2, CSL3 and CSL4 and the power supply circuits PIC1, PIC2, ​​PIC3 and PIC4. In the following, the description of the same or similar configurations is omitted, and the differences are mainly described.

[0252] refer to Fig.11 The display device 10 may include a pixel unit 110, a data distribution unit 170, a data driving circuit DIC, and power circuits PIC1, PIC2, ​​PIC3, and PIC4. The pixel unit 110 includes a sub-pixel Ps and a data line DL, and the data distribution unit 170 includes a sub-demultiplexer DMX. The data driving circuit DIC may be included in Figure 2 In the data driving unit 150 shown in FIG. 1 , the power supply circuits PIC1, PIC2, ​​PIC3, and PIC4 may be included. Figure 2 In the control circuit 180 shown in .

[0253] The data line DL may extend from the pixel unit 110 in a second direction (e.g., a y-axis direction) and may be connected to the data distribution unit 170. The data distribution unit 170 may be connected between a data output line (not shown) and the data line DL. The data distribution unit 170 may be connected to the data driving circuit DIC through the data output line.

[0254] The data driving circuits DIC may be arranged to be spaced apart from each other in a first direction (eg, an x-axis direction) and a plurality of power supply circuits PIC1, PIC2, ​​PIC3, and PIC4 may be arranged between the data driving circuits DIC.

[0255] The power circuits PIC1, PIC2, ​​PIC3 and PIC4 may include a first power circuit PIC1 supplying a first control signal CLA1, a second power circuit PIC2 supplying a second control signal CLB1, a third power circuit PIC3 supplying a third control signal CLA2, and a fourth power circuit PIC4 supplying a fourth control signal CLB2.

[0256] Control signal lines CSL1, CSL2, CSL3, and CSL4 extending in a first direction (e.g., the x-axis direction) may be disposed between the power circuits PIC1, PIC2, ​​PIC3, and PIC4 and the data distribution unit 170. Bridge lines BL1, BL2, BL3, and BL4 extending in a first direction (e.g., the x-axis direction) may be disposed between the control signal lines CSL1, CSL2, CSL3, and CSL4 and the power circuits PIC1, PIC2, ​​PIC3, and PIC4.

[0257] Each of the bridge wires BL1, BL2, BL3, and BL4 may connect the power circuits PIC1, PIC2, ​​PIC3, and PIC4 to a corresponding control signal line among the control signal lines CSL1, CSL2, CSL3, and CSL4. In an embodiment, for example, the first bridge wire BL1 may connect the first power circuit PIC1 to the first control signal line CSL1, the second bridge wire BL2 may connect the second power circuit PIC2 to the second control signal line CSL2, the third bridge wire BL3 may connect the third power circuit PIC3 to the third control signal line CSL3, and the fourth bridge wire BL4 may connect the fourth power circuit PIC4 to the fourth control signal line CSL4.

[0258] In an embodiment, for example, the display device 10 may include a first power output line POL1, a second power output line POL2, a third power output line POL3, and a fourth power output line POL4 extending in a second direction (e.g., a y-axis direction). The first power output line POL1 may connect the first bridge line BL1 to the first power circuit PIC1, the second power output line POL2 may connect the second bridge line BL2 to the second power circuit PIC2, ​​the third power output line POL3 may connect the third bridge line BL3 to the third power circuit PIC3, and the fourth power output line POL4 may connect the fourth bridge line BL4 to the fourth power circuit PIC4.

[0259] The display device 10 may include a first bridge connection line BCL1, a second bridge connection line BCL2, a third bridge connection line BCL3, and a fourth bridge connection line BCL4 extending in a second direction (e.g., a y-axis direction). Each of the bridge lines BL1, BL2, BL3, and BL4 may be connected to a corresponding control signal line through a corresponding bridge connection line among the first to fourth bridge connection lines BCL1, BCL2, BCL3, and BCL4. The first bridge connection line BCL1 may connect the first bridge connection line BL1 to the first control signal line CSL1, the second bridge connection line BCL2 may connect the second bridge connection line BL2 to the second control signal line CSL2, the third bridge connection line BCL3 may connect the third bridge connection line BL3 to the third control signal line CSL3, and the fourth bridge connection line BCL4 may connect the fourth bridge connection line BL4 to the fourth control signal line CSL4.

[0260] The number of the first bridge connection lines BCL1 may be greater than the number of the first power output lines POL1, the number of the second bridge connection lines BCL2 may be greater than the number of the second power output lines POL2, the number of the third bridge connection lines BCL3 may be greater than the number of the third power output lines POL3, and the number of the fourth bridge connection lines BCL4 may be greater than the number of the fourth power output lines POL4.

[0261] Each of the control signal lines CSL1 , CSL2 , CSL3 , and CSL4 may be connected to the data distribution unit 170 through a control gate line SGL.

[0262] The first control signal CLA1 supplied from the first power circuit PIC1 and the third control signal CLA2 supplied from the third power circuit PIC3 may have the same waveform and the same phase, and the second control signal CLB1 supplied from the second power circuit PIC2 and the fourth control signal CLB2 supplied from the fourth power circuit PIC4 may have the same waveform and the same phase.

[0263] In a comparative example, when the power supply circuit is directly connected to the control signal line, the control signal in the area adjacent to the input point to which the power output line is connected (hereinafter referred to as the "edge area") has a relatively high conversion rate, while the control signal in the area away from the input point to which the power output line is connected (hereinafter referred to as the "center area") may have a relatively low conversion rate.

[0264] like Fig.11As shown in, when the control signal lines CSL1, CSL2, CSL3 and CSL4 are connected to the power circuits PIC1, PIC2, ​​PIC3 and PIC4 through the bridge lines BL1, BL2, BL3 and BL4, the capacitance of the bridge lines BL1, BL2, BL3 and BL4 is relatively low, and therefore, the conversion rate of the control signal in the central area can be improved. In addition, since the number of bridge connection lines BCL is greater than the number of power output lines POL, the input points of each of the control signals increase, thereby reducing the conversion deviation between the control signal in the central area and the control signal in the edge area.

[0265] Fig.12 is a layout diagram schematically illustrating an embodiment of the data distribution unit 170. Fig.12 and Fig. 9 Similar, but different in that, in the former, the display device 10 further includes bridge lines BL1, BL2, BL3 and BL4 between the control signal lines CSL1, CSL2, CSL3 and CSL4 and the data output lines OL1, OL2, ..., OL12. In the following, the description of the same or similar configurations is omitted, and the differences are mainly described.

[0266] refer to Fig.12 , the data distribution unit 170 may include a plurality of switch transistors STR. Each of the switch transistors STR may be any one of a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4.

[0267] Control signal lines CSL1, CSL2, CSL3, and CSL4 extending in a first direction (e.g., the x-axis direction) may be disposed between the data distribution unit 170 and the data output lines OL1, OL2, ..., OL12. Bridge lines BL1, BL2, BL3, and BL4 extending in a first direction (e.g., the x-axis direction) may be disposed between the control signal lines CSL1, CSL2, CSL3, and CSL4 and the data output lines OL1, OL2, ..., OL12.

[0268] The first bridge line BL1 may be connected to the first power supply circuit PIC1 (refer to Fig.11 ), the second bridge line BL2 can be connected to the second power supply circuit PIC2 (reference Fig.11 ), the third bridge line BL3 can be connected to the third power supply circuit PIC3 (reference Fig.11 ), and the fourth bridge line BL4 can be connected to the fourth power supply circuit PIC4 (reference Fig.11). Since the bridge lines BL1, BL2, BL3, and BL4 are spaced apart from the switch transistor STR, a load smaller than that of the control signal lines CSL1, CSL2, CSL3, and CSL4 may be applied to the bridge lines BL1, BL2, BL3, and BL4.

[0269] The first bridge line BL1 can be connected to the first control signal line CSL1 through the first bridge connection line BCL1, the second bridge line BL2 can be connected to the second control signal line CSL2 through the second bridge connection line BCL2, the third bridge line BL3 can be connected to the third control signal line CSL3 through the third bridge connection line BCL3, and the fourth bridge line BL4 can be connected to the fourth control signal line CSL4 through the fourth bridge connection line BCL4.

[0270] exist Fig.12 In the embodiment, the first bridge connection line BCL1, the second bridge connection line BCL2, the third bridge connection line BCL3 and the fourth bridge connection line BCL4 each include two bridge connection lines. However, the present disclosure is not limited thereto. The number and arrangement of the first bridge connection line BCL1, the second bridge connection line BCL2, the third bridge connection line BCL3 and the fourth bridge connection line BCL4 can be designed in various ways.

[0271] Since the first bridge connection line BCL1, the second bridge connection line BCL2, the third bridge connection line BCL3 and the fourth bridge connection line BCL4 are each provided in plurality, the input points of the control signals in the control signal lines CSL1, CSL2, CSL3 and CSL4 are increased, thereby improving the conversion deviation between the control signals in the central area and the control signals in the edge area in each of the control signal lines CSL1, CSL2, CSL3 and CSL4.

[0272] Each of the data output lines OL1, OL2, ..., OL12 may be connected to a pair of connection lines. A pair of connection lines connected to one data output line may be arranged to be spaced apart from each other with two columns interposed therebetween. The connection lines may correspond one to one with the data lines DL1, DL2, ..., DL24. A switching transistor STR may be provided between each of the connection lines and the corresponding data line.

[0273] Each of the switching transistors STR may include a third electrode connected to the data lines DL1, DL2, . . . , DL24, first and second electrodes connected to the connection line, and first and second control gate lines connected to the control signal lines CSL1, CSL2, CSL3, and CSL4.

[0274] The first bridge line BL1 can transmit the first control signal CLA1 to the first control signal line CSL1 through the first bridge connection line BCL1, the second bridge line BL2 can transmit the second control signal CLB1 to the second control signal line CSL2 through the second bridge connection line BCL2, the third bridge line BL3 can transmit the third control signal CLA2 to the third control signal line CSL3 through the third bridge connection line BCL3, and the fourth bridge line BL4 can transmit the fourth control signal CLB2 to the fourth control signal line CSL4 through the fourth bridge connection line BCL4.

[0275] The switching transistor STR connected to the first control signal line CSL1 can connect the data lines DL1, DL2, DL3, DL13, DL14 and DL15 to the corresponding data output lines OL1, OL2, OL3, OL7, OL8 and OL9 in response to the first control signal CLA1. The switching transistor STR connected to the second control signal line CSL2 can connect the data lines DL4, DL5, DL6, DL16, DL17 and DL18 to the data output lines OL1, OL2, OL3, OL7, OL8 and OL9 in response to the second control signal CLB1. The switching transistor STR connected to the third control signal line CSL3 can connect the data lines DL7, DL8, DL9, DL19, DL20 and DL21 to the data output lines OL4, OL5, OL6, OL10, OL11 and OL12 in response to the third control signal CLA2. The switching transistor STR connected to the fourth control signal line CSL4 may connect the data lines DL10 , DL11 , DL12 , DL22 , DL23 , and DL24 to the data output lines OL4 , OL5 , OL6 , OL10 , OL11 , and OL12 in response to the fourth control signal CLB2 .

[0276] Fig.13A and Fig. 13B is a graph showing a control signal of a display device according to a comparative example and a control signal of a display device according to an embodiment.

[0277] exist Fig.13A In FIG. 1 , the first signal ES1 is a control signal measured in an edge region of a control signal line of a display device according to a comparative example, and the second signal ES2 is a control signal measured in an edge region of a first control signal line of a display device according to an embodiment. Fig. 13B , the third signal CS1 is a control signal measured in a central area of ​​a control signal line of the display device according to the comparative example, and the fourth signal CS2 is a control signal measured in a central area of ​​a first control signal line of the display device according to the embodiment.

[0278] The display device according to the comparative example includes only two control signal lines, and the data distribution unit may include only the first switch and the second switch connected to the first control signal line and the second control signal line, respectively.

[0279] like Fig.11 As shown in, the display device in the embodiment includes four control signal lines CSL1, CSL2, CSL3 and CSL4 and four bridge lines BL1, BL2, BL3 and BL4, and the data distribution unit 170 includes a first switch connected to the first control signal line CSL1, a second switch connected to the second control signal line CSL2, a third switch connected to the third control signal line CSL3, and a fourth switch connected to the fourth control signal line CSL4.

[0280] refer to Fig.13A and Fig. 13B , the rising time tr1 of the first signal ES1 is longer than the rising time tr2 of the second signal ES2, and the falling time tf1 of the first signal ES1 is longer than the falling time tf2 of the second signal ES2. Similarly, the rising time tr3 of the third signal CS1 is longer than the rising time tr4 of the fourth signal CS2, and the falling time tf3 of the third signal CS1 is longer than the falling time tf4 of the fourth signal CS2.

[0281] In addition, compared with the difference between the rise time tr1 of the first signal ES1 and the rise time tr3 of the third signal CS1, the difference between the rise time tr2 of the second signal ES2 and the rise time tr4 of the fourth signal CS2 is reduced, and compared with the difference between the fall time tf1 of the first signal ES1 and the fall time tf3 of the third signal CS1, the difference between the fall time tf2 of the second signal ES2 and the fall time tf4 of the fourth signal CS2 is reduced.

[0282] In other words, it has been confirmed that in the display device of the embodiment, the conversion rate of the control signal is improved, and the conversion deviation between the control signal in the edge region of the control signal line and the control signal in the center region of the control signal line is reduced.

[0283] Fig.14 is a diagram for describing an embodiment of a sub-demultiplexer DMX. Fig.14 and Figure 5 Similar, but different in that the sub-demux DMX includes only one switch.

[0284] refer to Fig.14 , the sub-demultiplexer DMX may selectively connect the kth data output line OLk to a pair of the ith data line DLi and the i+3th data line DLi+3. The sub-demultiplexer DMX may include only the first switch SW1.

[0285] The i-th data line DLi and the i+3-th data line DLi+3 may be data lines arranged to be spaced apart from each other with two columns interposed therebetween. In an embodiment, for example, the i+1-th data line and the i+2-th data line may be arranged between the i-th data line DLi and the i+3-th data line DLi+3. The i-th data line DLi may be connected to a sub-pixel in the i-th column (e.g., labeled by M1), and the i+3-th data line DLi+3 may be connected to a sub-pixel in the i+3-th column (e.g., labeled by M4).

[0286] The first switch SW1 may be provided between the kth data output line OLk and the ith data line DLi. The first switch SW1 may connect the kth data output line OLk to the ith data line DLi through the first control signal CLA and may apply the data signal DATA applied via the kth data output line OLk to the ith data line DLi.

[0287] The sub-demultiplexer DMX may connect the kth data output line OLk to the i+3th data line DLi+3. In other words, no switch is provided between the kth data output line OLk and the i+3th data line DLi+3, and the data signal DATA applied to the kth data output line OLk may be applied to the i+3th data line DLi+3 regardless of the control signal CCS.

[0288] In an embodiment, sub-pixels connected to the i-th data line DLi and the i+3-th data line DLi+3 may emit light of the same color. In this regard, Fig.14 It is shown that the sub-pixels connected to the i-th data line DLi and the i+3-th data line DLi+3 are red sub-pixels PR that emit red light. However, the present disclosure is not limited thereto. The connection between the data lines and the sub-pixels may be modified in various ways.

[0289] Fig.15 is a diagram schematically illustrating an embodiment of a display device. Fig.16 Is used to describe Fig.15 0 is a timing diagram of the operation of the display device shown in .

[0290] refer to Fig.15 , the data distribution unit 170 may include a first demultiplexer DMX1 and a second demultiplexer DMX2, and the pixel unit 110 may include a plurality of pixels PX. The pixel PX may include a red sub-pixel PR, a green sub-pixel PG, and a blue sub-pixel PB.

[0291] In the pixel unit 110, the columns in which the red sub-pixels PR are arranged in the second direction (e.g., the y-axis direction), the columns in which the green sub-pixels PG are arranged in the second direction (e.g., the y-axis direction), and the columns in which the blue sub-pixels PB are arranged in the second direction (e.g., the y-axis direction) may be alternately repeated in the first direction (e.g., the x-axis direction).

[0292] In an embodiment, in a first row, a first pixel, a second pixel, a third pixel, and a fourth pixel may be arranged sequentially in a first direction (e.g., an x-axis direction), for example, the first pixel may include three sub-pixels PR11, PG11, and PB11 in the first to third columns, the second pixel may include three sub-pixels PR12, PG12, and PB12 in the fourth to sixth columns, the third pixel may include three sub-pixels PR13, PG13, and PB13 in the seventh to ninth columns, and the fourth pixel may include three sub-pixels PR14, PG14, and PB14 in the tenth to twelfth columns.

[0293] A plurality of data lines DL1, DL2, . . . , DL12 and a plurality of gate lines GLn-3, GLn-2, ​​GLn-1, and GLn may be arranged in the pixel unit 110. The plurality of gate lines GLn-3, GLn-2, ​​GLn-1, and GLn may be Figure 2 The gate lines (eg, GL1, GL2, ..., GLn) shown in Figure 3A and Figure 3B The first gate line GWL is shown in FIG.

[0294] A gate line may be connected to sub-pixels arranged in the same row (line). A data line may be connected to sub-pixels arranged in the same column. A sub-pixel connected to the i-th data line DLi and a sub-pixel connected to the i+3-th data line DLi+3 may be sub-pixels emitting light of the same color. For ease of description, Fig.15 Only twelve data lines DL1, DL2, ..., DL12, four gate lines GLn-3, GLn-2, ​​GLn-1 and GLn, and six data output lines OL1, OL2, ..., OL6 are shown. However, the number of data lines, the number of gate lines, and the number of data output lines may be greater.

[0295] The first demultiplexer DMX1 may selectively connect the data output lines OL1, OL2, and OL3 belonging to the first group GR1 to the first to sixth data lines DL1, DL2, ..., and DL6, and the second demultiplexer DMX2 may selectively connect the data output lines OL4, OL5, and OL6 belonging to the second group GR2 to the seventh to twelfth data lines DL7, DL8, ..., and DL12.

[0296] Each of the first demultiplexer DMX1 and the second demultiplexer DMX2 may include a plurality of sub-demultiplexers DMX (refer to Fig.14 ). One sub-demultiplexer DMX may selectively connect one data output line to a pair of data lines. The pair of data lines connected to one sub-demultiplexer DMX may be spaced apart from each other with two columns interposed therebetween.

[0297] In an embodiment, for example, a pair of data lines connected to the first data output line OL1 belonging to the first group GR1 may be a first data line DL1 and a fourth data line DL4. The first data line DL1 may be connected to a red sub-pixel PR11 of a first pixel, and the fourth data line DL4 may be connected to a red sub-pixel PR12 of a second pixel.

[0298] A pair of data lines connected to the fourth data output line OL4 belonging to the second group GR2 may be seventh and tenth data lines DL7 and DL10. The seventh data line DL7 may be connected to the red subpixel PR13 of the third pixel, and the tenth data line DL10 may be connected to the red subpixel PR14 of the fourth pixel.

[0299] The first demultiplexer DMX1 may include first switches SW1. Each of the first switches SW1 may be provided between the first data output line OL1 and the first data line DL1, between the second data output line OL2 and the second data line DL2, and between the third data output line OL3 and the third data line DL3. The first switch SW1 may be turned on by a first control signal CLA1, and may connect the first data output line OL1 to the first data line DL1, the second data output line OL2 to the second data line DL2, and the third data output line OL3 to the third data line DL3.

[0300] The first demultiplexer DMX1 may connect the first data output line OL1 to the fourth data line DL4 , the second data output line OL2 to the fifth data line DL5 , and the third data output line OL3 to the sixth data line DL6 regardless of the first and third control signals CLA1 and CLA2 .

[0301] The first data signal DATA applied to the first data output line OL1 <1> The first sub-data signal R applied to the red sub-pixel PR and the second data signal DATA applied to the second data output line OL2 may be included. <2> The second sub-data signal G applied to the green sub-pixel PG and the third data signal DATA applied to the third data output line OL3 may be included. <3> A third sub-data signal B applied to the blue sub-pixel PB may be included.

[0302] The second demultiplexer DMX2 may include third switches SW3. Each of the third switches SW3 may be provided between the fourth data output line OL4 and the seventh data line DL7, between the fifth data output line OL5 and the eighth data line DL8, and between the sixth data output line OL6 and the ninth data line DL9. The third switch SW3 may be turned on by the third control signal CLA2, and may connect the fourth data output line OL4 to the seventh data line DL7, the fifth data output line OL5 to the eighth data line DL8, and the sixth data output line OL6 to the ninth data line DL9.

[0303] The second demultiplexer DMX2 may connect the fourth data output line OL4 to the tenth data line DL10 , the fifth data output line OL5 to the eleventh data line DL11 , and the sixth data output line OL6 to the twelfth data line DL12 regardless of the first and third control signals CLA1 and CLA2 .

[0304] The fourth data signal DATA applied to the fourth data output line OL4 <4> The first sub-data signal R applied to the red sub-pixel PR, the fifth data signal DATA applied to the fifth data output line OL5, <5> The second sub-data signal G applied to the green sub-pixel PG and the sixth data signal DATA applied to the sixth data output line OL6 may be included. <6> A third sub-data signal B applied to the blue sub-pixel PB may be included.

[0305] Fig.16 The data driving unit 150 (refer to Figure 2 ) The order of data signals applied to sub-pixels through data output lines. Hereinafter, when supplying or outputting any signal is described, this may mean the on-voltage of the supply signal.

[0306] Reference together Fig.15 and Fig.16 The first control signal CLA1 and the third control signal CLA2 can be obtained from the control circuit 180 (reference Figure 2 ) through the power output line POL (reference Figure 2 ) is supplied to the first demultiplexer DMX1 and the second demultiplexer DMX2.

[0307] Each of the first control signal CLA1 and the third control signal CLA2 may be a square wave signal in which a turn-on voltage that may turn on the first switch SW1 and the second switch SW2 and a turn-off voltage that may turn off the first switch SW1 and the second switch SW2 are repeated. In an embodiment, the turn-on voltage of the first control signal CLA1 and the third control signal CLA2 may be a high level voltage (first level voltage), and the turn-off voltage of the first control signal CLA1 and the third control signal CLA2 may be a low level voltage (second level voltage).

[0308] The first control signal CLA1 and the third control signal CLA2 may have the same phase. In an embodiment, for example, the on-voltage period of the first control signal CLA1 may overlap with the on-voltage period of the third control signal CLA2, and the off-voltage period of the first control signal CLA1 may overlap with the off-voltage period of the third control signal CLA2. In other words, the first switch SW1 and the third switch SW3 may be turned on or off at the same time according to the first control signal CLA1 and the third control signal CLA2.

[0309] During one frame, gate signals Gn-3, Gn-2, Gn-1, and Gn-2 can be obtained from the gate driving unit 130 (refer to Figure 2 ) is sequentially supplied through gate lines GLn-3, GLn-2, ​​GLn-1 and GLn. Gate signals Gn-3, Gn-2, Gn-1 and Gn may be gate control signals for controlling the conduction and cut-off of a data write transistor (e.g., a second transistor). Gate signals Gn-3, Gn-2, Gn-1 and Gn may be supplied with a turn-on voltage for turning on the data write transistor and a cut-off voltage for cutting off the data write transistor. In an embodiment, the turn-on voltage of gate signals Gn-3, Gn-2, Gn-1 and Gn may be a high level voltage (a first level voltage), and the cut-off voltage of gate signals Gn-3, Gn-2, Gn-1 and Gn may be a low level voltage (a second level voltage).

[0310] The on-voltage period of the gate signals Gn-3, Gn-2, Gn-1, and Gn-2 may also be referred to as a line period LT. The line period LT may be a period of time during which the display device 10 (refer to FIG. 1 ) Figure 1 ) for a row (a line) of sub-pixels Ps (reference Figure 2)The time required for writing the data signal DATA. In an embodiment, the line time period LT may be about 2H. The line time period LT may include a first sub-line time period LT1 and a second sub-line time period LT2 following the first sub-line time period LT1. Each of the first sub-line time period LT1 and the second sub-line time period LT2 may be about 1H. For each of the sub-line time periods LT1 and LT2, the turn-on voltage of the first control signal CLA1 may be supplied to the first demultiplexer DMX1, and the turn-on voltage of the third control signal CLA2 may be supplied to the second demultiplexer DMX2.

[0311] During a first sub-line period LT1 of a line period (hereinafter also referred to as a "current line period") of a row to which a gate signal is applied, a first control signal CLA1 and a third control signal CLA2 may be supplied. Similarly, during a second sub-line period LT2, a first control signal CLA1 and a third control signal CLA2 may be supplied. During the second sub-line period LT2, a data signal DATA corresponding to a sub-pixel Ps of a row to which a gate signal is supplied may be written.

[0312] The data driving unit 150 (reference Figure 2 ) can be synchronized with the control signals CLA1 and CLA2, and can supply the data signal DATA to each data output line.

[0313] In an embodiment, for example, when the n-3rd gate signal Gn-3 is supplied to the n-3rd gate line GLn-3 during the line period LT, the sub-pixels PR11, PG11, PB11, PR12, ..., PB14 connected to the n-3rd gate line GLn-3 may be selected, and the data driving unit 150 may drive the data signal DATA <1> ,DATA <2> ,…,DATA <6> Output to data output lines OL1, OL2, ..., OL6.

[0314] Similarly, for each of the subline periods LT1 and LT2, the first control signal CLA1 and the third control signal CLA2 may be supplied. The sub-data signal supplied during the first subline period LT1 may be a sub-data signal of a previous line period corresponding to a row (previous line) to which a previous gate signal is supplied.

[0315] During the second sub-line period LT2, the first control signal CLA1 may be supplied to the first switch SW1 of the first demultiplexer DMX1, and the third control signal CLA2 may be supplied to the third switch SW3 of the second demultiplexer DMX2. Accordingly, the corresponding sub-data signals R11, G11, B11, R13, G13, and B13 of the current line period may be supplied to the sub-pixels PR11, PG11, PB11, PR12, ..., PB14 connected to the n-3th gate line GLn-3, the sub-pixels PR11, PG11, and PB11 connected to the data lines DL1, DL2, and DL3 to which the first switch SW1 is connected, and the sub-pixels PR13, PG13, and PB13 connected to the data lines DL7, DL8, and DL9 to which the third switch SW3 is connected.

[0316] In this case, the sub-data signals R11, G11, B11, R13, G13 and B13 of the current line can also be supplied to the sub-pixels PR12, PG12, PB12, PR14, PG14 and PB14 connected to the data lines DL4, DL5, DL6, DL10, DL11 and DL12 connected to the data output lines OL1, OL2, ..., OL6 without passing through the switch.

[0317] Thereafter, the first control signal CLA1 is supplied with a cut-off voltage so that the first switch SW1 of the first demultiplexer DMX1 can be turned off, and the third control signal CLA2 is supplied with a cut-off voltage so that the third switch SW3 of the second demultiplexer DMX2 can be turned off. In this case, without passing through the switch, the corresponding sub-data signals R12, G12, B12, R14, G14 and B14 can also be supplied to the sub-pixels PR12, PG12, PB12, PR14, PG14 and PB14 connected to the data lines DL4, DL5, DL6, DL10, DL11 and DL12 connected to the data output lines OL1, OL2, ..., OL6. The sub-pixels PR12, PG12, PB12, PR14, PG14 and PB14 connected to the data lines DL4, DL5, DL6, DL10, DL11 and DL12 can be newly written with the corresponding sub-data signals R12, G12, B12, R14, G14 and B14.

[0318] The sub-data signal of the previous line period written to the sub-pixel Ps during the first sub-line period LT1 may be overwritten by the sub-data signal of the current line period written to the sub-pixel Ps during the second sub-line period LT2 .

[0319] Similarly, when the n-2 th gate signal Gn-2 is supplied to the n-2 th gate line GLn-2 during the line period LT, the sub-pixels PR21, PG21, PB21, PR22, ..., PB24 connected to the n-2 th gate line GLn-2 may be selected, and the data driving unit 150 may drive the data signal DATA <1> ,DATA <2> ,…,DATA <6> Output to data output lines OL1, OL2, ..., OL6.

[0320] The first sub-line period LT1 of the n-2 th gate signal Gn-2 may overlap with the second sub-line period LT2 of the n-3 th gate signal Gn-3. During the first sub-line period LT1 of the n-2 th gate signal Gn-2, the first control signal CLA1 may be supplied to the first switch SW1 of the first demultiplexer DMX1 with a turn-on voltage, and the third control signal CLA2 may be supplied to the third switch SW3 of the second demultiplexer DMX2 with a turn-on voltage. Accordingly, the sub-data signals R11, G11, B11, R13, G13 and B13 of the previous line time period can be supplied to the sub-pixels PR21, PG21, PB21, PR22, ..., PB24 connected to the n-2th gate line GLn-2, ​​the sub-pixels PR21, PG21 and PB21 connected to the data lines DL1, DL2 and DL3 to which the first switch SW1 is connected, and the sub-pixels PR23, PG23 and PB23 connected to the data lines DL7, DL8 and DL9 to which the third switch SW3 is connected.

[0321] In this case, the sub-data signals R11, G11, B11, R13, G13 and B13 of the previous line time period can also be supplied to the sub-pixels PR22, PG22, PB22, PR24, PG24 and PB24 connected to the data lines DL4, DL5, DL6, DL10, DL11 and DL12 connected to the data output lines OL1, OL2, OL3, OL4, OL5 and OL6 without passing through the switch.

[0322] Thereafter, the first control signal CLA1 is supplied with a cut-off voltage so that the first switch SW1 of the first demultiplexer DMX1 can be turned off, and the third control signal CLA2 is supplied with a cut-off voltage so that the third switch SW3 of the second demultiplexer DMX2 can be turned off. In this case, without passing through the switch, the sub-data signals R12, G12, B12, R14, G14 and B14 of the previous line period can be supplied to the sub-pixels PR22, PG22, PB22, PR24, PG24 and PB24 connected to the data lines DL4, DL5, DL6, DL10, DL11 and DL12 connected to the data output lines OL1, OL2, OL3, OL4, OL5 and OL6.

[0323] During the second sub-line period LT2 of the n-2 th gate signal Gn-2, the first control signal CLA1 may be supplied to the first switch SW1 of the first demultiplexer DMX1, and the third control signal CLA2 may be supplied to the third switch SW3 of the second demultiplexer DMX2. Accordingly, the sub-data signals R21, G21, B21, R23, G23, and B23 of the current line period may be supplied to the sub-pixels PR21, PG21, PB21, PR22, ..., PB24 connected to the n-2 th gate line GLn-2, ​​the sub-pixels PR21, PG21, and PB21 connected to the data lines DL1, DL2, and DL3 to which the first switch SW1 is connected, and the sub-pixels PR23, PG23, and PB23 connected to the data lines DL7, DL8, and DL9 to which the third switch SW3 is connected.

[0324] In this case, without passing through a switch, the sub-data signals R21, G21, B21, R23, G23 and B23 of the current line time period can also be supplied to the sub-pixels PR22, PG22, PB22, PR24, PG24 and PB24 connected to the data lines DL4, DL5, DL6, DL10, DL11 and DL12 connected to the data output lines OL1, OL2, ..., OL6.

[0325] Thereafter, the first control signal CLA1 is supplied with a cut-off voltage so that the first switch SW1 of the first demultiplexer DMX1 can be turned off, and the third control signal CLA2 is supplied with a cut-off voltage so that the third switch SW3 of the second demultiplexer DMX2 can be turned off. In this case, without passing through the switch, the corresponding sub-data signals R22, G22, B22, R24, G24 and B24 of the current line period can also be supplied to the sub-pixels PR22, PG22, PB22, PR24, PG24 and PB24 connected to the data lines DL4, DL5, DL6, DL10, DL11 and DL12 connected to the data output lines OL1, OL2, ..., OL6. Sub-pixels PR22, PG22, PB22, PR24, PG24 and PB24 connected to data lines DL4, DL5, DL6, DL10, DL11 and DL12 can newly write corresponding sub-data signals R22, G22, B22, R24, G24 and B24 of the current line time period.

[0326] In this manner, the data driving unit 150 may write data to all pixels PX during a single line period LT.

[0327] When the control signal CCS is applied, the second nodes N2 (reference Figure 3A) may be passed through the reference voltage line VL1 (reference Figure 3A ) is changed. This may cause line crosstalk, which may produce linear spots in the image of the display device. In the illustrated embodiment, some data lines are connected to the data output line without passing through the switch, and therefore, some of the control signals (for example, the second control signal and the fourth control signal) can be omitted. Accordingly, the line crosstalk can be reduced, and thus, the display device 10 (refer to FIG. 1 ) on which a high-quality image is displayed can be realized. Figure 1 ). In addition, since some control signals are omitted, the power consumption of the display device 10 can be reduced.

[0328] Fig.17 is a diagram schematically illustrating an embodiment of the display device 10 .

[0329] refer to Fig.17 , the display device 10 may include a pixel unit 110, a data distribution unit 170, a data driving circuit DIC, and power supply circuits PIC1 and PIC3. The data driving circuit DIC may be included in Figure 2 In the data driving unit 150 shown in FIG. 1 , the power supply circuits PIC1 and PIC3 may be included in Figure 2 In the control circuit 180 shown in .

[0330] The pixel unit 110 may include a data line DL and a plurality of sub-pixels Ps. Each of the plurality of sub-pixels Ps may be connected to a corresponding data line among the plurality of data lines DL. The data line DL may extend from the pixel unit 110 in a second direction (e.g., y-axis direction) and may be connected to the data distribution unit 170.

[0331] The data distribution unit 170 may be connected between a plurality of data output lines and a plurality of data lines DL. For ease of description, Fig.17 The data output line is omitted. The data distribution unit 170 may include a plurality of sub-demultiplexers DMX each including a switch. Fig.14 As described, the sub-demultiplexer DMX can selectively connect one data output line to a pair of data lines according to the first control signal CLA1 or the third control signal CLA2.

[0332] The data distribution unit 170 may be connected to the data driving circuit DIC through a plurality of data output lines. The data driving circuit DIC may be arranged spaced apart from each other in a first direction (eg, x-axis direction). A plurality of power supply circuits PIC1 and PIC3 may be arranged on opposite sides of the data driving circuit DIC.

[0333] The power circuits PIC1 and PIC3 may include a first power circuit PIC1 supplying a first control signal CLA1 and a third power circuit PIC3 supplying a third control signal CLA2. In an embodiment, the power circuits PIC1 and PIC3 may be power management ICs.

[0334] Control signal lines CSL1 and CSL3 extending in a first direction (e.g., x-axis direction) may be arranged between the power circuits PIC1 and PIC3 and the data distribution unit 170. The first control signal line CSL1 may be connected to the first power circuit PIC1 through the first power output line POL1, and the third control signal line CSL3 may be connected to the third power circuit PIC3 through the third power output line POL3.

[0335] The first control signal CLA1 supplied from the first power circuit PIC1 and the third control signal CLA2 supplied from the third power circuit PIC3 may have the same waveform and the same phase. Each of the control signal lines CSL1 and CSL3 may be connected to the data distribution unit 170 through a control gate line SGL.

[0336] By dividing the control signals CLA1 and CLA2 having the same waveform and the same phase into two control signal lines CSL1 and CSL3 and applying the control signals, the capacitance of each line can be halved. Therefore, the load of each of the power circuits PIC1 and PIC3 is reduced, the conversion rate of the control signals CLA1 and CLA2 can be improved, and the data distribution unit 170 can be driven within the allowable current range of the power circuits PIC1 and PIC3.

[0337] Fig.18 is a layout diagram schematically illustrating an embodiment of the data distribution unit 170 .

[0338] refer to Fig.18 , the data distribution unit 170 may include a plurality of switch transistors STR. Each of the switch transistors STR may be Fig.15 The first switch SW1 or the third switch SW3 shown in FIG.

[0339] The first control signal line CSL1 and the third control signal line CSL3 extending in the first direction (e.g., the x-axis direction) may be arranged between the data distribution unit 170 and the data output lines OL1, OL2, ..., OL6. In other words, in a plan view, the first control signal line CSL1 and the third control signal line CSL3 extending in the first direction (e.g., the x-axis direction) may be arranged between the data output lines OL1, OL2, ..., OL6 and the first switch SW1 and between the data output lines OL1, OL2, ..., OL6 and the third switch SW3.

[0340] The first control signal line CSL1 may be connected to the first power supply circuit PIC1 (refer to Fig.17 ), and the third control signal line CSL3 can be connected to the third power supply circuit PIC3 (reference Fig.17 The first control signal line CSL1 can transmit the first control signal CLA1 (reference Fig.17 ) is transmitted to the switch transistor STR connected thereto, and the third control signal line CSL3 can transmit the third control signal CLA2 (reference Fig.17 ) is transmitted to the switching transistor STR connected to it.

[0341] The switching transistor STR can be arranged between the first data output line OL1 and the first data line DL1, between the second data output line OL2 and the second data line DL2, between the third data output line OL3 and the third data line DL3, between the fourth data output line OL4 and the seventh data line DL7, between the fifth data output line OL5 and the eighth data line DL8, and between the sixth data output line OL6 and the ninth data line DL9.

[0342] Each of the switch transistors STR may include a first terminal connected to a corresponding data line among the data lines DL1, DL2, DL3, DL7, DL8, and DL9, a second terminal connected to a corresponding connection line among the connection lines CL1, CL2, CL3, CL7, CL8, and CL9, and a gate connected to a corresponding control signal line among the control signal lines CSL1 and CSL3. In an embodiment, each of the switch transistors STR may include a semiconductor layer Act, a first electrode SD1, a second electrode SD2, a first control gate line SGL1, a second control gate line SGL2, and a third electrode SD3.

[0343] The semiconductor layer Act may include an oxide-based semiconductor material. The oxide-based semiconductor material may include an oxide of at least one of In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, Al, Cs, Ce, and Zn. The oxide-based semiconductor material may be IGZO, ITZO, or IGTZO.

[0344] The first electrode SD1 and the second electrode SD2 may be respectively disposed at opposite ends of the semiconductor layer Act. The first electrode SD1 and the second electrode SD2 may extend in the second direction (e.g., the y-axis direction), and may be arranged to be substantially parallel and spaced apart in the first direction (e.g., the x-axis direction). In an embodiment, the first electrode SD1 and the second electrode SD2 may be connected to each other at one end of the switching transistor STR, and may be integrally provided as a single body. The first electrode SD1 and the second electrode SD2 may be connected to corresponding connection lines among the connection lines CL1, CL2, CL3, CL7, CL8, and CL9 at one end of the switching transistor STR.

[0345] The third electrode SD3 may be disposed between the first electrode SD1 and the second electrode SD2. The third electrode SD3 may pass through the center of the semiconductor layer Act and extend in the second direction (e.g., the y-axis direction). The third electrode SD3 may be connected to a corresponding data line among the data lines DL1, DL2, DL3, DL7, DL8, and DL9 at the opposite end of the switching transistor STR.

[0346] The first control gate line SGL1 may be disposed between the first electrode SD1 and the third electrode SD3, and the second control gate line SGL2 may be disposed between the third electrode SD3 and the second electrode SD2. Each of the first control gate line SGL1 and the second control gate line SGL2 may be Figure 8 Each of the first control gate line SGL1 and the second control gate line SGL2 may extend in a second direction (eg, a y-axis direction) and may be connected to a corresponding control signal line among the control signal lines CSL1 and CSL3.

[0347] Each of the data output lines OL1, OL2, ..., OL6 may be connected to a pair of connection lines. A pair of connection lines connected to one data output line may be spaced apart from each other with two columns interposed therebetween. In an embodiment, for example, the first data output line OL1 may be connected to the first connection line CL1 and the fourth connection line CL4, the second data output line OL2 may be connected to the second connection line CL2 and the fifth connection line CL5, the third data output line OL3 may be connected to the third connection line CL3 and the sixth connection line CL6, the fourth data output line OL4 may be connected to the seventh connection line CL7 and the tenth connection line CL10, the fifth data output line OL5 may be connected to the eighth connection line CL8 and the eleventh connection line CL11, and the sixth data output line OL6 may be connected to the ninth connection line CL9 and the twelfth connection line CL12. The connection lines CL1, CL2, ..., CL12 may correspond one to one with the data lines DL1, DL2, ..., DL12.

[0348] The first control gate line SGL1 and the second control gate line SGL2 of each of the switching transistor STR between the first connection line CL1 and the first data line DL1, the switching transistor STR between the second connection line CL2 and the second data line DL2, and the switching transistor STR between the third connection line CL3 and the third data line DL3 can be connected to the first control signal line CSL1. The first control gate line SGL1 and the second control gate line SGL2 of each of the switching transistor STR between the seventh connection line CL7 and the seventh data line DL7, the switching transistor STR between the eighth connection line CL8 and the eighth data line DL8, and the switching transistor STR between the ninth connection line CL9 and the ninth data line DL9 can be connected to the third control signal line CSL3.

[0349] In other words, the first control signal line CSL1 can transmit the first control signal CLA1 to the switching transistor STR between the first connection line CL1 and the first data line DL1, the switching transistor STR between the second connection line CL2 and the second data line DL2, and the switching transistor STR between the third connection line CL3 and the third data line DL3, and the third control signal line CSL3 can transmit the third control signal CLA2 to the switching transistor STR between the seventh connection line CL7 and the seventh data line DL7, the switching transistor STR between the eighth connection line CL8 and the eighth data line DL8, and the switching transistor STR between the ninth connection line CL9 and the ninth data line DL9.

[0350] The data distribution unit 170 may connect each of the fourth data line DL4, the fifth data line DL5, the sixth data line DL6, the tenth data line DL10, the eleventh data line DL11, and the twelfth data line DL12 to a corresponding data output line among the data output lines OL1, OL2, ..., OL6. In other words, each of the fourth data line DL4, the fifth data line DL5, the sixth data line DL6, the tenth data line DL10, the eleventh data line DL11, and the twelfth data line DL12 may be connected to a corresponding connection line among the fourth connection line CL4, the fifth connection line CL5, the sixth connection line CL6, the tenth connection line CL10, the eleventh connection line CL11, and the twelfth connection line CL12 without passing through the switching transistor STR. In an embodiment, each of the fourth data line DL4, the fifth data line DL5, the sixth data line DL6, the tenth data line DL10, the eleventh data line DL11 and the twelfth data line DL12 can be integrally provided as a monomer with a corresponding connection line among the fourth connection line CL4, the fifth connection line CL5, the sixth connection line CL6, the tenth connection line CL10, the eleventh connection line CL11 and the twelfth connection line CL12.

[0351] Since the switch transistor STR is not disposed between the data lines DL4, DL5, DL6, DL10, DL11, and DL12 and the connection lines CL4, CL5, CL6, CL10, CL11, and CL12, other lines or transistors, etc. can be arranged in the empty space, thereby reducing the area of ​​the dead zone. In addition, by omitting some of the control signals, the display device 10 (refer to Figure 1 ) line crosstalk can be reduced, allowing high-quality images to be displayed and power consumption to be reduced.

[0352] By dividing a control signal having the same waveform and the same phase into two different control signal lines and applying the control signals, the capacitance of each line can be halved.

[0353] Fig.19 is a diagram schematically illustrating an embodiment of the display device 10 . Fig.19 and Fig.17 Similar, but different in that, in the former, the display device 10 further includes bridge lines BL1 and BL3 between the control signal lines CSL1 and CSL3 and the power supply circuits PIC1 and PIC3. Hereinafter, description of the same or similar configurations is omitted, and differences are mainly described.

[0354] refer to Fig.19 The display device 10 may include a pixel unit 110, a data distribution unit 170, a data driving circuit DIC, and power supply circuits PIC1 and PIC4. The pixel unit 110 includes a sub-pixel Ps and a data line DL, and the data distribution unit 170 includes a sub-demultiplexer DMX. The data driving circuit DIC may be included in Figure 2 In the data driving unit 150 shown in FIG. 1 , the power supply circuits PIC1 and PIC3 may be included in Figure 2 In the control circuit 180 shown in .

[0355] The data line DL may extend from the pixel unit 110 in a second direction (e.g., a y-axis direction) and may be connected to the data distribution unit 170. The data distribution unit 170 may be connected between a data output line (not shown) and the data line DL. The data distribution unit 170 may be connected to the data driving circuit DIC through the data output line.

[0356] The data driving circuits DIC may be arranged to be spaced apart from each other in a first direction (eg, an x-axis direction) and a plurality of power supply circuits PIC1 and PIC3 may be arranged on opposite sides of the data driving circuit DIC.

[0357] The power supply circuits PIC1 and PIC3 may include a first power supply circuit PIC1 supplying a first control signal CLA1 and a third power supply circuit PIC3 supplying a third control signal CLA2 .

[0358] In a plan view, control signal lines CSL1 and CSL3 extending in a first direction (e.g., x-axis direction) may be arranged between power circuits PIC1 and PIC3 and the data distribution unit 170, and bridge lines BL1 and BL3 extending in a first direction (e.g., x-axis direction) may be arranged between the control signal lines CSL1 and CSL3 and the power circuits PIC1 and PIC3.

[0359] The bridge wires BL1 and BL3 may connect the power circuits PIC1 and PIC3 to the corresponding control signal lines CSL1 and CSL3, respectively. In an embodiment, for example, the first bridge wire BL1 may connect the first power circuit PIC1 and the first control signal line CSL1, and the third bridge wire BL3 may connect the third power circuit PIC3 to the third control signal line CSL3.

[0360] In an embodiment, for example, the first bridge wire BL1 may be connected to the first power circuit PIC1 through the first power output line POL1, and the third bridge wire BL3 may be connected to the third power circuit PIC3 through the third power output line POL3. Each of the bridge wires BL1 and BL3 may be connected to the corresponding control signal line through bridge connection lines BCL1 and BCL3 extending in the second direction (e.g., y-axis direction). The first bridge wire BL1 may be connected to the first control signal line CSL1 through the first bridge connection line BCL1, and the third bridge wire BL3 may be connected to the third control signal line CSL3 through the third bridge connection line BCL3.

[0361] The number of the first bridge connection lines BCL1 may be greater than the number of the first power output lines POL1 , and the number of the third bridge connection lines BCL3 may be greater than the number of the third power output lines POL3 .

[0362] Each of the control signal lines CSL1 and CSL3 may be connected to the data distribution unit 170 through a control gate line SGL.

[0363] The first control signal CLA1 supplied from the first power circuit PIC1 and the third control signal CLA2 supplied from the third power circuit PIC3 may have the same waveform and the same phase.

[0364] In a comparative example, when the power supply circuit is directly connected to the control signal line, the control signal in the area adjacent to the input point to which the power output line is connected (hereinafter referred to as the "edge area") has a relatively high conversion rate, while the control signal in the area away from the input point to which the power output line is connected (hereinafter referred to as the "center area") can have a relatively low conversion rate.

[0365] On the other hand, Fig.19 As shown in , when the control signal lines CSL1 and CSL3 are connected to the power circuits PIC1 and PIC3 through the bridge lines BL1 and BL3, the conversion rate of the control signal in the central area can be improved because the capacitance of the bridge lines BL1 and BL3 is relatively low. In addition, since the number of bridge connection lines BCL is greater than the number of power output lines POL, the input points of each of the control signals increase, thereby reducing the conversion deviation between the control signal in the central area and the control signal in the edge area.

[0366] Fig. 20 is a layout diagram schematically illustrating an embodiment of the data distribution unit 170 .

[0367] Fig. 20 and Fig.18 Similar, but different in that, in the former, the display device 10 further includes bridge lines BL1 and BL3 between the control signal lines CSL1 and CSL3 and the power supply circuit. Hereinafter, description of the same or similar configurations is omitted, and differences are mainly described.

[0368] refer to Fig. 20 , the data distribution unit 170 may include a plurality of switch transistors STR. Each of the switch transistors STR may be Fig.15 Any one of the first switch SW1 and the third switch SW3 shown in FIG.

[0369] Control signal lines CSL1 and CSL3 extending in a first direction (e.g., x-axis direction) may be disposed between the data distribution unit 170 and the data output lines OL1, OL2, ..., OL12. Bridge lines BL1 and BL3 extending in a first direction (e.g., x-axis direction) may be disposed between the control signal lines CSL1 and CSL3 and the data output lines OL1, OL2, ..., OL12.

[0370] The first bridge line BL1 may be connected to the first power supply circuit PIC1 (refer to Fig.19 ), and the third bridge line BL3 can be connected to the third power supply circuit PIC3 (reference Fig.19 ). Since the bridge lines BL1 and BL3 are spaced apart from the switch transistor STR, a load smaller than that of the control signal lines CSL1 and CSL3 may be applied to the bridge lines BL1 and BL3.

[0371] The first bridge line BL1 may be connected to the first control signal line CSL1 through the first bridge connection line BCL1 , and the third bridge line BL3 may be connected to the third control signal line CSL3 through the third bridge connection line BCL3 .

[0372] The number and arrangement of the first and third bridge connection lines BCL1 and BCL3 may be designed in various ways. When the first and third bridge connection lines BCL1 and BCL3 are provided in plural, the input points of the control signal in each of the control signal lines CSL1 and CSL3 increase, thereby improving the conversion deviation between the control signal in the central region of each of the control signal lines CSL1 and CSL3 and the control signal in the edge region of each of the control signal lines CSL1 and CSL3.

[0373] Each of the data output lines OL1, OL2, ..., OL6 may be connected to a pair of connection lines. A pair of connection lines connected to one data output line may be spaced apart from each other with two columns interposed therebetween. Connection lines CL1, CL2, ..., CL12 may correspond one-to-one to data lines DL1, DL2, ..., DL12.

[0374] Each of the switching transistors STR may include a first terminal connected to a corresponding data line among the data lines DL1, DL2, DL3, DL7, DL8 and DL9, a second terminal connected to a corresponding connection line among the connection lines CL1, CL2, CL3, CL7, CL8 and CL9, and a gate connected to a corresponding control signal line among the control signal lines CSL1 and CSL3.

[0375] The first control gate line SGL1 and the second control gate line SGL2 of each of the switching transistor STR between the first connection line CL1 and the first data line DL1, the switching transistor STR between the second connection line CL2 and the second data line DL2, and the switching transistor STR between the third connection line CL3 and the third data line DL3 can be connected to the first control signal line CSL1. The first control gate line SGL1 and the second control gate line SGL2 of each of the switching transistor STR between the seventh connection line CL7 and the seventh data line DL7, the switching transistor STR between the eighth connection line CL8 and the eighth data line DL8, and the switching transistor STR between the ninth connection line CL9 and the ninth data line DL9 can be connected to the third control signal line CSL3.

[0376] The switching transistor STR connected to the first control signal line CSL1 can connect the data lines DL1, DL2 and DL3 to the corresponding data output lines OL1, OL2 and OL3 in response to the first control signal CLA1. The switching transistor STR connected to the third control signal line CSL3 can connect the data lines DL7, DL8 and DL9 to the corresponding data output lines OL4, OL5 and OL6 in response to the third control signal CLA2.

[0377] The data distribution unit 170 may connect each of the fourth data line DL4, the fifth data line DL5, the sixth data line DL6, the tenth data line DL10, the eleventh data line DL11, and the twelfth data line DL12 to a corresponding data output line among the data output lines OL1, OL2, ..., OL6. In other words, each of the fourth data line DL4, the fifth data line DL5, the sixth data line DL6, the tenth data line DL10, the eleventh data line DL11, and the twelfth data line DL12 may be connected to a corresponding connection line among the fourth connection line CL4, the fifth connection line CL5, the sixth connection line CL6, the tenth connection line CL10, the eleventh connection line CL11, and the twelfth connection line CL12 without passing through the switching transistor STR. In an embodiment, each of the fourth data line DL4, the fifth data line DL5, the sixth data line DL6, the tenth data line DL10, the eleventh data line DL11 and the twelfth data line DL12 can be integrally provided as a monomer with a corresponding connection line among the fourth connection line CL4, the fifth connection line CL5, the sixth connection line CL6, the tenth connection line CL10, the eleventh connection line CL11 and the twelfth connection line CL12.

[0378] The first bridge line BL1 may transmit the first control signal CLA1 to the first control signal line CSL1 through the first bridge connection line BCL1 , and the third bridge line BL3 may transmit the third control signal CLA2 to the third control signal line CSL3 through the third bridge connection line BCL3 .

[0379] Since the switch transistor STR is not disposed between the data lines DL4, DL5, DL6, DL10, DL11, and DL12 and the connection lines CL4, CL5, CL6, CL10, CL11, and CL12, other lines or transistors, etc. can be arranged in the empty space, thereby reducing the area of ​​the dead zone. In addition, the number of control signal lines and the number of bridge lines can be reduced, so that the area of ​​the dead zone in the display device 10 can be reduced.

[0380] Fig.21 is a diagram for describing an embodiment of a sub-demultiplexer DMX. Fig.21 and Fig.14 Similar, but the difference is that in the former, the sub-demux DMX connects the three data lines to one data output line.

[0381] refer to Fig.21, the sub-demultiplexer DMX may selectively connect the kth data output line OLk to the ith data line DLi, the i+3th data line DLi+3, and the i+6th data line DLi+6. The sub-demultiplexer DMX may include a first switch SW1 connecting the kth data output line OLk to the ith data line DLi and a second switch SW2 connecting the kth data output line OLk to the i+3th data line DLi+3, and may connect the i+6th data line DLi+6 to the kth data output line OLk without passing through a switch.

[0382] The i-th data line DLi, the i+3-th data line DLi+3, and the i+6-th data line DLi+6 may be spaced apart from each other with two columns interposed therebetween. In an embodiment, for example, the i+1-th data line and the i+2-th data line may be arranged between the i-th data line DLi and the i+3-th data line DLi+3, and the i+4-th data line and the i+5-th data line may be arranged between the i+3-th data line DLi+3 and the i+6-th data line DLi+6. The i-th data line DLi may be connected to a sub-pixel in the i-th column (e.g., labeled by M1), the i+3-th data line DLi+3 may be connected to a sub-pixel in the i+3-th column (e.g., labeled by M4), and the i+6-th data line DLi+6 may be connected to a sub-pixel in the i+6-th column (e.g., labeled by M7).

[0383] The first switch SW1 may be provided between the kth data output line OLk and the ith data line DLi. The first switch SW1 may connect the kth data output line OLk to the ith data line DLi through the first control signal CLA and may apply the data signal DATA applied via the kth data output line OLk to the ith data line DLi.

[0384] The second switch SW2 may be provided between the kth data output line OLk and the i+3th data line DLi+3. The second switch SW2 may connect the kth data output line OLk to the i+3th data line DLi+3 through the second control signal CLB, and may apply the data signal DATA applied via the kth data output line OLk to the i+3th data line DLi+3.

[0385] The sub-demultiplexer DMX may connect the kth data output line OLk to the i+6th data line DLi+6. In other words, no switch is provided between the kth data output line OLk and the i+6th data line DLi+6, and the data signal DATA applied to the kth data output line OLk may be applied to the i+6th data line DLi+6 regardless of the control signals CLA and CLB.

[0386] In an embodiment, sub-pixels connected to the i-th data line DLi, the i+3-th data line DLi+3, and the i+6-th data line DLi+6 may emit light of the same color. In this regard, Fig.21 It is shown that the sub-pixels connected to the i-th data line DLi, the i+3-th data line DLi+3, and the i+6-th data line DLi+6 are red sub-pixels PR emitting red light. However, the present disclosure is not limited thereto. The connection between the data lines and the sub-pixels may be modified in various ways.

[0387] Fig. 22 is a diagram schematically illustrating an embodiment of a display device.

[0388] refer to Fig. 22 , the data distribution unit 170 may include a first demultiplexer DMX1 and a second demultiplexer DMX2, and the pixel unit 110 may include a plurality of pixels PX. The pixel PX may include a red sub-pixel PR, a green sub-pixel PG, and a blue sub-pixel PB.

[0389] In the pixel unit 110, the columns in which the red sub-pixels PR are arranged in the second direction (e.g., the y-axis direction), the columns in which the green sub-pixels PG are arranged in the second direction (e.g., the y-axis direction), and the columns in which the blue sub-pixels PB are arranged in the second direction (e.g., the y-axis direction) may be alternately repeated in the first direction (e.g., the x-axis direction).

[0390] In an embodiment, for example, in a first row, a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel are sequentially arranged in a first direction (e.g., an x-axis direction). The first pixel may include three sub-pixels PR11, PG11, and PB11 in the first to third columns, the second pixel may include three sub-pixels PR12, PG12, and PB12 in the fourth to sixth columns, the third pixel may include three sub-pixels PR13, PG13, and PB13 in the seventh to ninth columns, the fourth pixel may include three sub-pixels PR14, PG14, and PB14 in the tenth to twelfth columns, the fifth pixel may include three sub-pixels PR15, PG15, and PB15 in the thirteenth to fifteenth columns, and the sixth pixel may include three sub-pixels PR16, PG16, and PB16 in the sixteenth to eighteenth columns.

[0391] A plurality of data lines DL1, DL2, . . . , DL18 and a plurality of gate lines GLn-3, GLn-2, ​​GLn-1, and GLn may be arranged in the pixel unit 110. The plurality of gate lines GLn-3, GLn-2, ​​GLn-1, and GLn may be Figure 2 The gate lines (eg, GL1, GL2, ..., GLn) shown in Figure 3A and Figure 3BThe first gate line GWL is shown in FIG.

[0392] A gate line may be connected to sub-pixels arranged in the same row. A data line may be connected to sub-pixels arranged in the same column. A sub-pixel connected to the i-th data line DLi and a sub-pixel connected to the i+3-th data line DLi+3 may be sub-pixels emitting light of the same color. For ease of description, Fig. 22 Only eighteen data lines DL1, DL2, ..., DL18, four gate lines GLn-3, GLn-2, ​​GLn-1 and GLn, and six data output lines OL1, OL2, ..., OL6 are shown. However, the number of data lines, the number of gate lines, and the number of data output lines may be greater.

[0393] The first demultiplexer DMX1 may selectively connect the data output lines OL1, OL2, and OL3 belonging to the first group GR1 to the first to ninth data lines DL1, DL2, ..., and DL9, and the second demultiplexer DMX2 may selectively connect the data output lines OL4, OL5, and OL6 belonging to the second group GR2 to the tenth to eighteenth data lines DL10, DL11, ..., DL18.

[0394] Each of the first demultiplexer DMX1 and the second demultiplexer DMX2 may include a plurality of sub-demultiplexers DMX (refer to Fig.21 ). One sub-demultiplexer DMX may selectively connect one data output line to three data lines. The three data lines connected to one sub-demultiplexer DMX may be spaced apart from each other with two columns interposed therebetween.

[0395] In an embodiment, for example, three data lines connected to the first data output line OL1 belonging to the first group GR1 may be a first data line DL1, a fourth data line DL4, and a seventh data line DL7. The first data line DL1 may be connected to a red sub-pixel PR11 of a first pixel, the fourth data line DL4 may be connected to a red sub-pixel PR12 of a second pixel, and the seventh data line DL7 may be connected to a red sub-pixel PR13 of a third pixel.

[0396] The three data lines connected to the fourth data output line OL4 belonging to the second group GR2 may be a tenth data line DL10, a thirteenth data line DL13, and a sixteenth data line DL16. The tenth data line DL10 may be connected to a red sub-pixel PR14 of a fourth pixel, the thirteenth data line DL13 may be connected to a red sub-pixel PR15 of a fifth pixel, and the sixteenth data line DL16 may be connected to a red sub-pixel PR16 of a sixth pixel.

[0397] The first demultiplexer DMX1 may include a first switch SW1 and a second switch SW2. Each of the first switches SW1 may be provided between the first data output line OL1 and the first data line DL1, between the second data output line OL2 and the second data line DL2, and between the third data output line OL3 and the third data line DL3. The first switch SW1 may be turned on by a first control signal CLA1, and may connect the first data output line OL1 to the first data line DL1, the second data output line OL2 to the second data line DL2, and the third data output line OL3 to the third data line DL3.

[0398] Each of the second switches SW2 may be provided between the first data output line OL1 and the fourth data line DL4, between the second data output line OL2 and the fifth data line DL5, and between the third data output line OL3 and the sixth data line DL6. The second switch SW2 may be turned on by the second control signal CLB1, and may connect the first data output line OL1 to the fourth data line DL4, the second data output line OL2 to the fifth data line DL5, and the third data output line OL3 to the sixth data line DL6.

[0399] The first demultiplexer DMX1 may connect the first data output line OL1 to the seventh data line DL7 , the second data output line OL2 to the eighth data line DL8 , and the third data output line OL3 to the ninth data line DL9 regardless of the control signals CLA1 , CLA2 , CLB1 , and CLB2 .

[0400] The first data signal DATA applied to the first data output line OL1 <1> The first sub-data signal DATA applied to the red sub-pixel PR and the second data signal DATA applied to the second data output line OL2 may be included. <2> The second sub-data signal DATA applied to the green sub-pixel PG and the third data signal DATA applied to the third data output line OL3 may be included. <3> A third sub data signal applied to the blue sub-pixel PB may be included.

[0401] The second demultiplexer DMX2 may include a third switch SW3 and a fourth switch SW4. Each of the third switches SW3 may be provided between the fourth data output line OL4 and the tenth data line DL10, between the fifth data output line OL5 and the eleventh data line DL11, and between the sixth data output line OL6 and the twelfth data line DL12. The third switch SW3 may be turned on according to the third control signal CLA2, and may connect the fourth data output line OL4 to the tenth data line DL10, the fifth data output line OL5 to the eleventh data line DL11, and the sixth data output line OL6 to the twelfth data line DL12.

[0402] Each of the fourth switches SW4 may be provided between the fourth data output line OL4 and the thirteenth data line DL13, between the fifth data output line OL5 and the fourteenth data line DL14, and between the sixth data output line OL6 and the fifteenth data line DL15. The fourth switches SW4 may be turned on according to the fourth control signal CLB2, and may connect the fourth data output line OL4 to the thirteenth data line DL13, the fifth data output line OL5 to the fourteenth data line DL14, and the sixth data output line OL6 to the fifteenth data line DL15.

[0403] The second demultiplexer DMX2 may connect the fourth data output line OL4 to the sixteenth data line DL16 , the fifth data output line OL5 to the seventeenth data line DL17 , and the sixth data output line OL6 to the eighteenth data line DL18 regardless of the control signals CLA1 , CLA2 , CLB1 , and CLB2 .

[0404] The fourth data signal DATA applied to the fourth data output line OL4 <4> The first sub-data signal DATA applied to the red sub-pixel PR and the fifth data signal DATA applied to the fifth data output line OL5 may be included. <5> The second sub-data signal DATA applied to the green sub-pixel PG and the sixth data signal DATA applied to the sixth data output line OL6 may be included. <6> A third sub data signal applied to the blue sub-pixel PB may be included.

[0405] exist Fig.21 and Fig. 22 In the embodiment, the sub-demultiplexer DMX connects one data output line to three data lines. However, the present disclosure is not limited thereto. In an embodiment, the sub-demultiplexer DMX may connect one data output line to N data lines. In this case, the sub-demultiplexer DMX may include N-1 switches, and may connect one data line to the data output line without passing through the switch.

[0406] In an embodiment, the pixel unit 110 may include 2N data lines. Here, N may be a natural number satisfying 2≤N. For example, the data distribution unit 170 may include a first demultiplexer DMX1 and a second demultiplexer DMX2. N data lines among the 2N data lines may be connected to the first data output line through the first demultiplexer DMX1, and the remaining N data lines may be connected to the second data output line through the second demultiplexer DMX2.

[0407] The first demultiplexer DMX1 may include N-1 switches that connect the first data output line to each of the N-1 data lines. The first demultiplexer DMX1 may connect the first data output line to the Nth data line among the N data lines connected to the first data output line without passing through the switch. The second demultiplexer DMX2 may include N-1 switches that connect the second data output line to each of the N-1 data lines. The second demultiplexer DMX2 may connect the second data output line to the Nth data line among the N data lines connected to the second data output line without passing through the switch.

[0408] The control circuit may output a total of 2N-2 control signals, including N-1 control signals for turning on or off the N-1 switches included in the first demultiplexer DMX1 and N-1 control signals for turning on or off the N-1 switches included in the second demultiplexer DMX2. In this case, the i-th control signal (1≤i≤N-1, where i is a natural number) may have the same phase and the same waveform as the N+i-th control signal. As described above, by dividing the control signal having the same waveform and the same phase into two different control signal lines and applying the control signal, the capacitance of each line may be halved.

[0409] In addition, by connecting some data lines to the data output line without passing through the switch, some of the control signals can be omitted. When some of the control signals are omitted, the power consumption of the display device 10 can be reduced, thereby reducing the area of ​​the dead zone.

[0410] In an embodiment, each display device 10 may further include a bridge line connecting each of the control signal lines to the control circuit. Each of the bridge lines may be connected to a corresponding control signal line through a bridge connection line.

[0411] According to the embodiment configured as described above, the number of data output lines in the data driving unit can be reduced, thereby reducing the manufacturing cost of the display device. In addition, according to the embodiment, the conversion rate of the control signal can be increased, thereby allowing the display device to achieve high-quality images. However, the scope of the embodiment is not limited by these effects.

[0412] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or advantages within each embodiment should generally be considered applicable to other similar features or advantages in other embodiments. Although the embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: A pixel unit, comprising a first data line, a second data line, a third data line and a fourth data line; A data driving unit outputs a data signal through a data output line; a data distribution unit, comprising: a first switch, connecting a first data output line among the data output lines to the first data line according to a first control signal; a second switch, connecting the first data output line to the second data line according to a second control signal; a third switch, connecting a second data output line among the data output lines to the third data line according to a third control signal; and a fourth switch, connecting the second data output line to the fourth data line according to a fourth control signal; and The control circuit includes: a first power supply circuit, outputting the first control signal; a second power supply circuit, outputting the second control signal; a third power supply circuit, outputting the third control signal; and a fourth power supply circuit, outputting the fourth control signal. wherein the first control signal has the same phase as the third control signal, and The second control signal has the same phase as that of the fourth control signal.

2. The display device according to claim 1, wherein: The second data line and the first data line are spaced apart from each other with two columns interposed therebetween, and the fourth data line and the third data line are spaced apart from each other with two columns interposed therebetween.

3. The display device according to claim 1, further comprising: a first control signal line connecting the first switch and the first power circuit to each other; a second control signal line connecting the second switch and the second power supply circuit to each other; a third control signal line connecting the third switch and the third power supply circuit to each other; as well as A fourth control signal line connects the fourth switch and the fourth power supply circuit to each other.

4. The display device according to claim 3, further comprising: a first power output line connecting the first power circuit and the first control signal line to each other; a second power output line, connecting the second power circuit and the second control signal line to each other; a third power output line, connecting the third power circuit and the third control signal line to each other; as well as A fourth power output line connects the fourth power circuit and the fourth control signal line to each other.

5. The display device according to claim 3, further comprising: a first bridge line connecting the first power circuit and the first control signal line to each other; a second bridge line connecting the second power supply circuit and the second control signal line to each other; a third bridge line connecting the third power supply circuit and the third control signal line to each other; as well as The fourth bridge line connects the fourth power supply circuit and the fourth control signal line to each other.

6. The display device according to claim 5, further comprising: a first power output line connecting the first power circuit and the first bridge line to each other; a second power output line connecting the second power circuit and the second bridge line to each other; a third power output line connecting the third power circuit and the third bridge line to each other; as well as A fourth power output line connects the fourth power circuit and the fourth bridge line to each other.

7. The display device according to claim 6, further comprising: a first bridge connection line, connecting the first bridge line and the first control signal line to each other; a second bridge connection line, connecting the second bridge line and the second control signal line to each other; a third bridge connection line, connecting the third bridge line and the third control signal line to each other; as well as The fourth bridge connection line connects the fourth bridge line and the fourth control signal line to each other.

8. The display device according to claim 7, wherein: The number of each of the first, second, third and fourth bridge connection lines is greater than the number of each of the first, second, third and fourth power output lines.

9. The display device according to claim 7, wherein: Each of the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line and the first bridge line, the second bridge line, the third bridge line, and the fourth bridge line extends in a first direction, and Each of the first bridge connection line, the second bridge connection line, the third bridge connection line, and the fourth bridge connection line extends in a second direction crossing the first direction.

10. The display device according to claim 1, wherein: The pixel unit further includes a first pixel, a second pixel, a third pixel, and a fourth pixel arranged in the same row, The first data line is connected to one of the sub-pixels of the first pixel, and the second data line is connected to one of the sub-pixels of the second pixel, and The third data line is connected to one of the sub-pixels of the third pixel, and the fourth data line is connected to one of the sub-pixels of the fourth pixel.

11. The display device according to claim 10, wherein: The one sub-pixel of the sub-pixels of the first pixel connected to the first data line and the one sub-pixel of the sub-pixels of the second pixel connected to the second data line emit light of the same color, and The one of the sub-pixels of the third pixel connected to the third data line and the one of the sub-pixels of the fourth pixel connected to the fourth data line emit light of the same color.

12. The display device according to claim 10, wherein: The pixel unit further includes: a fifth data line between the first data line and the second data line; a sixth data line between the second data line and the third data line; a seventh data line between the third data line and the fourth data line; and an eighth data line, and The data distribution unit further includes: a fifth switch, a sixth switch, a seventh switch and an eighth switch, wherein the fifth switch connects a third data output line among the data output lines to the fifth data line according to the first control signal, the sixth switch connects the third data output line to the sixth data line according to the second control signal, the seventh switch connects a fourth data output line among the data output lines to the seventh data line according to the third control signal, and the eighth switch connects the fourth data output line to the eighth data line according to the fourth control signal.

13. The display device according to claim 12, wherein: The first switch and the fifth switch are connected to the first power supply circuit through a first control signal line, the second switch and the sixth switch are connected to the second power supply circuit through a second control signal line, the third switch and the seventh switch are connected to the third power supply circuit through a third control signal line, and the fourth switch and the eighth switch are connected to the fourth power supply circuit through a fourth control signal line.

14. A display device, comprising: A first data line, a second data line, a third data line and a fourth data line are connected to the sub-pixels respectively; A data output line connected to a data driving unit that outputs a data signal; A first switch transistor, a second switch transistor, a third switch transistor and a fourth switch transistor are connected to the first data line, the second data line, the third data line and the fourth data line, respectively, and each of the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor comprises: a semiconductor layer; a first gate line and a second gate line, which are arranged on the semiconductor layer; a first electrode and a second electrode, which are arranged on the first gate line and the second gate line; and a third electrode, which is arranged between the first electrode and the second electrode; and a first control signal line, a second control signal line, a third control signal line, and a fourth control signal line, arranged between the data output line and the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor in a plan view, and extending in a first direction, The first gate line and the second gate line extend in a second direction intersecting the first direction, and The first electrode and the second electrode extend in the second direction and are connected to opposite ends of the semiconductor layer, respectively.

15. The display device according to claim 14, wherein: The first electrode and the second electrode of each of the first switching transistor and the second switching transistor are connected to a first data output line among the data output lines, and The first electrode and the second electrode of each of the third switching transistor and the fourth switching transistor are connected to a second data output line among the data output lines.

16. The display device according to claim 14, wherein: The third electrode of the first switching transistor is connected to the first data line, the third electrode of the second switching transistor is connected to the second data line, the third electrode of the third switching transistor is connected to the third data line, and the third electrode of the fourth switching transistor is connected to the fourth data line.

17. The display device according to claim 14, wherein: The first gate line and the second gate line of the first switching transistor are connected to the first control signal line, the first gate line and the second gate line of the second switching transistor are connected to the second control signal line, the first gate line and the second gate line of the third switching transistor are connected to the third control signal line, and the first gate line and the second gate line of the fourth switching transistor are connected to the fourth control signal line.

18. The display device according to claim 17, further comprising: a first bridge wire, a second bridge wire, a third bridge wire, and a fourth bridge wire extending in the first direction and arranged between the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line and the control circuit in the plan view; as well as A first bridge connection line connecting the first bridge line and the first control signal line to each other, a second bridge connection line connecting the second bridge line and the second control signal line to each other, a third bridge connection line connecting the third bridge line and the third control signal line to each other, and a fourth bridge connection line connecting the fourth bridge line and the fourth control signal line to each other, the first bridge connection line, the second bridge connection line, the third bridge connection line and the fourth bridge connection line extend in the second direction.

19. The display device according to claim 14, wherein: the first control signal line transmits a first control signal to the first switch transistor, the second control signal line transmits a second control signal to the second switch transistor, the third control signal line transmits a third control signal to the third switch transistor, and the fourth control signal line transmits a fourth control signal to the fourth switch transistor, The first control signal has the same phase as the third control signal, and The second control signal has the same phase as that of the fourth control signal.

20. The display device according to claim 14, wherein: The semiconductor layer includes an oxide-based semiconductor material.

21. A display device, comprising: A pixel unit, comprising a first data line, a second data line, a third data line and a fourth data line; A data driving unit outputs a data signal through a data output line; a data distribution unit, connecting a first data output line among the data output lines to the second data line, and connecting a second data output line among the data output lines to the fourth data line, the data distribution unit comprising: a first switch, connecting the first data output line to the first data line according to a first control signal; and a second switch, connecting the second data output line to the third data line according to a second control signal; and The control circuit includes: a first power supply circuit, outputting the first control signal; and a second power supply circuit, outputting the second control signal. The first control signal has the same phase as that of the second control signal.

22. The display device according to claim 21, wherein: The second data line and the first data line are arranged spaced apart from each other with two columns interposed therebetween, and the fourth data line and the third data line are arranged spaced apart from each other with two columns interposed therebetween.

23. The display device according to claim 21, further comprising: a first control signal line connecting the first switch and the first power circuit to each other; as well as The second control signal line connects the second switch and the second power supply circuit to each other.

24. The display device according to claim 23, further comprising: a first power output line connecting the first power circuit and the first control signal line to each other; as well as The second power output line connects the second power circuit and the second control signal line to each other.

25. The display device according to claim 23, further comprising: a first bridge line connecting the first power circuit and the first control signal line to each other; as well as The second bridge line connects the second power supply circuit and the second control signal line to each other.

26. The display device according to claim 25, further comprising: a first power output line connecting the first power circuit and the first bridge line to each other; as well as The second power output line connects the second power circuit and the second bridge line to each other.

27. The display device according to claim 26, further comprising: a first bridge connection line, connecting the first bridge line and the first control signal line to each other; as well as The second bridge connection line connects the second bridge line and the second control signal line to each other.

28. The display device according to claim 27, wherein: The number of the first bridge connection lines is greater than the number of the first power output lines, and the number of the second bridge connection lines is greater than the number of the second power output lines.

29. The display device according to claim 27, wherein: The first control signal line, the second control signal line, the first bridge line, and the second bridge line extend in a first direction, and The first bridge connection line and the second bridge connection line extend in a second direction crossing the first direction.

30. The display device according to claim 21, wherein: The pixel unit further includes a first pixel, a second pixel, a third pixel, and a fourth pixel arranged in the same row, The first data line is connected to one of the sub-pixels of the first pixel, and the second data line is connected to one of the sub-pixels of the second pixel, and The third data line is connected to one of the sub-pixels of the third pixel, and the fourth data line is connected to one of the sub-pixels of the fourth pixel.

31. The display device according to claim 30, wherein: The one sub-pixel of the sub-pixels of the first pixel connected to the first data line and the one sub-pixel of the sub-pixels of the second pixel connected to the second data line emit light of the same color, and The one of the sub-pixels of the third pixel connected to the third data line and the one of the sub-pixels of the fourth pixel connected to the fourth data line emit light of the same color.

32. A display device comprising: A first data line, a second data line, a third data line and a fourth data line are connected to the sub-pixels respectively; a first data output line, connecting a data driving unit with the first data line and the second data line; a second data output line, connecting the data driving unit with the third data line and the fourth data line; a first switch transistor and a second switch transistor, the first switch transistor being connected between the first data line and the first data output line, the second switch transistor being connected between the third data line and the second data output line, each of the first switch transistor and the second switch transistor comprising: a semiconductor layer; a first gate line and a second gate line disposed on the semiconductor layer; a first electrode and a second electrode disposed on the first gate line and the second gate line and connected to opposite ends of the semiconductor layer, respectively; and a third electrode disposed between the first electrode and the second electrode; and a first control signal line and a second control signal line, arranged between the first data output line and the first switch transistor and between the second data output line and the second switch transistor in a plan view, and extending in a first direction, The first gate line and the second gate line extend in a second direction crossing the first direction.

33. The display device according to claim 32, wherein: The first electrode and the second electrode of the first switch transistor are connected to the first data output line, The first electrode and the second electrode of the second switch transistor are connected to the second data output line, The second data line is connected to the first data output line, and The fourth data line is connected to the second data output line.

34. The display device according to claim 33, wherein: The third electrode of the first switching transistor is connected to the first data line, and the third electrode of the second switching transistor is connected to the third data line.

35. The display device according to claim 32, wherein: The first gate line and the second gate line of the first switch transistor are connected to the first control signal line, and the first gate line and the second gate line of the second switch transistor are connected to the second control signal line.

36. The display device according to claim 35, further comprising: a first bridge wire and a second bridge wire extending in the first direction and arranged between the control circuit and the first control signal line and the second control signal line in the plan view; as well as A first bridge connection line and a second bridge connection line, the first bridge connection line connects the first bridge connection line and the first control signal line to each other, the second bridge connection line connects the second bridge connection line and the second control signal line to each other, and the first bridge connection line and the second bridge connection line extend in the second direction.

37. The display device according to claim 32, wherein: The first control signal line transmits a first control signal to the first switch transistor, and the second control signal line transmits a second control signal to the second switch transistor, and The first control signal and the second control signal have the same phase.

38. The display device according to claim 32, wherein: The semiconductor layer includes an oxide-based semiconductor material.

39. A display device comprising: A pixel unit includes 2N data lines, where N is a natural number satisfying 2≤N; A data driving unit outputs a data signal through a first data output line and a second data output line; a data distribution unit, connecting the first data output line to an Nth data line among the 2N data lines, and connecting the second data output line to a 2Nth data line among the 2N data lines, the data distribution unit comprising: N-1 switches connecting the first data output line to each of N-1 data lines among the 2N data lines; and N-1 switches connecting the second data output line to each of the remaining N-1 data lines among the 2N data lines; and a control circuit that outputs 2N-2 control signals for controlling each of the switches, The i-th control signal has the same phase as that of the N+i-th control signal, where i is a natural number satisfying 1≤i≤N-1.

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