In-memory computing circuit with optimized line resistance

Abstract

The invention discloses an in-memory computing circuit with optimized line resistance. The in-memory computing circuit comprises a plurality of rows and columns of in-memory computing units and an input and output control module, each in-memory computing unit comprises two transistors and a memory unit, and the switching of the writing mode and the computing mode of the circuit can be realized through the opening and closing of the gate line and the word line. The in-memory computing units controlled by the same group of input and output modules in each row share the same common source line, all in-memory computing units in each row share the same bit line, and the in-memory computing units are connected with the common source line through a common source line enabling switch to realize routing sharing. According to the invention, a single calculation unit only comprises two transistors and one nonvolatile device, and the routing resistance in a calculation mode is reduced through common source line multiplexing, so that the potential design scale and calculation precision of the storage and calculation array can be greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of novel storage and computing, and in particular relates to an in-memory computing circuit with optimized line resistance. Background Art

[0002] With the development of emerging applications such as autonomous driving, the Internet of Things, and artificial intelligence, the industry has increasingly increased its requirements for computing performance and power consumption constraints on computing devices. Computing in Memory (CiM), as a widely-watched data processing technology, stores weights in a memory array to implement matrix multiplication, avoiding the repeated transfer of weight data, which can greatly improve the computing energy efficiency and speed of the system.

[0003] In recent years, the implementation of in-memory computing based on new non-volatile memory (NVM) has been widely studied. The main feature of non-volatile memory is that it uses its inherent physical properties to store data, and the stored data will not be lost after power failure. Compared with SRAM cells, cells based on non-volatile memory only require one device and a gate transistor to cooperate to implement, and their area has obvious advantages; compared with DRAM cells, the static power consumption of non-volatile memory devices is greatly reduced, and the energy efficiency has significant advantages. Currently, the non-volatile storage structures that have received more attention include resistive random access memory (ReRAM), magnetic tunnel junction (MTJ), phase change memory (PCM) and ferroelectric tunnel junction (FTJ). However, most of the existing storage and computing circuits based on non-volatile memory still have disadvantages such as complex read and write operations and low calculation accuracy. Summary of the invention

[0004] In order to overcome the shortcomings of existing in-memory computing units such as low storage density and complex operation, the present invention proposes an in-memory computing circuit with optimized line resistance, which can efficiently realize in-memory multiplication and addition calculations. Compared with the existing technical solutions, it can greatly reduce computing power consumption and data transfer overhead, and effectively improve the scale and storage density of the memory computing array.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A line resistance optimized in-memory computing circuit comprises in-memory computing units of multiple rows and columns and an input-output control module; each in-memory computing unit comprises two transistors and a storage unit, the storage unit may be a two-terminal non-volatile memory device (including but not limited to MTJ, FTJ, ReRAM, etc.), one end of the storage unit is connected to a signal line (SIG), and the other end is connected to a common source end of two transistors, the gates of the two transistors are respectively controlled by a selection line (SEL) and a word line (WL), and the drain ends of the two transistors are respectively connected to a bit line (BL) and a common source line (CSL); the transistor controlled by the selection line (SEL) is used to implement a computing function, and the transistor controlled by the word line (WL) is used to implement a read-write function; each input-output control module (IO) corresponds to the SIG lines of several columns of in-memory computing units; the in-memory computing units in the same group of IOs in each row share the same CSL, and the CSL is suspended; all in-memory computing units in each row share the same BL, and at least one common source line enable switch (CSLEN) is connected between the BL and each CSL.

[0007] Furthermore, the in-memory computing circuit includes a write mode and a computing mode; in the write mode, each operation can change the weight value stored in a storage unit, and in the computing mode, a matrix-vector multiplication (MVM) can be completed within one computing clock cycle.

[0008] The beneficial effects of the present invention are as follows: the present invention proposes an in-memory computing circuit based on a 2-transistor + 1 storage unit (2T1M) structure, in which BL and CSL are connected by CSLEN rather than physically directly merged, so that the computing branch and the read-write branch are relatively independent in control, which can effectively reduce the accuracy loss caused by line resistance and retain greater design freedom; in addition, the design of in-memory computing is realized by using a non-volatile memory, which can greatly reduce the time cost caused by weight transfer and improve the energy efficiency and computing power of the in-memory computing module. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of the in-memory calculation circuit of the line resistance optimization solution of the present invention;

[0010] Figure 2 A schematic diagram of a write operation of an in-memory computing circuit in the present invention;

[0011] Figure 3 It is a schematic diagram of the calculation operation of the in-memory calculation circuit in the present invention. DETAILED DESCRIPTION

[0012] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments, which is intended to provide a basic understanding of the present invention, and is not intended to confirm the key or decisive elements of the present invention or the scope to be protected. It is easy to understand that without changing the essential spirit of the present invention, various replacements, changes and modifications are possible by those skilled in the art without departing from the spirit and scope of the present invention and the attached claims. Therefore, the following specific implementation methods and the accompanying drawings are only exemplary descriptions of the technical solution of the present invention, and should not be regarded as the entirety of the present invention or as a limitation or restriction of the technical solution of the present invention.

[0013] The object of the present invention is to provide an in-memory computing circuit with optimized line resistance. The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0014] Figure 1 The schematic diagram of the in-memory computing circuit of the line resistance optimization solution is shown. The circuit includes two working modes: write mode and calculation mode. The weight value stored in the non-volatile storage unit can be modified in the write mode, and the in-memory computing operation is realized in the calculation mode.

[0015] Figure 2 The schematic diagram of the write operation of the in-memory computing circuit is shown. Without loss of generality, it is assumed that a group of IOs corresponds to 64 storage cells in each row. Taking the write operation of the storage cell in the first column of the zeroth row in the array as an example, the write signal is sent from the bit line BL <0> SHIF, CSLEN <0> The corresponding transistor is selected, and the corresponding column word line (WL <1> ) applies a high potential, and the 64 selection signals turn off the corresponding 64 transistors used for calculation. The IO module writes the state to the signal line SIG <1> The corresponding potential is applied to the SIG lines, and the other 63 SIG lines in the same group are left floating.

[0016] Figure 3 The schematic diagram of the calculation operation of the in-memory calculation circuit is shown. Without loss of generality, the calculation process of the zeroth row is shown here. For matrix-vector multiplication calculation, multiple rows of input can be used. The input signal is from the bit line BL <0> On the application, CSLEN <0> The corresponding transistor is selected, and the corresponding word line of the memory cell involved in the calculation is applied with a low potential. The selection signal is applied with a high potential to turn on the transistor used for calculation. The calculation result is output from the corresponding SIG in the form of an analog signal. It is worth mentioning that the opening of the common source line enable switch allows the input signal in the calculation mode to share the two lines BL and CSL, which effectively reduces the line resistance of the metal line and can alleviate the IR-drop effect that is widely present in the in-memory calculation.

[0017] The above is only a preferred embodiment of the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present invention by using the above disclosed methods and technical contents without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A line resistance optimized in-memory computing circuit, characterized in that: It includes a multi-row and multi-column in-memory computing unit and an input-output control module; The in-memory computing unit comprises two transistors and a two-port storage unit, one end of the storage unit is connected to the signal line, and the other end is connected to the common source end of the two transistors, the gates of the two transistors are respectively controlled by the selection line and the word line, and the drain ends of the two transistors are respectively connected to the bit line and the common source line; The input-output control module corresponds to a number of signal lines, and is used to select one or more signal lines and set them to a specific potential, or read the matrix-vector multiplication calculation result.

2. The line resistance optimized in-memory computing circuit according to claim 1, characterized in that: The two-port storage unit in the in-memory computing unit is a two-terminal non-volatile storage device, including a resistive random access memory, a magnetic tunnel junction, a phase change memory, and a ferroelectric tunnel junction.

3. The line resistance optimized in-memory computing circuit according to claim 1, characterized in that: The bit lines and common source lines are arranged in a row direction, and the word lines, gate lines and signal lines are arranged in a column direction.

4. The line resistance optimized in-memory computing circuit according to claim 1, characterized in that: The in-memory computing units in the same group of input-output control modules in each row share the same suspended common source line; all the in-memory computing units in each row share the same bit line, and there is at least one common source line enable switch between the bit line and each common source line.

5. The in-memory computing circuit with optimized line resistance according to any one of claims 1 to 4, characterized in that: The circuit includes a write mode and a calculation mode, and the writing and calculation mode switching of the circuit is realized by turning on and off the gate line and the word line.

6. The in-memory computing circuit with optimized line resistance according to claim 5, characterized in that: In write mode, the selection line turns off the controlled transistor, the word line selects a column of storage cells, and a write signal is applied to the bit line where the cell to be written is located to change its state. At the same time, the common source line enable switch of the corresponding row is turned on together, and the current flows out from the signal line of the column where the cell is located.

7. The in-memory computing circuit with optimized line resistance according to claim 5, characterized in that: In the calculation mode, the word line turns off the controlled transistor, the selection line of the calculation column enables the corresponding transistor, the input signal is applied from the bit line of the calculation row, and the common source line enable switch of the relevant row is turned on together, and the calculation result is read from the signal line.

Images