Memory test method and device, equipment and storage medium

Abstract

The invention provides a memory test method, device and equipment and a storage medium, and the method comprises the steps: determining a target processor core from a plurality of processor cores of a memory, the target processor core being a processor core with the least completion number of error injection test commands in the plurality of processor cores; sending each operation instruction in the current error injection test command to the target processor core, and recording an execution response of the target processor core to each operation instruction; if the sending number of the operation instructions is equal to the execution response number and equal to the total number of the operation instructions in the current error injection test commands, increasing the completion number of the error injection test commands of the target processor core; each error correction instruction in the current error injection test command is sent to the target processor core, the error correction result of each error correction instruction is saved, and the test result is obtained, the method can test each processor core, and it is guaranteed that loads of the processor cores are balanced.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory testing method, device, equipment and storage medium. Background Art

[0002] In the prior art, the storage unit in the storage device is affected by physical properties, use environment, etc., which will inevitably lead to errors in stored data. For example, the core components of a solid state drive (SSD) include a control unit and a storage unit, wherein the storage unit is mainly composed of a Flash chip and a DRAM chip. At present, the storage medium used by most SSDs is NAND Flash, which is a non-volatile memory. The physical structure of NAND Flash is based on floating gate transistors, which makes it have high stability when storing data. However, due to physical properties such as charge leakage and oxide layer aging, NAND Flash may be affected by drift effects, over-programming effects, read operation interference, and temperature during long-term use, resulting in data errors such as bit inversion. Commonly used error handling technologies include soft decoding, hard decoding, ECC (Error Correction Code), XORE, CRC (Cyclic Redundancy Check), etc.

[0003] In order to ensure that the controller in the storage device can correctly handle the potential errors of the storage unit, module testing in the development phase is essential. In addition, as the read and write speed of the storage device is also increasing, the controller in the storage device usually uses a multi-core architecture to process data to achieve higher performance.

[0004] Therefore, how to effectively plan and balance multi-core processing in error injection testing to ensure the comprehensiveness and accuracy of the test is a technical problem that urgently needs to be solved in this field. Summary of the invention

[0005] The present invention provides a memory testing method, device, equipment and storage medium, which can test each processor core and ensure load balancing of multiple processor cores.

[0006] The present invention provides a memory testing method, the method comprising: determining a target processor core from a plurality of processor cores of a memory, the target processor core being the processor core having the least number of completed error injection test commands among the plurality of processor cores, the error injection test command comprising at least one operation instruction and at least one error correction instruction, the operation instruction being used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction being used to instruct the processor core to correct errors in data in the memory; sending each operation instruction in a current error injection test command to the target processor core, and recording the execution response of the target processor core to each operation instruction; if the number of operation instructions sent is equal to the number of execution responses, and is equal to the total number of operation instructions in the current error injection test command, then increasing the number of completed error injection test commands of the target processor core; sending each error correction instruction in the current error injection test command to the target processor core, and saving the error correction result of each error correction instruction to obtain a test result.

[0007] According to a memory testing method provided by the present invention, determining a target processor core from multiple processor cores of a memory includes: reading numerical values ​​from memory addresses corresponding to multiple processor cores to obtain multiple count values; determining a target processor core based on the multiple count values, the target processor core being the processor core corresponding to the smallest count value among the multiple count values.

[0008] According to a memory testing method provided by the present invention, the error correction instruction is used to instruct the processor core to perform error correction on data of a storage unit corresponding to the operation instruction.

[0009] According to a memory testing method provided by the present invention, an error injection test command is generated according to test configuration information, wherein the test configuration information is used to configure the triggering frequency of error correction instructions, the ratio of error correction instructions to operation instructions, and the triggering conditions for randomly sending error correction instructions.

[0010] The present invention also provides a memory testing method, the method comprising: determining a target processor core from a plurality of processor cores of a memory, the target processor core being the processor core having the least number of completed error injection test commands among the plurality of processor cores, the error injection test command comprising at least one operation instruction and at least one error correction instruction, the operation instruction being used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction being used to instruct the processor core to correct errors in data in the memory; determining a target error injection test instruction, the target error injection test instruction being an error injection test instruction including an operation instruction of a specified type; sending each operation instruction in the target error injection test command to the target processor core, and recording an execution response of the target processor core to each operation instruction; if the number of operation instructions sent is equal to the number of execution responses, and is equal to the number of operation instructions in the target error injection test command, then increasing the number of completed error injection test commands of the target processor core; sending each error correction instruction in the target error injection test command to the target processor core, and saving the error correction result of each error correction instruction to obtain a test result.

[0011] According to a memory testing method provided by the present invention, multiple operation instructions in each injection error test instruction are of the same type, and the types of the operation instructions include: read operation, write operation, and erase operation.

[0012] The present invention also provides a memory testing device, the device comprising: a determination module, used to determine a target processor core from a plurality of processor cores of a memory, the target processor core being the processor core having the least number of completed error injection test commands among the plurality of processor cores, the error injection test command comprising at least one operation instruction and at least one error correction instruction, the operation instruction being used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction being used to instruct the processor core to correct errors in data in the memory; an operation instruction sending module, used to send each operation instruction in a current error injection test command to the target processor core, and record the execution response of the target processor core to each operation instruction; a counting module, used to increase the number of completed error injection test commands of the target processor core if the number of operation instructions sent is equal to the number of execution responses and is equal to the total number of operation instructions in the current error injection test command; an error correction instruction sending module, used to send each error correction instruction in the current error injection test command to the target processor core, and save the error correction result of each error correction instruction to obtain a test result.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above-mentioned memory testing methods when executing the computer program.

[0014] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the memory testing method described in any one of the above is implemented.

[0015] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned memory testing methods.

[0016] The memory testing method, apparatus, device and storage medium provided by the present invention select a processor core with the least number of completed error injection test commands from multiple processor cores for testing, and try to ensure that the error injection test commands executed by each processor core are the same, so as to implement testing of each processor core and ensure load balancing of multiple processor cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a flow chart of a memory testing method provided by the present invention.

[0019] Figure 2 It is a flow chart of another memory testing method provided by the present invention.

[0020] Figure 3 It is a schematic diagram of the flow of a single test provided by the present invention.

[0021] Figure 4 It is a schematic diagram of the flow of multiple combined tests provided by the present invention.

[0022] Figure 5 It is a structural schematic diagram of the memory testing device provided by the present invention.

[0023] Figure 6 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Solid State Drive (SSD) is a revolutionary storage technology that has played an important role in modern computing devices with its excellent performance and reliability. Compared with traditional mechanical hard disks, SSDs use a solid-state electronic storage chip array to provide faster data access speeds and higher durability. The core components of SSDs include a control unit and a storage unit, where the storage unit is mainly composed of Flash chips and DRAM chips. Among the many SSDs, flash-based SSDs are particularly common. Their internal structure is relatively simple, and the main components include a PCB board on which a control chip, a cache chip (not all low-end hard disks are equipped with this chip), and a flash memory chip for storing data are installed. At present, the storage medium used by most SSDs is NAND Flash, which is a non-volatile memory.

[0026] The physical structure of NAND Flash is based on floating gate transistors, which makes it highly stable when storing data. However, due to physical characteristics such as charge leakage and oxide layer aging, NAND Flash may be affected by drift effects, over-programming effects, read operation interference, and temperature during long-term use, resulting in data errors such as bit inversion. Common error handling technologies include soft decoding, hard decoding, ECC, XORE, CRC, etc.

[0027] In order to ensure that the NAND Flash controller can handle these potential errors correctly, module testing during the development phase is crucial. The traditional method of passively waiting for errors to occur is inefficient, so during the development process, active error injection is usually used to simulate error conditions to verify whether the controller's error handling process is effective.

[0028] However, as the performance of front-end ports continues to improve, the read and write speed of SSDs is also increasing. To adapt to this trend, NAND Flash controllers usually use a multi-core architecture to process data to achieve higher performance. Therefore, how to effectively plan and balance multi-core processing in injection error testing to ensure the comprehensiveness and accuracy of the test is an important technical challenge faced by technicians in this field.

[0029] In view of this, an embodiment of the present invention provides a memory testing method, which selects a processor core with the least number of completed error injection test commands from multiple processor cores for testing, and tries to ensure that the error injection test commands executed by each processor core are the same, thereby realizing testing of each processor core and ensuring load balancing of multiple processor cores.

[0030] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0031] Figure 1 The present invention provides a flow chart of a memory test method, which can be applied to electronic devices, which can be various types of devices with information processing capabilities during implementation. For example, the electronic device can include a personal computer, a laptop, a PDA or a server, etc.; the electronic device can also be a mobile terminal, for example, a mobile phone, a car computer, a tablet computer or a projector, etc. Figure 1 As shown, the method may include the following steps 110 to 140: Step 110: Determine a target processor core from multiple processor cores of the memory, the target processor core being the processor core that completes the least number of error injection test commands among the multiple processor cores, the error injection test command comprising at least one operation instruction and at least one error correction instruction, the operation instruction being used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction being used to instruct the processor core to correct errors in data in the memory.

[0032] The method of the present application is used to test a memory, and the memory may be an independent module or may be mounted in an electronic device. The memory may be a solid-state drive, a memory, or the like.

[0033] The memory includes a control unit and a storage unit. The storage unit refers to a medium for information storage such as Flash, DRAM, etc. The control unit is used to manage the storage medium to realize the reading and writing of information, and the control unit is a multi-core architecture. The multi-core architecture means that two or more complete computing engines (cores) are integrated in the control unit. In this application, the computing engine is referred to as a processor core.

[0034] For multiple processor cores of the control unit of the memory, determine the target processor core for this round of testing. The target processor core is the processor core with the least number of completed error injection test commands among the multiple processor cores. For example, if the number of completed error injection test commands of the multiple processor cores is 1, 0, and 0 respectively, then randomly select one from the processor cores corresponding to the two 0 values ​​as the target processor core.

[0035] In the present application, the error injection test command is a process for testing the data error correction capability of the processor core, and the error injection test command includes at least one operation instruction and at least one error correction instruction. The operation instruction is used to instruct the processor core to operate the storage unit in the memory. For example, the operation instruction can be a read operation, a write operation, an erase operation, etc. When the processor core performs an operation, due to the influence of the firmware code, potential, etc., it will affect the data in the memory, resulting in data errors. At this time, it is necessary to correct such errors when reading the data. The error correction instruction is used to instruct the processor core to simulate the situation of data errors and correct the erroneous data. For example, the memory is provided with an ECC function. In the processing of NandFlash, a dedicated ECC check method is used to correct single-bit errors and detect double-bit errors. When this function is configured, for each 64-bit RAM data write, the memory will also write 8-bit ECC, that is, ECC RAM space. If there is any write access less than 64 bits, the read-modify-write process will be executed: read 64 bits of data, modify the specified bytes, write back the new data and return the new ECC. When reading data, in addition to the user data at the access address, the corresponding ECC bit is also read out and checked and corrected for data errors.

[0036] The memory is provided with an ECC test function. When the function is started, the read data will be flipped by 1 or 2 bits, resulting in the read data not corresponding to the check value, and error correction will be performed. The error correction instruction can be the start instruction of the test function. After executing one or more operation instructions, the error correction instruction is sent to the processor core to simulate the data error and correct the error data.

[0037] In one embodiment of the present application, determining a target processor core from multiple processor cores in a memory includes: reading numerical values ​​from memory addresses corresponding to multiple processor cores to obtain multiple count values; determining a target processor core based on the multiple count values, the target processor core being the processor core corresponding to the smallest count value among the multiple count values.

[0038] Before the test starts, the system will initialize a memory address range as a counter for a processor core, and each processor core is set with a counter. The memory address is used to record the value of the error injection test command completed by the corresponding processor core.

[0039] Data is read from the memory address corresponding to each processor core, thereby obtaining a count value corresponding to each processor core.

[0040] All count values ​​are compared, a minimum count value among the multiple count values ​​is obtained, and the minimum count value is determined as the target processor core.

[0041] In the above embodiment, a method for determining a target processor core is provided, which can quickly determine a target processor core from multiple processor cores.

[0042] Step 120: Send each operation instruction in the current error injection test command to the target processor core, and record the execution response of the target processor core to each operation instruction.

[0043] Step 130: If the number of operation instructions sent and the number of execution responses are equal, then the number of completed error injection test commands of the target processor core is increased.

[0044] Each operation instruction in the current error injection test command is sent to the target processor core, and the target processor core will execute the received operation instruction.

[0045] The target processor core packages the execution status of the operation instruction into an execution response message and returns it to the test end.

[0046] Step 130: If the number of sent operation instructions is equal to the number of executed responses and is equal to the number of operation instructions in the target error injection test command, then the number of completed error injection test commands of the target processor core is increased.

[0047] Compare the number of sent operation instructions and the number of executed responses. If the two are equal, and the value is equal to the number of operation instructions in the target error injection test command, increase the number of completed error injection test commands of the target processor core by a preset value, such as 1. Step 140: Send each error correction instruction in the current error injection test command to the target processor core, and save the error correction result of each error correction instruction to obtain a test result.

[0048] The error correction instruction in the current error test command is injected into the processor core to simulate the data error situation and correct the error data. The error correction result of each error correction instruction is saved, and the test result of the memory error correction function is obtained according to the error correction result of each processor core.

[0049] In the above embodiment, a processor core with the least number of completed error injection test commands is selected from multiple processor cores for testing, and it is ensured as much as possible that the error injection test commands executed by each processor core are the same, so that each processor core can be tested and the load balance of multiple processor cores can be guaranteed.

[0050] In one embodiment of the present application, the error correction instruction is used to instruct the processor core to perform error correction on data in a storage unit corresponding to the operation instruction.

[0051] The error correction instruction is used to correct errors in the data in the storage unit after the processor core executes the operation instruction.

[0052] In the above embodiment, error correction is performed on the storage unit after the operation instruction is executed, simulating the scenario where data errors are most likely to occur, so that the error correction function can be tested more accurately.

[0053] In one embodiment of the present application, the method further includes: generating an error injection test command according to test configuration information, wherein the test configuration information is used to configure the triggering frequency of error correction instructions and the ratio of error correction instructions to operation instructions.

[0054] The frequency of error correction can also be controlled through pre-set configuration information, for example, error correction can be set to be performed every 10 seconds. By adjusting the number and frequency of error correction triggers, various possible error scenarios can be simulated to comprehensively evaluate the error handling capabilities of the control unit. Similarly, setting an error correction after executing every 30 operation instructions improves the pertinence and effectiveness of the test and ensures that the test is performed within the fault tolerance range of the hardware.

[0055] In one embodiment of the present application, during the period of sending each operation instruction in the current error injection test command to the target processor core, the error correction instruction in the current error injection test command is randomly sent to the target processor core.

[0056] The error correction instruction can also be triggered randomly. For example, using a pseudo-random number generation method to generate random numbers 30, 35, 70, and 80, error correction is performed after 30 operations are performed on the processor core, after 35 operations are performed, after 70 operations are performed, and after 80 operations are performed.

[0057] In the above embodiment, random error correction is performed to ensure the comprehensiveness and unpredictability of the test.

[0058] Figure 2 is another flow chart of the memory testing method provided by the present invention, such as Figure 2 As shown, the method may include the following steps 210 to 250: Step 210, determining a target processor core from multiple processor cores of the memory, wherein the target processor core is the processor core that completes the least number of error injection test commands among the multiple processor cores, wherein the error injection test command includes at least one operation instruction and at least one error correction instruction, wherein the operation instruction is used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction is used to instruct the processor core to correct errors in data in the memory.

[0059] For multiple processor cores of the control unit of the memory, a target processor core for testing in this round is determined from among them. The target processor core is the processor core with the least number of completed error injection test commands among the multiple processor cores.

[0060] Step 220 , determining a target error injection test instruction, wherein the target error injection test instruction is an error injection test instruction including different types of operation instructions.

[0061] In multiple combination tests, the system can generate multiple types of error injection test commands. The operation instructions in each error injection test command are a combination of multiple types of operation instructions. For example, the operation commands in an error injection test command include read, write, erase, etc. For every three reads, an erase will be executed and a write will be executed.

[0062] Determine the error injection test instruction used in this test and use it as the target error injection test instruction.

[0063] Step 230: Send each operation instruction in the target error injection test command to the target processor core, and record the execution response of the target processor core to each operation instruction.

[0064] Step 240: If the number of operation instructions sent is equal to the number of execution responses and is equal to the number of operation instructions in the target error injection test command, then the number of completed error injection test commands of the target processor core is increased.

[0065] Each operation instruction in the current error injection test command is sent to the target processor core, and the target processor core will execute the received operation instruction.

[0066] The target processor core packages the execution status of the operation instruction into an execution response message and returns it to the test end.

[0067] Step 250, sending each error correction instruction in the target error injection test command to the target processor core, and saving the error correction result of each error correction instruction to obtain a test result.

[0068] The error correction instruction in the current error test command is injected into the processor core to simulate the data error situation and correct the error data. The error correction result of each error correction instruction is saved, and the test result of the memory error correction function is obtained according to the error correction result of each processor core.

[0069] The following describes an exemplary application of an embodiment of the present invention in a practical application scenario. Figure 3 A schematic diagram of a single test flow provided by an embodiment of the present invention. Figure 3As shown, after the system starts testing, the counter will be initialized first. Before the test starts, the system will initialize a memory address range as a counter to record the number of completed error injection test commands of each processor core.

[0070] The system will intelligently sort the number of commands sent to the processor cores that have completed the previous command, select the core with the least number of commands, and determine it as the target processor core, ensuring that the next test command is always sent to the core with the least number of current commands sent.

[0071] During the test, the system will send the operation instructions in the error injection test command, such as read, write, erase, etc., to the target processor core in sequence. The sending and return status of the instructions will be monitored in real time. When the number of sends is the same as the number of returns, it means that the instruction is completed. If the number of sends is greater than the number of returns, it means that the instruction has not been completed. If the number of sends is the same as the number of returns, and is equal to the number of operation instructions in the error injection test command, it is determined that the error injection test command of the target processor core is completed, and the counter of the core is increased by 1.

[0072] The system will detect the counter status to determine whether the counter of the target processor core increases. If the counter does not increase, it means that the injection error test command is not completed.

[0073] If the injection error test command is completed, the number of commands sent to the processor cores is intelligently sorted, and the core with the least number of commands is selected and determined as the target processor core. This process will continue, selecting each processor core for testing in turn, until the test is manually stopped or the preset time or number limit is reached.

[0074] Figure 4 The flowchart of the combined test provided by the embodiment of the present invention is shown in FIG. Figure 4 As shown, after the system starts testing, it will first initialize the counter. In multiple combination tests, the system will also initialize the memory address range as a counter, and the counter is also used to record the number of completed error injection test commands of each processor core.

[0075] In multiple combination tests, the system can generate multiple types of error injection test commands. The operation instructions in each error injection test command are a combination of multiple types of operation instructions. For example, the operation commands in an error injection test command include read, write, erase, etc. For every three reads, an erase will be executed and a write will be executed.

[0076] During the test, the system will send the operation instructions in the error test command to the target processor core in sequence, and record the instruction sending and returning status of the read, write and erase operations respectively.

[0077] For a type of operation instruction, when the number of sends is the same as the number of returns, it means that the instruction is completed. If the number of sends is greater than the number of returns, it means that the instruction has not been completed.

[0078] When the sending number and returning number corresponding to all operation instruction types involved in the error injection test command are the same and equal to the number of operation instructions in the error injection test command, it is determined that the error injection test command of the target processor core is completed, and the counter of the core is increased by 1.

[0079] The system will check the counter in real time to determine whether the counter of the target processor core increases. If the counter does not increase, it means that the injection error test command has not been completed.

[0080] If the error injection test command is completed, the number of commands sent to the processor cores is intelligently sorted, and the core with the least number of commands is selected and determined as the target processor core. At the same time, the type of the next error injection test command is determined.

[0081] This process will continue, selecting each processor core for testing in turn, until the test is manually stopped or the preset time or number limit is reached.

[0082] The above memory test method can be applied to SSD to implement the multi-core error injection function test of NAND Flash controller in SSD software code. This method uses serial port commands to perform precise read, write and erase operations on NAND Flash, and injects errors through the returned data to simulate various potential error scenarios.

[0083] The above test process is carefully designed, covering the three key links of read error handling, write error handling and erase error handling. Testers can flexibly set test parameters according to different needs to implement single test or multiple combination tests. The error injection mechanism can be triggered at a fixed time or executed randomly to ensure the comprehensiveness and unpredictability of the test.

[0084] In the above test method, the error handling process of each core of NAND Flash can be accurately controlled through the test configuration information, which not only improves the pertinence and effectiveness of the test, but also ensures that the test is carried out within the fault tolerance range of the hardware. It allows the number and frequency of error triggers to be adjusted as needed in different test phases, thereby simulating various possible error scenarios and comprehensively evaluating the error handling capability of the SSD.

[0085] In this way, it is possible to deeply verify whether the hardware functions of the error handling module meet the design specifications and whether it can accurately identify, correct and recover data in real-world applications. The proactive and predictive nature of this testing method can identify and fix potential hardware problems early before the product is released.

[0086] In addition, the testing method of the present invention also has the ability to actively verify the firmware code. During the software development process, problems such as logical errors and memory leaks may cause system instability or even crash. Through error injection testing, these problems can be discovered at an early stage and repaired and optimized in a timely manner. This not only improves the quality and reliability of the software, but also reduces the cost and complexity of later maintenance.

[0087] Error injection testing can maintain strict control and continuous optimization of error handling capabilities throughout the entire life cycle of SSDs, from development to deployment. This approach not only improves product reliability and performance, but also provides users with a more stable and secure storage solution.

[0088] Based on the foregoing embodiments, an embodiment of the present invention provides a memory testing device, and each module included in the device and each unit included in each module can be implemented by a processor; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0089] The memory testing device provided by the present invention is described below. The memory testing device described below and the memory testing method described above can be referred to each other.

[0090] Figure 5 Schematic diagram of the structure of a memory test device provided by an embodiment of the present invention. Figure 5 As shown, the device 500 includes a determination module 510, an operation instruction sending module 520, a counting module 530 and an error correction instruction sending module 540, wherein: A determination module 510 is used to determine a target processor core from multiple processor cores of the memory, wherein the target processor core is a processor core that completes the least number of error injection test commands among the multiple processor cores, wherein the error injection test command includes at least one operation instruction and at least one error correction instruction, wherein the operation instruction is used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction is used to instruct the processor core to correct errors in data in the memory; An operation instruction sending module 520, used to send each operation instruction in the current error injection test command to the target processor core, and record the execution response of the target processor core to each operation instruction; A counting module 530, configured to increase the number of completed error injection test commands of the target processor core if the number of sent operation instructions is equal to the number of executed responses and is equal to the total number of operation instructions in the current error injection test command; The error correction instruction sending module 540 is used to send each error correction instruction in the current error injection test command to the target processor core, and save the error correction result of each error correction instruction to obtain a test result.

[0091] In some embodiments, the determination module 510 is specifically used to read numerical values ​​from memory addresses corresponding to multiple processor cores to obtain multiple count values; determine the target processor core based on the multiple count values, and the target processor core is the processor core corresponding to the smallest count value among the multiple count values.

[0092] In some embodiments, the error correction instruction is used to instruct the processor core to perform error correction on data in a storage unit corresponding to the operation instruction.

[0093] In some embodiments, the apparatus further comprises a generating module, wherein the generating module is used to generate an error injection test command according to test configuration information, wherein the test configuration information is used to configure a triggering frequency of error correction instructions and a ratio of error correction instructions to operation instructions.

[0094] In some embodiments, during the period of sending each operation instruction in the current error injection test command to the target processor core, the error correction instruction in the current error injection test command is randomly sent to the target processor core.

[0095] Figure 6 A schematic diagram of the physical structure of the electronic device provided by the present invention, such as Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630 and a communication bus 640, wherein the processor 610, the communication interface 620 and the memory 630 communicate with each other through the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute the memory test methods provided by the above methods.

[0096] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0097] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the memory testing methods provided by the above methods.

[0098] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0099] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the memory testing method provided by the above methods.

[0100] The above-mentioned computer-readable storage medium can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0101] Computer-readable signal media may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0102] The program code embodied on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wire, optical cable, radio frequency (RF), etc., or any suitable combination of the foregoing.

[0103] Computer program code for performing the operations of the present specification may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0104] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory testing method, characterized in that: The method comprises: Determine a target processor core from a plurality of processor cores in a memory, the target processor core being a processor core that completes the least number of error injection test commands among the plurality of processor cores, the error injection test command comprising at least one operation instruction and at least one error correction instruction, the operation instruction being used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction being used to instruct the processor core to correct errors in data in the memory; Sending each operation instruction in the current error injection test command to the target processor core, and recording the execution response of the target processor core to each operation instruction; If the number of operation instructions sent is equal to the number of execution responses and is equal to the total number of operation instructions in the current error injection test command, then the number of completed error injection test commands of the target processor core is increased; Each error correction instruction in the current error injection test command is sent to the target processor core, and the error correction result of each error correction instruction is saved to obtain a test result.

2. The method according to claim 1, characterized in that The step of determining a target processor core from a plurality of processor cores in the memory comprises: Read values ​​from memory addresses corresponding to multiple processor cores to obtain multiple count values; A target processor core is determined according to the multiple count values, where the target processor core is a processor core corresponding to a smallest count value among the multiple count values.

3. The method according to claim 1, characterized in that The error correction instruction is used to instruct the processor core to perform error correction on the data of the storage unit corresponding to the operation instruction.

4. The method according to claim 1, characterized in that: The method further comprises: generating an error injection test command according to test configuration information, wherein the test configuration information is used to configure the triggering frequency of error correction instructions and the ratio of error correction instructions to operation instructions.

5. The method according to claim 1, characterized in that: During the period of sending each operation instruction in the current error injection test command to the target processor core, the error correction instruction in the current error injection test command is randomly sent to the target processor core.

6. A memory testing method, characterized in that: The method comprises: Determine a target processor core from a plurality of processor cores in a memory, the target processor core being a processor core that completes the least number of error injection test commands among the plurality of processor cores, the error injection test command comprising at least one operation instruction and at least one error correction instruction, the operation instruction being used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction being used to instruct the processor core to correct errors in data in the memory; Determine a target error injection test instruction, wherein the target error injection test instruction is an error injection test instruction including different types of operation instructions; Sending each operation instruction in the target error injection test command to the target processor core, and recording the execution response of the target processor core to each operation instruction; If the number of operation instructions sent is equal to the number of execution responses and is equal to the number of operation instructions in the target error injection test command, then the number of completed error injection test commands of the target processor core is increased; Each error correction instruction in the target error injection test command is sent to the target processor core, and the error correction result of each error correction instruction is saved to obtain the test result.

7. A memory testing device, characterized in that: The device comprises: a determination module, configured to determine a target processor core from a plurality of processor cores of a memory, wherein the target processor core is a processor core that completes the least number of error injection test commands among the plurality of processor cores, wherein the error injection test command includes at least one operation instruction and at least one error correction instruction, wherein the operation instruction is used to instruct the processor core to operate a storage unit in the memory, and the error correction instruction is used to instruct the processor core to correct errors in data in the memory; An operation instruction sending module, used for sending each operation instruction in the current error injection test command to the target processor core, and recording the execution response of the target processor core to each operation instruction; A counting module, configured to increase the number of completed error injection test commands of the target processor core if the number of sent operation instructions is equal to the number of executed responses and is equal to the total number of operation instructions in the current error injection test command; The error correction instruction sending module is used to send each error correction instruction in the current error injection test command to the target processor core, and save the error correction result of each error correction instruction to obtain the test result.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the memory testing method according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the memory testing method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the memory testing method according to any one of claims 1 to 6 is implemented.

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