Three-dimensional integrated chip and preparation method thereof

Abstract

The invention discloses a three-dimensional integrated chip and a preparation method thereof, and relates to the technical field of semiconductor packaging. The preparation method comprises the following steps: preparing a plurality of first modules; performing inversion processing on each salient point of the plurality of first modules to perform chip mounting so as to prepare a plurality of second modules; sequentially carrying out plastic packaging treatment and wafer overturning on a second module, and carrying out semiconductor process treatment and inversion treatment on a glass substrate of the second module to prepare a third module; inversely arranging a first module on the third module, and sequentially carrying out semiconductor process treatment on the glass substrates in the first module to form a base module; and stacking the plurality of inverted second modules on the substrate module through inversion processing to prepare the three-dimensional integrated chip. The three-dimensional integrated chip prepared by the invention is low in manufacturing cost and simple in process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a three-dimensional integrated chip and a preparation method thereof. Background Art

[0002] With the continuous development of semiconductor technology, the packaging requirements of integrated circuits are becoming increasingly complex, especially in the field of three-dimensional integrated chips that need to improve integration, performance and reliability. Three-dimensional integrated chips can achieve higher bandwidth, lower latency and smaller package size by vertically stacking multiple chips, and are widely used in high-performance computing, memory, RF devices, communication equipment and other fields.

[0003] In the prior art, through-silicon via (TSV) is a vertical interconnection technology that penetrates silicon wafers or chips and is a key technology in the existing three-dimensional packaging technology. It has high requirements for etching equipment and process capabilities, and its manufacturing cost is high. In addition, the TSV equipment itself is expensive, which limits its large-scale application. In addition, although TSV technology is usually used to achieve multi-layer chip stacking, due to the thermal expansion coefficient of silicon of about 10x10 -6 / ℃, the thermal expansion coefficient of silicon dioxide is about 5x10 -6 / ℃, that is, under the same temperature change, the length change of silicon is twice that of silicon dioxide. The thermal stress generated by silicon via is large, which will affect the stacking quality of the chip. Summary of the invention

[0004] One object of the first aspect of the present invention is to provide a method for preparing a three-dimensional integrated chip to solve the technical problems in the prior art of high manufacturing cost, complex manufacturing process and low quality of stacked chips of three-dimensional integrated chips.

[0005] Another object of the first aspect of the present invention is to ensure the stability and reliability of the electrical connection between modules.

[0006] The second aspect of the present invention aims to provide a three-dimensional integrated chip prepared according to the above preparation method.

[0007] According to the purpose of the first aspect of the present invention, the present invention provides a method for preparing a three-dimensional integrated chip, comprising:

[0008] Prepare a plurality of first modules, wherein the first modules include a glass substrate, an oxide layer, and a silicon nitride layer stacked in sequence from bottom to top, and each of the first modules is provided with at least one bump located on the top of the silicon nitride layer;

[0009] Performing a flip chip process on each of the bumps of the plurality of the first modules for chip mounting to prepare a plurality of second modules;

[0010] Performing a plastic encapsulation process and a wafer flipping process on one of the second modules in sequence, and performing a semiconductor process process and the flip-chip process on the glass substrate of the second module, so as to mount a chip on the bumps of the glass substrate of the second module, thereby preparing a third module;

[0011] Inverting one of the first modules onto the third module so that the bumps of the first module are connected to the chip of the third module, and sequentially performing the semiconductor process on the glass substrate in the first module to form a base module;

[0012] At least one inverted second module is stacked on the base module through a flip-chip process, so that the chip of the second module at the bottom is connected to the bump of the first module of the base module. When there are multiple second modules, the chips and bumps between adjacent second modules are connected to prepare the three-dimensional integrated chip.

[0013] Optionally, after the step of stacking a plurality of inverted second modules on the base module by flip-chip processing, the method further comprises:

[0014] The plastic encapsulation process is performed on the base modules and the at least one inverted second module which are sequentially stacked.

[0015] Optionally, the semiconductor processing technology includes substrate opening, electroplating, chemical mechanical polishing and bump processing.

[0016] Optionally, the step of preparing a plurality of first modules comprises:

[0017] obtaining a preprocessed microstructure, the microstructure comprising at least one first through hole extending through the top of the glass substrate;

[0018] The microstructure is subjected to the electroplating treatment, the chemical mechanical polishing treatment and the bump treatment in sequence to prepare the first module.

[0019] Optionally, after the step of sequentially performing plastic encapsulation on the second modules, the step further includes:

[0020] The second module that has been subjected to the plastic encapsulation process is bonded to a support layer.

[0021] Optionally, the glass substrate further includes a second through hole, and a ratio of an intersection surface between the second through hole and the first through hole is any value in a range of 0.5-0.8.

[0022] Optionally, each of the electroplating processes further includes:

[0023] A barrier layer and a seed layer are sequentially deposited in the first through hole.

[0024] Optionally, the first through hole is arranged to penetrate the oxide layer and the silicon nitride layer and has a variable cross-section that gradually expands from bottom to top.

[0025] Optionally, the substrate is opened by sequentially performing photolithography and etching on the glass substrate.

[0026] According to the purpose of the second aspect of the present invention, the present invention also provides a three-dimensional integrated chip prepared according to any of the preparation methods described above.

[0027] The present invention uses a flip-chip process to mount a chip on the bump of the first module to form a second module with at least one chip formed on the surface, and sequentially performs a plastic encapsulation process and a wafer flipping process on the prepared second module to flip the glass substrate of the second module to face the bottom upward, and performs a semiconductor process and a flip-chip process on the glass substrate of the second module to form a third module with chips mounted on the surface of the glass substrate and the surface of silicon nitride, and inverts a first module on the third module so that the bump of the first module is connected to the chip of the third module, and sequentially performs a semiconductor process on the glass substrate of the first module to prepare a substrate The invention discloses a three-dimensional integrated chip, wherein the plurality of second modules are stacked on the base module through flip-chip processing, so that the chip of the second module at the bottom is connected to the bump of the first module of the base module, and the chips and bumps of adjacent second modules are connected to each other, so as to realize multi-layer chip stacking and electrical connection of the three-dimensional integrated chip. That is, the present invention realizes the preparation of the three-dimensional integrated chip with simple structure, low manufacturing cost and easy operation by utilizing the integration of semiconductor manufacturing technology and combining the glass substrate. Moreover, since the thermal expansion coefficient of the glass substrate itself is small, the thermal stress between each layer of the glass substrate and the chip in the three-dimensional integrated chip can be significantly reduced, thereby improving the chip stacking quality of the three-dimensional integrated chip.

[0028] Furthermore, the present invention can ensure the consistency of the plastic packaging by performing a plastic packaging process on the base module and the second module that are stacked in sequence, while providing external mechanical protection for the stacking structure formed by the entire base module and at least one second module, which helps to improve the overall structural strength of the three-dimensional integrated chip, prevent mechanical damage caused by external forces during subsequent processing or use, and ensure the stability and reliability of the electrical connection between the modules.

[0029] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0031] Figure 1 is a schematic flow chart of a method for preparing a three-dimensional integrated chip according to an embodiment of the present invention;

[0032] Figure 2 is a schematic structural diagram of a three-dimensional integrated chip according to an embodiment of the present invention;

[0033] Figure 3 is a schematic structural diagram of a third module according to an embodiment of the present invention;

[0034] Figure 4 is a schematic structural diagram of a second module according to an embodiment of the present invention;

[0035] Figure 5 is a schematic structural diagram of a first module according to an embodiment of the present invention;

[0036] Figure 6 is a schematic structural diagram of a base module according to an embodiment of the present invention;

[0037] Figure 7 The figure is a schematic structural overall flow chart of a method for preparing a three-dimensional integrated chip according to an embodiment of the present invention.

[0038] Reference numerals:

[0039] 100-three-dimensional integrated chip, 10-first module, 11-glass substrate, 111-second through hole, 12-oxide layer, 13-silicon nitride layer, 14-bump, 21-chip, 20-second module, 30-third module, 40-base module, 15-microstructure, 151-first through hole, 50-support layer. DETAILED DESCRIPTION

[0040] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0041] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It is to be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some structures related to the present application are shown in the accompanying drawings, rather than all structures. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0042] The terms "including" and "having" and any variations thereof in this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0043] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0044] Figure 1 is a schematic flow chart of a method for preparing a three-dimensional integrated chip according to an embodiment of the present invention, Figure 2 is a schematic structural diagram of a three-dimensional integrated chip according to an embodiment of the present invention, Figure 3 is a schematic structural diagram of a third module according to an embodiment of the present invention, Figure 4 is a schematic structural diagram of a second module according to an embodiment of the present invention, Figure 5 is a schematic structural diagram of a first module according to an embodiment of the present invention, Figure 6 is a schematic structural diagram of a base module according to an embodiment of the present invention, Figure 7 The figure is a schematic structural overall flow chart of a method for preparing a three-dimensional integrated chip according to an embodiment of the present invention.

[0045] like Figure 1 As shown, the present invention provides a method for preparing a three-dimensional integrated chip 100, comprising:

[0046] Step S100: preparing a plurality of first modules 10, wherein the first modules 10 include a glass substrate 11, an oxide layer 12, and a silicon nitride layer 13 stacked in sequence from bottom to top, and each first module 10 is provided with at least one bump 14 located on the top of the silicon nitride layer 13;

[0047] Step S200: performing a flip chip process on each bump 14 of the plurality of first modules 10 to mount a chip 21 to prepare a plurality of second modules 20;

[0048] Step S300: performing a plastic encapsulation process and a wafer flipping process on a second module 20 in sequence, and performing a semiconductor process process and a flip-chip process on the glass substrate 11 of the second module 20, so as to mount a chip 21 on the bumps 14 of the glass substrate 11 of the second module 20, thereby preparing a third module 30;

[0049] Step S400: placing a first module 10 upside down on the third module 30 so that the bumps 14 of the first module 10 are connected to the chip 21 of the third module 30, and sequentially performing semiconductor process on the glass substrate 11 in the first module 10 to form a base module 40;

[0050] Step S500: at least one inverted second module 20 is stacked on the base module 40 through a flip-chip process, so that the chip 21 of the bottom second module 20 is connected to the bump 14 of the first module 10 of the base module 40. When there are multiple second modules 20, the chips 21 and the bumps 14 of adjacent second modules 20 are connected to prepare a three-dimensional integrated chip 100.

[0051] like Figure 2 As shown, in this embodiment, a plurality of first modules 10 (see Figure 5 ), so that the first module 10 includes a glass substrate 11, an oxide layer 12 and a silicon nitride layer 13 stacked in sequence from bottom to top (refer to Figure 3 ), and each first module 10 is provided with at least one bump 14 located on the top of the silicon nitride layer 13, and then a flip chip process is performed on each bump 14 of the plurality of first modules 10 to mount the chip 21 on the bump 14 of the first module 10, and a plurality of second modules 20 are prepared (refer to Figure 4 ), a second module 20 is sequentially subjected to plastic encapsulation processing, a wafer flipping, and a glass substrate 11 of the second module 20 is subjected to semiconductor process processing and flip-chip processing, so as to mount a chip 21 on the bump 14 of the glass substrate 11 of the second module 20, and a third module 30 is prepared (refer to Figure 3 ), then a first module 10 is inverted on the third module 30, so that the bumps 14 of the first module 10 are connected to the chip 21 of the third module 30, and the glass substrate 11 in the first module 10 is sequentially processed by semiconductor process to form a base module 40 (refer to Figure 6), and finally, a plurality of inverted second modules 20 are stacked on the base module 40 by flip-chip processing, so that the chip 21 of the bottom second module 20 is connected to the bump 14 of the first module 10 of the base module 40, and the chip 21 and the bump 14 between adjacent second modules 20 are connected, so as to prepare a three-dimensional integrated chip 100 capable of stacking multiple layers of chips 21. Here, the number of bumps 14 of each first module 10 can be one, two or more, and the number of chips 21 of each second module 20 is the same as the number of bumps 14.

[0052] In this embodiment, a chip 21 is mounted on the bump 14 of the first module 10 by using a flip-chip process to form a second module 20 with at least one chip 21 formed on the surface, a second module 20 prepared is sequentially subjected to a plastic encapsulation process and a wafer flipping process to flip the glass substrate 11 of the second module 20 to face the bottom upward, a semiconductor process process and a flip-chip process are performed on the glass substrate 11 of the second module 20 to form a third module 30 with the chip 21 mounted on the surface of the glass substrate 11 and the silicon nitride surface, a first module 10 is inverted on the third module 30 so that the bump 14 of the first module 10 is connected to the chip 21 of the third module 30, and a semiconductor process process is performed on the glass substrate 11 of the first module 10 in sequence to prepare a base module 30. Block 40, multiple second modules 20 are stacked on the base module 40 through flip-chip processing, so that the chip 21 of the bottom second module 20 is connected to the bump 14 of the first module 10 of the base module 40, and the chip 21 and the bump 14 between adjacent second modules 20 are connected, so as to realize the stacking and electrical connection of multiple layers of chips 21 of the three-dimensional integrated chip 100, that is, the present invention realizes the preparation of the three-dimensional integrated chip 100 with simple structure, low manufacturing cost and easy operation by utilizing the integration of semiconductor manufacturing technology and combining glass substrate 11, and because the thermal expansion coefficient of the glass substrate 11 itself is small, it can significantly reduce the thermal stress between each layer of glass substrate 11 and chip 21 in the three-dimensional integrated chip 100, thereby improving the stacking quality of the chip 21 of the three-dimensional integrated chip 100.

[0053] In this embodiment, silicon oxide and silicon nitride are sequentially deposited on the surface of the glass substrate 11 to form an oxide layer 12 and a silicon nitride layer 13 on the surface of the glass substrate 11. Since the oxide layer 12 and the silicon nitride layer 13 are insulating media, leakage and crosstalk between devices can be reduced, that is, when the conductive layer formed by electroplating treatment between the chips 21 and 21 is electrically connected, the presence of the oxide layer 12 and the silicon nitride layer 13 can reduce leakage and signal crosstalk between devices, ensure the safety and stability of the electrical connection between the chips 21, and thus reduce power consumption. Here, the material of the oxide layer 12 can be silicon oxide, aluminum oxide or titanium oxide.

[0054] In a further embodiment, the semiconductor processing process includes substrate opening, electroplating, chemical mechanical polishing and bump processing, that is, a through hole is formed in the glass substrate 11 by using the substrate opening, a conductive layer is deposited in the through hole by using the electroplating, and the conductive layer and the glass substrate 11 are cut by using the chemical mechanical polishing to provide a flat surface for the bumps formed by the subsequent bump processing.

[0055] In this embodiment, the electroplating treatment method is an electrochemical plating process, that is, a conductive layer for electrical connection between the chips 21 is deposited on the glass substrate 11 or the oxide layer 12 and the silicon nitride layer 13 by electrochemical deposition. The material of the conductive layer can be copper or nickel, or other conductive metal materials.

[0056] In this embodiment, the electrochemically deposited conductive layer is polished to a preset thickness by chemical mechanical polishing to ensure the flatness of the top surface of the conductive layer and the silicon nitride layer 13, to ensure the uniformity and precision of the bumps 14 prepared by the bump 14 process, to improve the reliability of subsequent chip 21 mounting, and to prevent problems such as poor contact and signal interference caused by inconsistent height or position deviation of the bumps 14. In addition, chemical mechanical polishing makes the surface of the silicon nitride layer 13 flat, which helps to reduce stress and prevent cracks or failures caused by excessive stress during the packaging process.

[0057] In this embodiment, the second module 20 is plastic-sealed to seal the chip 21, bumps 14, and microstructure 15 in the second module 20 in plastic, which not only enhances the mechanical strength of the second module 20 and facilitates subsequent process processing, but also prevents thermal expansion from causing failure of the solder joints where the bumps 14 contact the chip 21, thereby further improving the structural stability of the three-dimensional integrated chip 100.

[0058] In this embodiment, glass material is used as the substrate. Since silicon dioxide is the main component of glass and the thermal conductivity of silicon dioxide is 0.27W / cm·K, the glass substrate 11 has strong thermal conductivity, so that the three-dimensional integrated chip 100 prepared after the above process has better heat dissipation performance.

[0059] In a further embodiment, after step S500, the following steps are further included:

[0060] The base modules 40 and at least one inverted second module 20 stacked in sequence are plastic-sealed.

[0061] In this embodiment, by performing a plastic encapsulation process on the sequentially stacked base module 40 and the second module 20, the consistency of the plastic encapsulation can be ensured, and external mechanical protection can be provided for the stacked structure formed by the entire base module 40 and at least one second module 20, which helps to improve the overall structural strength of the three-dimensional integrated chip 100 and prevent mechanical damage caused by external forces during subsequent processing or use. At the same time, the plastic encapsulation can fix the relative position between the base module 40 and the second module 20, ensuring that they will not be relatively displaced during subsequent processing and use, thereby ensuring the stability and reliability of the electrical connection between the modules.

[0062] In a further embodiment, the step of preparing a plurality of first modules 10 includes:

[0063] A pre-processed microstructure 15 is obtained, wherein the microstructure 15 includes at least one first through hole 151 penetrating the top of the glass substrate 11;

[0064] The microstructure 15 is subjected to electroplating treatment, chemical mechanical polishing treatment and bump treatment in sequence to prepare the first module 10 .

[0065] In this embodiment, a pre-treated microstructure 15 is first obtained, and an electroplating treatment is performed in the first through hole 151 of the microstructure 15 to form a conductive layer in the first through hole 151. The electroplated microstructure 15 is then chemically polished and bumped to form bumps 14 on the surface of the microstructure 15, thereby preparing a surface having bumps 14 corresponding to the first through hole 151, which is convenient for the subsequent formation of a second module 20 with a chip 21 mounted thereon.

[0066] In this embodiment, the preprocessing step includes:

[0067] An oxide layer 12 and a silicon nitride layer 13 are sequentially deposited on a glass substrate 11;

[0068] Photolithography and etching are sequentially performed on the surface of the silicon nitride layer 13 to form a first through hole 151 penetrating the oxide layer 12 and the silicon nitride layer 13 on the top of the glass substrate 11 .

[0069] In this embodiment, after the oxide layer 12 and the silicon nitride layer 13 are formed on the glass substrate 11 by a deposition process, the silicon nitride layer 13 is photolithographically processed, and then the silicon nitride layer 13 and the oxide layer 12 are etched to form a first through hole 151 in the silicon nitride layer 13 and the oxide layer 12 of the microstructure 15. Through the photolithography process and the etching process, the position and size of the through hole can be accurately controlled to ensure the selective etching of the silicon nitride layer 13 and the oxide layer 12, so as to facilitate the subsequent deposition of a conductive layer in the first through hole 151 by electroplating. The process is mature and easy to operate.

[0070] In a further embodiment, after the step of sequentially performing the plastic sealing process on the second module 20, the following step is further included:

[0071] The second module 20 and the support layer 50 that have been plastic-sealed are bonded.

[0072] In this embodiment, before the subsequent substrate opening, electroplating and chemical mechanical polishing are performed on the second module 20, the second module 20 after the plastic encapsulation needs to be bonded to temporarily fix the second module 20 after the plastic encapsulation on the support layer 50, provide mechanical support while maintaining the flatness of the wafer, ensure the accuracy of subsequent processes, avoid damage, warping or deformation of the wafer or chip 21 in the second module 20, and prevent affecting the performance of the final product.

[0073] In this embodiment, the plastic encapsulation process is an epoxy injection molding process, which can provide external mechanical support, prevent micro cracks from forming on the chip 21, and improve the electrical reliability of the package. In other embodiments, the plastic encapsulation process can also be replaced by glass encapsulation.

[0074] In a further embodiment, the glass substrate 11 further includes a second through hole 111, and the ratio of the intersection surface of the second through hole 111 and the first through hole 151 is any value in the range of 0.5-0.8, that is, the ratio of the second through hole 111 in the glass substrate 11 to the intersection surface of the first through hole 151 of the silicon nitride layer 13 and the oxide layer 12 can be 0.5, 0.6, 0.7 or 0.8, or any value in the range of 0.5-0.8. By setting the ratio of the second through hole 111 to the first through hole 151 within the above range, the alignment connection of the first through hole 151 and the second through hole 111 is ensured, thereby ensuring that the conductive layer after the electroplating treatment is electrically connected, and ensuring that the signal transmission is not disturbed.

[0075] In a further embodiment, each electroplating process further includes:

[0076] A barrier layer and a seed layer are sequentially deposited in the first through hole 151 .

[0077] In this embodiment, before the electroplating process, a barrier layer and a seed layer are first deposited in the first through hole 151, and then a conductive layer is deposited on the surface of the seed layer to ensure the reliability of the electroplating process, improve the quality of metal deposition, and enhance the electrical performance between the chips 21 of each layer in the final three-dimensional integrated chip 100.

[0078] In a further embodiment, the first through hole 151 is configured to penetrate the oxide layer 12 and the silicon nitride layer 13 and have a variable cross-section that gradually expands from bottom to top. The variable cross-section setting makes the upper cross-section of the first through hole 151 wider, and the metal can enter and fill the entire first through hole 151 more smoothly, thereby improving the filling uniformity and reducing the defect rate. It can prevent the top of the straight cylindrical through hole from being closed prematurely during the electroplating deposition process, and prevent the incomplete filling inside the through hole from causing gaps or cracks.

[0079] In a further embodiment, the substrate is opened by sequentially performing photolithography and etching on the glass substrate 11. The photolithography process and the etching process can achieve high-precision micro-hole processing, meet the needs of high-density interconnection, improve the mechanical stability of the glass substrate 11, reduce cracks and stress concentration, and facilitate subsequent electroplating of the first through hole 151 or the second through hole 111, thereby ensuring the structural mechanical stability of the three-dimensional integrated chip 100.

[0080] like Figure 2 As shown, the present invention also provides a three-dimensional integrated chip 100 prepared according to the above preparation method. The three-dimensional integrated chip 100 includes a base module 40 and at least one second module 20 stacked from bottom to top, and the base module 40 and the second module 20, and the plurality of second modules 20 are connected to the bumps 14 through the chip 21. The preparation method of the three-dimensional integrated chip 100 will not be described here one by one.

[0081] In this embodiment, bumps 14 corresponding to the chips 21 in the second module 20 are formed on the surface of the glass substrate 11 on the top of the base module 40, so that the second module 20 is connected to the base module 40 through the connection between the chip 21 and the bumps 14, thereby realizing three-dimensional stacking of multiple chips 21 by utilizing semiconductor manufacturing technology, thereby reducing manufacturing difficulty and production cost.

[0082] In this embodiment, in each three-dimensional integrated chip 100, the number of the second modules 20 can be one, two or more, and the number of the second modules 20 can be selected according to actual production needs. When the number of the second module 20 in each three-dimensional integrated chip 100 is one, the stacking of three-layer chips 21 is realized in the three-dimensional integrated chip 100, that is, in the three-dimensional integrated chip 100 at this time, the three-layer chips 21 are stacked sequentially from bottom to top and the electrical connection between the three-layer chips 21 is realized through the electroplated conductive layer in the first through hole 151 of the microstructure 15 and the second through hole 111 of the glass substrate 11 in the base module 40, thereby realizing the stacking of the three-layer chips 21.

[0083] In this embodiment, when the number of second modules 20 in each three-dimensional integrated chip 100 is two, the two second modules 20 are stacked on the base module 40, and the chip 21 of the second module 20 far away from the base module 40 is connected to the bump 14 of the second module 20 close to the base module 40 through a flip-chip process to achieve electrical connection between the two second modules 20. The chip 21 of the second module 20 close to the base module 40 is connected to the bump 14 on the top of the base module 40 through a flip-chip process to achieve electrical connection between the second module 20 and the base module 40, thereby achieving stacking of four layers of chips 21.

[0084] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a three-dimensional integrated chip, characterized in that: include: Prepare a plurality of first modules, wherein the first modules include a glass substrate, an oxide layer, and a silicon nitride layer stacked in sequence from bottom to top, and each of the first modules is provided with at least one bump located on the top of the silicon nitride layer; Performing a flip chip process on each of the bumps of the plurality of the first modules for chip mounting to prepare a plurality of second modules; Performing a plastic encapsulation process and a wafer flipping process on one of the second modules in sequence, and performing a semiconductor process process and the flip-chip process on the glass substrate of the second module, so as to mount a chip on the bumps of the glass substrate of the second module, thereby preparing a third module; Inverting one of the first modules onto the third module so that the bumps of the first module are connected to the chip of the third module, and sequentially performing the semiconductor process on the glass substrate in the first module to form a base module; At least one inverted second module is stacked on the base module through a flip-chip process, so that the chip of the second module at the bottom is connected to the bump of the first module of the base module. When there are multiple second modules, the chips and bumps between adjacent second modules are connected to prepare the three-dimensional integrated chip.

2. The preparation method according to claim 1, characterized in that: After the step of stacking at least one inverted second module on the base module by flip-chip processing, the method further comprises: The plastic encapsulation process is performed on the base modules and the at least one inverted second module which are sequentially stacked.

3. The preparation method according to claim 2, characterized in that: The semiconductor processing technology includes substrate opening, electroplating, chemical mechanical polishing and bump processing.

4. The preparation method according to claim 3, characterized in that: The step of preparing a plurality of first modules comprises: obtaining a preprocessed microstructure, the microstructure comprising at least one first through hole extending through the top of the glass substrate; The microstructure is subjected to the electroplating treatment, the chemical mechanical polishing treatment and the bump treatment in sequence to prepare the first module.

5. The preparation method according to claim 4, characterized in that: After the step of sequentially performing plastic encapsulation on the second module, the following step further comprises: The second module that has been subjected to the plastic encapsulation process is bonded to a support layer.

6. The preparation method according to claim 5, characterized in that: The glass substrate further includes a second through hole, and a ratio of an intersection surface between the second through hole and the first through hole is any value in a range of 0.5-0.

8.

7. The preparation method according to claim 6, characterized in that: Each of the electroplating processes also includes: A barrier layer and a seed layer are sequentially deposited in the first through hole.

8. The preparation method according to claim 7, characterized in that: The first through hole is arranged to penetrate the oxide layer and the silicon nitride layer and has a variable cross-section that gradually expands from bottom to top.

9. The preparation method according to any one of claims 1 to 8, characterized in that: The substrate is opened by sequentially performing photolithography and etching on the glass substrate.

10. A three-dimensional integrated chip prepared by the preparation method according to any one of claims 1 to 9.

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