Integrated circuit packaging structure and packaging method

Abstract

The invention discloses an integrated circuit packaging structure and a packaging method, and belongs to the technical field of integrated circuit packaging. The packaging structure comprises a wafer, a metal contact and a circuit structure, the metal contact is arranged above the circuit structure, the wafer and the circuit structure are packaged through a plastic packaging material, the metal contact is exposed from the upper portion of the plastic packaging material, and the circuit structure comprises a PI layer, an RDL layer and a UBM layer. A substrate is additionally arranged on a traditional packaging structure to serve as a middle layer, so that the whole packaging structure is more complex, and more equipment and materials are needed, compared with traditional packaging, the steps of grinding and laser drilling are added, but compared with the mode that the substrate is additionally arranged on the traditional packaging structure to serve as the middle layer, needed equipment and materials are few, and cost is low. The method has an obvious cost advantage.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit packaging, and in particular relates to an integrated circuit packaging structure and a packaging method. Background Art

[0002] At present, FCBGA (flip chip ball grid array) products are generally encapsulated together with the substrate during the packaging process. After the plastic encapsulation is completed, the substrate will expose the IO pins or pads, and then the ballmount operation will be performed. However, before the ballmount, the tedious process of flux printing is required. This series of process flows is not only complex, involving fine operations and strict control of multiple links, but also requires a large number of different types of professional equipment to complete each step.

[0003] For example, the plastic sealing process requires high-precision plastic sealing equipment to ensure the quality of the plastic sealing, the flux printing requires professional printing equipment to ensure the uniform application of the flux, and the ball mount requires advanced mounting equipment to achieve the precise installation of the solder balls. The purchase, maintenance and operation of each type of equipment requires a lot of capital and manpower costs. At the same time, this traditional packaging method also has obvious problems in the use of materials. In addition to the materials required for the chip itself, substrates and a large number of solder balls are also used, which undoubtedly further increases the material cost. Moreover, the quality and performance of the substrate and solder balls will also affect the quality and stability of the final product. Once quality problems occur, additional testing and maintenance work is required, which increases production costs and time costs. Summary of the invention

[0004] In view of the above situation, in order to overcome the defects of the prior art, the present invention has additional grinding and laser drilling steps compared to traditional packaging, but requires less equipment and materials, and has obvious cost advantages.

[0005] In order to achieve the above object, the following technical solution is adopted: The present invention provides an integrated circuit packaging method, comprising the following steps:

[0006] preparing integrated circuit wafers to be packaged;

[0007] Using a temporary bonding carrier, bonding the wafer to the temporary bonding carrier;

[0008] Plastic-sealing the wafer and the temporary bonding carrier by using a plastic-sealing material;

[0009] Separating the packaged product from the temporary bonding carrier;

[0010] Use grinding to remove excess plastic packaging;

[0011] Drill holes through laser drilling to expose the metal;

[0012] Print flux and perform reflow operation;

[0013] The integrated circuit packaging structure is obtained.

[0014] Furthermore, in one embodiment of the present invention, the temporary bonding carrier includes a glass carrier and a UV film attached to the glass carrier; the method for separating the packaged product and the temporary bonding carrier includes: making the UV film lose its stickiness by irradiating it with light, thereby separating the packaged product and the temporary bonding carrier.

[0015] Furthermore, in another embodiment of the present invention, the temporary bonding carrier comprises a steel plate and a pyrolytic film attached to the steel plate; the method for separating the packaged product and the temporary bonding carrier comprises: making the pyrolytic film lose its stickiness by high-temperature baking, thereby separating the packaged product and the temporary bonding carrier.

[0016] The present invention also provides an integrated circuit packaging structure, comprising a chip, a metal contact and a circuit structure, wherein the metal contact is arranged above the circuit structure, the chip and the circuit structure are encapsulated by a plastic encapsulation material, and the metal contact is exposed from above the plastic encapsulation material, and the circuit structure comprises a PI layer, an RDL layer and a UBM layer.

[0017] Furthermore, the plastic package body is a solder ball or a copper column plus a solder ball.

[0018] Furthermore, the height of the solder ball exposed above the plastic packaging material is 30-50 μm.

[0019] The beneficial effects of the present invention are as follows: the traditional packaging structure adds a substrate as an intermediate layer, which not only makes the entire packaging structure more complicated, but also requires the use of more equipment and materials. Compared with the traditional packaging, the present invention has additional grinding and laser drilling steps, but compared with the traditional packaging that adds a substrate as an intermediate layer, the present invention requires less equipment and materials and has obvious cost advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a step of attaching a wafer to a temporary bonding carrier in an integrated circuit packaging method of the present invention;

[0021] Figure 2 It is a schematic diagram of a step of encapsulating a wafer and a temporary bonding carrier by means of a plastic encapsulation material in an integrated circuit packaging method of the present invention;

[0022] Figure 3 It is a schematic diagram of a step of separating a packaged product and a temporary bonding carrier in an integrated circuit packaging method of the present invention;

[0023] Figure 4A schematic diagram of a grinding step in an integrated circuit packaging method of the present invention;

[0024] Figure 5 A schematic diagram of a laser drilling step in an integrated circuit packaging method of the present invention;

[0025] Figure 6 A schematic diagram of a reflow soldering step in an integrated circuit packaging method of the present invention;

[0026] Figure 7 The figure is a schematic structural diagram of an integrated circuit packaging structure of the present invention.

[0027] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0028] Legend:

[0029] 1. Wafer; 2. Metal contact; 3. Circuit structure; 31. PI layer; 32. RDL layer; 33. UBM layer; 4. Plastic packaging material; 5. Glass carrier / steel plate; 6. UV film / pyrolytic film. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] Unless otherwise defined, all professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to those described herein may be applied to the present invention. The preferred implementation methods and materials described herein are for demonstration purposes only and are not intended to limit the content of this application.

[0032] The experimental methods in the following examples are conventional methods unless otherwise specified, and the experimental materials used in the following examples are purchased from commercial channels unless otherwise specified.

[0033] Example 1

[0034] Reference Figure 1-7 , an embodiment of the present invention provides: an integrated circuit packaging method, comprising the following steps:

[0035] Preparing an integrated circuit chip 1 to be packaged;

[0036] like Figure 1As shown, a temporary bonding carrier is used to bond the wafer to the temporary bonding carrier. In this embodiment, the temporary bonding carrier includes a glass carrier 5 and a UV film pre-bonded on the glass carrier 6;

[0037] like Figure 2 As shown, the wafer 1 and the temporary bonding carrier are sealed by a sealing material 4;

[0038] like Figure 3 As shown, in this embodiment, the UV film loses its stickiness by irradiating light, thereby separating the packaged product and the temporary bonding carrier;

[0039] like Figure 4 As shown, the excess plastic package is removed by grinding;

[0040] like Figure 5 As shown, holes are drilled by laser drilling to expose metal contacts 2, which may be solder balls or copper pillars plus solder balls;

[0041] like Figure 6 As shown, solder flux is printed and reflow soldering is performed to shape the solder ball and grow the required solder ball height. The height of the solder ball exposed from the top of the plastic packaging material 4 is: 30 microns to 50 microns;

[0042] like Figure 7 As shown, the integrated circuit packaging structure is obtained.

[0043] Example 2

[0044] Reference Figure 1-7 , an embodiment of the present invention provides: an integrated circuit packaging method, comprising the following steps:

[0045] Preparing an integrated circuit chip 1 to be packaged;

[0046] like Figure 1 As shown, a temporary bonding carrier is used to bond the wafer 1 onto the temporary bonding carrier. In this embodiment, the temporary bonding carrier includes a steel plate 5 and a pyrolytic film 6 attached to the steel plate.

[0047] like Figure 2 As shown, the wafer 1 and the temporary bonding carrier are sealed by a sealing material 4;

[0048] like Figure 3 As shown, in this embodiment, the pyrolysis film loses its viscosity by high-temperature baking, thereby separating the packaged product and the temporary bonding carrier;

[0049] like Figure 4 As shown, the excess plastic package is removed by grinding;

[0050] like Figure 5As shown, holes are drilled by laser drilling to expose metal contacts 2, which may be solder balls or copper pillars plus solder balls;

[0051] like Figure 6 As shown, solder flux is printed and reflow soldering is performed to shape the solder ball and grow the required solder ball height. The height of the solder ball exposed from the top of the plastic packaging material 4 is: 30 microns to 50 microns;

[0052] like Figure 7 As shown, the integrated circuit packaging structure is obtained.

[0053] Example 3

[0054] Reference Figure 7 The present invention provides an integrated circuit packaging structure. The structure is mainly composed of a chip 1, a metal contact 2, a circuit structure 3 and a plastic packaging material 4 wrapped around them. The circuit structure 3 includes a PI layer 31, an RDL layer 32 and a UBM layer 33.

[0055] In the actual manufacturing process, firstly, a wafer 1 with a size of 1.34×1.3 mm is placed on a suitable workbench. As the core component of the integrated circuit, the wafer 1 carries many electronic components and complex circuit connections, and its performance plays a decisive role in the function of the entire integrated circuit.

[0056] Then, the circuit structure 3 is constructed. The PI layer 31, the RDL layer 32 and the UBM layer 33 are formed on the wafer 1 in sequence. The PI layer 31 has the dual functions of insulation and support. The total thickness of the PI layer 31 and the wafer 1 can be, for example, 200μm. This size is obtained after a large number of experiments and precise calculations to ensure that the entire structure has good stability and performance. The RDL layer 32 undertakes the key task of rewiring. It cleverly guides the circuit connection inside the wafer 1 to the appropriate position, thereby achieving electrical connection with the outside. The UBM layer 33 acts as a metallization transition layer, which can significantly enhance the reliability of connection with other components.

[0057] After completing the construction of the circuit structure 3, the installation of the metal contact 2 begins. The metal contact 2 can be flexibly selected as a solder ball or a copper column plus a solder ball according to actual needs. Finally, the entire structure is encapsulated using a plastic encapsulation material 4. During the encapsulation process, the distance between the top of the PI layer 31 and the top of the plastic encapsulation material 4 can be, for example, 110 μm, while ensuring that the distance between the bottom of the chip 1 and the bottom of the plastic encapsulation material 4 can be, for example, 50 μm. In some embodiments, the thickness of the plastic encapsulation material 4 is: 0.25 to 0.55 mm. In some embodiments, the thickness of the plastic encapsulation material 4 is: 0.45 mm, so as to ensure that the size of the packaged structure fully meets the design requirements, and finally form an integrated circuit packaging structure with a size of 1.5×1.5 mm.

[0058] When the integrated circuit packaging structure is put into use, under working conditions, the signal or current on the chip 1 is first transmitted to the RDL layer 32 of the circuit structure 3 via the circuit inside the chip 1. The RDL layer 32 guides the signal or current to the UBM layer 33 according to the pre-designed wiring rules. The UBM layer 33 serves as a key node of the connection and stably transmits the signal or current to the metal contact 2.

[0059] If the metal contact 2 is a solder ball, the solder ball can conduct signals or currents well and realize connection with an external circuit. When the metal contact 2 is in the form of a copper column plus a solder ball, the copper column can quickly transmit the signal or current to the solder ball by virtue of its excellent conductive performance, and then the solder ball establishes an electrical connection with the external circuit. The plastic encapsulation material 4 can not only protect the internal structure of the chip from the influence of the external environment, but also ensure that the entire packaging structure has good mechanical stability, ensuring that under various complex working conditions, the signal or current can be stably transmitted in the packaging structure, thereby ensuring the normal operation of the integrated circuit.

[0060] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0061] The present invention and its implementation methods are described above, which is not restrictive. The drawings are only one of the implementation methods of the present invention, and the actual application is not limited thereto. In short, if ordinary technicians in the field are inspired by it and design methods and embodiments similar to the technical solution without creativity without departing from the purpose of the invention, they should all fall within the protection scope of the present invention.

Claims

1. A packaging method for an integrated circuit packaging structure, characterized in that: The following steps are involved: preparing integrated circuit wafers to be packaged; Using a temporary bonding carrier, bonding the wafer to the temporary bonding carrier; Plastic-sealing the wafer and the temporary bonding carrier by using a plastic-sealing material; Separating the packaged product from the temporary bonding carrier; Use grinding to remove excess plastic packaging; Drill holes through laser drilling to expose the metal; Print flux and perform reflow operation; The integrated circuit packaging structure is obtained.

2. The packaging method of an integrated circuit packaging structure according to claim 1, characterized in that: The temporary bonding carrier comprises a glass carrier and a UV film attached to the glass carrier.

3. The packaging method of an integrated circuit packaging structure according to claim 1, characterized in that: The temporary bonding carrier comprises a steel plate and a pyrolysis film attached to the steel plate.

4. The packaging method of an integrated circuit packaging structure according to claim 2, characterized in that: The method for separating the packaged product from the temporary bonding carrier comprises: irradiating light to make the UV film lose its stickiness, thereby separating the packaged product from the temporary bonding carrier.

5. The packaging method of an integrated circuit packaging structure according to claim 3, characterized in that: The method for separating the packaged product from the temporary bonding carrier comprises: making the pyrolysis film lose its stickiness by high-temperature baking, thereby separating the packaged product from the temporary bonding carrier.

6. The packaging structure obtained by the integrated circuit packaging method according to any one of claims 1 to 5, characterized in that: The invention comprises a chip (1), a metal contact (2) and a circuit structure (3), wherein the metal contact (2) is arranged above the circuit structure (3), the chip (1) and the circuit structure (3) are encapsulated by a plastic encapsulation material (4), and the metal contact (2) is exposed from above the plastic encapsulation material (4).

7. The integrated circuit packaging structure according to claim 6, characterized in that: The circuit structure (3) comprises a PI layer (31), an RDL layer (32) and a UBM layer (33).

8. The integrated circuit packaging structure according to claim 7, characterized in that: The metal contact (2) is a tin ball or a copper column plus a tin ball.

9. The integrated circuit packaging structure according to claim 8, characterized in that: The solder balls or the copper pillars plus solder balls are located above the UBM layer (33).

10. The integrated circuit packaging structure according to claim 8, characterized in that: The height of the solder ball exposed above the plastic packaging material (4) is 30-50 μm.

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