Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, the packaging structure comprises a first chip structure, the first chip structure comprises a first functional layer and a second functional layer which are stacked and bonded, the first functional layer is located on a first carrier plate and is electrically connected with the first carrier plate, the second functional layer is electrically connected with the first functional layer, one of the first functional layer and the second functional layer is a power supply layer, and the other is a second chip structure; the other layer is a signal layer; the first interconnection structure at the side part of the first chip structure is electrically connected with the first functional layer through the first carrier plate, and the first interconnection structure at the top of the second functional layer is electrically connected with the second functional layer; the power supply layer and the signal layer are stacked, so that the integration level is improved; moreover, through a first interconnection structure at the side part of the first chip structure and a first interconnection structure at the top of the second functional layer, a power supply circuit of the power supply layer can be separated from a signal transmission circuit of the signal layer, and the interference of the power supply circuit of the power supply layer on signals in the signal layer is effectively reduced, so that the overall voltage and power consumption of the packaging structure are reduced, and the reliability of the packaging structure is improved. Therefore, the efficiency of the packaging structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of packaging technology, and in particular to a packaging structure and a packaging method. Background Art

[0002] With the continuous evolution of semiconductor technology, in order to improve logic density and performance, the chip architecture and circuit design will also undergo major adjustments. Advanced packaging technology has gradually become one of the key factors in promoting chip performance improvement.

[0003] In traditional advanced packaging, the power layer and the signal layer are usually located on the same side of the substrate, that is, the signal transmission circuit of the signal layer and the power supply circuit of the power layer exist on the front side of the chip at the same time, and the signal transmission circuit and the power supply circuit share the space on the front side of the chip.

[0004] However, as the complexity and integration requirements of packaging structures continue to increase, the interference of power supply circuits on signals in the signal layer has attracted more and more attention. This interference can cause logic errors and may ultimately increase the overall voltage and power consumption of the packaging structure. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are beneficial to reducing the voltage and power consumption of the entire packaging structure.

[0006] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a first carrier board, the first carrier board having a first circuit; a first chip structure, including a first functional layer located on the first carrier board, and a second functional layer bonded to the first functional layer, the first functional layer is electrically connected to the first carrier board, the second functional layer is electrically connected to the first functional layer, one of the first functional layer and the second functional layer is a power layer, and the other is a signal layer; a first interconnection structure, respectively located on the first carrier board at the side of the first chip structure, and on the top of the second functional layer facing away from the first functional layer, the first interconnection structure at the side of the first chip structure is electrically connected to the first functional layer through the first circuit, and the first interconnection structure on the top of the second functional layer is electrically connected to the second functional layer.

[0007] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a first carrier board, the first carrier board having a first circuit; arranging a first chip structure on the first carrier board, the first chip structure including a first functional layer located on the first carrier board, and a second functional layer bonded to the first functional layer, the first functional layer is electrically connected to the first carrier board, the second functional layer is electrically connected to the first functional layer, one of the first functional layer and the second functional layer is a power supply layer, and the other is a signal layer; forming a first interconnection structure on the first carrier board at the side of the first chip structure and on the top of the second functional layer facing away from the first functional layer, the first interconnection structure at the side of the first chip structure is electrically connected to the first functional layer through the first circuit, and the first interconnection structure on the top of the second functional layer is electrically connected to the second functional layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a packaging structure, comprising: a first carrier having a first circuit; a first chip structure, comprising a first functional layer located on the first carrier, and a second functional layer bonded to the first functional layer, the first functional layer being electrically connected to the first carrier, the second functional layer being electrically connected to the first functional layer, one of the first functional layer and the second functional layer being a power layer, and the other being a signal layer; a first interconnection structure located on the first carrier at a side of the first chip structure, and on a top of the second functional layer facing away from the first functional layer, the first interconnection structure at the side of the first chip structure being electrically connected to the first functional layer through a first circuit, and the first interconnection structure at the top of the second functional layer being electrically connected to the first functional layer through a first circuit. The interconnection structure is electrically connected to the second functional layer; in the present embodiment, the power layer and the signal layer in the first chip structure are stacked, which is beneficial to improving the integration of the first chip structure and reducing the space occupied by the first chip structure in the packaging structure; in addition, the first interconnection structure on the side of the first chip structure is electrically connected to the first functional layer through the first carrier board, and the first interconnection structure on the top of the second functional layer is electrically connected to the second functional layer. Therefore, the power supply circuit of the power layer and the signal transmission circuit of the signal layer can be separated, effectively reducing the interference of the power supply circuit of the power layer on the signal in the signal layer, thereby reducing the overall voltage and power consumption of the packaging structure, thereby improving the performance of the packaging structure.

[0010] The embodiment of the present invention also provides a packaging method, wherein a first chip structure is arranged on a first carrier having a first circuit, the first chip structure includes a first functional layer located on the first carrier, and a second functional layer bonded to the first functional layer, the first functional layer is electrically connected to the first carrier, the second functional layer is electrically connected to the first functional layer, one of the first functional layer and the second functional layer is a power layer, and the other is a signal layer; a first interconnection structure is formed on the first carrier at a side of the first chip structure, and on a top of the second functional layer facing away from the first functional layer, the first interconnection structure at the side of the first chip structure is electrically connected to the first functional layer through the first circuit, and the top of the second functional layer is electrically connected to the first functional layer. The first interconnection structure at the bottom is electrically connected to the second functional layer; in this embodiment, the power layer and the signal layer in the first chip structure are stacked, which is beneficial to improving the integration of the first chip structure and reducing the space occupied by the first chip structure in the packaging structure; in addition, the first interconnection structure at the side of the first chip structure is electrically connected to the first functional layer through the first carrier board, and the first interconnection structure on the top of the second functional layer is electrically connected to the second functional layer. Therefore, the power supply circuit of the power supply layer and the signal transmission circuit of the signal layer can be separated, which effectively reduces the interference of the power supply circuit of the power supply layer on the signal in the signal layer, thereby reducing the overall voltage and power consumption of the packaging structure, thereby improving the performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic structural diagram of a first embodiment of a packaging structure of the present invention;

[0012] Figure 2 is a structural schematic diagram of a second embodiment of a packaging structure of the present invention;

[0013] Figures 3 to 9 is a schematic structural diagram corresponding to each step in the first embodiment of the packaging method of the present invention;

[0014] Fig.10 It is a structural schematic diagram corresponding to some steps in the second embodiment of the packaging method of the present invention. DETAILED DESCRIPTION

[0015] As known from the background art, the overall voltage and power consumption of the packaging structure need to be reduced.

[0016] In chip manufacturing and advanced packaging, there are usually signal transmission circuits of the signal layer and power supply circuits of the power layer on the front side of the chip. The signal transmission circuit and the power supply circuit share the space on the front side of the chip, making it difficult to further reduce the volume of the packaging structure. In addition, since the signal transmission circuit of the signal layer and the power supply circuit of the power layer are located on the front side of the chip at the same time, the power supply circuit interferes with the signal in the signal layer, thereby increasing the overall voltage and power consumption of the packaging structure.

[0017] In order to solve the technical problem, the packaging structure provided by the embodiment of the present invention includes: a first carrier board, the first carrier board has a first circuit; a first chip structure, including a first functional layer located on the first carrier board, and a second functional layer bonded to the first functional layer, the first functional layer is electrically connected to the first carrier board, the second functional layer is electrically connected to the first functional layer, one of the first functional layer and the second functional layer is a power layer, and the other is a signal layer; a first interconnection structure, respectively located on the first carrier board at the side of the first chip structure, and the top of the second functional layer facing away from the first functional layer, the first interconnection structure at the side of the first chip structure is electrically connected to the first functional layer through the first circuit, and the first interconnection structure at the top of the second functional layer is electrically connected to the second functional layer.

[0018] In the scheme disclosed in the embodiment of the present invention, the power layer and the signal layer in the first chip structure are stacked, which is beneficial to improving the integration of the first chip structure and reducing the space occupied by the first chip structure in the packaging structure; in addition, the first interconnection structure on the side of the first chip structure is electrically connected to the first functional layer through the first carrier board, and the first interconnection structure on the top of the second functional layer is electrically connected to the second functional layer. Therefore, the power supply circuit of the power layer and the signal transmission circuit of the signal layer can be separated, effectively reducing the interference of the power supply circuit of the power layer on the signal in the signal layer, thereby reducing the overall voltage and power consumption of the packaging structure, thereby improving the performance of the packaging structure.

[0019] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0020] Figure 1 It is a schematic structural diagram of the first embodiment of the packaging structure of the present invention.

[0021] refer to Figure 1 The packaging structure includes: a first carrier 100, the first carrier 100 has a first circuit 101; a first chip structure 102, including a first functional layer 103 located on the first carrier 100, and a second functional layer 104 bonded to the first functional layer 103, the first functional layer 103 is electrically connected to the first carrier 100, the second functional layer 104 is electrically connected to the first functional layer 103, one of the first functional layer 103 and the second functional layer 104 is a power layer, and the other is a signal layer; a first interconnection structure 105, which is respectively located on the first carrier 100 at the side of the first chip structure 102 and on the top of the second functional layer 104 facing away from the first functional layer 103, the first interconnection structure 105 at the side of the first chip structure 102 is electrically connected to the first functional layer 103 through the first circuit 101, and the first interconnection structure 105 on the top of the second functional layer 104 is electrically connected to the second functional layer 104.

[0022] The first carrier 100 is used as a packaging carrier to provide support for the first chip structure 102 and provide an electrical connection path between the first chip structure 102 and other circuits, thereby achieving packaging integration and electrical integration of the first chip structure 102 .

[0023] As an example, the first substrate 100 is a silicon substrate. In other embodiments, the first substrate may also be other types of substrates having a first circuit, for example, the first substrate may also be a glass substrate, a resin substrate, a ceramic substrate or a printed circuit board (PCB).

[0024] In this embodiment, the first circuit 101 is a redistribution layer (RDL), which is used to electrically connect the first functional layer 103 and the first interconnection structure 105 on the first substrate 100. In other embodiments, the first circuit may also be other types of wiring structures, for example, the first circuit may include an interconnection layer and an interconnection through-hole structure electrically connecting the interconnection layer.

[0025] In this embodiment, the first chip structure 102 is a logic chip structure with a specific function. Specifically, the type of the first chip structure 102 is determined according to actual functional requirements or application scenarios. For example, the first chip structure 102 includes a gate array, a cell substrate array, an embedded array, a structured application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a processing unit (XPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip, or a complementary metal oxide semiconductor (CMOS) image sensor.

[0026] One of the first functional layer 103 and the second functional layer 104 serves as a power supply layer, and the other serves as a signal layer.

[0027] In this embodiment, the first functional layer 103 is a power layer, and the second functional layer 104 is a signal layer. Accordingly, when the first chip structure 102 is subsequently bonded to the second carrier, it is convenient for the signal layer to be electrically connected to other chip structures through the second carrier. At the same time, the transmission path between the signal layer and the second carrier is shortened, reducing interference between lines.

[0028] Specifically, the external voltage supplies power to the signal layer through the power layer (ie, the first functional layer 103 ), and the signal layer (ie, the second functional layer 104 ) is used to realize signal transmission between different chip structures.

[0029] It should be noted that the first functional layer 103 includes a first conductive layer 121 and a first pin 120 electrically connected to the first conductive layer 121, the first pin 120 is located on the side of the first functional layer 103 facing the first carrier 100, and the other end of the first pin 120 is electrically connected to the first circuit 101; the second functional layer 104 includes a second conductive layer 122 and a second pin 123 electrically connected to the second conductive layer 122, the second pin 123 is located on the side of the second functional layer 104 facing away from the first carrier 100, and the other end of the second pin 123 is electrically connected to the first interconnect structure 105 on the top of the second functional layer 104.

[0030] In this embodiment, the second functional layer 104 is bonded to the first functional layer 103, that is, the first functional layer 103 and the second functional layer 104 can be prepared separately, thereby improving the process compatibility between the two. At the same time, the process flow can be simplified, the process complexity can be reduced, and the yield of the packaging structure can be improved.

[0031] In this embodiment, the first chip structure 102 further includes: a bonding layer 106 located between the first functional layer 103 and the second functional layer 104 , wherein the bonding layer 106 has a second interconnect structure 125 , and the second interconnect structure 125 electrically connects the first functional layer 103 and the second functional layer 104 .

[0032] Specifically, the bonding layer 106 is a hybrid bonding layer, and the bonding layer 106 includes an insulating layer 124 and a second interconnect structure 125 located in the insulating layer 124 . The first functional layer 103 and the second functional layer 104 are electrically connected via the second interconnect structure 125 .

[0033] It should be noted that the bonding layer 106 being a mixed bonding layer is beneficial to increasing the number of the second interconnect structures 125 and also beneficial to reducing the thickness of the packaging structure.

[0034] As an example, the second interconnect structure 125 is a conductive column penetrating the insulating layer 124 .

[0035] In other embodiments, according to actual process requirements, the second interconnect structure may also include an interconnect layer and an interconnect via structure electrically connecting the interconnect layer. In other embodiments, the bonding layer may also be composed of conductive bumps, and accordingly, the second interconnect structure in the bonding layer is a conductive bump.

[0036] In this embodiment, the height h of the first chip structure 102 should not be too large. If the height h of the first chip structure 102 is too large, it is easy to make the height difference between the first chip structure 102 and the first carrier 100 too large, thereby increasing the difficulty of forming the first interconnect structure 105 on the first carrier 100 at the side of the first chip structure 102 and on the top of the second functional layer 104. Therefore, in this embodiment, the height h of the first chip structure 102 is less than or equal to 50 microns.

[0037] In this embodiment, the height h of the first chip structure 102 refers to the sum of the height of the first functional layer 103 , the height of the second functional layer 104 , and the height of the bonding layer 106 .

[0038] The first interconnect structure 105 is used to realize electrical connection with the first functional layer 103 and is also used to realize electrical connection with the second functional layer 104 .

[0039] Specifically, the first functional layer 103 and the second functional layer 104 are electrically connected to the same side through the first interconnect structure 105 , thereby facilitating further packaging integration of the subsequent first chip structure 102 .

[0040] Moreover, the first interconnection structure 105 on the side of the first chip structure 102 is electrically connected to the first functional layer 103 through the first carrier 100, and the first interconnection structure 105 on the top of the second functional layer 104 is electrically connected to the second functional layer 104. Therefore, the power supply circuit of the power layer and the signal transmission circuit of the signal layer can be separated, effectively reducing the interference of the power supply circuit of the power layer on the signal in the signal layer, thereby reducing the overall voltage and power consumption of the packaging structure, thereby improving the performance of the packaging structure.

[0041] In this embodiment, the material of the first interconnect structure 105 includes copper, aluminum, gold or silver. Copper, aluminum, gold or silver has good electrical conductivity and thermal conductivity. As an example, the material of the first interconnect structure 105 is copper.

[0042] In the present embodiment, the height h1 of the first interconnection structure 105 on the side of the first chip structure 102 is equal to the sum of the height h of the first chip structure 102 and the height h2 of the first interconnection structure 105 on the top of the second functional layer 104, thereby making it easy to make the ends of each first interconnection structure 105 facing away from the first carrier 100 flush, and correspondingly improving the flatness of the top surface of the packaging module composed of the first carrier 100, the first chip structure 102 and the first interconnection structure 105, thereby facilitating the subsequent packaging integration of the packaging module.

[0043] In this embodiment, the packaging structure also includes: a second carrier 107, which is located on the side of the first interconnection structure 105 facing away from the first carrier 100, and the second carrier 107 has a second circuit 108 and a third circuit 109, the second circuit 108 is electrically connected to the first interconnection structure 105 electrically connected to the power supply layer, and the third circuit 109 is electrically connected to the first interconnection structure 105 electrically connected to the signal layer.

[0044] The second carrier board 107 is used to realize the electrical connection between the signal layer and other chip structures, and is also used to apply an external voltage to the power layer.

[0045] As an example, the second carrier 107 includes a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate or a printed circuit board.

[0046] It should be noted that the first interconnect structure 105 electrically connected to the power layer is electrically connected to the second carrier 107 through the second line 108, so that the power layer is electrically connected to the second carrier 107, and then the external circuit can apply an external voltage to the power layer separately through the second carrier 107; the first interconnect structure 105 electrically connected to the signal layer is electrically connected to the second carrier 107 through the third line 109, so that the signal layer is electrically connected to the second carrier 107, and then the signal layer can transmit signals with other chip structures through the second carrier 107.

[0047] It should also be noted that by setting the first circuit 101 in the first substrate 100 and setting the second circuit 108 and the third circuit 109 in the second substrate 107, on the one hand, the interference between the circuits can be reduced, and on the other hand, it is also helpful to simplify the wiring difficulty, thereby improving the yield of the packaging structure.

[0048] In other embodiments, the first interconnection structure may not be disposed on the second carrier, and accordingly, the packaging structure may not include the second carrier.

[0049] In this embodiment, the packaging structure further includes: a second chip structure 110 located on a second carrier board 107 at a side of the first carrier board 100 and electrically connected to the signal layer through a third circuit 109 of the second carrier board 107 .

[0050] Specifically, the second chip structure 110 realizes signal transmission with the signal layer in the first chip structure 102 through the third circuit 109 of the second carrier 107 .

[0051] In this embodiment, the first functional layer 103 is a power layer, and the second functional layer 104 is a signal layer. Therefore, the first interconnection structure 105 on the side of the first chip structure 102 is located on the side of the first chip structure 102 away from the second chip structure 110, which is conducive to shortening the transmission path between the signal layer and the second chip structure 110, thereby improving the integrity of the signal during the transmission process; at the same time, it is also conducive to reducing the interference of the power supply circuit on the signal transmission circuit. In other embodiments, the first interconnection structure on the side of the first chip structure can also be located at other positions.

[0052] In this embodiment, the surface of the first carrier 100 facing away from the second carrier 107 is flush with the surface of the second chip structure 110 facing away from the second carrier 107, that is, the surface of the first carrier 100 facing away from the second carrier 107 and the surface of the second chip structure 110 facing away from the second carrier 107 form a flat surface, which is beneficial to reduce mechanical stress concentration and correspondingly reduce the probability of cracks in the packaging structure during use.

[0053] Specifically, by adjusting the thickness of the first carrier 100 , the surface of the first carrier 100 facing away from the second carrier 107 is flush with the surface of the second chip structure 110 facing away from the second carrier 107 .

[0054] In other embodiments, the thickness of the first carrier and the thickness of the bonding layer may be adjusted so that the surface of the first carrier facing away from the second carrier is flush with the surface of the second chip structure facing away from the second carrier.

[0055] In this embodiment, the second chip structure 110 includes a memory chip structure 111 .

[0056] Specifically, the second chip structure 110 is composed of stacked memory chip structures 111, the number of memory chip structures 111 can be set according to actual needs, and adjacent memory chip structures 111 are connected through fourth conductive connectors 112. As an example, the fourth conductive connector 112 is a conductive bump. As an example, the material of the fourth conductive connector 112 includes one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, and tin-silver-antimony.

[0057] As an example, the memory chip structure 111 includes a volatile memory chip (e.g., a dynamic random access memory or a static random access memory) or a non-volatile memory chip (e.g., a flash memory, a phase change static random access memory, a magnetoresistive static random access memory, a ferroelectric static random access memory, or a resistive static random access memory).

[0058] In other embodiments, the memory chip structure may also be connected by hybrid bonding.

[0059] In this embodiment, the packaging structure further includes: a plastic layer 113 located on the first carrier 100 , the plastic layer 113 covers the first chip structure 102 and the first interconnection structure 105 , and the plastic layer 113 exposes one end of the first interconnection structure 105 facing away from the first carrier 100 .

[0060] It should be noted that the plastic encapsulation layer 113 can improve the stability of the first chip structure 102 and the first interconnection structure 105 on the first carrier 100, and also improve the rigidity among the first carrier 100, the first chip structure 102 and the first interconnection structure 105. Accordingly, in the process of bonding the first interconnection structure 105 to the second carrier 107, the reliability of the package is improved.

[0061] In some other embodiments, the plastic encapsulation layer may further encapsulate the second chip structure. In other embodiments, the packaging structure may not include the plastic encapsulation layer.

[0062] In this embodiment, the material of the plastic packaging layer 113 includes epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin.

[0063] It should be noted that the height h1 of the first interconnect structure 105 on the side of the first chip structure 102 is equal to the sum of the height h of the first chip structure 102 and the height h2 of the first interconnect structure 105 on the top of the second functional layer 104, which makes it easier for the plastic encapsulation layer 113 to expose one end of each first interconnect structure 105 facing away from the first carrier 100.

[0064] In this embodiment, the packaging structure also includes: a first conductive connector 114, located between the second carrier 107 and the first interconnection structure 105 on the side of the first chip structure 102, and electrically connecting the second carrier 107 and the first interconnection structure 105 on the side of the first chip structure 102; a second conductive connector 115, located between the second carrier 107 and the first interconnection structure 105 on the top of the second functional layer 104, and electrically connecting the second carrier 107 and the first interconnection structure 105 on the top of the second functional layer 104; a third conductive connector 116, located between the second chip structure 110 and the second carrier 107, and electrically connecting the second chip structure 110 and the second carrier 107.

[0065] Any of the first conductive connector 114, the second conductive connector 115 and the third conductive connector 116 can be a structure such as a conductive bump or a conductive column. The material of the conductive bump includes one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium and tin-silver-antimony, and the material of the conductive column includes one or more of copper, silver, nickel, gold and aluminum.

[0066] As an example, the first conductive connection member 114 , the second conductive connection member 115 , and the third conductive connection member 116 are all conductive bumps.

[0067] As an example, the first conductive connection member 114 , the second conductive connection member 115 , and the third conductive connection member 116 are made of the same material. For example, the first conductive connection member 114 , the second conductive connection member 115 , and the third conductive connection member 116 are all made of tin.

[0068] In other embodiments, the materials of the first conductive connection member, the second conductive connection member, and the third conductive connection member may also be different.

[0069] In this embodiment, the semiconductor structure further includes: a fifth conductive connecting member 117 located on the second carrier 107 and located on a side of the second carrier 107 facing away from the first chip structure 102 .

[0070] Specifically, the fifth conductive connector 117 facilitates the subsequent bonding of the second carrier 107 to another carrier (eg, a printed circuit board).

[0071] Specifically, the fifth conductive connection member 117 may be a conductive bump or a conductive column, wherein the material of the conductive bump includes one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, and tin-silver-antimony, and the material of the conductive column includes one or more of copper, silver, nickel, gold, and aluminum. As an example, the fifth conductive connection member 117 is a conductive bump.

[0072] Figure 2 It is a structural schematic diagram of the second embodiment of the packaging structure of the present invention.

[0073] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the first functional layer 203 is a signal layer, and the second functional layer 204 is a power layer.

[0074] Specifically, the external voltage supplies power to the signal layer through the power layer (ie, the second functional layer 204 ), and the signal layer (ie, the first functional layer 203 ) is used to realize signal transmission between different chip structures.

[0075] It should be noted that when the first functional layer 203 includes a first conductive layer 220 and a first pin 221 electrically connected to the first conductive layer 220, the first pin 221 is located on the side of the first functional layer 203 facing the first carrier 200, and the other end of the first pin 221 is electrically connected to the first circuit 201; the second functional layer 204 includes a second conductive layer 222 and a second pin 223 electrically connected to the second conductive layer 222, the second pin 223 is located on the side of the second functional layer 204 facing away from the first carrier 200, and the other end of the second pin 223 is electrically connected to the first interconnect structure 205 on the top of the power layer.

[0076] It should also be noted that the first functional layer 203 is a signal layer, and the second functional layer 204 is a power layer. Accordingly, the power layer is located on the side of the signal layer facing away from the first carrier 200, which means that when the first chip structure 202 is bonded to the second carrier 207, the power layer is closer to the second carrier 207, which is beneficial to shorten the power supply circuit and improve the power supply efficiency.

[0077] In addition, when the first functional layer 203 is a signal layer, the first interconnection structure 205 on the side of the first chip structure 202 is located on the side of the first chip structure 202 facing the second chip structure 210, which is conducive to shortening the transmission path between the signal layer and the second chip structure 210, thereby improving the integrity of the signal during the transmission process; at the same time, it is also conducive to reducing the interference of the power supply circuit on the signal transmission circuit. In other embodiments, the first interconnection structure on the side of the first chip structure can also be located at other positions.

[0078] Correspondingly, an embodiment of the present invention also provides a packaging method. Figures 3 to 9 It is a schematic structural diagram corresponding to each step in the first embodiment of the packaging method of the present invention.

[0079] refer to Figure 3 , providing a first carrier board 500 , the first carrier board 500 having a first circuit 501 .

[0080] As an example, the first carrier 500 is a silicon carrier. The relevant description of the first carrier 500 can refer to the above embodiment, and will not be repeated here.

[0081] In this embodiment, the first circuit 501 is a rewiring layer, which is used to electrically connect the first functional layer and the first interconnection structure on the first substrate 500. In other embodiments, the first circuit may also be other types of wiring structures, for example, the first circuit may include an interconnection layer and an interconnection through-hole structure electrically connecting the interconnection layer.

[0082] Continue to refer Figure 3A first chip structure 502 is arranged on a first carrier 500. The first chip structure 502 includes a first functional layer 503 located on the first carrier 500, and a second functional layer 504 bonded to the first functional layer 503. The first functional layer 503 is electrically connected to the first carrier 500, and the second functional layer 504 is electrically connected to the first functional layer 503. One of the first functional layer 503 and the second functional layer 504 is a power layer, and the other is a signal layer.

[0083] For the type of the first chip structure 502 , reference may be made to the corresponding descriptions of other embodiments, which will not be described in detail herein.

[0084] In this embodiment, the first chip structure 502 is disposed on the first carrier 500 by a hybrid bonding process.

[0085] It should be noted that the first carrier 500 is provided with a first circuit 501 and a first dielectric layer (not shown) exposing the area to be connected of the first circuit 501, and the first functional layer 503 includes a first pin 521 and a second dielectric layer (not shown) exposing the area to be connected of the first pin 521, so that the first chip structure 502 can be bonded to the first carrier 500 through a hybrid bonding process.

[0086] One of the first functional layer 503 and the second functional layer 504 is used as a power layer, and the other is used as a signal layer. In this embodiment, the first functional layer 503 is a power layer, and the second functional layer 504 is a signal layer. When the first chip structure 502 is subsequently bonded to the second carrier, it is convenient for the signal layer to be electrically connected to other chip structures through the second carrier. At the same time, the transmission path between the signal layer and the second carrier is shortened, reducing interference between lines.

[0087] Specifically, the external voltage supplies power to the signal layer through the power layer (ie, the first functional layer 503 ), and the signal layer (ie, the second functional layer 504 ) is used to realize signal transmission between different chip structures.

[0088] It should be noted that when the first functional layer 503 includes a first conductive layer 520 and a first pin 521 electrically connected to the first conductive layer 520, the first pin 521 is located on the side of the first functional layer 503 facing the first carrier 500, and the other end of the first pin 521 is electrically connected to the first circuit 501; the second functional layer 504 includes a second conductive layer 522 and a second pin 523 electrically connected to the second conductive layer 522, the second pin 523 is located on the side of the second functional layer 504 facing away from the first carrier 500, and the other end of the second pin 523 is electrically connected to the first interconnection structure at the top of the second functional layer 504.

[0089] In this embodiment, the second functional layer 504 is bonded to the first functional layer 503, that is, the first functional layer 503 and the second functional layer 504 can be prepared separately, thereby improving the process compatibility between the two, and at the same time, simplifying the process flow and reducing the process complexity.

[0090] In this embodiment, in the step of disposing the first chip structure 502 on the first carrier 500 , the first chip structure 502 further includes: a bonding layer 506 located between the first functional layer 503 and the second functional layer 504 and electrically connecting the first functional layer 503 and the second functional layer 504 .

[0091] Specifically, the bonding layer 506 includes an insulating layer 524 and a second interconnect structure 525 located in the insulating layer 524 , and the first functional layer 503 and the second functional layer 504 are electrically connected via the second interconnect structure 525 .

[0092] It should be noted that the bonding layer 506 being a mixed bonding layer is beneficial to increasing the number of the second interconnect structures 525 and also beneficial to reducing the thickness of the packaging structure.

[0093] As an example, the second interconnect structure 525 is a conductive column that penetrates the insulating layer 524. In other embodiments, according to actual process requirements, the second interconnect structure may also include an interconnect layer and an interconnect via structure that electrically connects the interconnect layer. In other embodiments, the bonding layer may also be composed of conductive bumps, and accordingly, the second interconnect structure in the bonding layer is a conductive bump.

[0094] In this embodiment, the height H of the first chip structure 502 is less than or equal to 50 micrometers.

[0095] refer to Figures 4 to 6 , respectively, on the first carrier 500 at the side of the first chip structure 502 and on the top of the second functional layer 504 facing away from the first functional layer 503 to form a first interconnection structure 505 (eg, Figure 5 and Figure 6 As shown), the first interconnect structure 505 on the side of the first chip structure 502 is electrically connected to the first functional layer 503 through the first line 501, and the first interconnect structure 505 on the top of the second functional layer 504 is electrically connected to the second functional layer 504.

[0096] The first interconnection structure 505 is used to realize electrical connection with the first functional layer 503, and is also used to realize electrical connection with the second functional layer 504. Specifically, through the first interconnection structure 505, the electrical properties of the first functional layer 503 and the second functional layer 504 are both connected to the same side, so as to facilitate the subsequent further packaging integration of the first chip structure 502. In addition, the first interconnection structure 505 on the side of the first chip structure 502 is electrically connected to the first functional layer 503 through the first carrier 500, and the first interconnection structure 505 on the top of the second functional layer 504 is electrically connected to the second functional layer 504. Therefore, the power supply circuit of the power supply layer can be separated from the signal transmission circuit of the signal layer, effectively reducing the interference of the power supply circuit of the power supply layer on the signal in the signal layer, thereby reducing the voltage and power consumption of the overall packaging structure, thereby improving the efficiency of the packaging structure.

[0097] In this embodiment, the material of the first interconnect structure 505 includes copper, aluminum, gold or silver. As an example, the material of the first interconnect structure 505 is copper.

[0098] refer to Figure 6 The height H1 of the first interconnection structure 505 on the side of the first chip structure 502 is equal to the sum of the height H of the first chip structure 502 and the height H2 of the first interconnection structure 505 on the top of the second functional layer 504, so that it is easy to make the ends of each first interconnection structure 505 facing away from the first carrier 500 flush, and correspondingly improve the flatness of the top surface of the packaging module composed of the first carrier 500, the first chip structure 502 and the first interconnection structure 505, thereby facilitating the subsequent packaging integration of the packaging module.

[0099] Specifically, the steps of forming the first interconnect structure 505 on the first carrier 500 at the side of the first chip structure 502 and on the top of the second functional layer 504 facing away from the first functional layer 503 include: Figure 4 , forming a sacrificial layer 517 on the first carrier, the sacrificial layer 517 also covers the top of the first chip structure 502; continue to refer to Figure 4 , an opening 518 is formed in the sacrificial layer 517, and the opening 518 penetrates the sacrificial layer 517 at the side of the first chip structure 502 and the sacrificial layer 517 at the top of the second functional layer 504 respectively; Figure 5 , forming a first interconnect structure 505 in the opening 518; referring to Figure 6 After forming the first interconnect structure 505 , the method further includes: removing the sacrificial layer 517 .

[0100] The sacrificial layer 517 is used as a temporary support structure to form the first interconnect structure 505. The opening 518 is used to provide a spatial position for the first interconnect structure 505.

[0101] It should be noted that, by forming the opening 518 in the sacrificial layer 517 and then forming the first interconnect structure 505 in the opening 518 , it is helpful to reduce the difficulty of forming the first interconnect structure 505 .

[0102] It should also be noted that after forming the first interconnect structure 505 , the sacrificial layer 517 is removed to prepare for the subsequent formation of a plastic encapsulation layer.

[0103] In this embodiment, in the step of forming the sacrificial layer 517 on the first carrier 500, the material of the sacrificial layer 517 includes photoresist. The photoresist can be directly patterned by the photolithography process, thereby reducing the complexity of forming the opening 518 and facilitating the precise control of the size of the opening 518; at the same time, the photoresist is easy to be removed, thereby reducing the complexity of the process and improving the production efficiency. In other embodiments, the sacrificial layer can also be made of other materials that can serve as a temporary support structure and are easy to be removed.

[0104] In other embodiments, the steps of forming a first interconnection structure on the first carrier on the side of the first chip structure and on the top of the second functional layer facing away from the first functional layer may also include: providing a first interconnection structure; forming a solder ball at the end of the first interconnection structure; and press-welding the first interconnection structure to the first carrier on the side of the first chip structure and on the top of the second functional layer facing away from the first functional layer through the solder ball, which is conducive to reducing process complexity and thus reducing production costs.

[0105] refer to Figures 7 and 8 Before bonding the first interconnect structure 505 to the second carrier, the packaging method further includes: forming a plastic encapsulation layer 513 (such as Figure 8 As shown in FIG. 5 , the plastic encapsulation layer 513 covers the first chip structure 502 and the first interconnection structure 505 , and the plastic encapsulation layer 513 exposes one end of the first interconnection structure 505 facing away from the first carrier 500 .

[0106] It should be noted that the plastic encapsulation layer 513 can improve the stability of the first chip structure 502 and the first interconnection structure 505 on the first carrier 500, and also improve the rigidity among the first carrier 500, the first chip structure 502 and the first interconnection structure 505. Accordingly, in the process of bonding the first interconnection structure 505 to the second carrier, the reliability of the packaging structure is improved.

[0107] In some other embodiments, the plastic encapsulation layer may further encapsulate the second chip structure. In other embodiments, the packaging structure may not include the plastic encapsulation layer.

[0108] In this embodiment, the material of the plastic packaging layer 513 includes epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin.

[0109] It should be noted that the height H1 of the first interconnect structure 505 on the side of the first chip structure 502 is equal to the sum of the height H of the first chip structure 502 and the height H2 of the first interconnect structure 505 on the top of the second functional layer 504, which makes it easier for the plastic encapsulation layer 513 to expose one end of each first interconnect structure 505 facing away from the first carrier 500.

[0110] Specifically, the step of forming the plastic encapsulation layer 513 on the first carrier 500 includes: referring to Figure 7 , a molding material layer 519 is formed on the first carrier 500, and the molding material layer 519 covers the first chip structure 502 and the first interconnection structure 505; Figure 8 , remove the molding material layer 519 that is higher than the end of the first interconnect structure 505 facing away from the first carrier 500 , and the remaining molding material layer 519 serves as the molding layer 513 .

[0111] The molding material layer 519 is used to form the molding layer 513 .

[0112] It should be noted that by forming the molding material layer 519 on the first carrier 500 and then removing the molding material layer 519 higher than the end of the first interconnect structure 505 facing away from the first carrier 500 , the thickness uniformity of the molding layer 513 can be improved.

[0113] It should also be noted that the plastic encapsulation material layer 519 higher than the end of the first interconnect structure 505 facing away from the first carrier 500 is removed to expose the end of the first interconnect structure 505 facing away from the first carrier 500, so as to facilitate the subsequent electrical connection between the end of the first interconnect structure 505 facing away from the first carrier 500 and the second carrier.

[0114] In this embodiment, the process of removing the plastic encapsulation material layer 519 higher than the end of the first interconnection structure 505 facing away from the first carrier 500 includes a grinding process. The grinding process can accurately control the thickness of the removed plastic encapsulation material layer 519, which is conducive to exposing the top of the first interconnection structure 505 and avoiding excessive removal of the plastic encapsulation material layer 519; in addition, it is also conducive to improving the flatness of the surface formed by the first interconnection structure 505 and the plastic encapsulation layer 513, preparing for subsequent processes.

[0115] Continue to refer Figure 8 After forming the plastic encapsulation layer 513 on the first carrier 500 and before the first interconnect structure 505 is bonded to the second carrier, it also includes: forming a first conductive connector 514 on the top of the first interconnect structure 505 on the side of the first chip structure 502, and forming a second conductive connector 515 on the top of the first interconnect structure 505 on the top of the second functional layer 504.

[0116] Any one of the first conductive connector 514 and the second conductive connector 515 can be a conductive bump or a conductive column, and the material of the conductive bump includes one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, and tin-silver-antimony. As an example, the first conductive connector 514 and the second conductive connector 515 are both conductive bumps.

[0117] As an example, the first conductive connector 514 and the second conductive connector 515 are made of the same material, for example, the first conductive connector 514 and the second conductive connector 515 are both made of tin. In other embodiments, the first conductive connector and the second conductive connector may also be made of different materials.

[0118] refer to Fig. 9 The packaging method further includes: providing a second carrier 507, the second carrier 507 having a second circuit 508 and a third circuit 509; after forming a first interconnection structure 505 on the first carrier 500 at the side of the first chip structure 502 and on the top of the second functional layer 504 facing away from the first functional layer 503, respectively, the first interconnection structure 505 is bonded to the second carrier 507, the first interconnection structure 505 electrically connecting the power layer is electrically connected to the second circuit 508, and the first interconnection structure 505 electrically connecting the signal layer is electrically connected to the third circuit 509; bonding the second chip structure 510 to the second carrier 507, the second chip structure 510 is located at the side of the first carrier 500, and the second chip structure 510 is electrically connected to the signal layer through the third circuit 509 of the second carrier 507.

[0119] The second carrier board 507 is used to realize the electrical connection between the signal layer and other chip structures, and is also used to apply an external voltage to the power layer. The relevant description of the second carrier board 507 can refer to the above embodiment, and will not be repeated here.

[0120] It should be noted that the first interconnection structure 505 electrically connected to the power supply layer is electrically connected to the second carrier board 507 through the second line 508, so that the power supply layer is electrically connected to the second carrier board 507, and then the external circuit can apply an external voltage to the power supply layer separately through the second carrier board 507; the first interconnection structure 505 electrically connected to the signal layer is electrically connected to the second carrier board 507 through the third line 509, so that the signal layer is electrically connected to the second carrier board 507, and then the signal layer can transmit signals with other chip structures through the second carrier board 507.

[0121] It should also be noted that by setting the first circuit 501 in the first carrier 500 and setting the second circuit 508 and the third circuit 509 in the second carrier 507, on the one hand, the interference between the circuits can be reduced, and on the other hand, it is also helpful to simplify the wiring difficulty, thereby improving the yield of the packaging structure.

[0122] In other embodiments, the first interconnection structure may not be disposed on the second carrier, and accordingly, the packaging structure may not include the second carrier.

[0123] Specifically, the second chip structure 510 realizes signal transmission with the signal layer in the first chip structure 502 through the third circuit 509 of the second carrier 507 .

[0124] In this embodiment, the first functional layer 503 is a power layer, and the second functional layer 504 is a signal layer. Therefore, the first interconnection structure 505 on the side of the first chip structure 502 is located on the side of the first chip structure 502 away from the second chip structure 510, which is beneficial to shorten the transmission path between the signal layer and the second chip structure 510, thereby improving the integrity of the signal during the transmission process; at the same time, it is also beneficial to reduce the interference of the power supply circuit on the signal transmission circuit.

[0125] In this embodiment, the surface of the first carrier 500 facing away from the second carrier 507 is flush with the surface of the second chip structure 510 facing away from the second carrier 507 by adjusting the thickness of the first carrier 500. In other embodiments, the surface of the first carrier facing away from the second carrier is flush with the surface of the second chip structure facing away from the second carrier by adjusting the thickness of the first carrier and the thickness of the bonding layer.

[0126] In this embodiment, the second chip structure 510 includes a memory chip structure 511. Specifically, the second chip structure 510 is composed of stacked memory chip structures 511, the number of memory chip structures 511 can be set according to actual needs, and adjacent memory chip structures 511 are connected through fourth conductive connectors 512. In other embodiments, the memory chip structures can also be connected by hybrid bonding.

[0127] For the material type of the fourth conductive connecting member 512 , reference may be made to the corresponding descriptions of other embodiments, which will not be described in detail here.

[0128] As an example, the memory chip structure 511 includes a volatile memory chip or a non-volatile memory chip.

[0129] refer to Fig. 9 The step of bonding the first interconnect structure 505 to the second carrier 507 includes: bonding the first interconnect structure 505 on the side of the first chip structure 502 to the second carrier 507 through the first conductive connecting member 514 and electrically connecting to the second carrier 507; bonding the first interconnect structure 505 electrically connected to the top of the second functional layer 504 to the second carrier 507 through the second conductive connecting member 515 and electrically connecting to the second carrier 507.

[0130] It should be noted that, in this embodiment, before the first interconnect structure 505 is bonded to the second carrier 507, the first conductive connector 514 and the second conductive connector 515 are respectively formed on the top of the first interconnect structure 505. In other embodiments, before the first interconnect structure is bonded to the second carrier, the first conductive connector and the second conductive connector may also be formed on the second carrier.

[0131] refer to Fig. 9 The step of bonding the second chip structure 510 to the second carrier 507 includes: bonding the second chip structure 510 to the second carrier 507 through the third conductive connecting member 516 and electrically connecting the second chip structure 510 to the second carrier 507 .

[0132] The material of the third conductive connection member 516 includes one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, and tin-silver-antimony. As an example, the third conductive connection member 516, the first conductive connection member 514, and the second conductive connection member 515 are made of the same material, for example, the third conductive connection member 516, the first conductive connection member 514, and the second conductive connection member 515 are all made of tin.

[0133] In other embodiments, the materials of the first conductive connection member, the second conductive connection member, and the third conductive connection member may also be different.

[0134] It should be noted that before bonding the second chip structure 510 to the second carrier 507 , the third conductive connecting member 516 may be formed on the second chip structure 510 or on the second carrier 507 .

[0135] refer to Fig. 9 The packaging method further includes: forming a fifth conductive connector 517 on a side of the second carrier 507 facing away from the first chip structure 502. For a detailed description of the fifth conductive connector 517, reference may be made to the relevant contents of the aforementioned embodiment, which will not be repeated here.

[0136] It should be noted that the packaging structure of the first embodiment can be obtained by using the packaging method of the first embodiment or other packaging methods. For the detailed description of the packaging method of the first embodiment, reference can be made to the relevant contents of the packaging structure of the first embodiment.

[0137] Fig.10 It is a structural schematic diagram corresponding to the steps in the second embodiment of the packaging method of the present invention.

[0138] The differences between this embodiment and the above embodiment are as follows: in the step of arranging the first chip structure 602 on the first carrier 600, the first functional layer 603 is a signal layer, and the second functional layer 604 is a power layer.

[0139] Specifically, the external voltage supplies power to the signal layer through the power layer (ie, the second functional layer 604), and the signal layer (ie, the first functional layer 603) is used to realize signal transmission between different chip structures.

[0140] It should be noted that the first functional layer 603 includes a first conductive layer 620 and a first pin 621 electrically connected to the first conductive layer 620, the first pin 621 is located on the side of the first functional layer 603 facing the first carrier 600, and the other end of the first pin 621 is electrically connected to the first circuit 601; the second functional layer 604 includes a second conductive layer 622 and a second pin 623 electrically connected to the second conductive layer 622, the second pin 623 is located on the side of the second functional layer 604 facing away from the first carrier 600, and the other end of the second pin 623 is electrically connected to the first interconnection structure 605 at the top of the power layer.

[0141] It should be noted that the first functional layer 603 is a signal layer, and the second functional layer 604 is a power layer. Accordingly, the power layer is located on the side of the signal layer facing away from the first carrier 600, which means that when the first chip structure 602 is bonded to the second carrier 607, the power layer is closer to the second carrier 607, which is beneficial to shorten the power supply circuit and improve the power supply efficiency.

[0142] It should also be noted that when the first functional layer 603 is a signal layer, the first interconnection structure 605 on the side of the first chip structure 602 is located on the side of the first chip structure 602 facing the second chip structure 610, which is beneficial to shorten the transmission path between the signal layer and the second chip structure 610, thereby improving the integrity of the signal during transmission.

[0143] It should be noted that the packaging structure of the second embodiment can be obtained by using the packaging method of the second embodiment or other packaging methods. For the detailed description of the packaging method of the second embodiment, reference can be made to the relevant contents of the packaging structure of the second embodiment.

[0144] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: A first carrier board, wherein the first carrier board has a first circuit; A first chip structure includes a first functional layer located on the first carrier, and a second functional layer bonded to the first functional layer, the first functional layer is electrically connected to the first carrier, the second functional layer is electrically connected to the first functional layer, one of the first functional layer and the second functional layer is a power layer, and the other is a signal layer; The first interconnection structure is respectively located on the first carrier plate on the side of the first chip structure and on the top of the second functional layer facing away from the first functional layer. The first interconnection structure on the side of the first chip structure is electrically connected to the first functional layer through the first line, and the first interconnection structure on the top of the second functional layer is electrically connected to the second functional layer.

2. The packaging structure according to claim 1, characterized in that: The first chip structure further includes: a bonding layer located between the first functional layer and the second functional layer, wherein the bonding layer has a second interconnection structure, and the second interconnection structure electrically connects the first functional layer and the second functional layer.

3. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a second carrier board, located on a side of the first interconnection structure facing away from the first carrier board, the second carrier board having a second circuit and a third circuit, the second circuit being electrically connected to the first interconnection structure electrically connected to the power layer, and the third circuit being electrically connected to the first interconnection structure electrically connected to the signal layer; The second chip structure is located on a second carrier board at the side of the first carrier board and is electrically connected to the signal layer through a third circuit of the second carrier board.

4. The packaging structure according to claim 1 or 3, characterized in that: The first functional layer is a power layer, and the second functional layer is a signal layer.

5. The packaging structure according to claim 1 or 3, characterized in that: The packaging structure further includes: a plastic encapsulation layer, which is located on the first carrier, and covers the first chip structure and the first interconnection structure, and the plastic encapsulation layer exposes an end of the first interconnection structure facing away from the first carrier.

6. The packaging structure according to claim 3, characterized in that: When the second functional layer is a signal layer, the first interconnection structure on the side of the first chip structure is located on a side of the first chip structure away from the second chip structure; Alternatively, when the first functional layer is a signal layer, the first interconnection structure on the side of the first chip structure is located on a side of the first chip structure facing the second chip structure.

7. The packaging structure according to claim 3, characterized in that: The packaging structure further includes: a first conductive connector, located between the second carrier and the first interconnect structure on the side of the first chip structure, and electrically connecting the second carrier and the first interconnect structure on the side of the first chip structure; A second conductive connecting member is located between the second carrier and the first interconnect structure on the top of the second functional layer, and electrically connects the second carrier and the first interconnect structure on the top of the second functional layer; The third conductive connecting member is located between the second chip structure and the second carrier, and electrically connects the second chip structure and the second carrier.

8. The packaging structure according to claim 3, characterized in that: The second chip structure includes a memory chip structure.

9. The packaging structure according to claim 3, characterized in that: A surface of the first carrier board facing away from the second carrier board is flush with a surface of the second chip structure facing away from the second carrier board.

10. The packaging structure according to claim 1, wherein: The material of the first interconnect structure includes copper, aluminum, gold or silver.

11. The packaging structure according to claim 1, characterized in that: The height of the first chip structure is less than or equal to 50 micrometers.

12. The packaging structure according to claim 1, wherein: The height of the first interconnection structure at the side of the first chip structure is equal to the sum of the height of the first chip structure and the height of the first interconnection structure at the top of the second functional layer.

13. A packaging method, characterized in that: include: Providing a first carrier board, wherein the first carrier board has a first circuit; A first chip structure is arranged on the first carrier, the first chip structure includes a first functional layer located on the first carrier, and a second functional layer bonded to the first functional layer, the first functional layer is electrically connected to the first carrier, the second functional layer is electrically connected to the first functional layer, one of the first functional layer and the second functional layer is a power layer, and the other is a signal layer; A first interconnection structure is formed on a first carrier plate on a side of the first chip structure and on a top of the second functional layer facing away from the first functional layer. The first interconnection structure on the side of the first chip structure is electrically connected to the first functional layer through the first line, and the first interconnection structure on the top of the second functional layer is electrically connected to the second functional layer.

14. The packaging method according to claim 13, characterized in that: The method of arranging the first chip structure on the first carrier includes: bonding the first functional layer to the first carrier through a hybrid bonding process.

15. The packaging method according to claim 13, characterized in that: In the step of setting the first chip structure on the first carrier, the first chip structure also includes: a bonding layer located between the first functional layer and the second functional layer, the bonding layer having a second interconnection structure, and the second interconnection structure electrically connects the first functional layer and the second functional layer.

16. The packaging method according to claim 13, characterized in that: The steps of forming a first interconnection structure on a first carrier at a side of the first chip structure and on a top of the second functional layer facing away from the first functional layer respectively include: forming a sacrificial layer on the first carrier, the sacrificial layer also covering the top of the first chip structure; forming an opening in the sacrificial layer, the opening respectively penetrating the sacrificial layer at a side of the first chip structure and the sacrificial layer at the top of the second functional layer; forming a first interconnection structure in the opening; after forming the first interconnection structure, further comprising: removing the sacrificial layer; Alternatively, the steps of forming a first interconnect structure on a first carrier on the side of the first chip structure and on a top of the second functional layer facing away from the first functional layer include: providing a first interconnect structure; forming a solder ball at an end of the first interconnect structure; and press-welding the first interconnect structure to a first line on the side of the first chip structure and on a top of the second functional layer facing away from the first functional layer through the solder ball.

17. The packaging method according to claim 16, characterized in that: In the step of forming a sacrificial layer on the first carrier, the material of the sacrificial layer includes photoresist.

18. The packaging method according to claim 13, characterized in that: The packaging method further includes: providing a second carrier board, wherein the second carrier board has a second circuit and a third circuit; After forming a first interconnection structure on a first carrier at a side of the first chip structure and on a top of the second functional layer facing away from the first functional layer, the first interconnection structure is bonded to the second carrier, the first interconnection structure of the power layer is electrically connected to the second circuit, and the first interconnection structure of the signal layer is electrically connected to the third circuit; The second chip structure is bonded to the second carrier board, the second chip structure is located on the side of the first carrier board, and the second chip structure is electrically connected to the signal layer through a third circuit of the second carrier board.

19. The packaging method according to claim 13 or 18, characterized in that: In the step of arranging the first chip structure on the first carrier board, the first functional layer is a power layer, and the second functional layer is a signal layer.

20. The packaging method according to claim 18, characterized in that: When the second functional layer is a signal layer, the first interconnection structure on the side of the first chip structure is located on a side of the first chip structure away from the second chip structure; Alternatively, when the first functional layer is a signal layer, the first interconnection structure on the side of the first chip structure is located on a side of the first chip structure facing the second chip structure.

21. The packaging method according to claim 18, characterized in that: Before bonding the first interconnection structure to the second carrier, the packaging method further includes: forming a plastic encapsulation layer on the first carrier, the plastic encapsulation layer covering the first chip structure and the first interconnection structure, and the plastic encapsulation layer exposing an end of the first interconnection structure facing away from the first carrier.

22. The packaging method according to claim 21, characterized in that: The step of forming a plastic encapsulation layer on the first carrier includes: forming a plastic encapsulation material layer on the first carrier, wherein the plastic encapsulation material layer covers the first chip structure and the first interconnection structure; The plastic encapsulation material layer higher than the end of the first interconnection structure facing away from the first carrier is removed, and the remaining plastic encapsulation material layer is used as the plastic encapsulation layer.

23. The packaging method according to claim 22, characterized in that: The process of removing the molding material layer above the end of the first interconnect structure facing away from the first carrier board includes a grinding process.

24. The packaging method according to claim 18, characterized in that: The step of bonding the first interconnection structure to the second carrier includes: bonding the first interconnection structure on the side of the first chip structure to the second carrier through a first conductive connector and electrically connecting the first interconnection structure to the second carrier; bonding the first interconnection structure on the top of the second functional layer to the second carrier through a second conductive connector and electrically connecting the first interconnection structure to the second carrier; The step of bonding the second chip structure to the second carrier includes: bonding the second chip structure to the second carrier through a third conductive connection member, and electrically connecting the second chip structure to the second carrier.

25. The packaging method according to claim 18, characterized in that: The second chip structure includes a memory chip structure.

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