Integrated circuit device

Abstract

An integrated circuit device is disclosed. The integrated circuit device includes: a plurality of device isolation layers extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; the gap filling insulating layer is arranged among the plurality of device isolating layers; a plurality of gate lines disposed on the gap filling insulating layer and extending longitudinally in a second horizontal direction; a plurality of source / drain regions disposed between adjacent ones of the plurality of gate lines; a plurality of source / drain connection structures disposed under the plurality of source / drain regions; and a first spacer structure and a second spacer structure in contact with an upper sidewall of the backside contact. The first spacer structure and the second spacer structure are disposed between the gap-fill insulating layer and the first source / drain connection structure.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0174887 filed on December 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to integrated circuit devices, and more particularly, to integrated circuit devices including backside contacts. Background Art

[0003] The development of electronic technology has driven the downscaling of integrated circuit devices. Since semiconductor devices require both high operating speeds and precise operation, research is ongoing to optimize the structure of transistors within these devices. Summary of the invention

[0004] Embodiments of the present disclosure relate to integrated circuit devices with improved reliability.

[0005] The tasks to be solved by the technical idea of ​​the present disclosure are not limited to the above-mentioned tasks, and other tasks not mentioned may be clearly understood by those of ordinary skill in the art from the following description.

[0006] According to one aspect of the present disclosure, the following integrated circuit device is provided.

[0007] According to an embodiment of the present disclosure, an integrated circuit device includes: a plurality of device isolation layers extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a gap filling insulating layer disposed between the plurality of device isolation layers; a plurality of gate lines disposed on the gap filling insulating layer and extending longitudinally in a second horizontal direction; a plurality of source / drain regions disposed between adjacent gate lines among the plurality of gate lines; a plurality of source / drain connection structures disposed below the plurality of source / drain regions, the plurality of source / drain connection structures including a first source / drain connection structure and a second source / drain connection structure; a backside contact extending through the gap filling insulating layer in a third direction perpendicular to the first horizontal direction and the second horizontal direction and connected to the first source / drain connection structure; and a first spacer structure and a second spacer structure contacting an upper sidewall of the backside contact. The first spacer structure and the second spacer structure are disposed between the gap filling insulating layer and the first source / drain connection structure.

[0008] According to an embodiment of the present disclosure, an integrated circuit device includes: a backside contact; a first spacer structure and a second spacer structure, which surround a first portion of the backside contact in a first horizontal direction and have a mirror-symmetric shape relative to the backside contact; a gap-filling insulating layer, which surrounds a second portion of the backside contact in a first horizontal direction, the second portion being below the first portion surrounded by the first spacer structure and the second spacer structure; a source / drain connection structure, which is disposed above the backside contact and in contact with the backside contact; a source / drain region, which is electrically connected to the backside contact through the source / drain connection structure; a plurality of gate lines, which are spaced apart from the source / drain region; and a gate dielectric layer, which is disposed between the source / drain region and the plurality of gate lines. The first spacer structure and the second spacer structure separate the backside contact from the gate dielectric layer, and the backside contact has a first horizontal width at the upper portion, which is greater than the second horizontal width at the lower portion.

[0009] According to an embodiment of the present disclosure, an integrated circuit device includes: a plurality of device isolation layers extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a gap-filling insulating layer disposed between two adjacent device isolation layers among the plurality of device isolation layers; at least one nanosheet disposed on the gap-filling insulating layer, spaced apart from a top surface of the gap-filling insulating layer in a vertical direction and facing the top surface of the gap-filling insulating layer; a gate line surrounding the at least one nanosheet on the gap-filling insulating layer and extending longitudinally in a second horizontal direction; a gate dielectric layer surrounding the gate line and separating the at least one nanosheet from the gate line; a source / drain region adjacent to the gate line on the gap-filling insulating layer and in contact with the at least one nanosheet; a source / drain connection structure in contact with a bottom surface of the source / drain region and including a first semiconductor layer and a second semiconductor layer; a backside contact extending in a vertical direction from the bottom surface of the gap-filling insulating layer and covering a first portion of a bottom surface of the source / drain connection structure; and a first spacer structure and a second spacer structure. In the cross-sectional view, each of the first spacer structure and the second spacer structure has a triangular shape and includes: a first surface, which is arranged between the back contact and the gap filling insulating layer and covers a second portion of the bottom surface of the source / drain connection structure, the second portion being the remaining portion of the bottom surface not covered by the back contact; and a second surface, which contacts the side wall of the back contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 is a plan layout diagram of a unit block of an integrated circuit device according to an embodiment of the present disclosure.

[0012] Figure 2 is a plan layout diagram showing an integrated circuit device according to an embodiment of the present disclosure.

[0013] Figure 3A It is along Figure 2 A cross-sectional view taken along line X1-X1'.

[0014] Figure 3B It is along Figure 2 A cross-sectional view taken along line Y1-Y1'.

[0015] Figure 3C yes Figure 3A An enlarged cross-sectional view of area EX2 in FIG.

[0016] Figure 4 yes Figure 3A An enlarged cross-sectional view of area EX2 in FIG.

[0017] Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig.10 , Fig.11A , Fig. 11B , Fig.12 , Fig.13 , Fig.14 , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18 , Fig.19 , Fig. 20A , Fig. 20B , Fig.21A and Fig.21B is a diagram illustrating a method of manufacturing an integrated circuit device according to an embodiment of the present disclosure.

[0018] Specifically, Figure 5 , Fig. 7A , Fig. 8A , Fig.9A , Fig.11A , Fig.12 , Fig.13 , Fig.14 , Fig.15A , Fig.16A , Fig.17A , Fig.18 , Fig.19 , Fig. 20A and Fig.21A is shown with Figure 2 The cross section X1-X1' corresponds to a diagram of the manufacturing process of the part, and Figure 6 , Figure 7B , Figure 8B , Fig. 9B , Fig.10 , Fig. 11B , Fig. 15B , Fig. 16B , Fig. 17B , Fig. 20B and Fig.21B is shown with Figure 2 The cross section Y1 - Y1 ′ corresponds to a diagram of the manufacturing process of the part. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

[0020] The present disclosure includes various embodiments, and some specific embodiments will be shown in the drawings and described in detail. However, this is not intended to limit the scope of the present disclosure to these specific embodiments, but should be understood to include changes, equivalents or substitutes within the scope of the disclosed concepts and technologies.

[0021] Figure 1 is a plan layout diagram of a unit block 12 of an integrated circuit device 10 according to an embodiment of the present disclosure.

[0022] Reference Figure 1 The cell block 12 of the integrated circuit device 10 may include a plurality of logic cells LC including circuit patterns for configuring various circuits. The plurality of logic cells LC may be arranged in a matrix form along a first horizontal direction (X direction) and a second horizontal direction (Y direction) within the cell block 12.

[0023] The plurality of logic cells LC may include a circuit pattern having a layout designed according to a placement and routing (PnR) technique to perform at least one logic function. The plurality of logic cells LC may be configured to perform various logic functions. In some embodiments, the plurality of logic cells LC may include a plurality of standard cells. In some embodiments, at least some of the plurality of logic cells LC may perform the same logic function. In other embodiments, at least some of the plurality of logic cells LC may perform different logic functions.

[0024] The plurality of logic cells LC may include various types of logic cells including a plurality of circuit elements. For example, the plurality of logic cells LC may include an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, an XNOR gate, an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), a multiplexer (MXT / MXIT), an OR / AND / inverter (OAI), an AND / OR (AO) gate, an AND / OR / inverter (AOI), a D flip-flop, a reset flip-flop, a master-slave flip-flop, a latch, or a combination thereof, but is not limited thereto.

[0025] In the cell block 12, at least some of the plurality of logic cells LC forming a row ROW1, ROW2, ROW3, ​​ROW4, ROW5, or ROW6 in the first horizontal direction (X direction) may have the same width. In addition, at least some of the plurality of logic cells LC constituting a row ROW1, ROW2, ROW3, ​​ROW4, ROW5, or ROW6 may have the same height. However, the technical concept of the present disclosure is not limited to Figure 1 , and at least some of the plurality of logic cells LC constituting a row ROW1, ROW2, ROW3, ​​ROW4, ROW5, or ROW6 may have different widths and heights.

[0026] The region of each of the plurality of logic cells LC included in the cell block 12 of the integrated circuit device 10 may be defined by a cell boundary CBD. Among the plurality of logic cells LC, a cell upper contact CBC where the respective cell boundaries CBD intersect may be included between two logic cells LC adjacent to each other in the first horizontal direction (X direction) or the second horizontal direction (Y direction).

[0027] In some embodiments, for a plurality of logic cells LC forming a row ROW1, ROW2, ROW3, ​​ROW4, ROW5, or ROW6, two logic cells LC adjacent to each other in the first horizontal direction may contact each other at the cell upper contact CBC without any spacing distance therebetween. In other embodiments, for a plurality of logic cells LC forming a row ROW1, ROW2, ROW3, ​​ROW4, ROW5, or ROW6, two adjacent logic cells LC adjacent to each other in the first horizontal direction (X direction) may be spaced apart from each other by a predetermined spacing distance.

[0028] In some embodiments, for a plurality of logic cells LC forming a row ROW1, ROW2, ROW3, ​​ROW4, ROW5, or ROW6, two adjacent logic cells LC adjacent to each other may perform the same function. In this case, the two adjacent logic cells LC may have substantially the same structure. In other embodiments, for a plurality of logic cells LC forming a row ROW1, ROW2, ROW3, ​​ROW4, ROW5, or ROW6, two adjacent logic cells LC adjacent to each other may perform different functions.

[0029] In some embodiments, any one logic cell LC selected from among the plurality of logic cells LC included in the cell block 12 of the integrated circuit device 10 and the second horizontal direction ( Figure 1 Another logic cell LC adjacent to the selected logic cell LC in the Y direction (in the Y direction of the reference logic cell LC_R) of the third row ROW3 and the lower logic cell LC_L in the second row ROW2 may have a symmetrical structure with respect to the upper cell contact CBC located therebetween. Similarly, the reference logic cell LC_R in the third row ROW3 and the upper logic cell LC_H in the fourth row ROW4 may have a symmetrical structure with respect to the upper cell contact CBC located therebetween.

[0030] Figure 1 The cell block 12 including six rows ROW1, ROW2, ROW3, ​​ROW4, ROW5, and ROW6 is shown, but this is only an example. The cell block 12 may include various numbers of rows selected as needed, and a row may include various numbers of logic cells selected as needed.

[0031] One ground line VSS selected from the plurality of ground lines VSS and one power line VDD selected from the plurality of power lines VDD may be arranged respectively between a plurality of rows ROW1, ROW2, ROW3, ​​ROW4, ROW5, and ROW6 including a plurality of logic cells LC arranged in a row along a first horizontal direction (X direction). The plurality of ground lines VSS and the plurality of power lines VDD may extend in the first horizontal direction (X direction) and may be spaced apart from each other in a second horizontal direction (Y direction). Therefore, each of the plurality of ground lines VSS and the plurality of power lines VDD may be arranged to overlap with a cell boundary CBD of the logic cell LC in the second horizontal direction (Y direction).

[0032] Figure 2 1 is a plan view showing an integrated circuit device 10 according to an embodiment of the present disclosure. Specifically, Figure 2 yes Figure 1 A magnified view of area EX1. Figure 3A It is along Figure 2A cross-sectional view taken along line X1-X1'. Figure 3B It is along Figure 2 A cross-sectional view taken along line Y1-Y1'. Figure 3C yes Figure 3A An enlarged cross-sectional view of area EX2 in FIG.

[0033] Reference Figure 2 and FIG. 3A to FIG. 3C An integrated circuit device 10 is described, including a field effect transistor (FET) having an active region in the shape of a nanowire or a nanosheet and a gate-all-around structure including a gate surrounding the active region. For example, the integrated circuit device 10 may include a multi-bridge channel FET (MBCFET) device. However, the technical concept of the present disclosure is not limited thereto, and the integrated circuit device 10 may include a planar FET device, a finFET device, and similar structures. The integrated circuit device 10 may be configured Figure 1 Some of the multiple logic cells LC are shown in FIG.

[0034] The integrated circuit device 10 includes a backside structure BSS and a frontside structure FSS disposed on the backside structure BSS. In some embodiments, the backside structure BSS includes a plurality of fin-type active regions F1, a plurality of device isolation layers 112 extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, a backside contact DBC disposed between the plurality of device isolation layers 112, a spacer structure 198a (or referred to as a first spacer structure or a left spacer structure) and a spacer structure 198b (or referred to as a second spacer structure or a right spacer structure) contacting an upper sidewall of the backside contact DBC, a gap-filling insulating layer 192 surrounding the backside contact DBC, a lower wiring layer M2 disposed on a rear surface 192B of the gap-filling insulating layer 192, and a lower insulating layer 199. The gap-filling insulating layer 192 is spaced apart from the backside contact DBC (e.g., an upper portion of the backside contact DBC) by the first spacer structure 198a and the second spacer structure 198b.

[0035] In some embodiments, the front side structure FSS is disposed on the front side surface 192F of the gap-filling insulating layer 192 and includes a plurality of nanosheet stacks NSS, a plurality of gate lines 160 disposed on the gap-filling insulating layer 192 and extending longitudinally in a second horizontal direction, a source / drain region SD disposed between adjacent gate lines among the plurality of gate lines 160, a source / drain connection structure CCS disposed below the source / drain region SD and including a first source / drain connection structure and a second source / drain connection structure, an insulating liner 142 disposed above the source / drain region SD, and a gate-to-gate insulating layer 144.

[0036] The front side structure FSS of the integrated circuit device 10 may include an active structure. The active structure may include a conductive channel region in which carriers (electrons or holes) flow and switching operations occur in a transistor device. For example, the active structure may have a fin shape, a nanowire shape, or a nanosheet shape. Although the active structure is FIG. 3A to FIG. 3C , it is shown as a nanosheet stack NSS, but the active structure is not limited thereto.

[0037] Each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing the front surface 192F of the gap-filling insulating layer 192 in the vertical direction (Z direction) at a position spaced apart from the front surface 192F of the gap-filling insulating layer 192. In an embodiment of the present specification, the term "nanosheet" may refer to a conductive structure having a cross-section substantially perpendicular to a current flow direction. The nanosheet may include a nanowire.

[0038] Each of the plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3, which are vertically stacked and overlap each other in the vertical direction (Z direction). The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 are located at different vertical distances (distances in the Z direction) from the front surface 192F of the gap-filling insulating layer 192. Each of the plurality of gate lines 160 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, which are included in the nanosheet stack NSS and overlap each other in the vertical direction (Z direction).

[0039] although Figure 2 The planar shape of the nanosheet stack NSS is shown as an approximate rectangle, but the embodiment is not limited to the rectangular shape. The nanosheet stack NSS may have other planar shapes corresponding to the planar shape of each of the plurality of gate lines 160. In this example, a plurality of nanosheet stacks NSS and a plurality of gate lines 160 are arranged on the gap-filling insulating layer 192, and the plurality of nanosheet stacks NSS are arranged in one line along the first horizontal direction (X direction) on the gap-filling insulating layer 192. However, the number of nanosheet stacks NSS and gate lines 160 arranged on the gap-filling insulating layer 192 may vary and is not limited to a specific value.

[0040] Each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may be used as a channel region. In some embodiments, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have a thickness selected from about 4 nanometers (nm) to about 6nm. However, the thickness is not limited thereto. Here, the thickness of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 represents a size in the vertical direction (Z direction). According to an embodiment, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have substantially the same thickness in the vertical direction (Z direction). Optionally, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different thicknesses in the vertical direction (Z direction). According to an embodiment, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may include a Si layer, a SiGe layer, or a combination thereof.

[0041] like Figure 3A As shown in , the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS may have the same or similar size in the first horizontal direction (X direction). However, in other embodiments, at least one of the plurality of nanosheets included in one nanosheet stack NSS may have a different size in the first horizontal direction (X direction). This embodiment shows that each of the plurality of nanosheet stacks NSS includes three nanosheets, but the number of nanosheets constituting the nanosheet stack NSS may vary and is not limited to a specific value.

[0042] like Figure 3A As shown in , the gate line 160 may extend longitudinally in the second horizontal direction (Y direction) and surround the plurality of nanosheet stacks NSS on the gap-filling insulating layer 192. The gate lines 160 may be parallel to each other. Each gate line 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M extends longitudinally in the Y direction and covers the top surface of the nanosheet stack NSS. The plurality of sub-gate portions 160S may be integrally connected to the main gate portion 160M, and the plurality of sub-gate portions 160S may be arranged between the first nanosheet N1 and the second nanosheet N2, between the second nanosheet N2 and the third nanosheet N3, and between the third nanosheet N3 and the gap-filling insulating layer 192, respectively. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 160S may be smaller than the thickness of the main gate portion 160M.

[0043] Each gate line 160 may include a metal, a metal nitride, a metal carbide layer, or a combination of these materials. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be TiN or TaN, and the metal carbide layer may be TiAlC. However, other materials may also be used for the gate line 160.

[0044] The gate dielectric layer 152 is disposed between the nanosheet stack NSS and the gate line 160. The gate dielectric layer 152 may have a stacked structure including an interface dielectric layer and a high dielectric layer. The interface dielectric layer may include a low dielectric material having a dielectric constant of about 9 or less (such as silicon oxide, silicon oxynitride, or a combination thereof). In some embodiments, the interface dielectric layer may be omitted. The high dielectric layer is made of a material having a dielectric constant higher than that of silicon oxide (ranging from about 10 to about 25). The high dielectric layer may include hafnium oxide, but other materials may also be used.

[0045] Both sidewalls of each sub-gate portion 160S of the gate line 160 may be spaced apart from the source / drain region SD, and the gate dielectric layer 152 is located between both sidewalls of each sub-gate portion 160S of the gate line 160 and the source / drain region SD. The gate dielectric layer 152 is disposed between the sub-gate portion 160S and each of the nanosheets (N1, N2, N3), and between the sub-gate portion 160S and the source / drain region SD.

[0046] In some embodiments, each of the gate dielectric layer 152 and the gate line 160 may include a portion overlapping the plurality of nanosheet stacks NSS, and the gate dielectric layer 152 may include a portion contacting the plurality of nanosheet stacks NSS.

[0047] According to an embodiment, a plurality of transistors may be formed in a portion where each of the nanosheet stack NSS, the gate line 160, and the gate dielectric layer 152 is stacked. The transistors may include a PMOS transistor and an NMOS transistor. Each transistor may include at least one nanosheet stack NSS, a gate dielectric layer 152, a gate line 160 surrounding the nanosheet stack NSS, and a source / drain region SD facing the nanosheet stack NSS in a first horizontal direction (X direction).

[0048] In some embodiments, each of the plurality of nanosheet stacks NSS may include an undoped Si layer. In other embodiments, each nanosheet stack NSS may include a doped Si layer. For a PMOS transistor, the nanosheet stack NSS may include a Si layer doped with a p-type dopant, such as boron (B) or gallium (G). In some examples, for an NMOS transistor, the nanosheet stack NSS may include a Si layer doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). However, embodiments of the present disclosure are not limited thereto.

[0049] A top surface of each of the gate dielectric layer 152 and the gate line 160 may be covered by a capping insulating pattern 168 , and the capping insulating pattern 168 may include a silicon nitride layer or a silicon oxide layer.

[0050] Both sidewalls of each gate line 160 and both sidewalls of the capping insulating pattern 168 may be covered by an outer insulating spacer 118. The outer insulating spacer 118 covers both sidewalls of the main gate portion 160M on the top surface of each of the plurality of nanosheet stacks NSS. The outer insulating spacer 118 is spaced apart from the gate line 160, and the gate dielectric layer 152 is located between the outer insulating spacer 118 and the gate line 160.

[0051] like Figure 3B As shown in FIG. 1 , a plurality of recessed side insulating spacers 119 covering sidewalls of the source / drain regions SD may be disposed on a top surface of the device isolation layer 112. In some embodiments, each of the plurality of recessed side insulating spacers 119 may be integrally connected to an adjacent outer insulating spacer 118.

[0052] Each of the plurality of outer insulating spacers 118 and the plurality of recessed side insulating spacers 119 may include silicon nitride, a silicon oxide layer, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination of these materials. The terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein represent materials including the elements mentioned in each term, and do not represent chemical formulas having a stoichiometric relationship.

[0053] A metal silicide layer 172 may be formed on the top surface of each of the plurality of source / drain regions SD. The metal silicide layer 172 may include a metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide layer 172 may include titanium silicide, but is not limited to this material.

[0054] The plurality of source / drain regions SD, the plurality of metal silicide layers 172, and the plurality of outer insulating spacers 118 may be covered by the insulating liner 142. In some embodiments, the insulating liner 142 may be omitted. The inter-gate insulating layer 144 may be disposed on the insulating liner 142. When the insulating liner 142 is omitted, the inter-gate insulating layer 144 may be in direct contact with the plurality of source / drain regions SD.

[0055] The insulating liner 142 and the inter-gate insulating layer 144 may be sequentially arranged on the plurality of source / drain regions SD and the plurality of metal silicide layers 172. The insulating liner 142 and the inter-gate insulating layer 144 may together constitute an insulating structure. In some embodiments, the insulating liner 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination of these materials, but is not limited to these options. The inter-gate insulating layer 144 may include a silicon oxide layer, but is not limited to this material.

[0056] like Figure 3A and Figure 3B As shown in , a plurality of source / drain connection structures CCS are arranged below the source / drain region SD. Each source / drain connection structure CCS is arranged below the corresponding source / drain region SD and contacts the corresponding source / drain region SD. The insulating liner 142 and the inter-gate insulating layer 144 are sequentially arranged above each source / drain region SD. This configuration results in the source / drain region SD being located between the insulating liner 142 and the source / drain connection structure CCS, and between the inter-gate insulating layer 144 and the source / drain connection structure CCS.

[0057] The arrangement of the source / drain connection structure CCS may vary according to the embodiment. In some embodiments, the source / drain connection structure CCS is disposed between adjacent nanosheet stacks NSS spaced apart in a first horizontal direction (X direction). In other embodiments, the source / drain connection structure CCS is located between adjacent device isolation layers 112 spaced apart in a second horizontal direction (Y direction). Furthermore, in some embodiments, the source / drain connection structure CCS is located between adjacent recessed side insulating spacers 119 spaced apart in the Y direction.

[0058] The source / drain connectors of the plurality of source / drain connection structures CCS may include a first semiconductor layer 132 and a second semiconductor layer 134. The first semiconductor layer 132 conformally extends along the sidewalls and the bottom surface of the second semiconductor layer 134. The first semiconductor layer 132 and the second semiconductor layer 134 are in contact with the source / drain region SD together. A portion of the first semiconductor layer 132 is arranged between the second semiconductor layer 134 and the back contact DBC, separating the second semiconductor layer 134 from the back contact DBC. In another embodiment, a portion of the first semiconductor layer 132 is arranged between the second semiconductor layer 134 and the gap-filling insulating layer 192, separating the second semiconductor layer 134 from the top surface 192F of the gap-filling insulating layer 192.

[0059] In some embodiments, the first semiconductor layer 132 and the second semiconductor layer 134 may include a silicon layer or a SiGe layer. As used herein, the term "SiGe" refers to a material composed of elemental silicon and germanium, and does not indicate a specific stoichiometric relationship. For example, the first semiconductor layer 132 and the second semiconductor layer 134 may include a single crystal silicon layer, a polycrystalline silicon layer, an amorphous silicon layer, a single crystal SiGe layer, a polycrystalline SiGe layer, or an amorphous SiGe layer. In some embodiments, the first semiconductor layer 132 may include a silicon layer, and the second semiconductor layer 134 may include a SiGe layer. In other embodiments, both the first semiconductor layer 132 and the second semiconductor layer 134 may include a SiGe layer, but the proportion of Ge contained in the first semiconductor layer 132 and the second semiconductor layer 134 may be different.

[0060] like Figure 3A As shown in FIG. 1 , a plurality of gate lines 160 may be arranged on a top surface 192F of a gap-filling insulating layer 192. The gap-filling insulating layer 192 may cover at least a portion of a bottom surface of a lowermost portion of the gate dielectric layer 152. In addition, the gap-filling insulating layer 192 may be arranged between a plurality of device isolation layers 112 spaced apart from each other.

[0061] In some embodiments, the gap-filling insulating layer 192 may include silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination of these materials, but is not limited thereto. The terms "SiV", "SiO", "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein represent materials including the elements mentioned in each term and do not represent chemical formulas having a stoichiometric relationship. In other embodiments, the gap-filling insulating layer 192 may include a low dielectric layer. The low dielectric layer may be fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon oxide, porous organic silicate glass, spin-on organic polymer dielectrics, spin-on silicon-based polymer dielectrics, or a combination of these materials, but is not limited to these examples.

[0062] In some embodiments, the back side contact DBC may be arranged below a source / drain connection structure CCS selected from a plurality of source / drain connection structures CCS. In the present specification, the source / drain connection structure CCS connected to the back side contact DBC may be defined as a first source / drain connection structure CCS1. In addition, the source / drain connection structure CCS not connected to the back side contact DBC may be defined as a second source / drain connection structure CCS2. The back side contact DBC may extend through the gap-filling insulating layer 192 and contact the first source / drain connection structure CCS1. In some embodiments, the back side contact DBC may include a back side barrier layer 194 and a back side via 196.

[0063] In some embodiments, the backside barrier layer 194 may include a metal or a metal nitride. For example, the backside barrier layer 194 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination of these materials, but is not limited thereto. The backside via 196 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination of these materials, or an alloy containing these materials, but is not limited thereto.

[0064] like Figure 3AAs shown in , the back side contact DBC may contact the spacer structures 198a and 198b and the gap-filling insulating layer 192 in the first horizontal direction (X direction). For example, the spacer structures 198a and 198b may cover the upper sidewalls of the back side contact DBC in the first horizontal direction (X direction), and the gap-filling insulating layer 192 may cover the lower sidewalls of the back side contact DBC in the first horizontal direction (X direction). The spacer structures 198a and 198b may be surrounded by the gate dielectric layer 152, the first source / drain connection structure CCS1, the gap-filling insulating layer 192, and the back side contact DBC. For example, the sidewalls of the spacer structures 198a and 198b may be surrounded by the gap-filling insulating layer 192. In some embodiments, the spacer structures 198a and 198b may include Si. In addition, as Figure 3B As shown in , the back side contact DBC may contact the device isolation layer 112 in the second horizontal direction (Y direction). For example, the device isolation layer 112 may cover the sidewall of the back side contact DBC in the second horizontal direction (Y direction).

[0065] In some embodiments, the spacer structures 198a and 198b may cover a portion of the bottom surface of the lowermost portion of the gate dielectric layer 152. The portion of the bottom surface of the gate dielectric layer 152 covered by the spacer structures 198a and 198b may be adjacent to the backside contact DBC. In some embodiments, the spacer structures 198a and 198b may separate the first source / drain connection structure CCS1 from the gap-filling insulating layer 192. For example, the gap-filling insulating layer 192 may be spaced apart from the first source / drain connection structure CCS1, and the spacer structures 198a and 198b are located between the gap-filling insulating layer 192 and the first source / drain connection structure CCS1. In some embodiments, the spacer structures 198a and 198b may be disposed between the gate dielectric layer 152 and the backside contact DBC, and the backside contact DBC may be spaced apart from the gate dielectric layer 152 by the spacer structures 198a and 198b.

[0066] In some embodiments, the backside contact DBC may cover a portion of the bottom surface of the first source / drain connection structure CCS1, and the spacer structures 198a and 198b may cover the remaining portion of the bottom surface of the first source / drain connection structure CCS1. For example, in a plan view, the backside contact DBC may be surrounded by the area occupied by the first source / drain connection structure CSS1.

[0067] like Figure 3CAs shown in , the spacer structures 198a and 198b may include a left spacer structure 198a formed at the upper left end of the back side contact DBC and a right spacer structure 198b formed at the upper right end of the back side contact DBC. The left spacer structure 198a and the right spacer structure 198b may be symmetrical to each other about the back side contact DBC, but the embodiment is not limited thereto. The spacer structures 198a and 198b may be a portion of the substrate 102 remaining after the etching process for forming the back side contact DBC. The following will refer to Fig.18 and Fig.19 The manufacturing process of the gate protection layer GP is described in detail.

[0068] In some embodiments, the spacer structures 198a and 198b are formed in a triangular shape and surround a portion of the upper sidewalls on both sides of the back side contact DBC. The width of the spacer structures 198a and 198b is defined as the length of the top surface of the spacer structures 198a and 198b in contact with the gate dielectric layer 152 in the first horizontal direction (X direction). The width W1 of the left spacer structure 198a may be the same as the width W2 of the right spacer structure 198b, but other configurations are also feasible. For example, in one embodiment, the spacer structures 198a and 198b may have a third horizontal width in the upper portion and a fourth horizontal width in the lower portion in the first horizontal direction (X direction), and the third horizontal width may be greater than the fourth horizontal width. Figure 3C As shown in FIG. 1 , the triangular shape of the spacer structures 198 a and 198 b may be generated during the wet etching process based on the difference in etching speed of the crystal orientation of the spacer structures 198 a and 198 b (see FIG. 1 ). Fig.18 ). In some embodiments, the width W1 of the spacer structure 198a and the width W2 of the spacer structure 198b may not exceed (approximately) 2 nm, but other dimensions are also possible. The length of the spacer structures 198a and 198b extending in the first horizontal direction (X direction) may depend on the gate line 160 (see Figure 3A ) in the X direction. In some examples, the triangular shape of the spacer structures 198a and 198b can be obtained by an anisotropic etching process, which is affected by different etching rates along various crystal planes, such as the Miller index (111) plane in a cubic crystal system (e.g., silicon). The Miller index (111) plane represents a specific crystal plane in a cubic crystal system (such as the diamond cubic structure found in silicon). The plane can be defined by the intercept of the lattice vector at a unit length along each axis, resulting in a triangular arrangement of atoms on the plane. For example, each of the spacer structures 198a and 198b may include a first surface in contact with a sidewall of the back side contact DBC, a second surface in contact with the gate dielectric layer 152, and a third surface (crystal plane) having a Miller index (111).

[0069] A pair of device isolation layers 112 selected from a plurality of device isolation layers 112 may be spaced apart from each other, and a gap filling insulating layer 192 is located between the pair of device isolation layers 112 selected from a plurality of device isolation layers 112. The device isolation layers 112 extend longitudinally in a first horizontal direction (X direction) and are parallel to each other. The device isolation layers 112 are spaced apart from each other in a second horizontal direction (Y direction). In some embodiments, the device isolation layer 112 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination of these materials. The back side contact DBC is surrounded by the gap filling insulating layer 192 in the first horizontal direction (X direction) and is surrounded by the device isolation layer 112 in the second horizontal direction (Y direction).

[0070] In addition, a pair of device isolation layers 112 selected from the plurality of device isolation layers 112 may be spaced apart from each other, and the fin type active region F1 is located between the pair of device isolation layers 112 selected from the plurality of device isolation layers 112. The plurality of fin type active regions F1 may extend longitudinally in a first horizontal direction (X direction) and may be parallel to each other. The plurality of fin type active regions F1 may be spaced apart from each other in a second horizontal direction (Y direction). The plurality of fin type active regions F1 may include a semiconductor (such as Si or Ge) or a compound semiconductor (such as SiGe, SiC, GaAs, InAs, InGaAs, or InP). The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" used herein represent materials composed of the elements mentioned in each term, and do not represent chemical formulas having a stoichiometric relationship.

[0071] In some embodiments, the gap-filling insulating layer 192 may extend longitudinally in the first horizontal direction (X direction) between the plurality of device isolation layers 112. In other embodiments, the gap-filling insulating layer 192 may extend in the first horizontal direction (X direction) between the plurality of device isolation layers 112, and may contact the fin type active region F1 adjacent to the gap-filling insulating layer 192 in the first horizontal direction (X direction).

[0072] like Figure 3B As shown in , the device isolation layer 112 may cover the sidewalls of the back contact DBC. In some embodiments, the device isolation layer 112 may cover at least a portion of the sidewalls of the source / drain connection structure CCS, and the plurality of recessed side insulating spacers 119 may cover the remaining portion of the sidewalls of the source / drain connection structure CCS. In other embodiments, the device isolation layer 112 may not cover the sidewalls of the source / drain connection structure CCS, but the plurality of recessed side insulating spacers 119 may cover the entire sidewalls of the source / drain connection structure CCS.

[0073] A plurality of source / drain contacts CA may be arranged on the plurality of source / drain regions SD. Each of the plurality of source / drain contacts CA may extend through the inter-gate insulating layer 144 and the insulating liner 142 in the vertical direction (Z direction) to contact the metal silicide layer 172. Each of the plurality of source / drain contacts CA may be configured to be electrically connected to the source / drain region SD through the metal silicide layer 172. Each of the plurality of source / drain contacts CA may be spaced apart from the main gate portion 160M in the first horizontal direction (X direction), and an external insulating spacer 118 is located between each of the plurality of source / drain contacts CA and the main gate portion 160M.

[0074] The plurality of source / drain contacts CA may include a conductive barrier pattern 174 and a contact plug 176 sequentially stacked on the source / drain region SD. The conductive barrier pattern 174 may surround the bottom surface and sidewall of the contact plug 176, and may contact the bottom surface and sidewall of the contact plug 176. Each of the plurality of source / drain contacts CA may extend through the inter-gate insulating layer 144 and the insulating liner 142, and may extend longitudinally in the vertical direction (Z direction). The conductive barrier pattern 174 may be arranged between the metal silicide layer 172 and the contact plug 176. The conductive barrier pattern 174 may have a surface in contact with the metal silicide layer 172 and a surface in contact with the contact plug 176. In some embodiments, the conductive barrier pattern 174 may include a metal or a metal nitride. For example, the conductive barrier pattern 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination of these materials, but is not limited thereto. The contact plug 176 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination of these materials, or an alloy including these materials, but is not limited thereto.

[0075] The top surface of each of the plurality of source / drain contacts CA, the plurality of capping insulating patterns 168, and the gate inter-insulating layer 144 may be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etch stop layer 182 and an interlayer insulating layer 184 sequentially stacked on each of the plurality of source / drain contacts CA, the plurality of capping insulating patterns 168, and the gate inter-insulating layer 144. The etch stop layer 182 may include silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination of these materials. The interlayer insulating layer 184 may include an oxide layer, a nitride layer, an ultra-low k (ULK) layer having an ultra-low dielectric constant K ranging from about 2.2 to about 2.4, or a combination of these materials. For example, the interlayer insulating layer 184 may include a tetraethyl orthosilicate (TEOS) layer, a high density plasma (HDP) oxide layer, a borophosphosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiN layer, a SiOC layer, a SiCOH layer, or a combination of these materials, but is not limited thereto.

[0076] A plurality of source / drain via contacts VA may be arranged on the plurality of source / drain contacts CA, respectively. Each of the plurality of source / drain via contacts VA may extend through the upper insulating structure 180 and contact the source / drain contact CA. Each of the plurality of source / drain regions SD may be constructed to be electrically connected to the source / drain via contact VA through the metal silicide layer 172 and the source / drain contact CA. The bottom surface of each of the plurality of source / drain via contacts VA may contact the top surface of the source / drain contact CA. Each of the plurality of source / drain via contacts VA may include molybdenum (Mo) or tungsten (W), but is not limited to these materials.

[0077] The top surface of each of the upper insulating structure 180 and the plurality of source / drain via contacts VA may be covered by an upper insulating layer 186. The material constituting the upper insulating layer 186 is substantially the same as the material described above with respect to the interlayer insulating layer 184.

[0078] The upper wiring layer M1 may extend through the upper insulating layer 186 to be connected to one source / drain via contact VA selected from among a plurality of source / drain via contacts VA below the upper wiring layer M1. The upper wiring layer M1 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination of these materials, or an alloy containing these materials, but is not limited thereto.

[0079] The bottom surface of each of the device isolation layer 112, the gap-filling insulating layer 192, and the backside contact DBC may be covered by a lower insulating layer 199. The material constituting the lower insulating layer 199 is substantially the same as the material described above with respect to the interlayer insulating layer 184.

[0080] The lower wiring layer M2 may extend through the lower insulating layer 199 to be connected to the backside contact DBC on the upper portion of the lower wiring layer M2. The lower wiring layer M2 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination of these materials, or an alloy including these materials, but is not limited thereto.

[0081] According to an embodiment of the technical concept of the present disclosure, the spacer structures 198 a and 198 b surround both upper sidewalls of the backside contact DBC to prevent unnecessary current from flowing into the source / drain region SD, thereby providing an integrated circuit device with improved reliability.

[0082] Figure 4 is a diagram illustrating an integrated circuit device according to another embodiment of the technical concept of the present disclosure. Figure 4 Shown with Figure 3A The area EX2 corresponds to the part. Figure 4 In, with Figure 2 and FIG. 3A to FIG. 3C Reference numerals with the same reference numerals as those in the figure denote the same elements, and redundant description thereof is omitted here. Figure 2 and FIG. 3A to FIG. 3C The described integrated circuit arrangement 10 differs only slightly in the shape of the backside contact DBC, and this difference is therefore described.

[0083] Reference Figure 4 ,and Figure 3C Differently, the back side contact DBC may be formed such that the area of ​​the uppermost surface of the back side contact DBC is larger than the area of ​​the lowermost surface of the back side contact DBC, resulting in a shape similar to the letter "Y". This may occur during the manufacturing process of the integrated circuit device 10a, and the embodiment is not limited by the shape of the back side contact DBC. For example, in one embodiment, the back side contact DBC may have a first horizontal width at the upper portion and a second horizontal width at the lower portion in the first horizontal direction (X direction), and as shown in FIG. Figure 3C and Figure 4 As shown in , the first horizontal width may be equal to or greater than the second horizontal width.

[0084] In some cases, when the area of ​​the uppermost surface of the back side contact DBC is formed to be larger than the area of ​​the lowermost surface of the back side contact DBC, the spacer structures 198 a and 198 b may not contact the first semiconductor layer 132 .

[0085] In some cases, when the area of ​​the uppermost surface of the backside contact DBC is larger than the area of ​​the lowermost surface of the backside contact DBC, the width W1′ of the spacer structure 198a and the width W2′ of the spacer structure 198b may be comparable. Figure 3C The widths W1 and W2 shown in the figure are small. The widths W1' and W2' are respectively defined as the lengths of the uppermost surfaces of the spacer structures 198a and 198b in contact with the gate dielectric layer 152 in the first horizontal direction (X direction). However, the widths W1' and W2' of the spacer structures 198a and 198b formed on both sides of the backside contact DBC may be adjusted based on the length of the sub-gate portion 160S. The adjustment may be performed within the range of preventing the spacer structures 198a and 198b from overlapping with other spacer structures formed on the upper sidewalls of the adjacent backside contacts DBC.

[0086] Next, a method of manufacturing an integrated circuit device according to an embodiment of the technical concept of the present disclosure is described.

[0087] Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig.10 , Fig.11A , Fig. 11B , Fig.12 , Fig.13 , Fig.14 , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18 , Fig.19 , Fig. 20A , Fig. 20B , Fig.21A and Fig.21B is a diagram illustrating a method of manufacturing an integrated circuit device according to an embodiment in process order.

[0088] Specifically, Figure 5 , Fig. 7A , Fig. 8A , Fig.9A , Fig.11A , Fig.12 , Fig.13 , Fig.14 , Fig.15A , Fig.16A , Fig.17A , Fig.18 , Fig.19 , Fig. 20A and Fig.21A is shown with Figure 2 The cross section X1-X1' corresponds to a diagram of the manufacturing process of the part, and Figure 6 , Figure 7B , Figure 8B , Fig. 9B , Fig.10 , Fig. 11B , Fig. 15B , Fig. 16B , Fig. 17B , Fig. 20B and Fig.21B is shown with Figure 2 The cross section Y1 - Y1 ′ corresponds to a diagram of the manufacturing process of the part.

[0089] exist Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig.10 , Fig.11A , Fig. 11B , Fig.12 , Fig.13 , Fig.14 , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18 , Fig.19 , Fig. 20A , Fig. 20B , Fig.21A and Fig.21B In, with Figure 2 and FIG. 3A to FIG. 3C The same reference numerals as in the figures denote the same components, and their detailed description will be omitted here.

[0090] Reference Figure 5, a plurality of sacrificial semiconductor layers 103 and a plurality of nanosheet semiconductor layers NS may be alternately stacked one after another on a substrate 102. The substrate 102 may include a semiconductor (such as Si or Ge) or a compound semiconductor (such as SiGe, SiC, GaAs, InAs, InGaAs or InP). The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs" and "InP" used herein represent materials composed of the elements mentioned in each term, and do not represent chemical formulas having a stoichiometric relationship. For example, the substrate 102 may be a bulk Si substrate. A stoichiometric relationship represents a quantitative relationship between reactants and products in a balanced chemical reaction. In a stoichiometric relationship, the relative amount of each element or compound may be expressed as an integer ratio. For example, "SiOC" represents a material containing silicon atoms, oxygen atoms and carbon atoms, but the relative proportions of these elements may vary depending on the specific composition and synthesis method. According to an embodiment of the present disclosure, the lack of a stoichiometric relationship indicates that the material does not have to have a fixed chemical formula, and the properties of the material may depend on the specific atomic ratios present.

[0091] The plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS include semiconductor materials having different etching selectivities. In some embodiments, the plurality of nanosheet semiconductor layers NS are made of Si, and the plurality of sacrificial semiconductor layers 103 may include SiGe layers. In some embodiments, the Ge content in the plurality of sacrificial semiconductor layers 103 may be constant throughout the layer. The specific Ge content in the SiGe layer of the sacrificial semiconductor layer 103 may be selected based on the desired etching selectivity.

[0092] like Figure 6 As shown in Figure 5 After forming a mask pattern MP1 on the structure, a fin-type active region F1 is formed on the substrate 102. This is accomplished by etching the sacrificial semiconductor layer 103, the nanosheet semiconductor layer NS, and portions of the substrate 102 using the mask pattern MP1 as an etching mask. The etching process defines a plurality of trench regions T1 on the substrate 102 separated by the fin-type active region F1. In some embodiments, the mask pattern MP1 has a stacked structure including an oxide layer pattern and a silicon nitride layer pattern. The mask patterns MP1 extend parallel to each other in a first horizontal direction (X direction) on the substrate 102. After the etching process, a stacked structure including the sacrificial semiconductor layer 103 and the remaining portions of the nanosheet semiconductor layer NS exists on the top surface FT of each fin-type active region F1.

[0093] Thereafter, a device isolation insulating layer P112 may be formed on the obtained resultant product. The device isolation insulating layer P112 may be formed to have a thickness sufficient to fill the remaining space of the plurality of trench regions T1 on the upper portion of the substrate 102. The device isolation insulating layer P112 may include a silicon oxide layer.

[0094] The device isolation insulating layer P112 may be formed using plasma enhanced chemical vapor deposition (PECVD), high density plasma CVD (HDP-CVD), inductively coupled plasma CVD (ICP-CVD), capacitor coupled plasma CVD (CCP), flowable chemical vapor deposition (FCVD), spin coating, and other methods.

[0095] Reference Fig. 7A and Figure 7B , in the right Figure 6 After the resulting product is planarized until the top surface of the mask pattern MP1 is exposed, a device isolation layer 112 may be formed by performing a recess process to remove the exposed mask pattern MP1 and a portion of the device isolation insulating layer P112. As a result, the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS (see Figure 6 ) may protrude from the top surface of the device isolation layer 112.

[0096] In order to perform the recess process of the device isolation insulating layer P112, dry etching, wet etching, or a combination of dry etching and wet etching can be used. In this case, a wet etching process using NH4OH, tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) or other etchants, or a dry etching process (such as inductively coupled plasma (ICP), transformer coupled plasma (TCP), electron cyclotron resistance (ECR), reactive ion etching (RIE) or similar methods) can be used. When the recess process of the device isolation insulating layer P112 is performed using a dry etching process, a fluorine-containing gas (such as CF4), a chlorine-containing gas (such as Cl2), HBr or a similar gas can be used as an etching gas.

[0097] A plurality of dummy gate structures DGS may be formed on the stacked structure of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS. Each of the plurality of dummy gate structures DGS may be formed to extend longitudinally in the second horizontal direction (Y direction). Each of the plurality of dummy gate structures DGS may have a structure in which an oxide layer D122, a dummy gate layer D124, and a capping layer D126 are sequentially stacked. In some embodiments, the oxide layer D122 may be a layer obtained by oxidizing the surface of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS. The dummy gate layer D124 may include polysilicon, and the capping layer D126 may include a silicon nitride layer.

[0098] After forming a plurality of external insulating spacers 118 covering the sidewalls of the oxide layer D122 and the dummy gate layer D124 in the plurality of dummy gate structures DGS, the plurality of dummy gate structures DGS and the plurality of external insulating spacers 118 may be used as etching masks to partially etch each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS. The process divides the plurality of nanosheet semiconductor layers NS into a plurality of nanosheet stacks NSS, each of which includes a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. In order to partially etch each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS, the etching may be performed using dry etching, wet etching, or a combination of these methods.

[0099] Thereafter, a first recess R1 may be formed by etching a portion of the fin type active region F1 exposed by etching a portion of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS. To form the first recess R1, etching may be performed using dry etching, wet etching, or a combination of these methods. After forming the first recess R1, a plurality of recess side insulating spacers 119 may be formed on the device isolation layer 112 adjacent to the first recess R1.

[0100] In some embodiments, the etching process for forming the first recess R1 may be performed until the bottom of the first recess R1 is at the same level as the top surface of the trench region T1 defining the fin type active region F1 in the vertical direction (Z direction). However, this is only an example, and the bottom of the first recess R1 may be at a height higher or lower than the height of the top surface of the trench region T1 defining the fin type active region F1.

[0101] Reference Fig. 8A and Figure 8B , a sacrificial insulating spacer 128 extending along the sidewalls of the capping layer D126, the sidewalls of the plurality of external insulating spacers 118, and the sidewalls of the plurality of nanosheet stacks NSS may be formed. The sacrificial insulating spacer 128 may extend to cover the sidewalls of the plurality of nanosheet stacks NSS. Fig. 7A and Figure 7B The resulting product exposes the top surface of the fin-type active region F1.

[0102] For example, the sacrificial insulating spacers 128 may include a silicon nitride layer. The sacrificial insulating spacers 128 may be deposited by various methods such as PECVD, HDPCVD, ICP CVD, CCP CVD, FCVD, and a spin coating process.

[0103] Thereafter, the portion of the sacrificial insulating spacer 128 extending along the inner wall of the first recess R1 may be removed, and a position retainer PH filling the first recess R1 may be formed. In some embodiments, the position retainer PH may include a SiGe layer. For example, the position retainer PH may include a single crystal SiGe layer, a polycrystalline SiGe layer, an amorphous SiGe layer, or a combination of these layers.

[0104] In some embodiments, the position retainer PH may be deposited using a raw material including an elemental precursor by various methods such as a PECVD process, an HDP CVD process, an ICP CVD process, a CCP CVD process, and an FCVD process. In other embodiments, in order to form the position retainer PH, a raw material including an elemental semiconductor precursor may be used to perform an LPCVD process, a SEG process, or a CDE process. The elemental semiconductor precursor may include a Si source including Si. Silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), and similar materials may be used as Si sources, but embodiments are not limited to these materials. In addition, the elemental semiconductor precursor may include a Ge source including Ge. Germane (GeH4), digermane (Ge2H6), trigermane (Ge3H8), tetragermane (Ge4H10), dichlorogermane (Ge2H2Cl2), and similar materials may be used as Ge sources, but embodiments are not limited to these materials. For example, the position retainer PH may be formed by epitaxially growing a SiGe layer from the surface of the fin type active region F1 exposed at the sidewall and the bottom of the first recess R1 In this case, the position retainer PH may include a single crystal SiGe layer.

[0105] In some embodiments, the Ge content in the place keeper PH may be constant. The Ge content in the SiGe layer constituting the place keeper PH may be selected within a range in which the etching selectivity between the place keeper PH and the fin type active region F1 is different.

[0106] Reference Fig.9A and Fig. 9B , a plurality of source / drain connection structures CCS may be formed after selectively removing the sacrificial insulating spacers 128. The sacrificial insulating spacers 128 may be selectively removed using a liquid etchant or a gas etchant. In some embodiments, in order to selectively remove the sacrificial insulating spacers 128, a CH3COOH-based etchant (such as an etchant including a mixture of CH3COOH, HNO3, and HF, or an etchant including a mixture of CH3COOH, H2O2, and HF) may be used, but the etchant is not limited to these examples.

[0107] Each of the plurality of source / drain connection structures CCS may include a first semiconductor layer 132 and a second semiconductor layer 134. The first semiconductor layer 132 and the second semiconductor layer 134 may include a single crystal layer, a polycrystalline layer, or an amorphous layer. The first semiconductor layer 132 and the second semiconductor layer 134 may include a Si layer or a SiGe layer. In some embodiments, the first semiconductor layer 132 may include a Si layer, and the second semiconductor layer 134 may include a SiGe layer.

[0108] The first semiconductor layer 132 and the second semiconductor layer 134 may be sequentially deposited using a raw material including an elemental precursor by various methods such as a PECVD process, an HDP CVD process, an ICP CVD process, a CCP CVD process, and an FCVD process. For example, the first semiconductor layer 132 may be formed by epitaxially growing a Si layer or a SiGe layer from a surface of the fin type active region F1, a surface of the position holder PH, and a sidewall of the nanosheet stack NSS. The second semiconductor layer 134 may be formed by epitaxially growing a SiGe layer from an inner surface of the first semiconductor layer 132.

[0109] Reference Fig.10 , available in Fig.9A and Fig. 9B A plurality of source / drain regions SD are formed on the resulting product.

[0110] In order to form a plurality of source / drain regions SD, the Fig.9A and Fig. 9B A semiconductor material is epitaxially grown on a surface of the source / drain connection structure CCS on the resultant product and a sidewall of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS.

[0111] Reference Fig.11A and Fig. 11B , forming coverage Fig.10 The insulating liner 142 of the resulting product is formed, and the gate insulating layer 144 is formed on the insulating liner 142. Then, a portion of each of the insulating liner 142 and the gate insulating layer 144 is etched to expose the top surface of the plurality of capping layers D126. Thereafter, the dummy gate layer D124 may be exposed by removing the plurality of capping layers D126, and the insulating liner 142 and the gate insulating layer 144 may be partially removed, so that the top surface of the gate insulating layer 144 and the top surface of the dummy gate layer D124 are at approximately the same height.

[0112] Reference Fig.12 , which can be obtained by Fig.11A and Fig. 11BThe dummy gate layer D124 and the lower oxide layer D122 are removed from the resulting product to provide a gate space GS, and the plurality of nanosheet stacks NSS can be exposed through the gate space GS. Thereafter, the plurality of sacrificial semiconductor layers 103 can be removed through the gate space GS to extend the gate space GS to the space between the first nanosheet N1 and the second nanosheet N2, between the second nanosheet N2 and the third nanosheet N3, and between the first nanosheet N1 and the top surface of the fin-type active region F1. In some embodiments, the difference in etching selectivity between the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the plurality of sacrificial semiconductor layers 103 can be used to selectively remove the plurality of sacrificial semiconductor layers 103.

[0113] In order to selectively remove the plurality of sacrificial semiconductor layers 103, a liquid etchant or a gas etchant may be used. In some embodiments, in order to selectively remove the plurality of sacrificial semiconductor layers 103, a CH3COOH-based etchant (such as an etchant including a mixture of CH3COOH, HNO3, and HF, or an etchant including a mixture of CH3COOH, H2O2, and HF) may be used, but the etchant is not limited to these examples.

[0114] Reference Fig.13 ,from Fig.12 The resulting product may form a gate dielectric layer 152 covering the exposed surface of each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fin type active region F1. The gate dielectric layer 152 may be formed using an atomic layer deposition (ALD) process.

[0115] Reference Fig.14 , a gate line 160 is formed to fill a portion of the gate space GS on the gate dielectric layer 152, and to fill the gate space GS between the first nanosheet N1 and the second nanosheet N2, between the second nanosheet N2 and the third nanosheet N3, and between the first nanosheet N1 and the top surface of the fin-type active region F1 (see Fig.13 ). In addition, a capping insulating pattern 168 is formed to cover top surfaces of both the gate line 160 and the gate dielectric layer 152 in the gate space GS.

[0116] Reference Fig.15A and Fig. 15B , by Fig.14The structure of the gate electrode 140 extends through the insulating structure including the insulating liner 142 and the inter-gate insulating layer 144 to form a source / drain contact hole (not shown) exposing the source / drain region SD. Next, a partial region of the source / drain region SD is removed by an anisotropic etching process through the source / drain contact hole, so that the source / drain contact hole extends in the vertical direction (Z direction). Next, a metal silicide layer 172 is formed on the source / drain region SD exposed by the bottom of the source / drain contact hole. In some embodiments, in order to form the metal silicide layer 172, a process involving forming a metal liner (not shown) that conformally covers the exposed surface of the source / drain region SD and causing a reaction between the source / drain region SD and the metal constituting the metal liner by heat treatment is included. Once the metal silicide layer 172 is formed, the remaining portion of the metal liner is removed. During the formation of the metal silicide layer 172, a portion of the source / drain region SD may be consumed. In some embodiments, when the metal silicide layer 172 includes a titanium silicide layer, the metal liner layer may include a Ti layer.

[0117] Subsequently, source / drain contacts CA including a conductive barrier pattern 174 and a contact plug 176 are formed on the metal silicide layer 172 .

[0118] Reference Fig.16A and Fig. 16B ,from Fig.15A and Fig. 15B Starting from the structure of the gate insulating layer 144, an etch stop layer 182 and an interlayer insulating layer 184 covering the top surface of the gate insulating layer 144, a plurality of source / drain contacts CA, and a plurality of insulating patterns 168 are sequentially formed to produce an upper insulating structure 180. Subsequently, a plurality of source / drain via contacts VA connected to the plurality of source / drain contacts CA are formed by extending through the upper insulating structure 180 in the vertical direction (Z direction).

[0119] Thereafter, an upper insulating layer 186 covering the upper insulating structure 180 and an upper wiring layer M1 extending through the upper insulating layer 186 and connected to the source / drain via contacts VA may be formed.

[0120] Reference Fig.17A and Fig. 17B , you can Fig.16A and Fig. 16B The resultant product is arranged such that the rear surface 102B of the substrate 102 faces upward and the front surface 102F of the substrate 102 faces downward. Thereafter, a chemical mechanical polishing process may be performed on the rear surface 102B of the substrate 102 to expose the place holder PH.

[0121] Reference Fig.18 , optionally remove the surrounding Fig.17A and Fig. 17BIn order to selectively remove the fin type active region F1 around the position holder PH, the difference in etching selectivity between the fin type active region F1, the position holder PH and the gate dielectric layer 152 may be used. For example, a wet etching process may be performed to selectively remove the fin type active region F1 around the exposed position holder PH.

[0122] In this case, a portion of the fin type active region F1 may be retained after the selective removal process of the fin type active region F1, forming the spacer structure 198. For example, when an etching process is performed using KOH, NHOH4, or TMAH, because the etching speed of a crystal surface in a specific direction (for example, a crystal surface in the (111) direction) is different from the etching speed of crystal surfaces in other directions, the spacer structure 198 may have an angular shape. For these reasons, the spacer structure 198 may be retained by being formed in a triangular shape surrounding the position retainer PH. The spacer structure 198 may be formed in a symmetrical shape on both side walls of the position retainer PH. The sidewalls of the spacer structure 198 may be in contact with the position retainer PH, and the bottom surface of the spacer structure 198 may be in contact with the gate dielectric layer 152.

[0123] Reference Fig.19 , which can be accessed through Fig.18 The resulting product selectively removes the fin type active area F1 around the exposed position holder PH ( Fig.17A , Fig. 17B and Fig.18 ) is formed in a space created by the gap-filling insulating layer 192. To form the gap-filling insulating layer 192, various methods (such as a PVD process, a CVD process, or an ALD process) may be used.

[0124] Thereafter, a chemical mechanical polishing process may be performed on the top surface of the gap-filling insulating layer 192 to planarize the top surface of the gap-filling insulating layer 192 .

[0125] Reference Fig. 20A and Fig. 20B , an etching process for removing the position retaining member PH may be performed to Fig.19 The back contact hole BCH is formed in the resultant product. The etching process for removing the position holder PH may be a selective etching process using the position holder PH including a material different from that of the gap-fill insulating layer 192. For example, RIE may be performed to remove the position holder PH. The sidewall of the spacer structure 198 may be exposed by removing the position holder PH.

[0126] The second recess R2 may be formed at a position where the position holder PH is removed, and the source / drain connection structure CCS may be exposed through a bottom surface of the second recess R2 .

[0127] Reference Fig.21A and Fig.21B , a backside contact DBC may be formed inside the second recess R2. The backside contact DBC may include a backside barrier layer 194 and a backside via 196. After the backside barrier layer 194 is formed to conformally extend along the inner wall of the second recess R2, the backside via 196 may be sequentially formed on the backside barrier layer 194. The backside barrier layer 194 and the backside via 196 may be deposited using CVD or ALD, and various processes may be used to deposit the backside barrier layer 194 and the backside via 196.

[0128] Thereafter, a lower insulating layer 199 covering the backside contact DBC, the gap-filling insulating layer 192 , and the plurality of device isolation layers 112 , and a lower wire layer M2 extending through the lower insulating layer 199 and connected to the backside contact DBC may be formed.

[0129] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: a plurality of device isolation layers extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a gap-filling insulating layer, disposed between the plurality of device isolation layers; a plurality of gate lines disposed on the gap-filling insulating layer and extending longitudinally in a second horizontal direction; a plurality of source / drain regions disposed between adjacent gate lines among the plurality of gate lines; A plurality of source / drain connection structures, disposed below the plurality of source / drain regions, the plurality of source / drain connection structures comprising a first source / drain connection structure and a second source / drain connection structure; a backside contact extending through the gap-fill insulating layer in a third direction perpendicular to the first horizontal direction and the second horizontal direction and connected to the first source / drain connection structure; as well as The first spacer structure and the second spacer structure are in contact with the upper sidewall of the backside contact, The first spacer structure and the second spacer structure are arranged between the gap-filling insulating layer and the first source / drain connection structure.

2. The integrated circuit device according to claim 1, wherein: The first spacer structure and the second spacer structure include silicon.

3. The integrated circuit device according to claim 1, wherein: The first spacer structure and the second spacer structure have a triangular shape and surround a portion of the upper sidewall on both sides of the backside contact.

4. The integrated circuit device according to claim 1, wherein: The first spacer structure and the second spacer structure have a mirror-symmetrical shape with respect to the backside contact.

5. The integrated circuit device according to claim 1, wherein: The first spacer structure and the second spacer structure include a crystal plane having a Miller index of 111.

6. The integrated circuit device according to claim 1, further comprising: A gate dielectric layer is disposed between the source / drain region and the plurality of gate lines, wherein the first spacer structure and the second spacer structure are disposed between the gate dielectric layer and the backside contact, and The backside contact is spaced apart from the gate dielectric layer by the first spacer structure and the second spacer structure.

7. The integrated circuit device according to claim 1, wherein: A backside contact covers a first portion of a bottom surface of the first source / drain connection structure, and The first spacer structure and the second spacer structure cover a second portion of the bottom surface of the first source / drain connection structure, wherein the second portion of the bottom surface of the first source / drain connection structure is a remaining portion of the bottom surface of the first source / drain connection structure not covered by the backside contact.

8. The integrated circuit device according to claim 1, wherein: Each of the plurality of source / drain connection structures comprises: a first semiconductor layer; and The second semiconductor layer has side walls and a bottom surface, wherein the first semiconductor layer surrounds the side walls and the bottom surface of the second semiconductor layer.

9. The integrated circuit device according to claim 1, wherein: The gap-fill insulating layer includes a silicon oxide layer, and The gap-fill insulation layer surrounds sidewalls of the first spacer structure and the second spacer structure.

10. The integrated circuit device according to claim 1, wherein: An uppermost surface of each of the first and second spacer structures has a length in the first horizontal direction of no more than 2 nanometers.

11. The integrated circuit device according to claim 1, wherein: In plan view, the backside contact is surrounded by the area occupied by the first source / drain connection structure.

12. An integrated circuit device comprising: Back side contact; a first spacer structure and a second spacer structure surrounding a first portion of the backside contact in a first horizontal direction and having a shape that is mirror-symmetrical with respect to the backside contact; a gap-filling insulating layer surrounding the second portion of the backside contact in a first horizontal direction, the second portion of the backside contact being below the first portion of the backside contact; a source / drain connection structure disposed above the back contact and in contact with the back contact; a source / drain region electrically connected to the backside contact via a source / drain connection structure; a plurality of gate lines spaced apart from the source / drain regions; as well as A gate dielectric layer is disposed between the source / drain region and the plurality of gate lines, wherein the first spacer structure and the second spacer structure separate the backside contact from the gate dielectric layer, and The back side contact has a first horizontal width at an upper portion and a second horizontal width at a lower portion in a first horizontal direction, and the first horizontal width is greater than or equal to the second horizontal width.

13. The integrated circuit device according to claim 12, wherein: Each of the first spacer structure and the second spacer structure comprises: a first surface in contact with a sidewall of the back contact; a second surface in contact with the gate dielectric layer; and The third surface has a Miller index of 111.

14. The integrated circuit device according to claim 12, wherein: The source / drain connection structure includes: a first semiconductor layer; and a second semiconductor layer having sidewalls and a bottom surface, wherein the first semiconductor layer surrounds the sidewalls and the bottom surface of the second semiconductor layer, wherein the first horizontal width is equal to the second horizontal width, and a top surface of the backside contact covers a first portion of a bottom surface of the source / drain connection structure, and Top surfaces of the first and second spacer structures cover a second portion of the bottom surface of the source / drain connection structure, which is a remaining portion of the bottom surface of the source / drain connection structure not covered by the backside contact.

15. An integrated circuit arrangement according to any one of claims 12 to 14, wherein: The first spacer structure and the second spacer structure have a third horizontal width at an upper portion and a fourth horizontal width at a lower portion in the first horizontal direction, and the third horizontal width is greater than the fourth horizontal width.

16. An integrated circuit arrangement according to any one of claims 12 to 14, wherein: The first spacer structure and the second spacer structure include silicon.

17. An integrated circuit device comprising: a plurality of device isolation layers extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a gap-filling insulating layer disposed between two adjacent device isolation layers among the plurality of device isolation layers; at least one nanosheet disposed on the gap-filling insulating layer, spaced apart from a top surface of the gap-filling insulating layer in a vertical direction, and facing the top surface of the gap-filling insulating layer; a gate line surrounding the at least one nanosheet on the gap-filling insulating layer and extending longitudinally in a second horizontal direction; a gate dielectric layer surrounding the gate line and separating the at least one nanosheet from the gate line; a source / drain region adjacent to the gate line on the gap-fill insulating layer and in contact with the at least one nanosheet; a source / drain connection structure in contact with a bottom surface of the source / drain region and comprising a first semiconductor layer and a second semiconductor layer; a backside contact extending in a vertical direction from a bottom surface of the gap-fill insulating layer and covering a first portion of a bottom surface of the source / drain connection structure; as well as a first spacer structure and a second spacer structure, Wherein, in a cross-sectional view, each of the first spacer structure and the second spacer structure has a triangular shape and comprises: a first surface in contact with the gate dielectric layer and covering a second portion of the bottom surface of the source / drain connection structure, the second portion of the bottom surface of the source / drain connection structure being a remaining portion of the bottom surface of the source / drain connection structure not covered by the backside contact; and The second surface contacts the sidewall of the back contact.

18. The integrated circuit device according to claim 17, wherein: Each of the first spacer structure and the second spacer structure further includes a crystal plane having a Miller index of 111.

19. An integrated circuit device according to claim 17 or 18, wherein: The first spacer structure and the second spacer structure have a mirror-symmetrical shape with respect to the backside contact.

20. The integrated circuit device according to claim 17 or 18, wherein: The first spacer structure and the second spacer structure include silicon.

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