Power half-bridge packaging structure and electronic equipment

Abstract

The invention provides a power half-bridge packaging structure and electronic equipment, and relates to the field of semiconductors, and the power half-bridge packaging structure comprises at least one single-core power half-bridge. An upper tube ceramic substrate, an upper tube chip, an upper tube D terminal, a lower tube S terminal, a lower tube chip, an alternating current connecting copper bar and a lower tube ceramic substrate in each single-core power half bridge are arranged in an up-and-down lamination mode, and the up-and-down lamination mode effectively shortens the distance between conductive parts. Therefore, the parasitic inductance of the device and the whole power system is obviously reduced, the problems of energy loss, signal distortion, electromagnetic interference and the like are reduced, and the improvement of the efficiency and the reliability of the system is further promoted.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power half-bridge packaging structure and electronic equipment. Background Art

[0002] Power semiconductor devices are semiconductor devices that can withstand large currents and high voltages. They are mainly used for high-power (usually referring to currents of tens to thousands of amperes and voltages of hundreds of volts or more) electronic devices in power conversion and power control circuits.

[0003] Figure 1 The figure is a schematic diagram of a packaging design scheme of a power semiconductor device in the prior art. Figure 1 In which 0101 refers to a base plate, 0102 refers to an insulating film, 0110 refers to a semiconductor, 0111 refers to a control terminal, 0112 refers to a second power terminal, 0120 refers to a substrate, 0130 refers to a supporting surface, 0140 refers to a package body, 0141 refers to a first opening, 0142 refers to a second opening, 0150 refers to a bonding wire, 0160 refers to a top side connection layer, and 0160' refers to a bottom side connection layer.

[0004] Figure 1 In the technical solution shown, the packaging structure of the power semiconductor device does not adopt an upper and lower stacked packaging design, so that the parasitic inductance generated when the terminals are connected is relatively high. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a power half-bridge packaging structure with a stacked design to reduce its designed inductance.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A power half-bridge packaging structure, comprising:

[0008] At least one single-core power half-bridge;

[0009] The single-core power half-bridge comprises:

[0010] An upper tube ceramic substrate, the upper tube ceramic substrate comprising: an upper tube ceramic substrate second copper clad layer, an upper tube ceramic substrate ceramic layer disposed on the upper tube ceramic substrate second copper clad layer, and an upper tube ceramic substrate first copper clad layer disposed on a side of the upper tube ceramic substrate ceramic layer away from the upper tube ceramic substrate second copper clad layer;

[0011] An upper tube chip is arranged on the first copper-clad layer of the upper tube ceramic substrate;

[0012] An upper tube D-pole terminal connected to the upper tube chip through the first copper-clad layer of the upper tube ceramic substrate, and the upper tube D-pole terminal is used to be connected to the positive electrode of an external power supply;

[0013] A lower tube S-pole connecting conductor is arranged on a side of the first copper-clad layer of the upper tube ceramic substrate away from the second copper-clad layer of the upper tube ceramic substrate through an insulating layer;

[0014] A lower tube S terminal connected to the lower tube S-pole connecting conductor, the lower tube S terminal being used to be connected to the negative electrode of an external power supply, and the lower tube S terminal being stacked with the upper tube D terminal;

[0015] A lower tube chip disposed on a side of the lower tube S-pole connecting conductor away from the second copper-clad layer of the upper tube ceramic substrate;

[0016] A lower tube ceramic substrate, the lower tube ceramic substrate comprising a lower tube ceramic substrate second copper clad layer, a lower tube ceramic substrate ceramic layer arranged on a side of the lower tube ceramic substrate second copper clad layer facing the upper tube ceramic substrate second copper clad layer, and a lower tube ceramic substrate first copper clad layer arranged on a side of the lower tube ceramic substrate ceramic layer away from the lower tube ceramic substrate second copper clad layer, wherein the lower tube ceramic substrate first copper clad layer and a side of the lower tube chip away from the upper tube ceramic substrate second copper clad layer are welded to each other;

[0017] The side of the upper tube chip away from the second copper clad layer of the upper tube ceramic substrate is connected to the first copper clad layer of the lower tube ceramic substrate through the upper tube S-pole connecting conductor;

[0018] An AC connecting copper busbar connected to the first copper-clad layer of the lower tube ceramic substrate.

[0019] Optionally, in the above power half-bridge packaging structure, the area where the upper tube chip is not connected to the first copper-clad layer of the upper tube ceramic substrate and the upper tube S-pole connecting conductor is covered with an insulating layer;

[0020] The area of ​​the lower tube chip that is not connected to the first copper-clad layer of the lower tube ceramic substrate and the lower tube S-pole connecting conductor is covered with an insulating layer.

[0021] Optionally, in the above power half-bridge packaging structure, each of the single-core power half-bridges shares an upper tube D terminal, a lower tube S terminal and an AC connection copper busbar.

[0022] Optionally, the above power half-bridge packaging structure includes:

[0023] The D-pole connection impedance of the upper tube chip of each single-core power half-bridge is equal;

[0024] The S-pole connection impedance of the upper tube chip of each single-core power half-bridge is equal;

[0025] The D-pole connection impedance of the lower tube chip of each single-core power half-bridge is equal;

[0026] The S-pole connection impedance of the lower tube chip of each single-core power half-bridge is equal.

[0027] Optionally, the above power half-bridge packaging structure includes:

[0028] The upper tube D terminal and the lower tube S terminal are distributed on a first side of the power half-bridge package structure, and the AC connection copper bus is arranged on a second side of the power half-bridge package structure, wherein the first side and the second side are symmetrical sides of the power half-bridge package structure;

[0029] The monitoring terminals and the temperature detection element of the power half-bridge packaging structure are arranged on the third side or the fourth side of the power half-bridge packaging structure, and the first side, the second side, the third side and the fourth side are the four sides of the power half-bridge packaging structure.

[0030] Optionally, in the above power half-bridge packaging structure, the monitoring terminal includes:

[0031] An upper tube D pole detection terminal, an upper tube G pole terminal, an upper tube S pole terminal, a lower tube G pole terminal, a lower tube S pole terminal, a first temperature detection terminal and a second temperature detection terminal;

[0032] The first temperature detection terminal and the second temperature detection terminal are respectively connected to the input end and the output end of the temperature detection element, and are used to provide a temperature detection signal to an external detection unit.

[0033] Optionally, the above power half-bridge packaging structure further includes:

[0034] Top tube radiator and down tube radiator;

[0035] The upper tube radiator is arranged on a side of the second copper-clad layer of the upper tube ceramic substrate away from the lower tube ceramic substrate;

[0036] The lower tube radiator is arranged on a side of the second copper-clad layer of the lower tube ceramic substrate away from the upper tube ceramic substrate.

[0037] Optionally, in the above power half-bridge packaging structure, the lower tube S-pole connecting conductor and the upper tube S-pole connecting conductor are flexible layer connecting conductors.

[0038] An electronic device comprises a power device formed by any one of the power half-bridge packaging structures described above. The electronic device is a car.

[0039] Based on the above technical solution, the power half-bridge packaging structure provided by the embodiment of the present invention includes at least one single-core power half-bridge. The upper tube ceramic substrate, upper tube chip, upper tube D terminal, lower tube S terminal, lower tube chip, AC connection copper bus and lower tube ceramic substrate in each single-core power half-bridge are arranged in an up-down stacking manner, thereby realizing efficient stacking of conductive components. This design method not only optimizes the performance and efficiency of the system, but also significantly improves the space utilization and integration. Through precise manufacturing and assembly processes, each conductive component is precisely stacked together to form a continuous conductive path, ensuring the physical and electrical integrity of the stacked structure. It not only helps to reduce the volume and weight of the system, but also enhances the connection reliability and stability between conductive components. More importantly, the up-down stacking method effectively shortens the distance between conductive components, thereby significantly reducing the parasitic inductance of the device itself and the entire power system, reducing energy loss, signal distortion and electromagnetic interference, and further promoting the improvement of system efficiency and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0041] Figure 1 A schematic diagram of a design scheme of a power semiconductor device package and a power system disclosed in the prior art;

[0042] Figure 2 A circuit topology diagram of an existing inverter main power system;

[0043] Figure 3 is the circuit symbol of IGBT;

[0044] Figure 4 It is a schematic diagram of the chip structure of IGBT;

[0045] Figure 5 is the electrical symbol of MOSFET;

[0046] Figure 6 It is a schematic diagram of the chip structure of MOSFET;

[0047] Figure 7 A cross-sectional view of a single-core power half-bridge in a power half-bridge packaging structure disclosed in an embodiment of the present application;

[0048] Figure 8 This is a schematic diagram of the structure of the power half-bridge packaging structure disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] First, the relevant terms in this application are explained:

[0051] Power electronic device: A device composed of power semiconductor devices, passive devices (inductors, capacitors), structural parts, heat dissipation systems and control devices that can transform and control electrical energy.

[0052] Power system: A system composed of high-voltage and high-power parts in a power electronic converter device, mainly including power semiconductor devices, passive devices (inductors or capacitors), and electrical connection components (such as copper busbars, wires, etc.).

[0053] Power semiconductor chip: Made of semiconductor materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), etc., it can achieve conversion and control of electric energy by fast switching on and off. It mainly includes IGBT (generally made of Si), MOSFET (generally made of Si, SiC, GaN), diode (made of Si or SiC), etc. This application refers to it as "chip".

[0054] Power semiconductor packaging: Power semiconductor chips cannot be used directly. They must be installed in a module through a series of processes to achieve functions such as connection between chips, electrical connection of chips to the outside, heat dissipation of chips, and protection of chips (insulation, waterproof, dustproof, anti-oxidation, and anti-mechanical damage). The structural form of this module is called power semiconductor packaging. It is referred to as "packaging" in this application.

[0055] Power semiconductor device: A module consisting of a power semiconductor chip and a power semiconductor package is called a power semiconductor device. This application refers to it as a "device".

[0056] Inverter: A power electronic device that converts DC power into AC power. Its main power system is as follows: Figure 2 shown. Figure 2 The left side is the DC input of the inverter, which is usually a DC power source such as a battery. Figure 2AC output on the right. The inverter consists of a three-phase inverter bridge arm. Power semiconductor devices S1 and S2 (MOSFET shown in the figure) form the A-phase inverter bridge arm. S1 is the upper tube of the inverter bridge arm, and the D pole of S1 is connected to the DC+ bus; S2 is the lower tube of the inverter bridge arm, and the S pole of S2 is connected to the DC- bus. Point A is the connection point between the S pole of S1 and the D pole of S2, which is the AC output point of the A-phase inverter bridge arm; S1 and S2 are alternately and complementary turned on, and AC voltage can be output at point A. Similarly, the working principles of phases B and C are the same.

[0057] IGBT: Insulated Gate Bipolar Transistor is a power semiconductor device, its symbol is as follows Figure 3 and Figure 4 As shown. IGBT has three terminals, namely the collector (C), emitter (E) and gate (G). When the voltage between the G and E poles exceeds a certain value (threshold voltage), the IGBT is turned on and the current can flow from the C pole to the E pole, but it cannot conduct in the reverse direction. In order to provide a reverse conduction path for the IGBT, a diode is generally connected in reverse parallel to the IGBT.

[0058] MOSFET: Metal Oxide Semiconductor FET is a power semiconductor device, its symbol is as follows Figure 5 and Figure 6 As shown. MOSFET has three terminals, namely the drain (D), source (S) and gate (G). When the voltage between the G and S poles exceeds a certain value (threshold voltage), the MOSFET is turned on and the current can flow from the D pole to the S pole. Due to the structure of the MOSFET, it has a parasitic diode, so whether the MOSFET is in the on state or not, the current can flow from the S pole to the D pole.

[0059] See also Figure 7 and Figure 8 , the present application discloses a power semiconductor device, comprising:

[0060] At least one single-core power half-bridge 100;

[0061] The single-core power half-bridge 100 comprises:

[0062] An upper tube ceramic substrate, the upper tube ceramic substrate comprising: an upper tube ceramic substrate second copper clad layer 121, an upper tube ceramic substrate ceramic layer 119 disposed on the upper tube ceramic substrate second copper clad layer 121, and an upper tube ceramic substrate first copper clad layer 118 disposed on a side of the upper tube ceramic substrate ceramic layer 119 away from the upper tube ceramic substrate second copper clad layer 121;

[0063] An upper tube chip 107 disposed on the first copper clad layer 118 of the upper tube ceramic substrate;

[0064] An upper tube D-pole terminal 102 connected to the upper tube chip 107 through the first copper-clad layer 118 of the upper tube ceramic substrate, and the upper tube D-pole terminal 102 is used to be connected to the positive electrode of an external power supply;

[0065] A lower tube S-pole connecting conductor 111 is provided on a side of the first copper-clad layer 118 of the upper tube ceramic substrate away from the second copper-clad layer 121 of the upper tube ceramic substrate through an insulating layer 108;

[0066] A lower tube S-pole terminal 103 connected to the lower tube S-pole connecting conductor 111, the lower tube S-pole terminal 103 is used to be connected to the negative electrode of an external power supply, and the lower tube S-pole terminal 103 is stacked with the upper tube D-pole terminal 102;

[0067] A lower tube chip 115 disposed on a side of the lower tube S-pole connecting conductor 111 away from the second copper cladding layer 121 of the upper tube ceramic substrate;

[0068] A lower tube ceramic substrate, the lower tube ceramic substrate comprising a lower tube ceramic substrate second copper clad layer 124, a lower tube ceramic substrate ceramic layer 123 arranged on a side of the lower tube ceramic substrate second copper clad layer 124 facing the upper tube ceramic substrate second copper clad layer, and a lower tube ceramic substrate first copper clad layer 120 arranged on a side of the lower tube ceramic substrate ceramic layer 123 away from the lower tube ceramic substrate second copper clad layer 124, the lower tube ceramic substrate first copper clad layer 120 and a side of the lower tube chip 115 away from the upper tube ceramic substrate second copper clad layer 121 are welded to each other;

[0069] The side of the upper tube chip 107 away from the second copper clad layer 121 of the upper tube ceramic substrate is connected to the first copper clad layer 120 of the lower tube ceramic substrate through the upper tube S-pole connecting conductor 110;

[0070] An AC connecting copper bus 117 connected to the first copper cladding layer 120 of the lower tube ceramic substrate.

[0071] The design of the stacked arrangement of the lower tube S terminal 103 and the upper tube D terminal 102 facilitates the integration of the power half-bridge packaging structure with an external power supply, bus capacitors, etc., ensures the integrity of the stacked part of the system design, and further reduces the parasitic inductance of the power integration system; the copper busbar connection in this design scheme adopts welding, and the welding process is easy to implement, which reduces the difficulty of power system design and simplifies the production process.

[0072] In the above structure, the upper tube D-pole terminal 102, the sintered silver welding area 105, and the first copper-clad layer 118 of the upper tube ceramic substrate together constitute the upper tube D-pole path 126 of the upper tube chip D-pole, the sintered silver welding area 106, the upper tube S-pole connecting conductor 110, and the sintered silver welding area 112 together constitute the upper tube S-pole path 127 of the upper tube chip S-pole connected to the D-pole of the lower tube chip 115, and similarly, the lower tube chip D-pole path 129 is composed of the sintered silver welding area 113, the first copper-clad layer 120 of the lower tube ceramic substrate, and the AC connection copper bus 117, and the lower tube chip S-pole path 128 is composed of the lower tube S-pole terminal 103, the sintered silver welding area 104, the lower tube S-pole connecting conductor 111, and the sintered silver welding area 114, and is connected to the outside through 103. The midpoint of the inverter bridge arm is connected to the outside through the AC connection copper bus 117.

[0073] As can be seen from the above structure, the above packaging structure is mainly divided into two layers, the lower layer is connected to the positive pole of the external power supply through the upper tube D terminal 102, flows back to the negative pole of the external power supply through the lower tube S terminal 103, and is connected to the outside through the AC connection copper bus 117. Arranged up and down in a three-dimensional space, the electromagnetic fields generated can offset each other, reducing the parasitic inductance of the entire power half-bridge.

[0074] As can be seen from the above scheme, the power half-bridge packaging structure disclosed in the above embodiment of the present application includes at least one single-core power half-bridge. The upper tube ceramic substrate, upper tube chip, upper tube D terminal, lower tube S terminal, lower tube chip, AC connection copper bus and lower tube ceramic substrate in each single-core power half-bridge are arranged in an up-down stacking manner, realizing efficient stacking of conductive components. This design method not only optimizes the performance and efficiency of the system, but also significantly improves the space utilization and integration. Through precise manufacturing and assembly processes, each conductive component is precisely stacked together to form a continuous conductive path, ensuring the physical and electrical integrity of the stacked structure. It not only helps to reduce the volume and weight of the system, but also enhances the connection reliability and stability between conductive components. More importantly, the up-down stacking method effectively shortens the distance between conductive components, thereby significantly reducing the parasitic inductance of the device itself and the entire power system, reducing energy loss, signal distortion and electromagnetic interference, and further promoting the improvement of system efficiency and reliability.

[0075] In this embodiment, in order to ensure the reliability of the power half-bridge packaging structure and prevent the upper tube chip 107 and the lower tube chip 115 in the power half-bridge packaging structure from short circuiting, see Figure 7 , the area where the upper tube chip 107 is not connected to the first copper cladding layer 118 of the upper tube ceramic substrate and the upper tube S-pole connecting conductor 110 is covered with an insulating layer; the area where the lower tube chip 115 is not connected to the first copper cladding layer 120 of the lower tube ceramic substrate and the lower tube S-pole connecting conductor 111 is covered with an insulating layer. In this application, the material of the insulating layer can be selected according to the design requirements, as long as electrical isolation can be achieved. For example, in this solution, the material of the insulating layer can be polyimide, which has high dielectric strength and good electrical insulation performance, can effectively prevent current leakage and electromagnetic interference, and ensure the safety and reliability of the chip.

[0076] Figure 6 In the figure, 108, 109, and 116 are all insulating layers. In the present embodiment, the material of the insulating layers can be polyimide. The insulating layer 109 serves to insulate and protect the upper tube chip 107, the insulating layer 116 serves to insulate and protect the lower tube chip 115, and the insulating layer 108 serves to insulate and protect 110 and 111.

[0077] In the technical solution disclosed in this embodiment, the power half-bridge packaging structure may include a plurality of single-core power half-bridges, and the structure of each single-core power half-bridge may be as follows: Figure 7 As shown, further, the arrangement of each single-core power half-bridge can be set according to user design requirements, such as Figure 8 As shown, each single-core power half-bridge can share the same upper tube D terminal, lower tube S terminal and AC connection copper bus.

[0078] In the technical solution disclosed in this embodiment, in order to improve the consistency of each of the single-core power half-bridges, it is necessary to keep the relevant impedances of each single-core power half-bridge equal, and these relevant impedances may include; the D-pole connection impedance of the upper tube chip, the S-pole connection impedance of the upper tube chip, the D-pole connection impedance of the lower tube chip and the S-pole connection impedance of the lower tube chip, that is, the D-pole connection impedance of the upper tube chip of each single-core power half-bridge is equal; the S-pole connection impedance of the upper tube chip of each single-core power half-bridge is equal; the D-pole connection impedance of the lower tube chip of each single-core power half-bridge is equal; and the S-pole connection impedance of the lower tube chip of each single-core power half-bridge is equal.

[0079] In this embodiment, the D-pole connection impedance of the upper tube chips of each single-core power half-bridge can be made equal by making the distance of the upper tube D-pole path 126 of the upper tube chips in all single-core power half-bridges equal, see Figure 5The upper tube D-pole path 126 is composed of 102, 105 (the connection area between the upper tube chip and the first copper clad layer of the upper tube ceramic substrate) and 118. In order to achieve the same length of the upper tube chip upper tube D-pole path 126 of each single-core power half-bridge, it is necessary to make the length of the upper tube D-pole terminal in each single-core power half-bridge equal, the size of the connection area between the upper tube chip in each single-core power half-bridge and the first copper clad layer of the upper tube ceramic substrate equal (in the following Table 1, the upper tube chip and the first copper clad layer of the upper tube ceramic substrate are welded by sintering silver), and the length of the first copper clad layer of the upper tube ceramic substrate in each single-core power half-bridge is equal.

[0080] In this embodiment, the S-pole connection impedance of the upper tube chip of each single-core power half-bridge can be made equal by making the distance of the S-pole path 127 of the upper tube chip in all single-core power half-bridges equal, see Figure 5 The upper tube chip S-pole path 127 is composed of 106 (the connection area between the upper tube S-pole connecting conductor and the upper tube chip), 110 and 112 (the connection area between the upper tube S-pole connecting conductor and the first copper cladding layer of the lower tube ceramic substrate). In order to make the length of the upper tube chip S-pole path 127 of each single-core power half-bridge equal, it is necessary to make the length of the upper tube S-pole connecting conductor in each single-core power half-bridge equal, the size of the connection area between the upper tube S-pole connecting conductor in each single-core power half-bridge and the upper tube chip the same, and the size of the connection area between the upper tube S-pole connecting conductor in each single-core power half-bridge and the first copper cladding layer of the lower tube ceramic substrate the same.

[0081] In this embodiment, the D-pole connection impedance of the lower tube chip of each single-core power half-bridge can be made equal by making the distance of the lower tube D-pole path 129 of the lower tube chip in all single-core power half-bridges equal, see Figure 5 The lower tube D-pole path 129 is composed of 113 (the connection area between the lower tube chip and the first copper-clad layer of the lower tube ceramic substrate), 120 and 117. In order to achieve the same length of the upper tube D-pole path 129 of the lower tube chip of each single-core power half-bridge, it is necessary to make the size of the connection area between the lower tube chip and the first copper-clad layer of the lower tube ceramic substrate in each single-core power half-bridge equal (in the following Table 1, the lower tube chip and the first copper-clad layer of the lower tube ceramic substrate are welded by sintering silver), the length of the first copper-clad layer of the lower tube ceramic substrate in each single-core power half-bridge is equal, and the length of the AC connection copper busbar in each single-core power half-bridge is equal.

[0082] In this embodiment, the S-pole connection impedance of the lower tube chip of each single-core power half-bridge can be made equal by making the distance of the S-pole path 128 of the lower tube chip in all single-core power half-bridges equal, see Figure 5The lower tube chip S-pole path 128 is composed of 103, 104 (the connection area between the lower tube S-pole connecting conductor and the lower tube S-pole terminal), 111 and 114 (the connection area between the lower tube chip and the lower tube S-pole connecting conductor). In order to make the length of the lower tube chip S-pole path 128 of each single-core power half-bridge equal, it is necessary to make the length of the lower tube S-pole terminal in each single-core power half-bridge equal, the size of the connection area between the lower tube S-pole connecting conductor and the lower tube S-pole terminal the same, the length of the lower tube S-pole connecting conductor is equal, and the size of the connection area between the lower tube chip and the lower tube S-pole connecting conductor is the same.

[0083] By configuring the upper tube D-pole path 126, the upper tube chip S-pole path 127, the lower tube chip S-pole path 128 and the lower tube D-pole path 129 in the above manner, a balanced design of the chip parallel electrical connection impedance is achieved, thereby improving the current sharing consistency between each single-core power half-bridge.

[0084] In the technical solution disclosed in this embodiment, in order to facilitate the connection between the power half-bridge packaging structure and external devices, the distribution positions of each connection terminal in the power half-bridge packaging structure can also be planned. Specifically, the upper tube D terminal and the lower tube S terminal are distributed on the first side of the power half-bridge packaging structure, and the AC connection copper bus is arranged on the second side of the power half-bridge packaging structure, and the first side and the second side are the symmetrical sides of the power half-bridge packaging structure; the monitoring terminal and the temperature detection element of the power half-bridge packaging structure are arranged on the third side or the fourth side of the power half-bridge packaging structure, and the first side, the second side, the third side and the fourth side are the four sides of the power half-bridge packaging structure, and the first side, the second side, the third side and the fourth side form a closed rectangular area.

[0085] In this embodiment, the monitoring terminal includes: an upper tube D pole detection terminal, an upper tube G pole terminal, an upper tube S pole terminal, a lower tube G pole terminal, a lower tube S pole terminal, a first temperature detection terminal and a second temperature detection terminal; wherein the first temperature detection terminal and the second temperature detection terminal are respectively connected to the input end and the output end of the temperature detection element, and are used to provide a temperature detection signal to an external detection unit.

[0086] In this embodiment, if Figure 8 As shown, the monitoring terminals and temperature detection elements of the power half-bridge package structure are arranged on the side of the electrical connection terminals (102, 103 and 117). Figure 8The example shown is that the control monitoring terminal 215 and the temperature detection terminal 214 are on the right side of the electrical connection terminal. The control monitoring terminal 215 is on the right side of the electrical connection terminal. Of course, 214 and 215 can also be located on the left side of the electrical connection terminal at the same time. The control monitoring terminal 215 includes an upper tube D pole detection terminal 202, an upper tube G pole terminal 204, an upper tube S pole terminal 206, a lower tube G pole terminal 208, and a lower tube S pole terminal 210. The first temperature detection terminal 212 and the second temperature detection terminal 213 in the temperature detection terminal 214 are respectively connected to the input end and the output end of the temperature detection element, and are used to provide a temperature detection signal to an external detection unit. These monitoring terminals are led out from the side of the power half-bridge packaging structure, and the side is the third side and the fourth side mentioned above.

[0087] In this embodiment, the material of the lower tube S-pole connecting conductor and the upper tube S-pole connecting conductor can be selected according to design requirements, for example, they can be flexible layer connecting conductors.

[0088] In this embodiment, in order to make the power half-bridge packaging structure have an excellent heat dissipation effect, the power half-bridge packaging structure can adopt a double-sided water cooling design. Figure 7 As shown, the power half-bridge packaging structure further includes an upper tube radiator 122 and a lower tube radiator 125; the upper tube radiator 122 is arranged on a side of the upper tube ceramic substrate away from the lower tube ceramic substrate; the lower tube radiator 125 is arranged on a side of the lower tube ceramic substrate away from the upper tube ceramic substrate. For details, see Figure 7 The heat generated by the upper tube chip 107 and the lower tube chip 115 can be transferred and dissipated through the upper tube radiator 122 and the lower tube radiator 125 at the same time. The main heat dissipation of the upper tube chip 107 is carried out through the upper tube radiator 122, and the secondary heat dissipation path is carried out through the lower tube radiator 125. The main heat dissipation of the lower tube chip 115 is carried out through the lower tube radiator 125, and the secondary heat dissipation path is carried out through the upper tube radiator 122. The double-sided water cooling design makes the external equivalent thermal resistance of the upper and lower chips smaller, and the heat dissipation effect and the chip's current output capacity are effectively improved.

[0089] In a specific embodiment, the components of the power half-bridge packaging structure and the numbers, names and functions of each component are shown in Table 1.

[0090]

[0091]

[0092]

[0093] Table 1

[0094] An electronic device comprises: the power half-bridge packaging structure described in any one of the above items, wherein the electronic device is a household appliance or a car.

[0095] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0096] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusions, and also include other elements not explicitly listed, or also include elements inherent to such articles or equipment. In the absence of further restrictions, the elements defined by the statement "comprises a ..." do not exclude the presence of other identical elements in the articles or equipment that include the elements.

[0097] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0098] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A power half-bridge packaging structure, characterized in that: include: At least one single-core power half-bridge; The single-core power half-bridge comprises: An upper tube ceramic substrate, the upper tube ceramic substrate comprising: an upper tube ceramic substrate second copper clad layer, an upper tube ceramic substrate ceramic layer disposed on the upper tube ceramic substrate second copper clad layer, and an upper tube ceramic substrate first copper clad layer disposed on a side of the upper tube ceramic substrate ceramic layer away from the upper tube ceramic substrate second copper clad layer; An upper tube chip is arranged on the first copper-clad layer of the upper tube ceramic substrate; An upper tube D-pole terminal connected to the upper tube chip through the first copper-clad layer of the upper tube ceramic substrate, and the upper tube D-pole terminal is used to be connected to the positive electrode of an external power supply; A lower tube S-pole connecting conductor is arranged on a side of the first copper-clad layer of the upper tube ceramic substrate away from the second copper-clad layer of the upper tube ceramic substrate through an insulating layer; A lower tube S terminal connected to the lower tube S-pole connecting conductor, the lower tube S terminal being used to be connected to the negative electrode of an external power supply, and the lower tube S terminal and the upper tube D terminal being stacked; A lower tube chip disposed on a side of the lower tube S-pole connecting conductor away from the second copper-clad layer of the upper tube ceramic substrate; A lower tube ceramic substrate, the lower tube ceramic substrate comprising a lower tube ceramic substrate second copper clad layer, a lower tube ceramic substrate ceramic layer arranged on a side of the lower tube ceramic substrate second copper clad layer facing the upper tube ceramic substrate second copper clad layer, and a lower tube ceramic substrate first copper clad layer arranged on a side of the lower tube ceramic substrate ceramic layer away from the lower tube ceramic substrate second copper clad layer, wherein the lower tube ceramic substrate first copper clad layer and a side of the lower tube chip away from the upper tube ceramic substrate second copper clad layer are welded to each other; The side of the upper tube chip away from the second copper clad layer of the upper tube ceramic substrate is connected to the first copper clad layer of the lower tube ceramic substrate through the upper tube S-pole connecting conductor; An AC connecting copper busbar connected to the first copper-clad layer of the lower tube ceramic substrate.

2. The power half-bridge packaging structure according to claim 1, characterized in that: The area of ​​the upper tube chip that is not connected to the first copper-clad layer of the upper tube ceramic substrate and the upper tube S-pole connecting conductor is covered with an insulating layer; The area of ​​the lower tube chip that is not connected to the first copper-clad layer of the lower tube ceramic substrate and the lower tube S-pole connecting conductor is covered with an insulating layer.

3. The power half-bridge packaging structure according to claim 1, characterized in that: Each of the single-core power half-bridges shares an upper tube D terminal, a lower tube S terminal and an AC connection copper busbar.

4. The power half-bridge packaging structure according to claim 1, characterized in that: include: The D-pole connection impedance of the upper tube chip of each single-core power half-bridge is equal; The S-pole connection impedance of the upper tube chip of each single-core power half-bridge is equal; The D-pole connection impedance of the lower tube chip of each single-core power half-bridge is equal; The S-pole connection impedance of the lower tube chip of each single-core power half-bridge is equal.

5. The power half-bridge packaging structure according to claim 1, characterized in that: include: The upper tube D terminal and the lower tube S terminal are distributed on a first side of the power half-bridge package structure, and the AC connection copper bus is arranged on a second side of the power half-bridge package structure, wherein the first side and the second side are symmetrical sides of the power half-bridge package structure; The monitoring terminals and the temperature detection element of the power half-bridge packaging structure are arranged on the third side or the fourth side of the power half-bridge packaging structure, and the first side, the second side, the third side and the fourth side are the four sides of the power half-bridge packaging structure.

6. The power half-bridge packaging structure according to claim 5, characterized in that: The monitoring terminal comprises: An upper tube D pole detection terminal, an upper tube G pole terminal, an upper tube S pole terminal, a lower tube G pole terminal, a lower tube S pole terminal, a first temperature detection terminal and a second temperature detection terminal; The first temperature detection terminal and the second temperature detection terminal are respectively connected to the input end and the output end of the temperature detection element, and are used to provide a temperature detection signal to an external detection unit.

7. The power half-bridge packaging structure according to claim 1, characterized in that: Also includes: upper tube radiator and down tube radiator; The upper tube radiator is arranged on a side of the second copper-clad layer of the upper tube ceramic substrate away from the lower tube ceramic substrate; The lower tube radiator is arranged on a side of the second copper-clad layer of the lower tube ceramic substrate away from the upper tube ceramic substrate.

8. The power half-bridge packaging structure according to claim 1, characterized in that: The lower tube S-pole connecting conductor and the upper tube S-pole connecting conductor are flexible layer connecting conductors.

9. An electronic device, characterized in that: A power device comprising the power half-bridge packaging structure according to any one of claims 1 to 8.

10. The electronic device according to claim 9, characterized in that: The electronic device is a car.

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