PLC task jitter suppression method and system based on switch TDMA
By configuring the TDMA function on the switches of the PLC system, dividing the main task and the low-priority time slice and assigning priority, the impact of low-priority task interruption on the main task performance is solved, and lower task jitter and higher system performance are achieved.
Patent Information
- Application Number
- CN202510225168.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-06-06
AI Technical Summary
In the case of low main task scanning cycle in the existing PLC system, interrupts of low-priority tasks such as TCP/IP communication and Modbus TCP have an impact on the main task performance and jitter, resulting in large task jitter.
By configuring the TDMA function on the switch, the scan period is divided into the main task time slice and the low priority time slice, and each time slice is assigned priority, the network communication frame can only be sent to the CPU within the time slice of the corresponding priority, thereby isolating the main task and the network communication task in time.
It effectively reduces the interference of interrupts on the main task, reduces task jitter, improves system performance, and does not require software intervention to achieve established functions without additional performance consumption.
Smart Images
Figure CN120111010A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a PLC motion control method, and in particular to a PLC task jitter suppression method and system based on switch TDMA. Background Art
[0002] At present, most of the mainstream small PLCs (programmable logic controllers) on the market use ARM chips as the main control. In addition, many chips using the RISC-V instruction set have entered the market. Most of these chips have cache functions, which can reduce access to low-speed storage devices by hitting the cache and improve the efficiency of system operation.
[0003] In actual applications, most of the operating systems of these small PLCs use the Linux real-time kernel version, or lightweight real-time operating systems such as FREERTOS and UCOS. With the improvement of the performance of the main control chip, the performance of the PLC is getting stronger and stronger. The main task scanning cycle can be achieved at 1ms, 500us or even lower, and the task jitter is also getting lower and lower.
[0004] Most of the above PLCs have multi-tasking functions, in which the main task has a higher priority, and other tasks such as TCP / IP communication, modbus TCP, etc. are processed in low-priority tasks. The main task and low-priority tasks run in coordination under the scheduling of Linux or other RTOS, and time-sharing multi-task control is achieved through time slice scheduling and preemption. The real-time performance of the main task, programming convenience and overall system efficiency have been greatly improved compared to traditional single-task PLCs. However, the following problems still exist in this architecture:
[0005] First, as the scanning cycle of the PLC's main task becomes lower and lower, higher requirements are placed on task jitter. Although low-priority tasks such as TCP / IP communication and Modbus TCP cannot interrupt the main task during its execution, the reception interruption caused by the network port communication will interrupt the execution of the main task, affecting the performance and jitter of the main task.
[0006] Taking the ARM core chip and FREERTOS operating system as an example, after the chip MAC receives the network frame and generates a network port receive interrupt, it saves the scene in the IRQ interrupt (it is likely that the FPU floating-point registers will also need to be saved), and finds the corresponding interrupt response function through the interrupt vector table. The interrupt response function will call the operating system interface and add the low-priority communication task (such as TCP / IP task) to the operating system's Ready task list. It will wait for the higher-priority main task to be completed before executing the low-priority communication task.
[0007] The execution time of this process may be between hundreds of nanoseconds and several microseconds, depending on the performance of the main control chip. If multiple network frames are received during the execution of the main task (especially when the PLC is connected to an open network through a switch), it may have a significant impact on the main task, and even cause jitter at the 10us level. In addition, since network interruptions will interrupt the CPU instruction pipeline of the PLC main task, it may also reduce the cache hit rate and affect the performance of the main task. Summary of the invention
[0008] The technical problem to be solved by the present invention is to provide a PLC task jitter suppression method and system based on switch TDMA, which can improve the performance of PLC main tasks and does not generate additional performance consumption, in view of the shortcomings of the existing technology.
[0009] In order to solve the above technical problems, the present invention adopts the following technical solutions.
[0010] A PLC task jitter suppression method based on switch TDMA includes: a time slice division step: dividing a scanning cycle into a main task time slice and a low priority time slice, wherein the main task time slice only allows the main task to run, and the low priority time slice allows the communication task to be processed; a priority control step: assigning corresponding priorities to the time slices divided in the scanning cycle, and network communication frames can be sent to the CPU only in the time slices of corresponding priorities.
[0011] Preferably, in the time slice division step, a reserved time slice is further divided from the scanning cycle, and the reserved time slice is used to separate the main task time slice from the low priority time slice.
[0012] A PLC task jitter suppression system based on switch TDMA includes a time slice allocation module and a priority allocation module, wherein: the time slice allocation module is used to execute a time slice division step, in which the scanning cycle is divided into a main task time slice and a low priority time slice, the main task time slice only allows the main task to run, and the low priority time slice allows the processing of communication tasks; the priority allocation module is used to execute a priority control step, in which a corresponding priority is allocated to the time slice divided in the scanning cycle, and a network communication frame can be sent to the CPU only in the time slice of the corresponding priority.
[0013] Preferably, the time slice allocation module is further used to divide a reserved time slice from the scanning cycle, and the reserved time slice is used to separate the main task time slice from the low priority time slice.
[0014] Preferably, the time slice allocation module divides the scanning period according to user configuration.
[0015] In the PLC task jitter suppression method based on switch TDMA disclosed by the present invention, by configuring the TDMA function of the on-chip switch, a certain time slice is allocated to the main task and the low-priority network communication task. In the main task time slice, the switch will block the network frame and will not send the received network frame to the MAC port of the chip. The network frame will not arrive at the MAC port until the low-priority time slice arrives, and a network reception interruption is generated on the chip. Compared with the prior art, the present invention utilizes the hardware function (TDMA) of the switch to isolate the main task and the network communication task in time, reduce the interference of the interruption to the main task, thereby reducing task jitter and improving system performance. Moreover, the established function can be realized without software intervention, and no additional performance consumption is generated. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a data flow diagram of an on-chip switch that implements the PLC task jitter suppression method;
[0017] Figure 2 It is a schematic diagram of time slices divided according to the scanning cycle of the present invention. DETAILED DESCRIPTION
[0018] The present invention is described in more detail below with reference to the accompanying drawings and embodiments.
[0019] The present invention discloses a PLC task jitter suppression method based on switch TDMA, combined with Figure 1 and Figure 2 As shown, it includes:
[0020] Time slice division step: dividing the scanning cycle into a main task time slice and a low priority time slice, wherein the main task time slice only allows the main task to run, and the low priority time slice allows the communication task to be processed;
[0021] Priority control steps: assign corresponding priorities to the time slices divided within the scan cycle, and the network communication frame can be sent to the CPU only within the time slices of the corresponding priority.
[0022] Furthermore, in the time slice division step, a reserved time slice is also divided from the scanning cycle, and the reserved time slice is used to separate the main task time slice from the low priority time slice.
[0023] In the above method, by configuring the TDMA function of the on-chip switch, a certain time slice is allocated to the main task and the low-priority network communication task. In the main task time slice, the switch will block the network frame and will not send the received network frame to the MAC port of the chip. The network frame will not arrive at the MAC port until the low-priority time slice arrives, and a network reception interruption is generated on the chip. Compared with the prior art, the present invention utilizes the hardware function (TDMA) of the switch to isolate the main task and the network communication task in time, reduce the interference of the interruption to the main task, thereby reducing task jitter and improving system performance. Moreover, the established function can be realized without software intervention, and no additional performance consumption is generated.
[0024] In practical applications, the present invention can optimize the jitter of the PLC main task and improve the performance of the PLC main task. It has a better effect on PLCs with higher performance. For example, the scanning cycle of some high-performance PLCs can reach 125 microseconds. At this time, jitter at the microsecond or even 10 microsecond level will have a greater impact on the system. However, after adopting the technical solution of the invention, the problem is better solved.
[0025] To implement the above method, the present invention proposes a PLC task jitter suppression system based on switch TDMA, which includes a time slice allocation module and a priority allocation module, wherein:
[0026] The time slice allocation module is used to perform a time slice division step, in which the scanning cycle is divided into a main task time slice and a low priority time slice, wherein the main task time slice only allows the main task to run, and the low priority time slice allows the communication task to be processed;
[0027] The priority allocation module is used to execute a priority control step. In the priority control step, corresponding priorities are allocated to time slices divided within a scanning cycle, and network communication frames can be sent to the CPU only within time slices of corresponding priorities.
[0028] Furthermore, the time slice allocation module is further used to divide a reserved time slice from the scanning cycle, and the reserved time slice is used to separate the main task time slice from the low priority time slice.
[0029] In a preferred embodiment of the present invention, a time slice allocation module, a priority allocation module, and a runtime TDMA module are included. Specifically:
[0030] Time slice allocation module: according to the scanning cycle of the main task and user configuration, the scanning cycle is divided into several parts. The first part is the main task time slice, the second part is the low priority task time slice, and the third part is the reserved time slice.
[0031] Priority allocation module: responsible for allocating respective priorities to the time slices of the scanning cycle. Network communication frames can be sent to the CPU only within the time slices of the corresponding priority.
[0032] Runtime TDMA module: It is a function on the switch peripheral of the chip. After the user configures the time slice and priority, TDMA can run automatically and decide when to send the network frame of the corresponding priority to the MAC module according to the time slice.
[0033] As a preferred implementation, the time slice allocation module divides the scanning period according to user configuration.
[0034] In a preferred embodiment of the present invention, the time slice allocation module needs to be determined according to the scanning cycle of the main task and the time allocation of the PLC main task by the user. Figure 2 The main task time slice needs to consider the user's requirements for the main task load. If the user has a low load requirement, the main task time slice ratio can be set lower accordingly. If the load is heavy, the corresponding ratio needs to be increased. The low-priority task time slice needs to consider the communication task load. If the communication task load is high, the low-priority task time slice ratio needs to be increased. At the same time, the length of the switch buffer queue needs to be considered to avoid useful Ethernet frames being flushed away.
[0035] The purpose of reserving time slices is to separate the main task time slices from the low-priority time slices, to avoid receiving network frames at the end of the low-priority time slices, and to prevent affecting the scheduling of the main task. In actual applications, the proportion of the reserved time slices needs to be determined based on chip selection, operating system performance, etc.
[0036] The following uses the Ethernet Switch function of the Renesas RZT2 chip as an example to illustrate:
[0037] See also Figure 1 , which is a block diagram of the Ethernet subsystem of the Renesas RZT2 chip. Two priority queues are allocated, where the priority 0 (low priority) queue identifies standard Ethernet frames, and the priority 1 (high priority) queue identifies Ethernet frames of special protocols (such frames do not actually exist);
[0038] Among them, the main task time slice and the reserved time slice only allow frames with a priority greater than or equal to 1 to be sent to the MAC through the switch, while the low priority time slice allows network frames with a priority of 0 and above to pass through. Figure 1All network frames received by port0, port1, and port2 are marked as queues with priority 0, so that in the main task time slice, no general Ethernet frame can reach the MAC through the switch. Based on the above process, the purpose of the present invention can be achieved: in the main task time slice, the chip will not generate a network port reception interrupt, thereby reducing the main task jitter and improving system performance.
[0039] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions or improvements made within the technical scope of the present invention should be included in the scope of protection of the present invention.
Claims
1. A PLC task jitter suppression method based on switch TDMA, characterized in that: include: Time slice division step: dividing the scanning cycle into a main task time slice and a low priority time slice, wherein the main task time slice only allows the main task to run, and the low priority time slice allows the communication task to be processed; Priority control steps: assign corresponding priorities to the time slices divided within the scan cycle, and the network communication frame can be sent to the CPU only within the time slices of the corresponding priority.
2. The PLC task jitter suppression method based on switch TDMA as claimed in claim 1, characterized in that: In the time slice division step, a reserved time slice is further divided from the scanning cycle, and the reserved time slice is used to separate the main task time slice from the low priority time slice.
3. A PLC task jitter suppression system based on switch TDMA, characterized in that: It includes a time slice allocation module and a priority allocation module, wherein: The time slice allocation module is used to perform a time slice division step, in which the scanning cycle is divided into a main task time slice and a low priority time slice, wherein the main task time slice only allows the main task to run, and the low priority time slice allows the communication task to be processed; The priority allocation module is used to execute a priority control step. In the priority control step, corresponding priorities are allocated to time slices divided within a scanning cycle, and network communication frames can be sent to the CPU only within time slices of corresponding priorities.
4. The PLC task jitter suppression system based on switch TDMA as claimed in claim 3 is characterized in that: The time slice allocation module is further used to divide a reserved time slice from a scanning cycle, and the reserved time slice is used to separate the main task time slice from the low priority time slice.
5. The PLC task jitter suppression system based on switch TDMA as claimed in claim 3, characterized in that: The time slice allocation module divides the scanning cycle according to user configuration.