IGBT device preparation method and IGBT device

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) device preparation method and an IGBT device. The preparation method comprises the following steps of providing a substrate; forming a plurality of gate trenches on the substrate; forming a first insulating layer with a preset thickness in the gate trench; oxidizing the side wall of the n-type emitter layer, etching the substrate and forming an undercut structure at the opening of the gate trench; etching the first nitride layer and the first insulating layer in the gate trench until the thickness of the first insulating layer reaches a set threshold value; growing gate oxide layers on the side walls of the plurality of gate trenches and the surface of the substrate; the polycrystalline silicon gates are formed by filling polycrystalline silicon in the plurality of gate trenches, and the height of the polycrystalline silicon gates is smaller than the depth of the gate trenches; depositing an interlayer dielectric layer on the plurality of gate trenches and exposing the surface of the substrate, wherein the interlayer dielectric layer is a boron-phosphorosilicate glass layer; forming a plurality of contact holes in the surface of the substrate through self-alignment etching, wherein the contact holes extend to the p-type well region layer; and filling the plurality of contact holes to form contact hole filling, and forming a front metal layer on the first surface of the substrate.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor devices, and in particular to an IGBT device preparation method and an IGBT device. Background Art

[0002] As a hybrid power device, the Insulated Gate Bipolar Transistor (IGBT) has the characteristics of a metal-oxide-semiconductor (MOS) structure input and a bipolar structure output. Therefore, it has the advantages of a metal-oxide-semiconductor field-effect transistor (MOSFET), such as high input impedance, low drive circuit power, simple drive, fast switching speed, and low switching loss, as well as the advantages of a bipolar power transistor, such as high current density, strong current handling capability, and low on-saturation voltage drop. Since the early 1980s, IGBT has been widely studied at home and abroad. At present, it has broad application prospects and is widely used in many fields such as new energy vehicles, industrial frequency conversion, photovoltaics, smart grids, and locomotives. In addition, the Chinese IGBT market accounts for about one-third of the global IGBT market.

[0003] After nearly four decades of development, IGBT has evolved from a planar type to a trench type, and the pitch of the cell (minimum repeating unit) is getting smaller and smaller, and the distance from the contact hole in the active area to the trench gate is also getting smaller and smaller, and the alignment accuracy requirements for the contact hole mask and the gate trench mask are getting higher and higher. If the alignment accuracy of the contact hole mask and the gate trench mask is poor, and the distance from the contact hole to the trench gate is insufficient, the saturation voltage drop Vcesat in the IGBT wafer will be discrete and increase. The consistency of the distance from the contact hole to the trench gate depends entirely on the alignment consistency of the contact hole mask and the gate trench mask.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0005] In view of the problems in the prior art, an object of the present invention is to provide a method for preparing an IGBT device and an IGBT device.

[0006] Specifically, the first aspect of the present invention provides a method for preparing an IGBT device, the method comprising the following steps:

[0007] A substrate is provided, the substrate comprising a base, an n-type carrier storage layer, a p-type well region layer and an n-type emitter layer stacked in sequence, a hard mask layer is formed on a first surface of the substrate, the hard mask layer comprising a first oxide layer, a first nitride layer and a second oxide layer stacked in sequence;

[0008] Etching the hard mask layer and the substrate to form a plurality of gate trenches, wherein the plurality of gate trenches penetrate the n-type emitter layer, the p-type well region layer and the n-type carrier storage layer;

[0009] Depositing a first insulating layer, wherein the thickness of the first insulating layer is greater than the depth of the gate trench, and etching the first insulating layer on the surface of the substrate and the first insulating layer at a partial depth in the gate trench by using a first etching process;

[0010] Forming a first insulating layer of a preset thickness in the gate trench;

[0011] Etching the substrate using a second etching process for selectively etching oxide and forming an undercut structure at the opening of the gate trench;

[0012] Using a third etching process to etch the first nitride layer and the first insulating layer in the gate trench until the thickness of the first insulating layer reaches a set threshold;

[0013] Growing a gate oxide layer on the sidewalls of the plurality of gate trenches and the surface of the substrate;

[0014] A polysilicon gate formed by filling polysilicon in the plurality of gate trenches, wherein the height of the polysilicon gate is less than the depth of the gate trench;

[0015] Depositing an interlayer dielectric layer in the plurality of gate trenches to expose the surface of the substrate, wherein the interlayer dielectric layer comprises a borophosphosilicate glass layer;

[0016] A plurality of contact holes are formed on the surface of the substrate by a self-aligned etching process, wherein the contact holes extend to the p-type well region layer;

[0017] Filling a plurality of the contact holes forms contact hole filling and forming a front metal layer on the first surface of the substrate.

[0018] According to the first aspect of the present invention, the first insulating layer includes a silicon nitride layer.

[0019] According to a first aspect of the present invention, the step of forming a first insulating layer of a preset thickness in the gate trench comprises:

[0020] Depositing a first insulating layer, wherein the thickness of the first insulating layer is greater than 1 / 2 of the width of the gate trench;

[0021] The first insulating layer on the surface of the substrate and the first insulating layer at a partial depth in the gate trench are etched using a first etching process.

[0022] According to the first aspect of the present invention, after the step of etching the first insulating layer on the surface of the substrate and the first insulating layer at a partial depth in the gate trench, the distance between the surface of the first insulating layer in the gate trench and the surface of the n-type emitter layer in the thickness direction is h1, satisfying: 3000 angstroms ≤ h1 ≤ 5000 angstroms.

[0023] According to the first aspect of the present invention, the n-type emitter layer includes a plurality of sub-emitter layers, and the etching rate of the plurality of sub-emitter layers from top to bottom in the second etching process gradually decreases.

[0024] According to the first aspect of the present invention, an angle β between the sidewall of the gate trench at the n-type emitter layer and the first surface of the substrate is between 80° and 86°.

[0025] According to the first aspect of the present invention, the surface of the polysilicon gate formed by filling the gate trench with polysilicon is higher than the p-type well region layer.

[0026] According to the first aspect of the present invention, the first insulating layer in the gate trench is etched by a third etching process until the thickness of the first insulating layer reaches a set threshold, and the surface of the first insulating layer is lower than the p-type well region layer.

[0027] According to the first aspect of the present invention, after the first insulating layer in the gate trench is etched by a third etching process until the thickness of the first insulating layer reaches a set threshold, the thickness of the first insulating layer is between 3000 angstroms and 10000 angstroms.

[0028] According to the first aspect of the present invention, an angle α between the sidewall of the contact hole and the first surface of the substrate is between 70° and 83°.

[0029] According to the first aspect of the present invention, the preparation method further comprises the following steps:

[0030] A backside structure is formed on the second surface of the substrate, wherein the backside structure includes a buffer layer, a p-type doped collector region layer and a backside metal layer which are sequentially stacked on the second surface of the substrate.

[0031] A second aspect of the present invention provides an IGBT device, which is obtained by using the preparation method provided by the first aspect.

[0032] Compared with the prior art, the IGBT device preparation method of the present invention is suitable for the preparation of IGBT devices with a distance between the contact hole and the gate trench less than 0.2 μm. The self-alignment process greatly reduces the alignment accuracy requirements of the contact hole mask and the gate trench mask, and improves the collector-emitter saturation voltage Vcesat consistency of the IGBT devices within and between wafers. At the same time, Si is added at the bottom of the gate trench of the IGBT device. 3 N 4 layer, and Si 3 N 4 The adjustable thickness of the layer can reduce the feedback capacitance of the device, reduce the switching loss of the device and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0034] Figure 1 A flow chart of a method for preparing an IGBT device according to an embodiment of the present invention;

[0035] Figures 2 to 12 It is a schematic diagram of the structure of the substrate corresponding to each step in the preparation process of the IGBT device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0037] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0038] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0039] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0040] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0041] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0042] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0043] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0044] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0045] The IGBT device preparation method and the IGBT device of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments. It can be understood that the various specific embodiments are not intended to limit the protection scope of the present invention.

[0046] The present invention provides a method for preparing an IGBT device. Figure 1 This is a flow chart of a method for preparing an IGBT device according to an embodiment of the present invention. Specifically, the preparation method comprises the following steps:

[0047] Step S1: providing a substrate, the substrate comprising a base 1, an n-type carrier storage layer 2, a p-type well region layer 3 and an n-type emitter layer 4 stacked in sequence, and forming a hard mask layer 7 on a first surface of the substrate.

[0048] Among them, the substrate 1 can be an N-type doped silicon wafer, and the doping concentration and thickness depend on the withstand voltage requirements of the IGBT device. The n-type carrier storage layer 2 can be obtained by an ion implantation process, and the selected impurity ions can be phosphorus (P), arsenic (As), etc. By adjusting the parameters such as ion implantation energy, dosage and implantation time, the impurity ions are implanted to a certain depth on the substrate surface, and annealing is performed after implantation to activate the doped atoms on the one hand and eliminate the lattice defects caused by ion implantation on the other hand, and finally form an n-type carrier storage layer. For example, the implanted ions of the n-type carrier storage layer 2 can be phosphorus, and the implantation agent is 5e 12 ~5e 13 cm -2 The injection energy is 80keV-2MeV, the advancement temperature is 1050~1250℃, and the advancement time is 30~300 minutes.

[0049] Similarly, the p-type well region layer 3 can also be obtained by ion implantation, the difference being that the implanted impurity particles are p-type impurity ions such as boron (B) ions. The boron ions are implanted into the substrate where the n-type carrier storage layer has been formed, and the implanted area will form a p-type well region. For example, the implanted ions of the p-type well region layer 3 are boron, and the implantation dose is 1e 14 ~6e 14 cm-2, the injection energy is 60keV~200keV, the driving temperature is 1000-1150℃, and the driving time is 5~120 minutes.

[0050] Ion implantation technology is used again to implant n-type impurity ions into the p-type well region layer 3 to form an n-type emitter layer 4. The hard mask layer 7 in step S1 includes a first oxide layer 71, a first nitride layer 72, and a second oxide layer 73 stacked in sequence. Preferably, the first oxide layer 71 and the second oxide layer 73 are silicon oxide layers, the first nitride layer 72 is a silicon nitride layer, the first oxide layer 71 has a thickness of 100 to 300 angstroms, the first nitride layer 72 has a thickness of 500 to 2000 angstroms, and the second oxide layer 73 has a thickness of 4000 to 8000 angstroms.

[0051] Step S2: Etching the hard mask layer 7 and the substrate to form a plurality of gate trenches C, wherein the plurality of gate trenches C penetrate the n-type emitter layer 4, the p-type well region layer 3 and the n-type carrier storage layer 2 to the substrate 1. Figure 2In step S2, a photoresist layer can be coated on the surface of the hard mask layer 7, and then the photoresist layer is exposed and developed to form a patterned photoresist layer. Then, the photoresist pattern is used as a mask layer, and a dry etching process such as reactive ion etching (RIE) is used to etch the hard mask layer 7 and part of the substrate to form a gate trench C. The width and depth of the gate trench C can be set according to the structure or performance of the IGBT device to be prepared. Preferably, the depth of the gate trench C is 2μm to 8μm.

[0052] Step S3: forming a first insulating layer 5' with a preset thickness in the gate trench C. In the embodiment, the first insulating layer 5 is a silicon nitride layer (Si 3 N 4 Specifically, step S3 may include the following steps: S3a: depositing a first insulating layer 5, the thickness of the first insulating layer 5 being greater than 1 / 2 of the width of the gate trench C, and in step S3a, a chemical vapor deposition (CVD) process may be used to deposit silicon nitride, with a thickness between 5000 angstroms and 10000 angstroms, see Figure 3 ; S3b: using a first etching process to etch the first insulating layer 5 on the surface of the substrate and the first insulating layer at a depth of a portion of the gate trench, the first etching process in step S3b may be a dry etching process, after etching a portion of the first insulating layer, a first insulating layer 5' having a preset thickness is formed, and the surface is lower than the surface of the n-type emitter layer 4, see Figure 4 Preferably, the distance h1 between the surface of the first insulating layer 5' in the gate trench and the surface of the n-type emitter layer 4 in the thickness direction satisfies: 3000 angstroms ≤ h1 ≤ 5000 angstroms. The preset thickness of the first insulating layer 5' is the difference between the depth of the gate trench C and the distance h1.

[0053] Step S4: oxidize the sidewalls of the n-type emitter layer 4 in the gate trench C, and etch the substrate and the oxidized sidewalls of the n-type emitter layer using a second etching process for selectively etching the oxide, forming an undercut structure U at the opening of the gate trench C; in some embodiments, the second etching process is wet etching, and the selective etching of the oxide layer, or the etching rate of the oxide layer, is much greater than the etching rate of the nitride layer, so that the etching of the nitride layer can be ignored. The oxidation of the sidewalls of the n-type emitter layer 4 in step S4 and the etching after oxidation can be achieved in the same step. For example, the etching solution can be a silicon etching solution, and the silicon etching solution is 70% nitric acid HNO 3 and 50% concentration of hydrofluoric acid HF (volume ratio 10 to 2:1). During the etching process, nitric acid is used as an oxidant, and the side wall of the n-type emitter layer 4 is oxidized to form SiO 2Reacts with HF, so that the corrosion process continues. At the same time, in this process, the etching rate of silicon oxide is significantly higher than that of silicon nitride, and the typical selection ratio is SiO 2 :Si 3 N 4 >50:1, the lower the concentration of hydrofluoric acid, the lower the etching rate of silicon nitride, but the etching rate of silicon oxide will also decrease. After step S4, the first oxide layer 71 is etched away, and the first nitride layer 72 basically maintains its original width due to its extremely low etching rate. The first oxide layer 71 and the n-type emitter layer 4 are below the first nitride layer 72, and the sidewalls of the first oxide layer 71 and the n-type emitter layer 4 in the gate trench C are etched, forming a protruding undercut structure U (Undercut) of the first nitride layer 72 at the opening of the gate trench C relative to the first oxide layer 71, see Figure 5 In the dotted oval frame, the etching time of step S4 is generally between tens of seconds and several minutes, and the etching time can be adjusted according to the thickness of the first oxide layer 71, the first nitride layer 72 and the second oxide layer 73 and the undercut structure U to be obtained.

[0054] In a preferred embodiment, the n-type emitter layer 4 includes a plurality of sub-emitter layers, and the etching rate of the plurality of sub-emitter layers from top to bottom in the second etching process gradually decreases. Figure 5 In the embodiment, the n-type emitter layer 4 includes three sequentially stacked sub-emitter layers, namely the first sub-emitter layer 41, the second sub-emitter layer 42 and the third sub-emitter layer 43, and the etching rate of the first sub-emitter layer 41, the second sub-emitter layer 42 and the third sub-emitter layer 43 in the second etching process gradually increases. The etching rate of the sub-emitter layers from top to bottom gradually decreases, which can be achieved by sequentially reducing the doping concentration of n-type ions in the third sub-emitter layer 43, the second sub-emitter layer 42 and the first sub-emitter layer 41. When the etching rates of the multiple sub-emitter layers from top to bottom gradually decrease, the gap on the third sub-emitter layer 43 at the opening of the gate trench C obtained after step S4 is larger than the gap on the second sub-emitter layer 42 thereunder, and the gap on the second sub-emitter layer 42 is larger than the gap on the first sub-emitter layer 41 thereunder, that is, the side wall of the gate trench C at the n-type emitter layer 4 is not perpendicular to the first surface (horizontal direction) of the substrate, and the angle between the side wall of the gate trench C at the n-type emitter layer 4 and the first surface of the substrate is defined as β, preferably, the angle β is between 80° and 86°, such as 82° or 84°. In practice, the first sub-emitter layer 41, the second sub-emitter layer 42 and the third sub-emitter layer 43 can be etched with different doses of Ar(5e 12 ~5e 14 cm -2) injection adjustment angle β, the adjustment of the angle β of the side wall of the gate trench C at the n-type emitter layer 4 can optimize the emission efficiency of the parasitic NPN transistor. At the same time, the reverse bias safe operating area (RBSOA) and short circuit safe operating area (SCSOA) of the transistor can be adjusted.

[0055] Step S5: Etch the first nitride layer 72 and the first insulating layer 5' in the gate trench by a third etching process until the thickness of the first insulating layer reaches a set threshold. At this time, the first insulating layer constitutes the insulating layer 51 at the bottom of the gate trench. Figure 6 . The third etching process can be a wet etching process, and the etching solution can be a phosphoric acid solution, such as 85% concentrated phosphoric acid mixed with a small amount of water, and the etching temperature is between 140°C and 200°C. Preferably, when the thickness of the first insulating layer reaches the set threshold, the surface of the first insulating layer (insulating layer 51) is lower than the p-type well region layer 3. Preferably, the distance between the surface of the insulating layer 51 and the bottom surface of the p-type well region layer 3 is between 0.5μm and 1μm. At the same time, in order to improve the voltage resistance performance at the bottom of the gate trench, the thickness of the insulating layer 51 is greater than 2000 angstroms. Preferably, the thickness of the insulating layer 51 is between 3000 angstroms and 10000 angstroms. Si is added to the bottom of the gate trench 3 N 4 layer, which is equivalent to adding a layer of high-quality insulating medium between the electrodes. According to the feedback capacitance formula (Cgc=(εA N- ) / t, where ε is the dielectric constant of the dielectric layer, A N- is the area of ​​the n-type doped region covered by the gate, and t is the thickness of the dielectric layer. It can be seen that when the gate coverage area and the dielectric layer thickness are relatively fixed, increasing the dielectric layer thickness can reduce the feedback capacitance. Although Si 3 N 4 The dielectric constant of the layer is SiO 2 Nearly twice as much, but Si 3 N 4 The layer thickness is SiO 2 The gate oxide thickness is 3-10 times, so a thick Si is added at the bottom of the gate trench. 3 N 4 layer, which can reduce feedback capacitance and switching loss. 3 N 4 Layer ratio SiO 2 The layer has a higher dielectric constant, which can reduce the impact of the high electric field at the bottom of the gate trench on the dielectric layer and improve device reliability.

[0056] Step S6: growing a gate oxide layer 52 on the sidewalls of the plurality of gate trenches and the surface of the substrate, Figure 7The gate oxide layer 52 may be prepared by a thermal growth process. Preferably, the thickness of the gate oxide layer 52 is between 1000 angstroms and 1500 angstroms.

[0057] Step S7: Filling a plurality of gate trenches C with polysilicon to form a polysilicon gate 53, wherein the height of the polysilicon gate 53 is less than the depth of the gate trench C. Figure 8 In step S7, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or the like can be used to fill the polysilicon. Specifically, the substrate in step S6 is placed in a deposition device, and an appropriate amount of silicon source gas, such as silane (SiH 4 ), etc. Under set conditions such as temperature, pressure and gas flow, the silicon source gas decomposes and chemically reacts on the surface of the gate trench C, and silicon atoms are deposited in the gate trench C, gradually filling the gate trench C. In order to ensure that the gate trench is completely filled and to avoid defects such as gaps or cracks, multiple cycles of deposition and etching may be required, that is, first depositing a certain thickness of polysilicon, and then using an etching process to remove the closed layer or uneven portion that may be formed on the top of the gate trench, opening the filling gap, and then performing the next polysilicon deposition. After the filling is completed, the surface of the polysilicon layer can be flattened by a chemical mechanical polishing (CMP) process. According to the design requirements of the IGBT device, in some embodiments, the filled polysilicon needs to be etched back to etch the polysilicon to a specific depth or shape to form the desired gate structure, such as Figure 8 Preferably, the depth of the polysilicon filling and etching back is greater than 0.3 μm, and the surface of the polysilicon gate 53 is higher than the surface of the p-type well region layer 3 .

[0058] Step S8: depositing an interlayer dielectric layer in the plurality of gate trenches. The interlayer dielectric layer may be a boron-phosphorus silicate glass (BPSG) layer. The BPSG layer is used to provide electrical isolation between different metal layers of the device and optimize the device performance by utilizing its own characteristics. The thickness of the deposited interlayer dielectric layer may be between 5000 angstroms and 15000 angstroms. The interlayer dielectric layer is etched back until the surface of the substrate is exposed, that is, only the interlayer dielectric layer 54 is retained at the top of the gate trench. Fig. 9 .

[0059] Step S9: Due to SiO 2 Compared with Si etching, the self-aligned etching is used to form a plurality of contact holes H on the substrate surface. The contact holes H penetrate the n-type emitter layer 4 and extend into the p-type well region layer 3. Fig.10The self-aligned etching technology reduces the alignment accuracy requirements of the contact hole mask and the gate trench mask, ensuring the precise alignment between the contact hole and the device structure (such as the gate, source / drain region), providing a guarantee for obtaining IGBT device wafers with highly consistent collector-emitter saturation voltage Vcesat. Fig.10 In the embodiment, the side wall of the contact hole H is not perpendicular to the first surface (horizontal direction) of the substrate, and the angle between the side wall of the contact hole H and the first surface of the substrate is defined as α. Preferably, the angle α is between 70° and 83°, such as 75° or 80°.

[0060] Step S10: Fill the plurality of contact holes H to form a contact hole filling 6 and form a front metal layer 61 on the first surface of the substrate. Fig.11 The contact hole filling 6 of step S10 can be obtained by depositing a filling layer in the contact hole H by chemical vapor deposition (CVD) or physical vapor deposition (PVD) and then removing excess filling material on the surface. The filling material can be a conductive metal such as tungsten (W). In some embodiments, the contact hole filling 6 is Ti / TiN / W filling. Exemplarily, the front metal layer 61 is an AlCu layer.

[0061] In some other embodiments, the preparation method of the present invention further comprises the following steps:

[0062] Step S11: forming a back surface structure on the second surface of the substrate, the back surface structure comprising a buffer layer 81, a p-type doped collector region layer 8 and a back surface metal layer 9 sequentially stacked on the second surface of the substrate, Fig.12 In some embodiments, in step S11, the substrate is first turned over, and the base 1 is thinned to a set thickness, which depends on the withstand voltage requirement of the IGBT device, and then p-type doping ions are implanted into the base 1 to form a p-type doped collector region layer 8. For example, boron ions are implanted into the base 1, and the implantation energy is 60 to 20 KeV and the implantation dose is 1e 12 ~1e 14 cm -2 , laser annealing is used to activate the injected boron ions to form a p-type doped collector region layer 8; then hydrogen injection, phosphorus injection, or hydrogen and phosphorus injection and annealing are performed from the back side of the substrate to form a buffer layer 81; finally, a back metal layer 9 is deposited, and the back metal layer 9 can be an Al / Ti / Ni / Ag layer.

[0063] The present invention also provides an IGBT device, which is obtained by the above-mentioned preparation method. The specific structure can be seen in Fig.12The distance between the contact hole and the trench gate of the IGBT device can be less than 0.2μm. At the same time, since the preparation method adopts a self-alignment process, the alignment accuracy requirement of the contact hole mask and the gate trench mask is greatly reduced. The IGBT device in the wafer has a highly consistent collector-emitter saturation voltage (Vcesat). Furthermore, a Si with adjustable thickness is added to the bottom of the gate trench. 3 N 4 The device has lower feedback capacitance, lower switching loss and higher reliability.

[0064] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0065] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A method for preparing an IGBT device, characterized in that: The preparation method comprises the following steps: A substrate is provided, the substrate comprising a base, an n-type carrier storage layer, a p-type well region layer and an n-type emitter layer stacked in sequence, a hard mask layer is formed on a first surface of the substrate, the hard mask layer comprising a first oxide layer, a first nitride layer and a second oxide layer stacked in sequence; Etching the hard mask layer and the substrate to form a plurality of gate trenches, wherein the plurality of gate trenches penetrate the n-type emitter layer, the p-type well region layer and the n-type carrier storage layer; Forming a first insulating layer of a preset thickness in the gate trench; Oxidizing the sidewalls of the n-type emitter layer in the gate trench, etching the substrate and the oxidized sidewalls of the n-type emitter layer using a second etching process for selectively etching oxide, and forming an undercut structure at the opening of the gate trench; Using a third etching process to etch the first nitride layer and the first insulating layer in the gate trench until the thickness of the first insulating layer reaches a set threshold; Growing a gate oxide layer on the sidewalls of the plurality of gate trenches and the surface of the substrate; A polysilicon gate formed by filling polysilicon in the plurality of gate trenches, wherein the height of the polysilicon gate is less than the depth of the gate trench; Depositing an interlayer dielectric layer in the plurality of gate trenches to expose the surface of the substrate, wherein the interlayer dielectric layer comprises a borophosphosilicate glass layer; A plurality of contact holes are formed on the surface of the substrate by a self-aligned etching process, wherein the contact holes extend to the p-type well region layer; Filling a plurality of the contact holes forms contact hole filling and forming a front metal layer on the first surface of the substrate.

2. The method for preparing an IGBT device according to claim 1, characterized in that: The first insulating layer includes a silicon nitride layer.

3. The method for preparing an IGBT device according to claim 1, characterized in that: The step of forming a first insulating layer of a preset thickness in the gate trench comprises: Depositing a first insulating layer, wherein the thickness of the first insulating layer is greater than 1 / 2 of the width of the gate trench; The first insulating layer on the surface of the substrate and the first insulating layer at a partial depth in the gate trench are etched using a first etching process.

4. The method for preparing an IGBT device according to claim 3, characterized in that: After etching the first insulating layer on the substrate surface and the first insulating layer at a partial depth in the gate trench, the distance between the surface of the first insulating layer in the gate trench and the surface of the n-type emitter layer in the thickness direction is h1, satisfying: 3000 angstroms ≤ h1 ≤ 5000 angstroms.

5. The method for preparing an IGBT device according to claim 1, characterized in that: The n-type emitter layer includes a plurality of sub-emitter layers, and the etching rate of the plurality of sub-emitter layers from top to bottom in the second etching process gradually decreases.

6. The method for preparing an IGBT device according to claim 5, characterized in that: An included angle β between a sidewall of the gate trench at the n-type emitter layer and the first surface of the substrate is between 80° and 86°.

7. The method for preparing an IGBT device according to claim 5, characterized in that: The surface of the polysilicon gate formed by filling the gate trench with polysilicon is higher than the p-type well region layer.

8. The method for preparing an IGBT device according to claim 1, characterized in that: The first insulating layer in the gate trench is etched by a third etching process until the thickness of the first insulating layer reaches a set threshold, and the surface of the first insulating layer is lower than the p-type well region layer.

9. The method for preparing an IGBT device according to claim 1, characterized in that: After the first insulating layer in the gate trench is etched by a third etching process until the thickness of the first insulating layer reaches a set threshold, the thickness of the first insulating layer is between 3000 angstroms and 10000 angstroms.

10. The method for preparing an IGBT device according to claim 1, characterized in that: An included angle α between the sidewall of the contact hole and the first surface of the substrate is between 70° and 83°.

11. The method for preparing an IGBT device according to claim 1, characterized in that: The preparation method further comprises the following steps: A backside structure is formed on the second surface of the substrate, wherein the backside structure includes a buffer layer, a p-type doped collector region layer and a backside metal layer which are sequentially stacked on the second surface of the substrate.

12. An IGBT device, characterized in that: The IGBT device is obtained by the preparation method described in any one of claims 1 to 11.

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