Silicon-based microstructure chip unit and preparation method thereof, and silicon-based microstructure neutron detector

Abstract

The invention relates to the technical field of silicon-based neutron detectors, in particular to a silicon-based microstructure chip unit, a preparation method and a silicon-based microstructure neutron detector. Each silicon-based microstructure chip unit comprises an N-type silicon substrate, a silicon dioxide thick gate isolation layer, a boron ion layer, a silicon dioxide thin gate passivation layer, a phosphorus ion layer, a P-face metal electrode, an N-face metal electrode and a neutron material filling layer, and a deep-hole type silicon-based PIPS microstructure is formed. On the other hand, due to the reasonable design of the size of the deep hole type microstructure, the energy of secondary charged particles is deposited in the silicon to a greater extent, and a guarantee is provided for obtaining higher thermal neutron detection efficiency. According to the invention, a silicon PIPS preparation process is adopted, so that the microstructure neutron detector has lower noise, higher energy resolution and position resolution and higher working stability when being used for detecting secondary charged particles with different energies.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon-based neutron detectors, and in particular to a silicon-based microstructure chip unit and a preparation method thereof, and a silicon-based microstructure neutron detector. Background Art

[0002] Neutron detection is an important part of nuclear science and technology. Neutron detectors based on silicon semiconductor devices have the advantages of fast response time, small size, and easy identification of neutron-gamma (γ), especially microstructured silicon-based neutron detectors. Because microstructures are etched in silicon, on the one hand, the filling amount of neutron conversion materials is increased, and the absorption utilization rate of incident neutrons is improved; on the other hand, the contact area between the neutron conversion material and the semiconductor material is significantly increased, and the probability of charged particles produced after nuclear reactions entering the sensitive volume of the detector is increased. Theoretically, this can greatly improve the efficiency of neutron detection.

[0003] Existing microstructured neutron detectors mainly increase the conversion material filling amount and contact area by etching microstructures (such as grooves and inverted pyramids) in silicon. For microstructured neutron detectors, the main factors affecting their performance are microstructure design and preparation process. Existing microstructured detectors still have the following problems in structure and preparation process: Structural defects: The groove-type or inverted pyramid-type microstructure has edge electric field distortion, which affects the uniformity of charge collection. In addition, the microstructure filling rate is insufficient, and the improvement of neutron absorption efficiency is limited.

[0004] Process limitations: Silicon-based microstructure neutron detectors are mostly prepared using the gold-silicon surface barrier process. Affected by the coating process, they are suitable for the preparation of detectors with large open structures. The detectors prepared by this process have large leakage current and high noise, which is not conducive to the detection of low-energy charged particles. They are also sensitive to the ambient atmosphere and are not suitable for applications with high humidity and poor environmental conditions. For the diffusion doping process, the PN junction dead layer formed by thermal diffusion is thick (several microns), which reduces the detection efficiency of low-energy particles and makes it difficult to achieve a microstructure with a high aspect ratio. Summary of the invention

[0005] The present invention provides a silicon-based microstructure chip unit and a preparation method, and a silicon-based microstructure neutron detector, which are used to solve the defects in the structure and preparation process of the microstructure detector in the prior art, maximize the advantages of the silicon-based nuclear radiation detector, and at the same time improve the neutron detection efficiency and working stability of the detector.

[0006] The present invention provides a silicon-based microstructure chip unit, comprising an N-type silicon substrate, a silicon dioxide thick gate isolation layer, a boron ion layer, a silicon dioxide thin gate passivation layer, a phosphorus ion layer, a P-side metal electrode, an N-side metal electrode and a neutron material filling layer, wherein a plurality of neutron material filling holes are formed on the N-type silicon substrate; the silicon dioxide thick gate isolation layer is located on a first surface of the N-type silicon substrate, and the silicon dioxide thick gate isolation layer is formed with a plurality of first through holes, a plurality of second through holes and an electrode groove penetrating the silicon dioxide thick gate isolation layer, wherein the first through holes are correspondingly connected to the neutron material filling holes; the boron ion layer is formed on a first surface of the N-type silicon substrate The silicon dioxide thin gate passivation layer is located in the second through hole and in contact with the boron ion layer; the phosphorus ion layer is formed in the surface layer of the second surface of the N-type silicon substrate; the P-side metal electrode is arranged in the electrode groove and in contact with the boron ion layer; the N-side metal electrode is located on the second surface of the N-type silicon substrate and in contact with the phosphorus ion layer; the neutron material filling layer is filled in the first through hole, the neutron material filling hole and the second through hole and covers the upper surface of the silicon dioxide thick gate isolation layer.

[0007] According to a silicon-based microstructure chip unit provided by the present invention, a plurality of neutron material filling holes are arranged in a matrix on the N-type silicon substrate, a plurality of first through holes are arranged in one-to-one correspondence with the plurality of neutron material filling holes on the silicon dioxide thick gate isolation layer, a plurality of second through holes are arranged in a matrix on the silicon dioxide thick gate isolation layer, and the electrode groove is located at the edge of the silicon dioxide thick gate isolation layer to form an annular contact electrode window.

[0008] According to a silicon-based microstructure chip unit provided by the present invention, the thickness of the N-type silicon substrate is 250 μm-350 μm, and the resistivity is not less than 10000 Ω·cm.

[0009] The pore diameter of the neutron material filling hole is 20 μm to 40 μm, the pore depth of the neutron material filling hole is 170 μm to 230 μm, and the center distance between two adjacent neutron material filling holes is 80 μm to 120 μm.

[0010] According to a silicon-based microstructure chip unit provided by the present invention, the thickness of the silicon dioxide thick gate isolation layer is 0.5 μm to 0.9 μm, and the thickness of the silicon dioxide thin gate passivation layer is 0.1 μm to 0.3 μm.

[0011] The boron ion layer is formed by implanting boron ions into the surface layer of the first surface of the N-type silicon substrate by an ion implanter, wherein the energy of the implanted boron ions is 90 keV and the implantation dose satisfies 2×10 14 ions / cm 2The phosphorus ion layer is formed by implanting phosphorus ions into the surface layer of the second surface of the N-type silicon substrate by an ion implanter, the energy of the implanted phosphorus ions is 65keV, and the implantation dose satisfies 1×10 16 ions / cm 2 .

[0012] According to a silicon-based microstructure chip unit provided by the present invention, the P-side metal electrode and the N-side metal electrode adopt composite metal electrodes, and the composite metal electrode includes a titanium metal layer, a nickel metal layer and a silver metal layer from bottom to top, and satisfies a thickness ratio of titanium metal layer: nickel metal layer: silver metal layer = 1:1:2.

[0013] The neutron material filling layer includes at least one of boron carbide particles and lithium fluoride particles, and the particle size of the particles is less than 1 μm.

[0014] The present invention also provides a method for preparing a silicon-based microstructure chip unit, which is suitable for preparing any one of the silicon-based microstructure chip units described above, and the method for preparing the silicon-based microstructure chip unit comprises: The N-type silicon substrate is subjected to wet oxygen oxidation to form a silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate.

[0015] Spin-coat photoresist on the silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate, and etch a second through hole and an electrode groove on the silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate by photolithography.

[0016] The second through hole and the electrode groove are subjected to dry oxygen oxidation in the projection area of ​​the N-type silicon substrate to form a silicon dioxide thin gate passivation layer.

[0017] Boron ions are injected into the surface layer of the projection area of ​​the N-type silicon substrate through the second through hole and the electrode groove to form a boron ion layer in the first surface layer of the N-type silicon substrate; phosphorus ions are injected into the second surface layer of the N-type silicon substrate to form a phosphorus ion layer.

[0018] The photoresist after photolithography is removed, and the photoresist is re-spin-coated on the silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate, and the electrode groove is photolithographically processed and the silicon dioxide thin gate passivation layer in the electrode groove is removed.

[0019] The photoresist after photolithography is removed, and electrode material is sputtered in the electrode groove to form a P-side metal electrode, and electrode material is sputtered on the second surface of the N-type silicon substrate to form an N-side metal electrode.

[0020] The photoresist is re-spin-coated on the silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate, a first through hole is etched on the silicon dioxide thick gate isolation layer, and etching is continued to etch a neutron material filling hole on the N-type silicon substrate to form a neutron material filling frame.

[0021] The photoresist after photolithography is removed, and the formed neutron material filling frame is filled with neutron conversion material, so that the neutron conversion material fills the first through hole, the neutron material filling hole and the second through hole and covers the upper surface of the silicon dioxide thick gate isolation layer to form a neutron material filling layer, thereby completing the preparation of the silicon-based microstructure chip unit.

[0022] According to a method for preparing a silicon-based microstructure chip unit provided by the present invention, the step of filling the formed neutron material filling framework with neutron conversion material comprises: Prepare the neutron conversion fill solution.

[0023] Ultrasonic vibration is used to make the neutron conversion filling solution form a colloidal solution.

[0024] The neutron material filling frame is placed at the bottom of the colloidal solution, and bubbles in the first through hole, the neutron material filling hole and the second through hole are removed by ultrasonic vibration and the colloidal solution is filled.

[0025] The neutron material filling frame and the filled colloidal solution are transferred to a shaker for low-speed filling, the shaker speed is 100 rpm, and the low-speed filling time is 30 minutes.

[0026] The colloidal solution on the neutron material filling frame is dried in an oven to form a neutron material filling layer.

[0027] According to a method for preparing a silicon-based microstructure chip unit provided by the present invention, the neutron conversion filling solution includes: isopropanol and boron carbide particles, and the ratio of isopropanol: boron carbide particles = 10mL: 0.05g is satisfied; or, isopropanol and lithium fluoride particles, and the ratio of isopropanol: lithium fluoride particles = 10mL: 0.05g is satisfied; or, isopropanol and neutron conversion material, and the ratio of isopropanol: neutron conversion material = 10mL: 0.05g is satisfied, the neutron conversion material includes boron carbide particles and lithium fluoride particles, and the boron carbide particles and the lithium fluoride particles satisfy a mass ratio of 3:1.

[0028] The present invention also provides a silicon-based microstructure neutron detector, which is packaged using any one of the silicon-based microstructure chip units described above.

[0029] According to a silicon-based microstructure neutron detector provided by the present invention, the silicon-based microstructure neutron detector includes a PCB board and a radio frequency coaxial connector interface, the silicon-based microstructure chip unit is embedded on the PCB board, the P-side metal electrode of the silicon-based microstructure chip unit is bonded to a pad on the PCB board through silicon-aluminum wire bonding, the pad is connected to a pin at one end of the radio frequency coaxial connector interface, and the N-side metal electrode of the silicon-based microstructure chip unit is connected to another pin at one end of the radio frequency coaxial connector interface.

[0030] The silicon-based microstructure chip unit provided by the present invention is a deep-hole silicon-based PIPS microstructure, in which the neutron material filling hole on the N-type silicon substrate and the first through hole of the silicon dioxide thick gate isolation layer form a cylindrical deep hole structure for filling the neutron material filling layer. Structurally, the cylindrical deep hole in the silicon-based microstructure chip unit of the present invention can effectively suppress the edge effect of the groove-type and inverted pyramid-type microstructures, avoid the edge electric field distortion of the groove-type / inverted pyramid structure, and ensure the uniformity of charge collection; compared with other microstructures, the cylindrical deep hole microstructure has a higher conversion material filling rate. From a process perspective, the microstructure formed by the silicon-based microstructure chip unit of the present invention adopts the PIPS process, which can break through the limitation of the microstructure shape and prepare a microstructure with a higher filling rate. Among them, the silicon dioxide thin gate passivation layer serves as a passivation protection with strong resistance to the influence of environmental atmosphere. The surface isolation technology of the silicon dioxide thick gate isolation layer, as an isolation layer between deep holes and sensitive areas, can ensure the efficient collection of carriers generated by charged particles in the sensitive area on the electrode, and at the same time can also inhibit the increase of leakage current caused by microstructure etching damage to a certain extent, thereby reducing the noise of the detector. The silicon dioxide thick gate isolation layer and the silicon dioxide thin gate passivation layer work synergistically to reduce the leakage current (<1nA) and noise level, and enhance the stability of the detector in complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a schematic diagram of the cross-sectional structure of the silicon-based microstructure chip unit provided by the present invention.

[0033] Figure 2 It is a schematic flow chart of the method for preparing the silicon-based microstructure chip unit provided by the present invention.

[0034] Figure 3The present invention is a schematic diagram of a process of forming a silicon dioxide thick gate isolation layer, a silicon dioxide thin gate passivation layer, a boron ion layer and a phosphorus ion layer on an N-type silicon substrate.

[0035] Figure 4 It is a schematic diagram of the process of sputtering electrode material in the electrode groove of the present invention.

[0036] Figure 5 It is a schematic diagram of the formation process of the P-side metal electrode and the N-side metal electrode of the present invention.

[0037] Figure 6 It is a schematic diagram of the formation process of the neutron material filling layer of the present invention.

[0038] Figure 7 It is a schematic diagram of the structure of the silicon-based microstructure neutron detector provided by the present invention.

[0039] Reference numerals: 1. N-type silicon substrate; 11. Neutron material filling hole; 2. Silicon dioxide thick gate isolation layer; 21. First through hole; 22. Second through hole; 23. Electrode groove; 3. Boron ion layer; 4. Silicon dioxide thin gate passivation layer; 5. Phosphorus ion layer; 6. P-side metal electrode; 7. N-side metal electrode; 8. Neutron material filling layer; 100. PCB board; 200. RF coaxial connector interface; 300. Pad. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Combine the following Figures 1 to 7 The present invention describes a silicon-based microstructure chip unit and a preparation method, and a silicon-based microstructure neutron detector.

[0042] One embodiment of the present invention provides a silicon-based microstructure chip unit, see Figure 1As shown, the silicon-based microstructure chip unit includes an N-type silicon substrate 1, a silicon dioxide thick gate isolation layer 2, a boron ion layer 3, a silicon dioxide thin gate passivation layer 4, a phosphorus ion layer 5, a P-side metal electrode 6, an N-side metal electrode 7 and a neutron material filling layer 8, and a plurality of neutron material filling holes 11 are formed on the N-type silicon substrate 1; the silicon dioxide thick gate isolation layer 2 is located on the front side (first surface) of the N-type silicon substrate 1, and the silicon dioxide thick gate isolation layer 2 is formed with a plurality of first through holes 21, a plurality of second through holes 22 and an electrode groove 23 penetrating the silicon dioxide thick gate isolation layer 2, and the first through holes 21 are correspondingly connected to the neutron material filling hole 11; the boron ion layer 3 is formed The N-type silicon substrate 1 is formed in the surface layer on the front side, and is distributed in the second through hole 22 and the projection area of ​​the electrode groove 23 on the N-type silicon substrate 1; the silicon dioxide thin gate passivation layer 4 is located in the second through hole 22 and is in contact with the boron ion layer 3; the phosphorus ion layer 5 is formed in the surface layer on the back side (second surface) of the N-type silicon substrate 1; the P-side metal electrode 6 is arranged in the electrode groove 23 and is in contact with the boron ion layer 3; the N-side metal electrode 7 is located on the back side of the N-type silicon substrate 1 and is in contact with the phosphorus ion layer 5; the neutron material filling layer 8 is filled in the first through hole 21, the neutron material filling hole 11 and the second through hole 22 and covers the upper surface of the silicon dioxide thick gate isolation layer 2.

[0043] It can be understood that the silicon-based microstructure chip unit of the present embodiment is a deep-hole type silicon-based PIPS (Passivated Implanted Planar Silicon, ion-type passivated planar silicon manufacturing process) microstructure. The neutron material filling hole 11 on the N-type silicon substrate 1 and the first through hole 21 of the silicon dioxide thick gate isolation layer 2 form a cylindrical deep hole structure for filling the neutron material filling layer 8 to increase the contact area between silicon and the neutron conversion material. The incident neutrons react with the neutron material filling layer 8 to release charged particles (α particles or tritium nuclei). The charged particles enter the sensitive area of ​​the N-type silicon substrate 1 to generate electron-hole pairs. The boron ion layer 3 and the phosphorus ion layer 5 form a PN junction, and a depletion layer is established under reverse bias to drive carriers to migrate to the electrodes. The P-side metal electrode 6 and the N-side metal electrode 7 collect charges and output electrical signals. The silicon dioxide thick gate isolation layer 2 isolates the deep hole from the sensitive area to reduce leakage current; the silicon dioxide thin gate passivation layer 4 passivates surface defects to suppress environmental interference.

[0044] From a structural point of view, the cylindrical deep hole in the silicon-based microstructure chip unit of this embodiment can effectively suppress the edge effect of the groove-type and inverted pyramid-type microstructures, avoid the edge electric field distortion of the groove-type / inverted pyramid structure, and ensure the uniformity of charge collection; compared with other microstructures, the cylindrical deep hole microstructure has a higher conversion material filling rate. From a process point of view, the microstructure formed by the silicon-based microstructure chip unit of this embodiment adopts the PIPS process, which can break through the limitation of the microstructure shape and prepare a microstructure with a higher filling rate, wherein the silicon dioxide thin gate passivation layer 4 is used as a passivation protection, and has a strong ability to resist the influence of the environmental atmosphere, and the surface isolation technology of the silicon dioxide thick gate isolation layer 2, as an isolation layer between the deep hole and the sensitive area, can ensure the efficient collection of the carriers generated by the charged particles in the sensitive area on the electrode, and at the same time, it can also suppress the increase of the leakage current caused by the microstructure etching damage to a certain extent, thereby reducing the noise of the detector, and the silicon dioxide thick gate isolation layer 2 and the silicon dioxide thin gate passivation layer 4 work together to reduce the leakage current (<1nA) and the noise level, and enhance the stability of the detector in a complex environment.

[0045] In some embodiments of the silicon-based microstructure chip unit of the present invention, a plurality of neutron material-filled holes 11 are arranged in a matrix on an N-type silicon substrate 1, a plurality of first through holes 21 are arranged one-to-one corresponding to the plurality of neutron material-filled holes 11 on a silicon dioxide thick gate isolation layer 2, a plurality of second through holes 22 are arranged in a matrix on the silicon dioxide thick gate isolation layer 2, and an electrode groove 23 is located at the edge of the silicon dioxide thick gate isolation layer 2 to form an annular contact electrode window.

[0046] It can be understood that the neutron material filling holes 11 are arranged in a regular matrix form (such as a 10×10 array) on the N-type silicon substrate 1, and the size, depth and spacing of each hole are optimized. This arrangement forms a periodic deep hole structure on the N-type silicon substrate 1 through periodic repetition of units, maximizing the filling density of the neutron conversion material. The matrix arrangement avoids the waste of gaps between holes, and the filling rate can reach more than 90%, which significantly improves the neutron absorption efficiency. The regular arrangement reduces local electric field distortion, ensures uniform charge collection, and reduces signal noise.

[0047] The first through hole 21 on the silicon dioxide thick gate isolation layer 2 is vertically aligned with the neutron material filling hole 11 in the silicon substrate to form a continuous "filling channel". In the process, the through hole position is synchronously defined by photolithography and etching technology to ensure that the two are accurately aligned. When the neutron material is filled, the solution flows into the neutron material filling hole 11 through the first through hole 21 to achieve non-dead angle penetration. The second through hole 22 is also arranged in a matrix on the silicon dioxide thick gate isolation layer 2, but its function is different from that of the first through hole 21. The second through hole 22 corresponds to the boron ion layer 3 area below, which is used for the formation of the silicon dioxide thin gate passivation layer 4 and electrode contact. The generated silicon dioxide thin gate passivation layer 4 protects the boron doped area from environmental erosion. The through hole design of this embodiment only passivates the key area (such as the boron ion layer 3), reduces the process complexity, and the through holes arranged in the matrix evenly distribute the electric field to improve the carrier migration efficiency. The electrode groove 23 is located at the edge of the silicon dioxide thick gate isolation layer 2 and is designed in an annular shape. A groove is opened at the edge of the thick gate layer by photolithography and etching to expose the boron ion layer 3 underneath. Subsequently, a composite metal (Ti / Ni / Ag) is sputtered to form a P-side metal electrode 6. The annular structure covers the perimeter of the chip to ensure that the contact area between the electrode and the silicon substrate is maximized.

[0048] In some embodiments of the silicon-based microstructure chip unit of the present invention, the thickness of the N-type silicon substrate 1 is 250μm~350μm, and the resistivity is not less than 10000Ω·cm. The thickness of the N-type silicon substrate 1 of 250μm~350μm (preferably 300μm) balances the mechanical strength and neutron penetration ability. A thinner substrate (such as <250μm) is easy to break, while a thicker substrate (such as >350μm) will increase neutron attenuation and reduce detection sensitivity. The thickness of 250μm~350μm allows the depth of the sensitive area to reach more than 200μm, covering the range (about 20~50μm) of charged particles (such as alpha particles) released by the neutron conversion material, ensuring efficient charge collection. Resistivity ≥10000Ω·cm ensures that the silicon substrate has a low background carrier concentration, reduces leakage current (typical value <1nA), and at the same time increases the width of the depletion layer under reverse bias and expands the volume of the sensitive area. The high resistivity silicon substrate reduces thermal noise and improves the signal-to-noise ratio (SNR>50dB).

[0049] In some examples, the pore diameter of the neutron material filled hole 11 is 20μm~40μm, the pore depth of the neutron material filled hole 11 is 170μm~230μm, and the center spacing between two adjacent neutron material filled holes 11 is 80μm~120μm. It can be understood that the neutron material filled hole 11 with a pore diameter of 20~40μm (preferably 30μm) and a hole depth of 170~230μm (preferably 200μm) forms a cylindrical micropore with an aspect ratio of 4:1~11:1. High aspect ratio etching is achieved through the Bosch process (alternating etching and passivation) to avoid filling defects caused by rough side walls. The center spacing of 80~120μm ensures that the remaining thickness of the silicon substrate between adjacent holes is ≥40μm, preventing brittle fracture of the structure while maintaining a high filling rate (>85%). The deep hole structure formed in this example increases the filling amount of neutron conversion material to more than twice that of the traditional groove structure, and the neutron detection efficiency can reach 50%~60%. Through reasonable spacing design, the chip's bending strength is >200MPa, meeting industrial-grade reliability requirements.

[0050] In some specific examples, the thickness of the silicon dioxide thick gate isolation layer 2 is 0.5 μm to 0.9 μm, and the thickness of the silicon dioxide thin gate passivation layer 4 is 0.1 μm to 0.3 μm. It can be understood that the 0.5-0.9 μm silicon dioxide thick gate isolation layer 2 acts as a dielectric isolation layer to block the leakage path between the silicon substrate and the sensitive area, while providing mechanical support. The 0.1 μm to 0.3 μm silicon dioxide thin gate passivation layer 4 covers the boron ion layer 3 area, and can be used to generate a dense passivation film by dry oxygen oxidation (900°C, 30 min), reducing the surface state density (<10 10 cm -2 ·eV -1） , inhibiting interface recombination. In this example, the thick silicon dioxide gate isolation layer 2 limits the leakage current to <1nA (the leakage current of the traditional gold-silicon surface barrier detector is about 10nA), and the thin silicon dioxide gate passivation layer 4 reduces the dark current by 30%~50%, improving the detection efficiency of low-energy particles.

[0051] In some examples, the boron ion layer 3 is formed by implanting boron ions into the surface layer of the front side of the N-type silicon substrate 1 by an ion implanter, and the energy of the implanted boron ions is 90 keV, and the implantation dose satisfies 2×10 14 ions / cm 2 The phosphorus ion layer 5 is formed by an ion implanter implanting phosphorus ions into the surface layer on the back of the N-type silicon substrate 1. The energy of the implanted phosphorus ions is 65keV, and the implantation dose satisfies 1×10 16 ions / cm 2 It can be understood that the boron ion layer 3 and the phosphorus ion layer 5 form a PN junction. The 90keV boron ion energy makes the boron ion projection range (Rp) on the N-type silicon substrate 1 about 0.3μm, forming a shallow junction (junction depth <0.5μm), reducing the dead layer thickness; the implantation dose meets 2×1014 ions / cm 2 Achieve surface doping concentration less than 10 19 cm -3 , ensuring ohmic contact. For phosphorus ion layer 5, 65keV energy phosphorus ion implantation corresponds to Rp≈0.1μm, combined with a high dose of 1×10 16 ions / cm 2 Formation of heavily doped N⁺ layer (concentration>10 20 cm -3 ), reducing the back contact resistance (<1Ω·cm).

[0052] In some examples, the P-side metal electrode 6 and the N-side metal electrode 7 adopt composite metal electrodes, which include a titanium metal layer, a nickel metal layer and a silver metal layer from bottom to top, and satisfy the thickness ratio of titanium metal layer: nickel metal layer: silver metal layer = 1:1:2. It can be understood that the P-side metal electrode 6 and the N-side metal electrode 7 in this example both adopt a stacked design, which are titanium (Ti) metal layer, nickel (Ni) metal layer, and silver (Ag) metal layer from bottom to top, with a thickness ratio of 1:1:2 (for example: Ti layer 50nm, Ni layer 50nm, Ag layer 100nm), and each layer of metal is deposited in sequence by magnetron sputtering or electron beam evaporation to ensure that the interlayers are tightly bonded without voids.

[0053] Among them, the titanium layer (Ti) is in direct contact with the silicon substrate as the bottom layer, and the high adhesion of titanium (binding energy>5J / m 2 ) and low barrier characteristics, forming an ohmic contact, Ti reacts slightly with the silicon surface to form TiSi 2 phase, reduce contact resistance (<10 -4 Ω·cm). The nickel layer (Ni) acts as a barrier layer to prevent the upper silver atoms from diffusing into the silicon substrate and forming intermetallic compounds (such as AgSi) that lead to contact failure. The diffusion coefficient of nickel (D≈10 -14 cm 2 / s, 300K) is much lower than silver (D≈10 -8 cm 2 / s, effectively protecting the underlying structure. The silver layer (Ag) is used as a conductive layer, taking advantage of the high electrical conductivity of silver (σ=6.3×10 7 S / m), reducing the overall resistance of the electrode and increasing the signal transmission speed. Through the stacking design, the contact resistance of the composite electrode is reduced to <0.1Ω·mm 2 (Conventional Al electrode is about 1Ω·mm 2 ), improve the detector response speed (rise time <10ns); the nickel layer blocks metal diffusion, and the resistance change of the electrode is <5% after working for 1000 hours at high temperature (85°C); the surface oxidation rate of the silver layer is low (Ag 2O generation rate <1nm / year), adapt to high humidity environment (RH>80%).

[0054] The neutron material filling layer 8 includes at least one of boron carbide particles and lithium fluoride particles, and the particle size of the particles is less than 1 μm. 4 C) By 10 B(n,α) 7 Li reacts (thermal neutron absorption cross section 3840 barn), releasing alpha particles (energy 2.3 MeV) and lithium nuclei. Lithium fluoride (LiF) is produced by 6 Li(n,α) 3 H reaction (thermal neutron absorption cross section 940 barn), releasing alpha particles (energy 2.1 MeV) and tritium nuclei. Boron carbide (B 4 C) When filled, the thermal neutron detection efficiency is >50% (about 30% for traditional planar structure); mixed material (B 4 C:LiF=3:1) takes into account both fast neutron and thermal neutron detection, and the efficiency is increased to 60%. In this example, submicron particles reduce the voids in the pores, the filling density is >2.5g / cm³ (theoretical value 2.9g / cm³), and the small particle size shortens the range of charged particles in the material (α particles in B 4 C range <5μm), more energy is deposited in the silicon sensitive area.

[0055] Another aspect of the present invention provides a method for preparing a silicon-based microstructure chip unit, which is suitable for preparing any of the above-mentioned silicon-based microstructure chip units, see Figure 2 As shown, the method for preparing the silicon-based microstructure chip unit includes the following steps S1 to S8.

[0056] S1. See Figure 3 As shown, the N-type silicon substrate 1 is subjected to wet oxygen oxidation to form a silicon dioxide thick gate isolation layer 2 on the front side of the N-type silicon substrate 1 .

[0057] The N-type silicon substrate 1 is placed in a high-temperature oxidation furnace and water vapor (H 2 O) and oxygen (O 2 ) mixed gas, the temperature is controlled at 950~1050°C, the oxidation time is 2~4 hours, and a silicon dioxide thick gate isolation layer 2 with a thickness of 0.5~0.9μm is generated (the silicon dioxide thick gate isolation layer 2 will be generated on both the front and back sides of the N-type silicon substrate 1, and the silicon dioxide thick gate isolation layer 2 on the back side will not be spin-coated with photoresist later. When the silicon dioxide thick gate isolation layer 2 on the front side is photolithographically processed, the silicon dioxide thick gate isolation layer 2 on the back side is removed at the same time). The silicon dioxide thick gate isolation layer 2 serves as a dielectric isolation layer to block the leakage path in the subsequent process and provide a flat surface for subsequent photolithography.

[0058] S2. Continue to see Figure 3As shown, photoresist is spin-coated on the silicon dioxide thick gate isolation layer 2 on the front side of the N-type silicon substrate 1, and a second through hole 22 and an electrode groove 23 are etched on the silicon dioxide thick gate isolation layer 2 on the front side of the N-type silicon substrate 1 by photolithography.

[0059] Specifically, a positive photoresist (such as AZ5214E) was used, with a spin coating thickness of 1.5-2 μm, pre-baked (90°C, 1 min) and then exposed through a mask (wavelength 365 nm, dose 200 mJ / cm 2 ), and a through-hole pattern is formed after development. Reactive ion etching (RIE) is used, and the gas is CF 4 / O 2 The mixed gas has an etching rate of 100 nm / min, and the silicon dioxide thick gate isolation layer 2 is accurately etched through to form a second through hole 22 and an annular electrode groove 23 .

[0060] S3 , performing dry oxygen oxidation on the projection area of ​​the second through hole 22 and the electrode groove 23 in the N-type silicon substrate 1 to form a silicon dioxide thin gate passivation layer 4 .

[0061] In a dry oxygen environment (pure O 2 ), the temperature is 900°C, the oxidation time is 30-60 minutes, and a silicon dioxide thin gate passivation layer 4 with a thickness of 0.1-0.3 μm is generated to cover the surface of the N-type silicon substrate 1 corresponding to the second through hole 22 and the electrode groove 23 (the silicon dioxide thin gate passivation layer 4 is also generated on the back of the N-type silicon substrate 1 at this time, and it will be removed when etching the electrode window later), passivating the surface defects of the N-type silicon substrate 1 (such as dangling bonds), and reducing the interface state density to <10¹ 0 cm -2 eV -1 .

[0062] S4. Continue to see Figure 3 As shown, boron ions are injected into the surface layer of the projection area of ​​the second through hole 22 and the electrode groove 23 of the N-type silicon substrate 1 to form a boron ion layer 3 in the front surface layer of the N-type silicon substrate 1; phosphorus ions are injected into the back surface layer of the N-type silicon substrate 1 to form a phosphorus ion layer 5.

[0063] Boron ion implantation was performed using an ion implanter: energy 90 keV, dose 2×10 14 ions / cm 2 A shallow junction (junction depth < 0.5 μm) is formed on the second through hole 22 and the projection area of ​​the electrode groove 23 on the front side of the N-type silicon substrate 1, and the surface doping concentration is less than 10¹ 9 cm -3 , that is, boron ion layer 3.

[0064] Phosphorus ion implantation was performed using an ion implanter: energy 65 keV, dose 1×10 16 ions / cm2 , forming an N⁺ layer (concentration>10²) on the back of the N-type silicon substrate 1 0 cm⁻³), that is, phosphorus ion layer 5.

[0065] After ion implantation, annealing is performed: rapid thermal annealing (RTA) is performed at 950°C for 10 seconds to activate the doped ions.

[0066] S5. See Figure 4 As shown, the photoresist after photolithography is removed, and the photoresist is re-spin-coated on the silicon dioxide thick gate isolation layer 2 on the front side of the N-type silicon substrate 1, and the electrode groove 23 is photolithographically processed and the silicon dioxide thin gate passivation layer 4 in the electrode groove 23 is removed.

[0067] Specifically, the photoresist is re-spin-coated, and the electrode groove 23 area is selectively exposed through a mask. After development, the silicon dioxide thin gate passivation layer 4 in the electrode groove 23 is exposed, and buffered hydrofluoric acid (BHF) wet etching is used to remove the silicon dioxide thin gate passivation layer 4 in the electrode groove 23 to expose the boron ion layer 3 below.

[0068] S6 , removing the photoresist after photolithography, sputtering electrode material in the electrode groove 23 to form a P-side metal electrode 6 , and sputtering electrode material on the back side of the N-type silicon substrate 1 to form an N-side metal electrode 7 .

[0069] Specifically, magnetron sputtering is used to sequentially deposit titanium (Ti, 50nm), nickel (Ni, 50nm), and silver (Ag, 100nm) with a thickness ratio of 1:1:2, a sputtering power of 200W, a deposition rate of Ti0.5nm / s, Ni0.3nm / s, and Ag1.2nm / s to form a composite electrode on the silicon dioxide thick gate isolation layer 2 and the back side of the N-type silicon substrate 1. The contact resistance of the formed composite electrode is <0.1Ω·mm 2 .

[0070] See also Figure 5 As shown, for the composite electrode on the silicon dioxide thick gate isolation layer 2, the photoresist is spin-coated again, and then all the redundant metal electrodes except the composite electrode corresponding to the electrode groove 23 are etched away, leaving only the electrode at the electrode groove 23 as the P-side metal electrode 6.

[0071] S7, see Figure 6 As shown, photoresist is re-spin-coated on the silicon dioxide thick gate isolation layer 2 on the front side of the N-type silicon substrate 1, a first through hole 21 is etched on the silicon dioxide thick gate isolation layer 2, and etching is continued to etch a neutron material filling hole 11 on the N-type silicon substrate 1 to form a neutron material filling frame.

[0072] Specifically, using the Bosch process (etching / passivation cycle), SF 6 Etching gas and C 4F 6 Passivation gas is introduced alternately, and the etching rate is 5-10μm / min, forming a neutron material filling hole 11 with a hole diameter of 30μm and a hole depth of 200μm. The first through hole 21 is vertically aligned with the neutron material filling hole 11, with a deviation of <1μm. The aspect ratio of the neutron material filling hole 11 is 11:1 (hole diameter 20μm, depth 220μm), the filling rate is >90%, and the side wall roughness is <50nm, avoiding filling material residue.

[0073] S8. Remove the photoresist after photolithography, and fill the formed neutron material filling frame with neutron conversion material, so that the neutron conversion material fills the first through hole 21, the neutron material filling hole 11 and the second through hole 22 and covers the upper surface of the silicon dioxide thick gate isolation layer 2 to form a neutron material filling layer 8, thereby completing the preparation of the silicon-based microstructure chip unit.

[0074] The method for preparing the silicon-based microstructure chip unit of this embodiment systematically solves the problems of low filling rate, thick dead layer, and large leakage current of traditional silicon-based neutron detectors through key technologies such as wet oxygen / dry oxygen oxidation synergy, high-precision photolithography etching, shallow junction ion implantation, and ultrasonic-assisted filling. Based on deep hole etching and precise alignment, a high aspect ratio filling structure is realized; through composite electrodes and thin gate passivation, low resistance and high stability are taken into account; through submicron neutron material filling, neutron absorption efficiency is maximized. The method for preparing the silicon-based microstructure chip unit of this embodiment provides a high-sensitivity and high-reliability detector preparation path for the fields of nuclear radiation monitoring, neutron imaging, etc.

[0075] In some embodiments of the method for preparing the silicon-based microstructure chip unit of the present invention, filling the formed neutron material filling frame with neutron conversion material includes: preparing a neutron conversion filling solution. In some specific examples, the proportion of the neutron conversion filling solution may be boron carbide (B 4 C) Solution: 10 mL of isopropanol + 0.05 g of boron carbide particles, particle size <1 μm (D50≈500 nm), or lithium fluoride (LiF) solution: 10 mL of isopropanol + 0.05 g of lithium fluoride particles, particle size <1 μm; or a mixed solution: 10 mL of isopropanol + 0.0375 g of boron carbide + 0.0125 g of lithium fluoride (mass ratio 3:1). Ultrasonic vibration is used to make the neutron conversion filling solution form a colloidal solution; the neutron material filling frame is placed at the bottom of the colloidal solution, and the bubbles in the first through hole 21, the neutron material filling hole 11 and the second through hole 22 are removed by ultrasonic vibration and filled with colloidal solution; the neutron material filling frame and the filled colloidal solution are transferred to a shaker for low-speed filling, the shaker speed is 100 rpm, and the low-speed filling time is 30 minutes; the colloidal solution on the neutron material filling frame is dried in an oven to form a neutron material filling layer 8.

[0076] Another aspect of the present invention provides a silicon-based microstructure neutron detector, which is packaged using the silicon-based microstructure chip unit of any one of the above embodiments or examples. Figure 7 As shown, the silicon-based microstructure neutron detector includes a PCB board 100 and a radio frequency coaxial connector interface 200, a silicon-based microstructure chip unit is embedded on the PCB board 100, the P-side metal electrode 6 of the silicon-based microstructure chip unit is bonded to a pad 300 on the PCB board 100 by silicon-aluminum wire bonding, the pad 300 is connected to a pin at one end of the radio frequency coaxial connector interface 200, and the N-side metal electrode 7 of the silicon-based microstructure chip unit is connected to another pin at one end of the radio frequency coaxial connector interface 200.

[0077] It can be understood that in the silicon-based microstructure neutron detector structure of this embodiment, the silicon-based microstructure chip unit is such as the silicon-based microstructure chip unit in any of the above embodiments or examples, including a neutron material filling layer 8, a P-side metal electrode 6, an N-side metal electrode 7 and a high-resistivity N-type silicon substrate 1, etc., which are responsible for neutron absorption, charge conversion and signal generation; the PCB board 100 can adopt FR-4 or ceramic substrate, and the surface is designed with pads 300 and signal traces to provide mechanical support and electrical signal transmission paths; the RF coaxial connector interface 200 can use an SMA or BNC interface, with an impedance of 50Ω and a frequency range of DC-6 GHz, for low-noise signal output. Since the silicon-based microstructure neutron detector of this embodiment is packaged and constructed using the silicon-based microstructure chip unit of the present invention, it must have all the advantages of the silicon-based microstructure chip unit of the present invention.

[0078] The silicon-based microstructure chip unit is fixed to the central area of ​​the PCB board 100 by conductive glue or eutectic welding (such as Au-Si, temperature 400°C), and the P-side metal electrode 6 is connected to the PCB pad 300 by ultrasonic bonding (frequency 60kHz, pressure 0.5N, time 20ms) using silicon aluminum wire (diameter 25μm); the N-side metal electrode 7 is connected to the other pin of the RF coaxial connector interface 200 by gold wire ball welding (diameter 30μm) or direct welding. Epoxy resin (such as EPO-TEK 353ND) or ceramic shell is used for airtight packaging, and nitrogen gas (dew point <-40°C) is filled inside, with a protection level of IP67. Neutron incidence induces charged particles to generate electron-hole pairs, and a current signal is formed under the reverse bias of the PN junction. The signal is transmitted to the pad 300 through the silicon aluminum wire (P-side) and the gold wire (N-side), and output to the external amplifier and data processing system through the RF coaxial connector interface 200.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon-based microstructure chip unit, characterized in that: include: An N-type silicon substrate (1), wherein a plurality of neutron material-filled holes (11) are formed on the N-type silicon substrate (1); A silicon dioxide thick gate isolation layer (2) is located on the first surface of the N-type silicon substrate (1), the silicon dioxide thick gate isolation layer (2) is formed with a plurality of first through holes (21), a plurality of second through holes (22) and an electrode groove (23) penetrating the silicon dioxide thick gate isolation layer (2), the first through holes (21) being correspondingly connected to the neutron material filling holes (11); A boron ion layer (3) is formed in a surface layer of the first surface of the N-type silicon substrate (1) and is distributed in a projection area of ​​the second through hole (22) and the electrode groove (23) on the N-type silicon substrate (1); A silicon dioxide thin gate passivation layer (4), located in the second through hole (22) and in contact with the boron ion layer (3); A phosphorus ion layer (5) formed in a surface layer of the second surface of the N-type silicon substrate (1); A P-surface metal electrode (6) disposed in the electrode groove (23) and in contact with the boron ion layer (3); An N-side metal electrode (7) located on the second surface of the N-type silicon substrate (1) and in contact with the phosphorus ion layer (5); A neutron material filling layer (8) is filled in the first through hole (21), the neutron material filling hole (11) and the second through hole (22), and covers the upper surface of the silicon dioxide thick gate isolation layer (2).

2. The silicon-based microstructure chip unit according to claim 1, characterized in that: A plurality of neutron material filling holes (11) are arranged in a matrix on the N-type silicon substrate (1); a plurality of first through holes (21) are arranged on the silicon dioxide thick gate isolation layer (2) in a one-to-one correspondence with the plurality of neutron material filling holes (11); a plurality of second through holes (22) are arranged in a matrix on the silicon dioxide thick gate isolation layer (2); and the electrode groove (23) is located at the edge of the silicon dioxide thick gate isolation layer (2) to form an annular contact electrode window.

3. The silicon-based microstructure chip unit according to claim 2, characterized in that: The N-type silicon substrate (1) has a thickness of 250 μm to 350 μm and a resistivity of not less than 10000 Ω·cm; The neutron material filling hole (11) has a hole diameter of 20 μm to 40 μm, a hole depth of 170 μm to 230 μm, and a center distance between two adjacent neutron material filling holes (11) of 80 μm to 120 μm.

4. The silicon-based microstructure chip unit according to claim 1, characterized in that: The silicon dioxide thick gate isolation layer (2) has a thickness of 0.5 μm to 0.9 μm, and the silicon dioxide thin gate passivation layer (4) has a thickness of 0.1 μm to 0.3 μm; The boron ion layer (3) is formed by implanting boron ions into the surface layer of the first surface of the N-type silicon substrate (1) using an ion implanter, wherein the energy of the implanted boron ions is 90 keV and the implantation dose satisfies 2×10 14 ions / cm 2 The phosphorus ion layer (5) is formed by an ion implanter implanting phosphorus ions into the surface layer of the second surface of the N-type silicon substrate (1), the energy of the implanted phosphorus ions is 65 keV, and the implantation dose satisfies 1×10 16 ions / cm 2 .

5. The silicon-based microstructure chip unit according to claim 1, characterized in that: The P-side metal electrode (6) and the N-side metal electrode (7) are composite metal electrodes, and the composite metal electrode comprises a titanium metal layer, a nickel metal layer and a silver metal layer in order from bottom to top, and the thickness ratio of the titanium metal layer: the nickel metal layer: the silver metal layer is 1:1:2; The neutron material filling layer (8) comprises at least one of boron carbide particles and lithium fluoride particles, and the particle size of the particles is less than 1 μm.

6. A method for preparing a silicon-based microstructure chip unit, characterized in that: Suitable for preparing the silicon-based microstructure chip unit according to any one of claims 1 to 5, the preparation method of the silicon-based microstructure chip unit comprises: Performing wet oxygen oxidation on an N-type silicon substrate (1) to form a silicon dioxide thick gate isolation layer (2) on a first surface of the N-type silicon substrate (1); Spin-coating photoresist on the silicon dioxide thick gate isolation layer (2) on the first surface of the N-type silicon substrate (1), and etching a second through hole (22) and an electrode groove (23) on the silicon dioxide thick gate isolation layer (2) on the first surface of the N-type silicon substrate (1) by photolithography; Performing dry oxygen oxidation on the second through hole (22) and the electrode groove (23) in the projection area of ​​the N-type silicon substrate (1) to form a silicon dioxide thin gate passivation layer (4); Injecting boron ions into the surface layer of the projection area of ​​the N-type silicon substrate (1) in the second through hole (22) and the electrode groove (23) to form a boron ion layer (3) in the first surface layer of the N-type silicon substrate (1); and injecting phosphorus ions into the second surface layer of the N-type silicon substrate (1) to form a phosphorus ion layer (5); Removing the photoresist after photolithography, re-spinning the photoresist on the silicon dioxide thick gate isolation layer (2) on the first surface of the N-type silicon substrate (1), photolithography the electrode groove (23) and removing the silicon dioxide thin gate passivation layer (4) in the electrode groove (23); Removing the photoresist after photolithography, sputtering electrode material in the electrode groove (23) to form a P-side metal electrode (6), and sputtering electrode material on the second surface of the N-type silicon substrate (1) to form an N-side metal electrode (7); Spin-coating photoresist again on the silicon dioxide thick gate isolation layer (2) on the first surface of the N-type silicon substrate (1), etching a first through hole (21) on the silicon dioxide thick gate isolation layer (2), and continuing etching to etch a neutron material filling hole (11) on the N-type silicon substrate (1) to form a neutron material filling framework; The photoresist after photolithography is removed, and the formed neutron material filling frame is filled with neutron conversion material, so that the neutron conversion material fills the first through hole (21), the neutron material filling hole (11) and the second through hole (22) and covers the upper surface of the silicon dioxide thick gate isolation layer (2) to form a neutron material filling layer (8), thereby completing the preparation of the silicon-based microstructure chip unit.

7. The method for preparing a silicon-based microstructure chip unit according to claim 6, characterized in that: The filling of the formed neutron material filling framework with neutron conversion material comprises: Prepare neutron conversion filling solution; Ultrasonic vibration is used to convert the neutron filling solution into a colloidal solution; Placing the neutron material filling frame at the bottom of the colloidal solution, removing bubbles in the first through hole (21), the neutron material filling hole (11) and the second through hole (22) by using ultrasonic vibration, and filling the colloidal solution; Transferring the neutron material filling frame and the filled colloidal solution to a shaker for low-speed filling, the shaker speed is 100 rpm, and the low-speed filling time is 30 minutes; The colloidal solution on the neutron material filling frame is dried in an oven to form a neutron material filling layer (8).

8. The method for preparing a silicon-based microstructure chip unit according to claim 6, characterized in that: Neutron conversion fill solution includes: Isopropyl alcohol and boron carbide particles, and the ratio of isopropyl alcohol: boron carbide particles = 10mL: 0.05g; or, Isopropyl alcohol and lithium fluoride particles, and the ratio of isopropyl alcohol: lithium fluoride particles = 10mL: 0.05g; or, Isopropyl alcohol and neutron conversion material, and the ratio of isopropyl alcohol: neutron conversion material = 10 mL: 0.05 g, the neutron conversion material comprises boron carbide particles and lithium fluoride particles, and the boron carbide particles and the lithium fluoride particles meet a mass ratio of 3:

1.

9. A silicon-based microstructure neutron detector, characterized in that: The silicon-based microstructure neutron detector is packaged using the silicon-based microstructure chip unit described in any one of claims 1 to 5.

10. The silicon-based microstructure neutron detector according to claim 9, characterized in that: The silicon-based microstructure neutron detector comprises a PCB board (100) and a radio frequency coaxial connector interface (200); the silicon-based microstructure chip unit is embedded on the PCB board (100); the P-side metal electrode (6) of the silicon-based microstructure chip unit is bonded to a pad (300) on the PCB board (100) by silicon-aluminum wire bonding; the pad (300) is connected to a pin at one end of the radio frequency coaxial connector interface (200); and the N-side metal electrode (7) of the silicon-based microstructure chip unit is connected to another pin at one end of the radio frequency coaxial connector interface (200).

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