TSHJ solar cell structure and preparation method thereof, and photovoltaic module
By adopting the TSHJ structure in the SHJ solar cell, and using the poly passivation structure and the aluminum oxide and silicon nitride passivation structure, the problem of frontal current loss of SHJ solar cell is solved, which improves Voc and reduces the ultraviolet light fading, and reduces the demand for light-to-film.
Patent Information
- Application Number
- CN202510262735.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-06
- Publication Date
- 2025-06-06
AI Technical Summary
The front current loss of SHJ solar cells is large, and this defect needs to be overcome.
The TSHJ solar cell structure is adopted, and the front side is made of the gate line region of the poly passivation structure and the non-gate line region of the passivation structure of alumina and silicon nitride passivation structure. It is prepared by double-sided fleece making, tunneling oxide layer deposition, phosphorus doped amorphous silicon layer crystallization, laser ablation and etching.
The open circuit voltage (Voc) of solar cells is increased, the current loss problem on the front of traditional SHJ solar cells is overcome, and the problem of passivation of amorphous silicon ultraviolet light is reduced, and the demand for light-to-film is reduced.
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Figure CN120111986A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of crystalline silicon solar cells, and in particular relates to a TSHJ solar cell structure and a preparation method thereof, and a photovoltaic module. Background Art
[0002] Photovoltaic power generation is a system that uses solar cells to directly convert sunlight energy into electrical energy based on the principle of the photovoltaic effect. The basic structure of a solar cell is a large-area planar PN junction. When sunlight shines on the PN junction, the PN junction absorbs light energy to excite electrons and holes, and then generates voltage in the PN junction to achieve photoelectric conversion. Therefore, the core structure that realizes the conversion of sunlight energy and electrical energy in crystalline silicon cells is the PN junction.
[0003] At present, the mainstream solar cell structures include Topcon (tunnel oxide passivation contact), SHJ (heterojunction), and IBC (interdigitated back contact). Among them, SHJ technology has been recognized by many manufacturers and institutions because of its fewer production processes, small equipment footprint, and the expected further reduction in production costs.
[0004] The advantages of SHJ cells include high efficiency, low light decay, high bifaciality, low temperature coefficient, good weak light response, etc. In addition, SHJ cells also have good stability and low decay rate, which can ensure long-term and stable power generation effect.
[0005] However, SHJ solar cells also have some defects, such as large current loss on the front side of the cell due to the poor conductivity of amorphous silicon.
[0006] Therefore, how to overcome the defect of front current loss in SHJ solar cells is a technical problem that needs to be solved urgently in this field.
[0007] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Summary of the invention
[0008] The embodiments of the present disclosure at least provide a TSHJ solar cell structure and a preparation method thereof, and a photovoltaic module.
[0009] In a first aspect, the disclosed embodiment provides a method for preparing a TSHJ solar cell, comprising the following steps: step S1, performing double-sided texturing on a silicon wafer to prepare a clean silicon wafer surface with a pyramid texturing morphology; step S2, oxidizing the front side of the silicon wafer to prepare a tunneling oxide layer, and depositing a phosphorus-doped amorphous silicon layer thereon; step S3, performing high-temperature annealing on the silicon wafer to crystallize the phosphorus-doped amorphous silicon layer into a polycrystalline silicon layer, and forming an N+ emitter; step S4, performing patterned etching on the front side of the silicon wafer by laser ablation to form a groove and expose the silicon substrate; step S5, polishing the grooved portion of the grooved silicon wafer to make it smooth Process and clean; step S6, depositing a layer of i: a-Si layer from top to bottom on the back side of the silicon wafer, and then depositing a P: a-Si layer from top to bottom after HPT cleaning the deposited surface; step S7, depositing an aluminum oxide layer and a silicon nitride layer from top to bottom on the front side of the silicon wafer; step S8, depositing a layer of TCO layer on the back side of the silicon wafer; step S9, patterning the aluminum oxide layer and the silicon nitride layer in the printed area on the front side of the silicon wafer by laser ablation to expose the polysilicon layer; step S10, printing metal slurry on the exposed area of the polysilicon layer on the front side of the silicon wafer and on the back side respectively, drying and curing, and completing the preparation of the battery.
[0010] In an optional implementation manner, the reflectivity of the silicon wafer surface after texturing in step S1 is 9-12%; the width of the pyramid is 1-5 μm, and the height is 0.5-5 μm.
[0011] In an optional embodiment, the component of the tunneling oxide layer in step S2 includes SiO 2 , and the thickness is 0.5-3nm; the thickness of the phosphorus-doped amorphous silicon layer is 10-300nm, and the phosphorus doping concentration is 1E+19cm -3 ~1E+22cm -3 .
[0012] In an optional embodiment, the annealing time in step S3 is 30-90 minutes, and the annealing temperature is 850-950°C.
[0013] In an optional implementation, the width of the laser etching in step S4 is 50-500 μm.
[0014] In an optional embodiment, the thickness of the i:a-Si layer in step S6 is 2-10 nm; the P:a-Si layer includes P:a-Si layer and P-uc-SiO x C y Layering; wherein the thickness of the P: a-Si layer is 10-20nm and the doping concentration is 1E+18cm -3 ~5E+18cm -3 :The P-uc-SiO xC y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .
[0015] In an optional implementation, in step S8, the TCO layer has a thickness of 70-150 nm and a sheet resistance of 50-120.
[0016] In an optional implementation, the width of the laser etching in step S9 is 50-300 μm.
[0017] In the second aspect, the embodiment of the present disclosure also provides a TSHJ solar cell structure, which is prepared by the method as described above, including: a gate line area and a non-gate line area located on the front side; wherein the gate line area includes a poly structure; and the non-gate line area includes a stacked passivation structure of an aluminum oxide layer and a silicon nitride layer.
[0018] In a second aspect, the embodiments of the present disclosure further provide a photovoltaic module, which adopts the TSHJ solar cell structure as described above.
[0019] The beneficial effects of the present invention are that the TSHJ solar cell structure and its preparation method, and the front of the photovoltaic module adopt a grid line area with a poly passivation structure and a non-grid line area with an aluminum oxide and silicon nitride passivation structure, thereby obtaining a higher Voc, overcoming the current loss problem on the front of the traditional SHJ solar cell, and also solving the ultraviolet light attenuation problem of the amorphous silicon passivation on the front of the SHJ solar cell, thereby reducing the demand for light transfer film.
[0020] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.
[0021] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1A schematic diagram of the structure of a TSHJ solar cell provided in an embodiment of the present disclosure;
[0024] Figure 2 A schematic diagram of the structure of a TSHJ solar cell provided in an embodiment of the present disclosure;
[0025] Figure 3 A schematic diagram of the structure of a TSHJ solar cell provided in an embodiment of the present disclosure;
[0026] Figure 4 A schematic diagram of the structure of a TSHJ solar cell provided in an embodiment of the present disclosure;
[0027] Figure 5 A schematic diagram of the structure of a TSHJ solar cell provided in an embodiment of the present disclosure;
[0028] Figure 6 A schematic diagram of the structure of a TSHJ solar cell provided in an embodiment of the present disclosure;
[0029] Figure 7 A schematic diagram of the structure of a TSHJ solar cell provided in an embodiment of the present disclosure;
[0030] Figure 8 A schematic diagram of the structure of a TSHJ solar cell provided in an embodiment of the present disclosure.
[0031] In the figure:
[0032] 1. Silicon wafer; 2. Tunneling oxide layer; 3. Polysilicon layer; 4. i: a-Si layer; 5. P: a-Si layer; 6. Aluminum oxide layer; 7. Silicon nitride layer; 8. TCO layer; 9. Metal electrode. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0034] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Therefore, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, so that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. On the contrary, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.
[0035] Herein, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.
[0036] The terms used herein are only used to describe specific exemplary configurations and are not intended to be limited. As used herein, the singular articles "one", "an" and "the" may also be intended to include plural forms, unless it is clearly indicated above that this is not the case. The terms "comprise", "include" and "have" are inclusive, and therefore specify the presence of features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the specific order discussed or shown, unless specifically identified as an execution order. Additional or alternative steps may be adopted.
[0037] Prior art 1: Patent No. CN 116093169 A
[0038] Solution steps: 1. Double-sided texturing; 2. Front deposition of ia:Si; 3. Front deposition of na:Si; 4. Back deposition of ia:Si+pa:Si stacking; 5. Front and back deposition of ITO; 6. Screen printing and curing
[0039] Concept: 1. From top to bottom: TCO-na:Si-ia:Si---suede---silicon---suede---ia:Si---pa:Si----TCO-silver paste SHJ battery structure;
[0040] 2. Both the front and back sides have ia:Si+n / pa:Si+TCO structures, with fewer processes.
[0041] shortcoming:
[0042] 1. Front ia: Si+na: Si+TCO structure, amorphous silicon has serious parasitic absorption of photons;
[0043] 2. The front ia: Si+na: Si+TCO structure has a loss in the lateral transmission of current, which affects the front current of the battery;
[0044] 3. In this process, amorphous silicon is exposed for a long time without a protective film, which affects the passivation of the battery.
[0045] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.
[0046] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0047] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0048] Step S1, double-sided polishing of the silicon wafer to prepare a low-reflection smooth alkali-polished tower base morphology and a clean silicon wafer surface, and obtain Figure 1 The specific process of the silicon wafer shown is as follows:
[0049] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 2min-5min.
[0050] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0051] A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to form a low-reflectivity pyramid velvet morphology on the surface of the silicon wafer and remove cutting damage. The process temperature is 60°C-85°C and the process time is (3min-5min).
[0052] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0053] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.
[0054] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0055] Use hydrofluoric acid (0.1%-2%) and hydrochloric acid (0.1%-2%) and O 3 (10ppm-50ppm) mixed solution, clean the silicon wafer surface, and at the same time 3 The weak etching system with HF can lubricate the surface of silicon wafer and reduce the burr defects on the surface of silicon wafer (more conducive to the passivation of amorphous silicon). The process temperature is 15℃-25℃ and the process time is 2min-3min.
[0056] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0057] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;
[0058] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0059] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.
[0060] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;
[0061] Wafer weight reduction: 0.3g-0.6g; (taking 182.2 size wafer as an example)
[0062] Surface reflectivity: 9%-12%;
[0063] Tower base size: 1um-3um;
[0064] Tower height: 0.5um-3um.
[0065] Step S2, a tunnel oxide layer and phosphorus-doped amorphous silicon are sequentially deposited on the front side of the silicon wafer to obtain Figure 2 The specific process of the silicon wafer shown is as follows:
[0066] The flat-plate PECVD method is used to oxidize the front side of the cleaned and textured silicon wafer to produce SiO 2, a layer of phosphorus-doped amorphous silicon is deposited on the oxidized silicon wafer by flat-plate PVD method;
[0067] The cleaned and textured silicon wafer is placed on a hollow carrier plate and transferred to reaction chamber 1. The pecvd method is used to ionize O 2 To the plasma, the surface of the silicon wafer is oxidized from bottom to top through the hollow carrier, the carrier passes through the transition chamber, and is transferred to the reaction chamber 2, and an amorphous silicon film is deposited from bottom to top through the hollow carrier by PVD method;
[0068] Reaction chamber 1: When PECVD method is used to oxidize silicon wafers, oxygen is used as the process gas. Process temperature: 200-500℃;
[0069] Reaction chamber 2: When the phosphorus-doped amorphous silicon layer is prepared by PVD method, a silicon target is used, argon is used as the working gas, phosphine is used as the doping gas, and the process temperature is 200-500°C;
[0070] Silicon oxide: thickness 0.5nm-3nm, freely adjustable;
[0071] Phosphorus-doped amorphous silicon: thickness 10nm-300nm, phosphorus doping concentration: 1E+19cm -3 ~1E+22cm -3 , can be freely adjusted.
[0072] Step S3, the silicon wafer is placed in a high temperature annealing furnace, and at a certain temperature and time, the amorphous silicon is crystallized and the doping atoms are activated and pushed forward. The specific process is as follows:
[0073] Insert the silicon wafer horizontally or vertically into the quartz boat and transfer it to the high-temperature furnace tube through the silicon carbide slurry;
[0074] The doped amorphous silicon film is crystallized into polysilicon through high temperature annealing, and the phosphorus atoms are activated to reduce the resistivity of the film layer and penetrate the oxide layer to be doped into the silicon base to form an N+ emitter;
[0075] Annealing time: 30min-90min;
[0076] Annealing temperature: 850-950℃.
[0077] 4. Laser groove on the front to obtain Figure 3 The specific process of the silicon wafer shown is as follows:
[0078] Use laser ablation technology to remove part of the silicon substrate, oxide layer and doped amorphous silicon layer according to a certain pattern. The battery is placed on a horizontal platform surface, and a pulsed ultraviolet nanosecond laser is used to locally etch part of the silicon substrate, silicon oxide, and phosphorus-doped amorphous silicon.
[0079] Laser power: 300w-600w;
[0080] Etching width: 100um-500um, freely adjustable.
[0081] Step S5, polishing and cleaning, the specific process is as follows:
[0082] Use a mixed solution of potassium hydroxide (1%-10%) and alkali polishing additive (0.5%-5%) to clean, remove the film damage, and continue to corrode the silicon base to a certain depth. The process temperature is 55℃-70℃, and the process time is 0.5min-1.5min.
[0083] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0084] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.
[0085] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0086] A mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%) and O3 (10ppm-50ppm) is used to clean the surface of the silicon wafer. At the same time, the weak etching system of O3 and HF lubricates the surface of the silicon wafer, reduces burr defects on the surface of the silicon wafer, and is more conducive to the passivation of aluminum oxide silicon nitride. The process temperature is 15℃-25℃, and the process time is 2min-3min.
[0087] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0088] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;
[0089] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;
[0090] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.
[0091] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;
[0092] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the morphology of the back groove;
[0093] Reflectivity of corroded area: 35%-45%;
[0094] The size of the tower base in the corroded area: 5um-15um;
[0095] Corrosion depth of corroded area: 0.5um-2um.
[0096] Step S6, i: a-Si and P: a-Si are sequentially deposited on the back side to obtain Figure 4 The specific process of the silicon wafer shown is as follows:
[0097] A flat-plate PECVD method is used to deposit a layer of ia:Si from top to bottom on the back of the silicon wafer after the step 6 process, and then the deposited surface is cleaned by HPT (H ion cleaning), and then a flat-plate PECVD method is used to deposit pa:Si from top to bottom on the back of the silicon wafer. The deposition includes (a layer of pa:Si and a layer of p-uc-Si)
[0098] The silicon wafer transferred from step 6 is placed on a hollow carrier, transferred to reaction chamber 3 to deposit ia:Si from top to bottom, and then transferred to HPT cleaning chamber, where H ions clean the deposition surface to complete the preparation of ia:Si; then transferred to reaction chamber 4 to deposit a layer of pa:Si and a layer of p-uc-Si from top to bottom to complete the preparation of pa:Si;
[0099] PECVD3 reaction chamber 3: PECVD method to prepare ia: Si, SiH 4 , H 2 For process gas, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH 4 :H 2 Flow ratio: 1:10-1:30, power: 50W-300W;
[0100] PECVD4 reaction chamber 4: PECVD method to prepare pa:Si, pa:Si is divided into two layers: conventional B-doped amorphous silicon (pa:Si) and B-doped microcrystalline silicon (p-uc-Si);
[0101] Conventional B-doped amorphous silicon (Pa:Si) is prepared with SiH 4 , H 2 , BH 3 For process gas, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH 4 :H 2 : BH 3 (2%) Flow ratio: 1:20:5-1:30:15, Power: 50W-300W;
[0102] Preparation of B-doped microcrystalline silicon oxycarbide (P-uc-Si) with SiH4 , H 2 , BH 3 For process gas, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH 4 :H 2 : BH 3 (2%) Flow ratio: 1:30:10-1:60:30, Power: 300w-500W;
[0103] Buffered HPT cleaning chamber: PECVD method is used to ionize H and clean the deposited surface of the silicon wafer. 2 For process gas,
[0104] Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W;
[0105] i: a-Si thickness: 2nm-10nm, freely adjustable;
[0106] P: a-Si thickness: 10nm-20nm, P-uc-Si thickness: 20nm-50nm, thickness can be freely adjusted;
[0107] P: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 ,P-uc-Si doping concentration: 5E+18cm -3 ~2E+19cm -3 , the doping amount can be freely adjusted.
[0108] Step S7, aluminum oxide and silicon nitride are deposited on the front surface to obtain Figure 5 The specific process of the silicon wafer shown is as follows:
[0109] Alumina was deposited by single-atom deposition. The process gases were trimethylaluminum and water. The process conditions were: temperature 200-250°C. The process was: TMA 4-8s, purge 7-10s, H 2 O 4-8s, purge 7-10s, and the number of cycles is 22-51 times.
[0110] Silicon nitride is deposited by plasma chemical vapor deposition, the process gases are ammonia and silane, and the process conditions are: temperature is 450-500°C, and pressure is 200-300Pa.
[0111] Step S8, depositing TCO on the back to obtain Figure 6 The specific process of the silicon wafer shown is as follows:
[0112] When TCO is prepared by PVD method, ITO target (In 2 O3 / SnO 2 Mass ratio: 90:10-97:3), with argon and oxygen as working gases, process temperature: 100-250°C, process pressure: 0.2Pa-2Pa, TCO film thickness: 10nm-200nm, which can be freely adjusted;
[0113] Ar / O 2 Flow ratio: 200:1-100:1, power: 5000W-40000W;
[0114] TCO square resistance: 50-120.
[0115] Step S9, groove the front aluminum oxide silicon nitride, remove the aluminum oxide and silicon nitride in the front printing area, and obtain Figure 7 The specific process of the silicon wafer shown is as follows:
[0116] Laser ablation technology is used to graphically etch the aluminum oxide and silicon nitride films in the front printing area. The battery is placed on a horizontal platform and a pulsed ultraviolet nanosecond laser is used to partially etch the aluminum oxide and silicon nitride films.
[0117] Laser power: 300w-600w;
[0118] Etching width: 50um-300um, freely adjustable.
[0119] Step S10, screen printing on the exposed front surface and screen printing on the back surface to obtain Figure 8 The specific process of the silicon wafer shown is as follows:
[0120] The exposed area (poly) on the front side is printed with metal paste, and the back side is printed with paste;
[0121] After printing, the silicon wafer is transferred to a curing furnace, dried and cured to form an ohmic contact with the silicon wafer.
[0122] In summary, the TSHJ solar cell structure and its preparation method, the front of the photovoltaic module adopts a poly passivation structure in the grid line area and an aluminum oxide and silicon nitride passivation structure in the non-grid line area, which achieves a higher Voc, overcomes the current loss problem on the front of the traditional SHJ solar cell, and also solves the ultraviolet light attenuation problem of amorphous silicon passivation on the front of the SHJ solar cell, reducing the demand for light transfer film.
[0123] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.
Claims
1. A method for preparing a TSHJ solar cell, characterized in that: The steps include: Step S1, performing double-sided texturing on a silicon wafer to prepare a clean silicon wafer surface with a pyramid texturing morphology; Step S2, oxidizing the front side of the silicon wafer to prepare a tunneling oxide layer, and depositing a phosphorus-doped amorphous silicon layer thereon; Step S3, annealing the silicon wafer at high temperature to crystallize the phosphorus-doped amorphous silicon layer into a polycrystalline silicon layer and form an N+ emitter; Step S4, patterning and etching the front side of the silicon wafer by laser ablation to form grooves and expose the silicon substrate; Step S5, polishing and cleaning the grooved portion of the grooved silicon wafer; Step S6, depositing an i: a-Si layer from top to bottom on the back side of the silicon wafer, performing HPT cleaning on the deposited surface, and then depositing a P: a-Si layer from top to bottom in sequence; Step S7, depositing an aluminum oxide layer and a silicon nitride layer in sequence from top to bottom on the front side of the silicon wafer; Step S8, depositing a TCO layer on the back side of the silicon wafer; Step S9, patterning and etching the aluminum oxide layer and the silicon nitride layer in the front printing area of the silicon wafer by laser ablation to expose the polysilicon layer; Step S10, printing metal paste on the exposed area of the polysilicon layer on the front side and the back side of the silicon wafer respectively, drying and curing, and completing the preparation of the battery.
2. The preparation method according to claim 1, characterized in that The surface reflectivity of the silicon wafer after texturing in step S1 is 9-12%; The width of the pyramids is 1-5 μm and the height is 0.5-5 μm.
3. The preparation method according to claim 1, characterized in that: In step S2, the tunnel oxide layer comprises SiO2 and has a thickness of 0.5-3 nm; The thickness of the phosphorus-doped amorphous silicon layer is 10-300 nm, and the phosphorus doping concentration is 1E+19 cm -3 ~1E+22cm -3 .
4. The preparation method according to claim 1, characterized in that: The annealing time in step S3 is 30-90 minutes, and the annealing temperature is 850-950°C.
5. The preparation method according to claim 1, characterized in that: The width of the laser etching in step S4 is 50-500 μm.
6. The preparation method according to claim 1, characterized in that: In step S6 The thickness of the i:a-Si layer is 2-10 nm; The P:a-Si layer includes a P:a-Si layer and a P-uc-SiO x C y Layering; in The thickness of the P:a-Si layer is 10-20nm, and the doping concentration is 1E+18cm -3 ~5E+18cm -3 : The P-uc-SiO x C y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .
7. The preparation method according to claim 1, characterized in that: In step S8 The TCO layer has a thickness of 70-150 nm and a sheet resistance of 50-120 nm.
8. The preparation method according to claim 1, characterized in that: The width of the laser etching in step S9 is 50-300 μm.
9. A TSHJ solar cell structure, characterized in that: Prepared by the method according to any one of claims 1 to 8, comprising: The grid line area and the non-grid line area are located on the front side; The gate line region includes a poly structure; The non-gate line region includes a stacked passivation structure of an aluminum oxide layer and a silicon nitride layer.
10. A photovoltaic module, characterized in that: The TSHJ solar cell structure as claimed in claim 9 is used.
Citation Information
Patent Citations
HJT battery and preparation process
CN116093169A