Hybrid passivation back contact battery with insulating material isolation and preparation method thereof

Abstract

The invention belongs to the technical field of back contact cells, and particularly relates to a mixed passivation back contact cell with insulating material isolation and a preparation method thereof, the mixed passivation back contact cell comprises an N-type silicon substrate, the N-type silicon substrate is provided with a light receiving surface with pyramid suede morphology and a backlight surface with alkali polishing tower footing morphology; an FSF front surface passivation field and a passivation antireflection layer are sequentially stacked on the light receiving surface; an insulating material isolation region is arranged on the backlight surface, and a first semiconductor region and a second semiconductor region are arranged on the two sides of the insulating material isolation region respectively to form an interdigital arrangement structure; the transparent conductive film layer is arranged on the sides, away from the backlight face, of the insulating material isolation area, the first semiconductor area and the second semiconductor area in a covering mode, and an opening is formed in the insulating material isolation area; and the metal electrodes are respectively arranged on the transparent conductive film layers corresponding to the first semiconductor region and the second semiconductor region.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a hybrid passivated back contact battery with insulating material isolation and a preparation method thereof. Background Art

[0002] BC cells are different from other crystalline silicon cells. The emitter, surface field and metal electrode are all on the back of the cell, arranged in a cross-finger pattern. There is no grid line blocking the front of the cell, which makes maximum use of incident light and reduces optical losses. It has a high conversion efficiency and a beautiful appearance.

[0003] HTBC cell (hybrid passivated back contact cell) is a combination of BC technology and HJT&Topcon technology, taking into account the high efficiency of HBC and the low cost of TBC. The existing hybrid passivated back contact cell structure is set up from top to bottom including: passivation anti-reflection layer, front pyramid velvet morphology, silicon base, back alkali polished tower base morphology, second semiconductor, first semiconductor, transparent conductive film, first semiconductor second semiconductor isolation region, metal electrode.

[0004] The existing first semiconductor and second semiconductor isolation region is prepared by laser film opening or patterned mask etching to remove the transparent conductive film and semiconductor material at the junction of the first semiconductor and the second semiconductor, so as to achieve a structure in which the first semiconductor and the second semiconductor are arranged in fingers, isolate the PN region, and avoid leakage.

[0005] However, both laser film opening and patterned mask etching methods have a high risk of PN conduction leakage. Therefore, how to provide a low-leakage hybrid passivated back contact battery is a technical problem that needs to be solved urgently in this field.

[0006] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Summary of the invention

[0007] The embodiments of the present disclosure at least provide a hybrid passivated back contact battery with insulating material isolation and a preparation method thereof.

[0008] In the first aspect, the embodiments of the present disclosure provide a hybrid passivated back-contact battery with insulating material isolation, comprising: an N-type silicon base, wherein the N-type silicon base is provided with a light-receiving surface with a pyramid velvet morphology and a backlight surface with an alkali-polished tower base morphology; the light-receiving surface is sequentially stacked with an FSF front-surface passivation field and a passivation anti-reflection layer; the backlight surface is provided with an insulating material isolation area, and the first semiconductor area and the second semiconductor area are respectively provided on both sides of the insulating material isolation area to form an interdigitated arrangement structure; a transparent conductive film layer is covered and arranged on the side of the insulating material isolation area, the first semiconductor area and the second semiconductor area away from the backlight surface, and an opening is opened in the insulating material isolation area; metal electrodes are respectively arranged on the transparent conductive film layers corresponding to the first semiconductor area and the second semiconductor area.

[0009] In an optional embodiment, the N-type silicon substrate includes any one of a Czochralski single crystal and a cast single crystal.

[0010] In an optional embodiment, the reflectivity of the pyramid velvet surface is 9%-12%, the pyramid height is 0.8μm-5μm, and the pyramid width is 1μm-5μm; the reflectivity of the alkali-polished tower base is 35%-45%, and the tower base size is 5μm-15μm.

[0011] In an optional embodiment, the passivation anti-reflection layer includes any one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, and hydrogenated amorphous silicon; the passivation anti-reflection layer has a thickness of 50-200 nm and a refractive index of 1.8-2.2.

[0012] In an optional embodiment, the insulating material isolation region includes a tunneling oxide layer disposed on the backlight side and an insulating material disposed on the transparent conductive film side; the insulating material includes one or more combinations of silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, and silicon oxynitride, and the resistivity of the insulating material is greater than 10 10 Ω·m; wherein the thickness of the insulating material is 100nm-300nm, the width of the insulating material isolation region is 50μm-100μm, and the back deposition area accounts for 5%-10%.

[0013] In an optional embodiment, the first semiconductor region includes a tunneling oxide layer arranged on the backlight side and a phosphorus-doped polysilicon layer arranged on the transparent conductive film side; wherein the width of the first semiconductor region is 200 μm-400 μm, the thickness ratio of the tunneling oxide layer to the phosphorus-doped polysilicon layer is 1:50-1:200, and the backside deposition area accounts for 20%-45%; the thickness of the tunneling oxide layer is 0.5 nm-3 nm, the thickness of the phosphorus-doped polysilicon layer is 50 nm-200 nm, and the effective doping concentration is 5×10 19 / cm 3 ~1×10 22 / cm 3 .

[0014] In an optional embodiment, the second semiconductor region is stacked with an intrinsic hydrogenated amorphous silicon layer, a boron-doped amorphous silicon layer and a boron-doped carbon oxide microcrystalline layer in sequence from the backlight side; wherein the width of the second semiconductor region is 300-500 μm, and the backside deposition area accounts for 45%-75%; the thickness of the intrinsic hydrogenated amorphous silicon layer is 3nm-10nm, the thickness of the boron-doped amorphous silicon layer is 3nm-10nm, and the doping concentration is 1×10 19 / cm 3 ~5×10 19 / cm 3 The thickness of the boron-doped carbon-doped silicon oxide microcrystalline layer is 10nm-30nm, and the doping concentration is 5×10 19 / cm 3 ~2×10 20 / cm 3 , and the thickness ratio of the three layers is 1:1:1 to 1:1:3.

[0015] In an optional implementation, the opening width of the transparent conductive film layer is 10 μm-50 μm.

[0016] In an optional implementation, an area ratio of the first semiconductor region, the second semiconductor region, and the insulating material isolation region is 4:9:1 to 9:15:2.

[0017] In a second aspect, the embodiment of the present disclosure further provides a method for preparing a hybrid passivated back contact cell as described above, comprising the following steps: step S1, providing a clean double-sided polished silicon wafer; step S2, sequentially preparing a tunneling oxide layer, an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the backlight side of the silicon wafer; step S3, preparing a first opening interval on the doped amorphous silicon layer to expose the intrinsic amorphous silicon layer; step S4, sequentially depositing phosphorus-doped amorphous silicon and a silicon oxide mask on the backlight side of the silicon wafer; step S5, preparing a pyramid velvet morphology on the light-receiving side of the silicon wafer, and removing the silicon oxide mask on the backlight side; step S6, preparing a first semiconductor region in the first opening interval, and depositing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer; step S7, preparing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer; step S8, preparing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer; step S9, preparing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer; step S10, preparing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer; step S11, preparing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer; step S12, preparing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer; step S13, preparing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer; step S14, preparing a first semiconductor region in the first semiconductor region of the doped amorphous silicon layer An insulating material isolation region is prepared in the area outside the body region; step S7, a second opening interval is prepared on the insulating material isolation region; step S8, a second semiconductor region is prepared in the second opening interval; step S9, a third opening interval is prepared to expose the first semiconductor region and part of the insulating material isolation region; step S10, a transparent conductive film layer is deposited on the backlight side of the silicon wafer; step S11, a FSF front surface passivation field and a passivation anti-reflection layer are sequentially prepared on the light-receiving side of the silicon wafer; step S12, a fourth opening interval is prepared on the transparent conductive film layer to expose part of the insulating material isolation region; step S13, the first semiconductor region and the second semiconductor region are metallized to prepare metal electrodes to form ohmic contacts.

[0018] The beneficial effect of the present invention is that the hybrid passivated back contact battery with insulating material isolation and the preparation method thereof, by setting an insulating material isolation area, allows the insulating material to form an interdigitated arrangement structure with the first semiconductor area and the second semiconductor area while also having the effect of a mask, thereby solving the current problems of high leakage risk and insufficient passivation of the isolation area in BC hybrid batteries, and the amorphous passivation area of ​​the structure does not require laser processing, thus avoiding the problem of laser film opening damage.

[0019] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0023] Figure 2 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0025] Figure 4 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0027] Figure 6 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0029] Figure 8 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0030] Fig. 9 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0031] Fig.10 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0032] Fig.11 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0033] Fig.12 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0034] Fig.13 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0035] Fig.14 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0036] Fig.15A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0037] Fig.16 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0038] Fig.17 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0039] Fig.18 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0040] Fig.19 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0041] Fig. 20 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0042] Fig.21 A process flow chart of a hybrid passivated back contact cell provided in an embodiment of the present disclosure;

[0043] Fig. 22 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure;

[0044] Fig.23 A schematic diagram of the structure of a hybrid passivated back contact battery provided in an embodiment of the present disclosure.

[0045] In the figure:

[0046] 1. N-type silicon base; 2. Tunneling oxide layer; 3. Intrinsic amorphous silicon layer; 4. Doped amorphous silicon layer; 5. First opening interval; 6. Phosphorus-doped amorphous silicon; 7. Silicon oxide mask;

[0047] 8. first semiconductor region; 81. phosphorus-doped polysilicon; 82. phosphorus internal diffusion;

[0048] 9. Insulation material isolation area; 91. Insulation material;

[0049] 10. second semiconductor region; 101. intrinsic hydrogenated amorphous silicon layer; 102. boron-doped amorphous silicon layer / boron-doped carbon-oxide microcrystalline layer;

[0050] 11. Second opening interval; 12. Third opening interval; 13. Transparent conductive film; 14. FSF front surface passivation field; 15. Passivation anti-reflection layer; 16. Fourth opening interval; 17. Metal electrode. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Therefore, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, so that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. On the contrary, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0053] Herein, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0054] The terms used herein are only used to describe specific exemplary configurations and are not intended to be limited. As used herein, the singular articles "one", "an" and "the" may also be intended to include plural forms, unless it is clearly indicated above that this is not the case. The terms "comprise", "include" and "have" are inclusive, and therefore specify the presence of features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the specific order discussed or shown, unless specifically identified as an execution order. Additional or alternative steps may be adopted.

[0055] Laser film opening to prepare the first semiconductor and the second semiconductor isolation region requires precise etching to remove the transparent conductive film and the semiconductor at the intersection of the first semiconductor and the second semiconductor. The lateral and vertical etching accuracy requirements are high, which can easily cause unstable battery leakage. At the same time, the passivation film of the second semiconductor region is hydrogenated amorphous silicon, which is sensitive to temperature, energy, and cleanliness. High-energy laser film opening can easily cause passivation damage to the amorphous silicon. At the same time, the isolation area is not protected by a dense passivation film, which affects the passivation of the battery surface.

[0056] The graphic mask etching method requires mask printing-curing-etching-mask cleaning-drying and other processes, which has the problems of high cost and complicated preparation. At the same time, amorphous silicon and transparent conductive film are more sensitive to acid and alkali, which can easily cause passivation damage. At the same time, the isolation area is not protected by a dense passivation film, which affects the passivation of the battery surface.

[0057] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0058] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0059] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0060] The disclosed embodiment provides a hybrid passivation back contact cell with insulating material isolation, comprising: an N-type silicon base, wherein the N-type silicon base is provided with a light-receiving surface with a pyramid velvet morphology and a backlight surface with an alkali-polished tower base morphology; an FSF front surface passivation field and a passivation anti-reflection layer are sequentially stacked on the light-receiving surface; an insulating material isolation area is provided on the backlight surface, and a first semiconductor area and a second semiconductor area are respectively provided on both sides of the insulating material isolation area to form an interdigitated arrangement structure; a transparent conductive film layer is covered and provided on the side of the insulating material isolation area, the first semiconductor area and the second semiconductor area away from the backlight surface, and an opening is opened in the insulating material isolation area; metal electrodes are respectively provided on the transparent conductive film layers corresponding to the first semiconductor area and the second semiconductor area.

[0061] In some embodiments, specifically, the N-type silicon substrate includes any one of a Czochralski single crystal and a cast single crystal.

[0062] In some embodiments, specifically, the reflectivity of the pyramid velvet morphology is 9%-12%, the pyramid height is 0.8μm-5μm, and the pyramid width is 1μm-5μm; the reflectivity of the alkali-polished tower base morphology is 35%-45%, and the tower base size is 5μm-15μm.

[0063] In some embodiments, specifically, the passivation anti-reflection layer includes any one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, and hydrogenated amorphous silicon; the thickness of the passivation anti-reflection layer is 50-200 nm, and the refractive index is 1.8-2.2.

[0064] In some embodiments, specifically, the insulating material isolation region includes a tunneling oxide layer disposed on the backlight side and an insulating material disposed on the transparent conductive film side; the insulating material includes one or more combinations of silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, and silicon oxynitride, and the resistivity of the insulating material is greater than 10 10 Ω·m; wherein the thickness of the insulating material is 100nm-300nm, the width of the insulating material isolation region is 50μm-100μm, and the back deposition area accounts for 5%-10%.

[0065] In some embodiments, specifically, the first semiconductor region includes a tunneling oxide layer disposed on the backlight side and a phosphorus-doped polysilicon layer disposed on the side of the transparent conductive film layer; wherein the width of the first semiconductor region is 200 μm-400 μm, the ratio of the thickness of the tunneling oxide layer to the phosphorus-doped polysilicon layer is 1:50-1:200, and the backside deposition area accounts for 20%-45%; the thickness of the tunneling oxide layer is 0.5 nm-3 nm, the thickness of the phosphorus-doped polysilicon layer is 50 nm-200 nm, and the effective doping concentration is 5×10 19 / cm 3 ~1×10 22 / cm 3 .

[0066] In some embodiments, specifically, the second semiconductor region is stacked with an intrinsic hydrogenated amorphous silicon layer, a boron-doped amorphous silicon layer and a boron-doped carbon oxide microcrystalline layer in sequence from the backlight side; wherein the width of the second semiconductor region is 300-500 μm, and the back deposition area accounts for 45%-75%; the thickness of the intrinsic hydrogenated amorphous silicon layer is 3nm-10nm, the thickness of the boron-doped amorphous silicon layer is 3nm-10nm, and the doping concentration is 1×10 19 / cm 3 ~5×10 19 / cm 3 The thickness of the boron-doped carbon-doped silicon oxide microcrystalline layer is 10nm-30nm, and the doping concentration is 5×10 19 / cm3 ~2×10 20 / cm 3 , and the thickness ratio of the three layers is 1:1:1 to 1:1:3.

[0067] In some embodiments, specifically, the opening width of the transparent conductive film layer is 10 μm-50 μm.

[0068] In some embodiments, specifically, the area ratio of the first semiconductor region, the second semiconductor region, and the insulating material isolation region is 4:9:1 to 9:15:2.

[0069] Specifically, the function of the functional cavity used in the embodiments of the present disclosure is as follows:

[0070] Loading chamber: The transfer chamber where the carrier enters the vacuum state from the atmospheric state. 2 For filling gas;

[0071] Unloading chamber: The transfer chamber where the carrier enters the atmospheric state from the vacuum state. 2 For filling gas;

[0072] Transition chamber: a transfer chamber for different coating methods of the substrate. It is mainly used for process pressure conversion balance and isolation conversion of different process gases. Argon is used as the filling gas.

[0073] Buffer chamber: avoids the secondary isolation of different process gases from "cross-flowing";

[0074] Cooling chamber: The transfer chamber from the coating chamber to the unloading chamber, mainly for the process pressure conversion balance and isolation conversion of different process gases.

[0075] The present disclosure also provides a method for preparing a hybrid passivated back contact cell as described above, comprising the following steps:

[0076] Step S1, providing a clean double-sided polished silicon wafer, Figure 1 The structure shown;

[0077] In this step, wet cleaning is used to obtain a clean silicon wafer surface, see Figure 2 The specific implementation steps and results are as follows:

[0078] A mixed solution of potassium hydroxide (concentration 1%-10%, the same below) and hydrogen peroxide (concentration 5%-15%, the same below) is used to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55°C-70°C and the process time is 2min-5min.

[0079] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0080] A mixed solution of potassium hydroxide (1%-10%) and additives (concentration 0.5%-5%, the same below) is used to polish the surface of the silicon wafer to form an alkali polishing tower base morphology and remove cutting damage. The process temperature is 60℃-85℃ and the process time is 3min-5min.

[0081] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0082] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0083] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0084] Use hydrofluoric acid (concentration 0.1%-2%, the same below) and hydrochloric acid (concentration 0.1%-2%, the same below) and O 3 (10ppm-50ppm) mixed solution, clean the silicon wafer surface, and at the same time 3 The weak etching system with HF can lubricate the surface of silicon wafer, reduce the burr defects on the surface of silicon wafer, and is more conducive to the passivation of amorphous silicon. The process temperature is 15℃-25℃ and the process time is 2min-3min.

[0085] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0086] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;

[0087] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0088] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0089] Place the silicon wafer in a drying tank and purge it at high temperature to dry the surface of the silicon wafer. The purge gas is nitrogen or compressed air. The temperature is 80℃-100℃ and the drying time is 5min-15min.

[0090] Specifically, the weight reduction of silicon wafer is: 0.3g-0.6g (taking 182.2 size silicon wafer as an example); the surface reflectivity is: 35%-45%; the tower base size is: 5um-15um.

[0091] Step S2, sequentially preparing a tunneling oxide layer, an intrinsic amorphous silicon layer and a doped amorphous silicon layer on the backlight side of the silicon wafer to obtain Figure 3The structure shown;

[0092] In this step, the tunnel oxide layer can be prepared by using any one of tubular LP (low pressure chemical vapor deposition), PE (plasma enhanced chemical vapor deposition), ALD (atomic layer deposition), plate PE, PVD, ALD, and tank wet oxygen; intrinsic amorphous silicon can be prepared by using any one of plate PVD, PE, tubular LP, and PE; doped amorphous silicon can be prepared by using any one of plate PVD, PE, and tubular PE; the doped amorphous silicon layer (insulating barrier layer) can be any one or more of doped C, O, and N;

[0093] In this embodiment, plate-type PECVD is preferably used to prepare the tunnel oxide layer, plate-type PVD is used to prepare the intrinsic amorphous silicon, and plate-type PVD is used to prepare the doped amorphous silicon layer (insulating barrier layer). Plate-type PVD has the characteristics of single-sided deposition without wrap-around plating, fast deposition rate, easy in-situ doping, and easy crystallization. At the same time, the plate-type equipment has the advantages of integrated coating of different types of film layers, reducing equipment investment and the frequency of vacuum coating of the battery;

[0094] In this embodiment, the preferred doping gas for the doped amorphous silicon layer (insulating barrier layer) is CO 2 Doping elements C, O, CO 2 With the characteristics of low cost and safety, the silicon oxycarbide film layer has the advantages of high density, high resistivity and good optical effect;

[0095] In this embodiment, plate-type PECVD is used to prepare the tunnel oxide layer. 2 , O 3 、N 2 O and SiH 4 One or more combinations thereof are used for preparation. In this embodiment, low-cost and high-safety O 2 preparation;

[0096] The specific implementation steps and results are as follows: Figure 4 As shown:

[0097] The back side of the double-sided alkaline polished silicon wafer is oxidized by flat-plate PECVD to prepare a tunneling oxide layer, and a layer of intrinsic amorphous silicon and a layer of doped amorphous silicon layer (insulating barrier layer) are deposited on the oxidized silicon wafer by flat-plate PVD.

[0098] After double-sided alkali polishing, the silicon wafer is placed on a hollow carrier plate, and the gate valve 1 is opened. The carrier plate is transferred to the loading chamber 1. The chamber is evacuated to (PECVD1 reaction chamber 1 pressure - 2Pa) < loading chamber 1 bottom pressure < PECVD1 reaction chamber 1 pressure. The gate valve 2 is opened, and the carrier plate is transferred to the preheating chamber 1 to heat the silicon wafer. The carrier plate is transferred to the PECVD1 reaction chamber 1, and the PECVD method is used to ionize O 2To plasma, through the hollow carrier plate from bottom to top oxidize the silicon wafer surface to prepare tunneling silicon oxide, the transition chamber 1 is filled with argon gas to a pressure greater than (PECVD1 reaction chamber 1 pressure + 2Pa), the gate valve 3 is opened, the carrier plate is transferred to the transition chamber 1, the cavity is evacuated to (PVD1 reaction chamber 2 pressure -0.2Pa) < pressure <PVD1 reaction chamber 2 pressure, the gate valve 4 is opened, the carrier plate is transferred to the buffer chamber 1, and then transferred to the PVD1 reaction chamber 2, and the PVD method is used to sink from bottom to top through the hollow carrier plate. The intrinsic amorphous silicon is accumulated and then transferred to the PVD2 reaction chamber 3. The PVD method is used to deposit C, O-doped amorphous silicon (insulating barrier layer) from bottom to top through the hollow carrier, and then transferred to the buffer chamber 2. The cooling chamber is evacuated to a pressure less than that of the PVD2 reaction chamber 3. The gate valve 5 is opened, and the carrier is transferred to the cooling chamber. The unloading chamber is evacuated to below 50Pa. The gate valve 6 is opened, and the carrier is transferred to the unloading chamber 1. The unloading chamber is backfilled with nitrogen to the atmospheric state. The gate valve 7 is opened, and the carrier is transferred out of the cavity. The silicon wafer is collected to complete the film preparation.

[0099] PECVD1 reaction chamber 1: When the tunnel oxide layer is prepared by oxidation using the PECVD method, oxygen is used as the process gas, the process pressure is 5Pa-20Pa, the process temperature is 150℃-350℃, the power is 50W-500W, and the process belt speed is 10cm / min-500cm / min;

[0100] PVD1 reaction chamber 2: When the intrinsic amorphous silicon is prepared by PVD method, a silicon target is used as the silicon source, and argon is used as the working gas, the process pressure is: 0.1Pa-1Pa, the process temperature is: 200℃-500℃, the power is 10kW-40KW, and the process belt speed is: 10cm / min-500cm / min;

[0101] PVD2 reaction chamber 3: When preparing C and O doped amorphous silicon by PVD method, silicon target is used as silicon source, argon is used as working gas, CO 2 The doping gas is used, process pressure: 0.1Pa-1Pa, process temperature: 200℃-500℃, power: 10kW-40KW, process belt speed: 10cm / min-500cm / min, CO 2 Flow rate: 5sccm-50sccm;

[0102] Tunneling silicon oxide thickness: 0.5nm-3nm, which can be freely adjusted by power, belt speed, flow rate and temperature to meet process requirements;

[0103] Intrinsic amorphous silicon thickness: 50nm-200nm, which can be freely adjusted by power, belt speed, flow, temperature, and number of silicon targets to meet process requirements;

[0104] The thickness of the doped amorphous silicon layer (insulating barrier layer) is 50nm-200nm, which can be freely adjusted by power, belt speed, flow, temperature and number of silicon targets to meet the process requirements;

[0105] Doped amorphous silicon layer (insulating barrier layer) C, O doping concentration: 1×10 19 / cm 3 ~1×10 21 / cm 3 , can be obtained through CO 2 The flow rate can be freely adjusted.

[0106] Step S3, preparing a first opening interval on the doped amorphous silicon layer to expose the intrinsic amorphous silicon layer, and obtaining Figure 5 The structure shown;

[0107] In this step, the first opening area can be prepared by using a laser film opening method or a pattern mask etching method;

[0108] This embodiment preferably uses a laser film opening method, which has the advantages of fast speed and low cost;

[0109] Further, the laser may be a nanosecond laser, a picosecond laser, or a femtosecond laser. In this embodiment, a nanosecond laser with low cost, low loss, and high film opening rate is preferably used, and combined with subsequent wet micro-etching to remove damage and high temperature annealing repair, the first opening area can be prepared without loss.

[0110] The specific implementation steps and results are as follows: Figure 6 As shown:

[0111] The battery is placed on a horizontal surface, and a pulsed ultraviolet nanosecond laser is used to etch the doped amorphous silicon layer (insulating barrier layer) and part of the intrinsic amorphous silicon layer in the first opening area, leaving part of the intrinsic amorphous silicon layer and the tunneling oxide layer;

[0112] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt and laser dust on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 0.5min-1min.

[0113] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0114] A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to slightly etch the damaged layer in the first opening area, with a process temperature of 60°C-85°C and a process time of 0.5min-1min;

[0115] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0116] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 0.5min-1min.

[0117] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0118] Use hydrochloric acid (1%-10%) solution to clean the silicon wafer surface, process temperature: room temperature, process time: 3min-5min;

[0119] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0120] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0121] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0122] Laser power: 50W-500W;

[0123] Width of the first opening area: 200um-400um;

[0124] The first opening region retains an intrinsic amorphous silicon thickness of 30nm-180nm.

[0125] Step S4, depositing phosphorus-doped amorphous silicon and silicon oxide masks on the backlight side of the silicon wafer in sequence to obtain Figure 7 The structure shown;

[0126] In this step, phosphorus-doped amorphous silicon is used as a doping source for the first semiconductor region, and the mask is used as a protective layer for subsequent single-sided texturing;

[0127] In this step, the phosphorus-doped amorphous silicon and the mask can be prepared by using any one of tubular PE, tubular LP, plate PE, and plate PVD;

[0128] In this embodiment, plate-type PVD is preferably used to prepare phosphorus-doped amorphous silicon and masks. Plate-type PVD has the characteristics of single-sided deposition without wrap-around plating, fast deposition rate, easy in-situ doping, and easy crystallization. At the same time, plate-type equipment has the advantages of integrated coating of different types of film layers, reducing equipment investment and the frequency of battery vacuum coating;

[0129] In this step, the phosphorus doping source can be any one of phosphine, phosphorus oxychloride, phosphorus, phosphorus-doped target, etc.;

[0130] In this embodiment, phosphine is preferably used as the doping gas. Phosphine has the characteristics of high doping efficiency, easy decomposition, and high compatibility with PVD coating.

[0131] In this step, the mask may be one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride;

[0132] The specific implementation steps are as follows: Figure 8 As shown:

[0133] A layer of phosphorus-doped amorphous silicon is deposited on the back of the cleaned silicon wafer using a flat-plate PVD method;

[0134] The cleaned silicon wafer is placed on a hollow carrier plate, and the gate valve 8 is opened. The carrier plate is transferred to the loading chamber 2, and the chamber is evacuated to <15Pa. The transition chamber 2 is filled with argon gas to a pressure greater than the bottom pressure of the loading chamber. The gate valve 9 is opened, and the carrier plate is transferred to the transition chamber 2. The transition chamber 2 is evacuated to (PVD3 reaction chamber 4 bottom pressure - 0.2) Pa < pressure < PVD3 reaction chamber 4 bottom pressure. The gate valve 10 is opened, and the carrier plate is transferred to the buffer chamber 3. The carrier plate is transferred to the PVD3 reaction chamber 4, and phosphorus-doped amorphous silicon is deposited from bottom to top through the hollow carrier plate by PVD. The carrier plate is then transferred to the PVD4 reaction chamber 5, and silicon oxide mask is deposited from bottom to top through the hollow carrier plate by PVD, and then transferred to the buffer chamber 4. The gate valve 11 is opened, and the carrier plate is transferred to the cooling chamber 2. The gate valve 12 is opened, and the carrier plate is transferred to the unloading chamber 2. The unloading chamber 2 is backfilled with nitrogen to the atmospheric state. The gate valve 13 is opened, and the carrier plate is transferred out of the cavity, and the silicon wafer is collected to complete the film preparation.

[0135] Phosphorus-doped amorphous silicon thickness: 20-100nm; can be freely adjusted through power, belt speed, flow, temperature, and number of silicon targets to meet process requirements;

[0136] Phosphorus-doped amorphous silicon doping concentration: 5×10 19 / cm 3 ~1×10 22 / cm 3 ; Phosphine flow, process pressure and process time can be freely adjusted to meet process requirements;

[0137] Mask thickness: 50nm-100nm, which can be freely adjusted by power, belt speed, flow, temperature and number of silicon targets to meet process requirements.

[0138] Step S5, preparing a pyramid velvet morphology on the light-receiving side of the silicon wafer, and removing the silicon oxide mask on the backlight side, to obtain Fig. 9 The structure shown;

[0139] In this step, a wet cleaning method is used to prepare the pyramid morphology on the front side and remove the mask on the back side;

[0140] The specific steps are as follows: Fig.10 As shown:

[0141] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 1min-3min.

[0142] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0143] A mixed solution of potassium hydroxide (1%-10%) and a texturing additive (0.5%-5%) is used to form a pyramid velvet surface on the front side of the silicon wafer. The process temperature is 70℃-85℃ and the process time is 3min-5min.

[0144] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0145] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 1min-3min.

[0146] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0147] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;

[0148] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0149] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0150] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0151] Wafer weight reduction: 0.2g-0.3g (taking 182.2 size wafer as an example);

[0152] Suede reflectivity: 9%-12%;

[0153] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the groove morphology on the back side.

[0154] Step S6, preparing a first semiconductor region in the first opening area, and preparing an insulating material isolation region outside the first semiconductor region of the doped amorphous silicon layer, to obtain Fig.11 The structure shown;

[0155] In this embodiment, the first semiconductor is: phosphorus-doped polysilicon, tunnel oxide layer, phosphorus internal expansion; the insulating isolation material is: tunnel oxide layer, crystallized silicon carbide;

[0156] High temperature oxidation annealing is used to push phosphorus atoms of phosphorus-doped amorphous silicon into intrinsic amorphous silicon, and at the same time, the intrinsic amorphous silicon is crystallized under high temperature to prepare dense phosphorus-doped polycrystalline silicon; under the action of high temperature annealing, phosphorus atoms penetrate the tunneling oxide layer and enter the silicon base to form tunneling pinholes;

[0157] Specifically, C and O doped amorphous silicon combines with intrinsic amorphous silicon under the action of high temperature annealing to form dense silicon carbide (insulating material). At the same time, the solid solubility of phosphorus atoms in silicon carbide is one tenth of that of silicon. Under the same annealing conditions, it is difficult for the phosphorus atoms in phosphorus-doped amorphous silicon to advance to silicon carbide and affect the resistivity of the material. In this embodiment, the silicon carbide amorphous layer acts as both a mask and a dopant for the insulating material.

[0158] Specifically, phosphorus-doped amorphous silicon forms dense silicon oxide under high-temperature oxidation annealing conditions.

[0159] Specifically, high temperature annealing has the function of repairing the damage of the first opening laser film opening.

[0160] The specific implementation steps and results are as follows:

[0161] The silicon wafer with back-side coating is inserted into a quartz carrier and transferred to a high-temperature annealing furnace tube. The oxidation annealing is completed through the following steps: opening the furnace door - entering the boat - evacuating the vacuum - heating up - maintaining a constant temperature - leak detection - heating up - maintaining a constant temperature - oxidation - cooling - breaking the vacuum - exiting the boat.

[0162] Specifically, in the heating step after leak detection, gradient heating is adopted to reduce the difference in starting temperature from furnace mouth, furnace center to furnace tail caused by opening the furnace door, which leads to difference in annealing process effect. The specific heating method is as follows: 800℃-820℃-840℃-860℃-880℃ instead of the traditional 800℃-840℃-880℃; different oxidation annealing temperatures are adopted in different temperature zones to avoid difference in annealing process effect at different positions due to fast cooling of furnace mouth and furnace tail caused by water cooling of furnace tubes, slow heating of furnace mouth and fast heating of furnace tail caused by opening the furnace door. The specific temperature setting method is as follows: furnace mouth-furnace center-furnace tail: 890℃-880℃-885℃ instead of the traditional furnace mouth-furnace center-furnace tail: 880℃-880℃-880℃.

[0163] Specifically, oxidation annealing time: 30min-120min, oxidation annealing temperature: 840℃-950℃, oxidation annealing pressure: 600mBar-900mBar; phosphorus-doped polysilicon doping effective doping concentration: 5×10 19 / cm 3 ~2×10 21 / cm 3 ; Phosphorus diffusion depth: 0.1um-0.2um.

[0164] Step S7, preparing a second opening interval on the insulating material isolation region to obtain Fig.12 The structure shown;

[0165] In this step, the second opening area can be prepared by using a laser film opening method or a pattern mask etching method;

[0166] This embodiment preferably uses a laser film opening method, which has the advantages of fast speed and low cost;

[0167] Furthermore, the laser may be a nanosecond laser, a picosecond laser, or a femtosecond laser. In this embodiment, a nanosecond laser with low cost, low loss, and high film opening rate is preferably used, and combined with subsequent wet etching to remove the damaged layer, the second opening area can be prepared without loss.

[0168] The specific implementation steps are as follows: Fig.13 As shown:

[0169] The battery is placed on a horizontal surface, and a pulsed ultraviolet nanosecond laser is used to completely etch the annealed silicon oxide, insulating material (silicon oxycarbide), and tunnel oxide layer in the second opening area vertically, leaking out of the silicon wafer substrate, and a certain width of insulating material area is retained horizontally between the first opening area and the second opening area;

[0170] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt and laser dust on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0171] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0172] A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to polish the surface of the second opening area of ​​the silicon wafer to form an alkali polishing tower base morphology and remove the laser damaged layer. The process temperature is 60°C-85°C and the process time is 3min-5min.

[0173] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0174] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0175] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0176] Use hydrochloric acid (1%-10%) solution to clean the silicon wafer surface, process temperature: room temperature, process time: 3min-5min;

[0177] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0178] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0179] Place the silicon wafer in a drying tank and purge it at high temperature to dry the surface of the silicon wafer. The purge gas is nitrogen or compressed air. The temperature is 80℃-100℃ and the drying time is 5min-15min.

[0180] Specifically, laser power: 50W-500W; width of the second opening area: 300um-500um; corrosion depth of the second opening area: 0.5um-1.5um; width of the insulating material reserved area: 50um-100um.

[0181] Step S8, preparing a second semiconductor region in the second opening interval to obtain Fig.14 The structure shown;

[0182] The second semiconductor of this embodiment is a stacked film of hydrogenated intrinsic amorphous silicon, boron-doped amorphous silicon, and boron-doped microcrystalline carbon oxide silicon from the inside to the outside;

[0183] The deposition method may be plate-type PECVD or plate-type HWCVD, and plate-type PECVD is preferably used to deposit the second semiconductor;

[0184] Boron-doped microcrystalline silicon oxide, the carbon and oxygen sources can be CH 4 , CO 2 ,TMB,O 2 One or more of the following are obtained; preferably CO 2 , TMB is the carbon and oxygen source;

[0185] The specific implementation steps and results are as follows: Fig.15 As shown:

[0186] A flat-plate PECVD method is used to first deposit a layer of ia:Si from top to bottom on the back of the double-cleaned silicon wafer, and then the deposited surface is HPT-cleaned (H ion-cleaned), and finally a flat-plate PECVD method is used to first deposit Pa:Si from top to bottom on the back of the silicon wafer. The deposition includes (a layer of Pa:Si and a layer of P-uc-SiOxCy);

[0187] The double-sided cleaned silicon wafer is placed on a hollow carrier, the gate valve 14 is opened, the carrier is transferred to the loading chamber 3, the chamber is evacuated to (PECVD2 reaction chamber 6 pressure - 2pa) < loading chamber 3 bottom pressure < PECVD2 reaction chamber 6 pressure, the gate valve 15 is opened, the carrier is transferred to the preheating buffer chamber 6, and then transferred to the PECVD2 reaction chamber 6 to deposit a layer of ia: Si from top to bottom, and then transferred to the HPT cleaning buffer chamber 6, H ions are used to clean the deposited surface, and the preparation of ia: Si is completed;

[0188] The transition chamber 3 is filled with argon until the pressure of the PECVD2 reaction chamber 6 is less than the pressure of the transition chamber 3 and less than the pressure of the PECVD3 reaction chamber 7. The gate valve 17 is opened, and the carrier is transferred to the buffer chamber 7. The carrier is transferred to the PECVD3 reaction chamber 7, and a layer of Pa:Si and a layer of P-uc-SiOxCy are deposited from top to bottom, and then transferred to the buffer 8 to complete the preparation of Pa:Si.

[0189] Open the gate valve 18, transfer the carrier to the unloading chamber 3, fill it back to the atmospheric state with nitrogen, open the gate valve 19, transfer the carrier out, collect the silicon wafer, and complete the preparation of the second semiconductor on the back side;

[0190] PECVD2 reaction chamber 6: PECVD method to prepare ia: Si, SiH 4 , H 2 For process gas, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH 4 :H 2 Flow ratio: 1:10-1:30, power: 50W-300W;

[0191] PECVD2 reaction chamber 3: Pa:Si is prepared by PECVD method. Pa:Si is divided into two layers: conventional B-doped amorphous silicon (Pa:Si) and B-doped microcrystalline carbon oxide silicon (P-uc-SiOxCy);

[0192] Conventional B-doped amorphous silicon (Pa:Si) is prepared with SiH 4 , H 2 , B 2 H 6 For process gas, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH 4 :H 2 :B2 H 6 (2%) Flow ratio: 1:20:5-1:30:15, Power: 50W-300W;

[0193] B-doped microcrystalline silicon oxycarbide (P-uc-SiOxCy) was prepared by SiH 4 , H 2 , B 2 H 6 , CO 2 , TMB is the process gas, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH 4 :H 2 :B 2 H 6 (2%) Flow ratio: 1:30:10-1:60:30, CO 2 With TMB, the gas flow rate is 5sccm-20sccm, and the power is 300w-500W;

[0194] HPT cleaning buffer chamber 2: ionize H using the PECVD method to clean the deposited surface of the silicon wafer. 2 For process gas,

[0195] Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W;

[0196] i: a-Si thickness: 2nm-10nm, which can be freely adjusted by power, belt speed, flow, temperature, and number of ion sources to meet process requirements;

[0197] P: a-Si thickness: 10nm-20nm, P-uc-SiOxCy thickness: 20nm-50nm, which can be freely adjusted by power, belt speed, flow, temperature, and number of ion sources to meet process requirements;

[0198] P: a-Si doping concentration: 1×10 18 / cm 3 ~5×10 18 / cm 3 :P-uc-SiOxCy doping concentration: 5×10 18 / cm 3 ~2×10 19 / cm 3 The doping amount can be freely adjusted through belt speed, pressure, flow rate and temperature to meet the process requirements.

[0199] Specifically, hydrogenated intrinsic amorphous silicon is ia:Si, boron-doped amorphous silicon is Pa:Si, and boron-doped microcrystalline carbon oxide silicon is P-uc-SiOxCy.

[0200] Step S9, preparing a third opening interval to expose the first semiconductor region and part of the insulating material isolation region, and obtaining Fig.16 The structure shown;

[0201] In this step, the third opening area can be prepared by laser film opening method or pattern mask etching method, preferably by laser film opening method, which has the advantages of fast speed and low cost;

[0202] Furthermore, the laser can use nanosecond laser, picosecond laser, femtosecond laser, preferably a low-cost, low-loss, high film opening rate nanosecond laser, combined with the protection of the silicon oxide mask to prepare the third opening without damaging the first semiconductor layer.

[0203] The specific implementation steps are as follows: Fig.17 As shown:

[0204] The battery is placed on a horizontal platform, and a pulsed ultraviolet nanosecond laser is used to laterally etch the first semiconductor region and part of the insulating material region, and to longitudinally etch the second semiconductor and part of the silicon oxide;

[0205] Wet cleaning removes the oxide layer in the third opening area and the front oxide layer;

[0206] Use water to remove surface dirt, cleaning time: 2min-3min;

[0207] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;

[0208] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0209] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0210] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0211] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the groove morphology on the back side.

[0212] Step S10, depositing a transparent conductive film layer on the backlight side of the silicon wafer to obtain Fig.18 The structure shown;

[0213] In this step, the transparent conductive film layer can be prepared by plate PVD, plate RPD, or plate ALD. The transparent conductive film can be one or more combinations of ITO, IWO, AZO, and IGZO. It is preferred to use plate PVD coating to deposit ITO to prepare a back-side transparent conductive film. Plate PVD has the characteristics of fast deposition rate and excellent uniformity between and within sheets. ITO has the characteristics of high light transmittance and high conductivity.

[0214] The specific implementation steps are as follows: Fig.19 As shown:

[0215] The cleaned silicon wafer is placed on a hollow carrier with the back side facing up, the gate valve 20 is opened, the carrier is transferred to the loading chamber 4, and evacuated to <15Pa, the transition chamber 4 is backfilled with argon to 15Pa<pressure<20Pa, the gate valve 21 is opened, the carrier is transferred to the transition chamber 4, and evacuated to (PVD5 reaction chamber 8 bottom pressure-0.2)Pa<pressure<PVD5 reaction chamber 8 bottom pressure, the gate valve 22 is opened, the carrier is transferred to the buffer chamber 9, the carrier is transferred to the PVD5 reaction chamber 8, a layer of ITO is deposited from top to bottom, and then transferred to the buffer chamber 10, and then transferred to the cooling chamber 3, the gate valve 24 is opened, the carrier is transferred to the unloading chamber 4, and backfilled to the atmosphere with nitrogen, the gate valve 25 is opened, the carrier is transferred out of the cavity, the silicon wafer is collected, and the preparation of the transparent conductive film is completed.

[0216] PVD5 reaction chamber 8: When TCO is prepared by PVD method, ITO target (In 2 O 3 / SnO 2 Mass ratio: 90:10-97:3), and argon and oxygen are used as working gases, process temperature: 100-250℃, process pressure: 0.2Pa-2Pa, Ar / O 2 Flow ratio: 200:1-100:1, power: 5000W-40000W;

[0217] Specifically, TCO thickness: 70nm-150nm; TCO square resistance: 50-120.

[0218] Step S11, sequentially prepare the FSF front surface passivation field and the passivation anti-reflection layer on the light-receiving side of the silicon wafer to obtain Fig. 20 The structure shown;

[0219] Passivation anti-reflection film is used to reduce light reflection on the surface of silicon wafers, H passivates the surface of silicon wafers; FSF uses field passivation effect to reduce surface minority carrier concentration and reduce surface recombination rate;

[0220] The front passivation anti-reflection layer comprises one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, and amorphous silicon, preferably phosphorus-doped hydrogenated amorphous silicon, aluminum oxide, and silicon nitride as the passivation anti-reflection film;

[0221] Phosphorus-doped hydrogenated amorphous silicon can be prepared using plate PECVD and plate HWCVD; aluminum oxide can be prepared using plate PECVD, plate ALD, plate PVD, tubular PECVD, and tubular ALD; silicon nitride can be prepared using plate PECVD, plate PVD, and tubular PECVD;

[0222] This embodiment preferably uses plate-type PECVD to prepare phosphorus-doped hydrogenated amorphous silicon, plate-type PECVD to prepare aluminum oxide, and plate-type PECVD to prepare silicon nitride. The plate-type coating equipment has no tube-type equipment card point printing, and the front of the battery is beautiful. At the same time, the ultra-thin phosphorus-doped hydrogenated amorphous silicon + aluminum oxide + silicon nitride laminated film design provides excellent passivation and optical effects for the battery.

[0223] The specific implementation steps are as follows: Fig.21 As shown:

[0224] The silicon wafer after TCO deposition is placed on a hollow carrier, the gate valve 26 is opened, the carrier is transferred to the loading chamber 5, and the vacuum is evacuated to (PECVD4 reaction chamber 9 pressure - 2Pa) < pressure < PECVD4 reaction chamber 9 pressure, the gate valve 27 is opened, the carrier is transferred to the buffer chamber 11, the carrier is transferred to the PECVD4 reaction chamber 9, a layer of phosphorus-doped amorphous silicon is deposited, and then it is transferred to the buffer chamber 12;

[0225] The transition chamber 5 is backfilled with argon gas until the pressure of the PECVD4 reaction chamber 9 is less than the pressure of (the pressure of the PECVD4 reaction chamber 9 + 2Pa), the gate valve 28 is opened, the carrier is transferred to the transition chamber 5, the transition chamber 5 is evacuated to 1Pa, and then backfilled with argon gas until the pressure of (the pressure of the PECVD5 reaction chamber 10 - 2Pa) is less than the pressure of the PECVD5 reaction chamber 10, the gate valve 29 is opened, the carrier is transferred to the buffer chamber 13, the carrier is transferred to the PECVD5 reaction chamber 10, a layer of aluminum oxide is deposited, and then the carrier is transferred to the buffer chamber 14;

[0226] The transition chamber 6 is backfilled with argon gas to the pressure of the PECVD5 reaction chamber 10 < pressure < (PECVD5 reaction chamber 10 pressure + 2Pa), the gate valve 30 is opened, and the carrier is transferred to the transition chamber. The transition chamber is evacuated to 1Pa, and then backfilled with argon gas to (PECVD6 reaction chamber 11 pressure - 2Pa) < pressure < PECVD6 reaction chamber 11 pressure, the gate valve 31 is opened, and the carrier is then transferred to the buffer chamber 15, and the carrier is transferred to the PECVD6 reaction chamber 11, and a layer of high H content SiNx, a layer of high Si content SiNx, and a layer of high N content SiNx are deposited from top to bottom, and the carrier is transferred to the buffer chamber 16, and the gate valve 32 is opened, and the carrier is transferred to the unloading chamber 6, and the unloading chamber 6 is backfilled with nitrogen gas to the atmosphere, and the gate valve 33 is opened, and the carrier is transferred out of the cavity, and the silicon wafer is collected to complete the preparation of the passivation anti-reflection film;

[0227] PECVD4 reaction chamber 9: A layer of ultra-thin phosphorus-doped hydrogenated amorphous silicon is prepared by PECVD, which has a certain phosphorus injection function and forms FSF (front surface passivation field) on the surface of the silicon wafer; SiH 4 , PH 3 , H 2 For process gas, high PH 3 Proportional high pressure and high power to complete phosphorus implantation & ultra-thin phosphorus-doped hydrogenated amorphous silicon preparation; process temperature: 100℃-250℃, process pressure: 80Pa-120Pa, SiH 4 / PH 3 / H 2 Flow ratio: 1:10:1-1:20:5; Power: 200W-300W;

[0228] PECVD5 reaction chamber 10: Alumina is prepared by PECVD with TMA, H 2 O is process gas, process temperature: 100℃-250℃, process pressure: 30Pa-50Pa, TMA / H 2 OFlow ratio: 1:3-3:1, power: 100W-300W;

[0229] PECVD6 reaction chamber 11: SiNx laminated gradient passivation anti-reflection film is prepared by PECVD method, which is divided into three layers;

[0230] SiNx-1: SiH 4 , H 2 NH 3 For process gas, high H 2 Proportional high pressure and high power preparation of high H content silicon nitride, passivation of silicon wafer interface, process temperature: 100℃-250℃, process pressure: 80Pa-120Pa, SiH 4 / NH 3 / H 2 Flow ratio: 1:1:6-2:2:20; Power: 200W-300W;

[0231] SiNx-2: SiH 4 NH 3 For process gas, high SiH 4 Proportional low pressure and low power are used to prepare high Si content and high density silicon nitride, protect high H content silicon nitride, and at the same time, low power coating reduces SiNx-1 passivation damage. Process temperature: 100℃-250℃, process pressure: 30Pa-50Pa, SiH 4 / NH 3 Flow ratio: 2:1-6:1;

[0232] SiNx-3: SiH 4 NH3 For process gas, high NH 3 Proportional low pressure and low power preparation of high N content silicon nitride, reduce the overall film refractive index, reduce the front reflectivity of the battery, increase the current density, process temperature: 100 ℃ -250 ℃, process pressure: 30Pa-50Pa, SiH 4 / NH 3 Flow ratio: 1:2-1:6;

[0233] FSF doping concentration: 3×10 18 / cm 3 ~5×10 19 / cm 3 ; Can be freely adjusted by power, flow, belt speed and temperature;

[0234] FSF doping depth: 0.1um-0.5um; can be freely adjusted by power, flow, belt speed and temperature;

[0235] Alumina thickness: 5nm-50nm; can be freely adjusted by power, flow, belt speed, temperature, and number of ion sources;

[0236] SiNx thickness: 75nm-105nm; can be freely adjusted by power, flow, belt speed, temperature, and number of ion sources;

[0237] SiNx refractive index: 1.8-2.2; can be freely adjusted by gas flow ratio, temperature and power.

[0238] Step S12, preparing a fourth opening interval on the transparent conductive film layer to expose a portion of the insulating material isolation area, and obtaining Fig. 22 The structure shown;

[0239] In this step, the fourth opening is a TCO film opening in the insulating material region, which is used to electrically isolate the first semiconductor N region from the second semiconductor P region;

[0240] In this step, the fourth opening area can be prepared by using a laser film opening method or a pattern mask etching method, preferably by using a laser film opening method, which has the advantages of fast speed and low cost;

[0241] Furthermore, the laser may be a nanosecond laser, a picosecond laser, or a femtosecond laser, and preferably a femtosecond laser with low cost, low loss, and high film opening rate is used.

[0242] The specific implementation steps are as follows:

[0243] The battery is placed on a horizontal surface, and a pulsed ultraviolet femtosecond laser is used to laterally etch part of the insulating material area and vertically etch the TCO to part of the insulating material.

[0244] Step S13, metallizing the first semiconductor region and the second semiconductor region to prepare metal electrodes to form ohmic contacts, and obtaining Fig.23 The structure shown;

[0245] The first semiconductor region and the second semiconductor region are metallized to form an ohmic contact;

[0246] The metallization method can be electroplating or screen printing metal slurry curing method; the present embodiment preferably uses the simple and environmentally friendly screen printing metal slurry curing method; the metal slurry can be one or more combinations of silver slurry, silver-coated copper slurry, and copper slurry, and silver-coated copper slurry is preferably used.

[0247] The specific implementation steps are as follows:

[0248] After the fourth opening on the back is prepared, the silicon wafer is placed on a horizontal surface. The silver-coated copper paste is printed on the first and second semiconductor regions on the back of the battery using screen printing technology.

[0249] After printing, the silicon wafer is transferred to a curing oven, dried and cured to form an ohmic contact with the TCO;

[0250] The battery is transferred to the annealing furnace, where annealing light is injected to excite H and improve passivation;

[0251] Complete battery preparation.

[0252] Specifically, this embodiment applies a large number of plate-type continuous coating equipment to BC battery production, reducing the preparation process of hybrid passivated back contact batteries from 16 steps to 13 steps, thereby improving battery efficiency, reducing preparation difficulty, and cutting costs.

[0253] Specifically, the amorphous passivation area of ​​the present embodiment is not laser processed, thereby solving the problem that the amorphous passivation area of ​​the current BC battery is easily damaged by laser film opening.

[0254] In summary, the hybrid passivated back contact battery with insulating material isolation and the preparation method thereof set an insulating material isolation area so that the insulating material forms a finger arrangement structure with the first semiconductor area and the second semiconductor area while also having the effect of a mask, thereby solving the current problems of high leakage risk and insufficient passivation of the isolation area of ​​the BC hybrid battery. In addition, the amorphous passivation area of ​​the structure does not require laser processing, thus avoiding the problem of laser film opening damage.

[0255] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A hybrid passivated back contact cell with insulating material isolation, characterized in that: include: An N-type silicon substrate (1) having a light-receiving surface with a pyramid velvet morphology and a backlight surface with an alkali-polished tower base morphology; the light-receiving surface is provided with a FSF front surface passivation field (14) and a passivation anti-reflection layer (15) in sequence; and the backlight surface is provided with an insulating material isolation region (9), and the two sides of the insulating material isolation region (9) are respectively provided with a first semiconductor region (8) and a second semiconductor region (10) which together form an interdigitated arrangement structure; A transparent conductive film layer (13) is arranged to cover the insulating material isolation region (9), the first semiconductor region (8) and the second semiconductor region (10) on a side away from the backlight surface, and an opening is provided in the insulating material isolation region (9); The metal electrodes (17) are respectively arranged on the transparent conductive film layers corresponding to the first semiconductor region (8) and the second semiconductor region (10).

2. The hybrid passivated back contact cell according to claim 1, characterized in that: The N-type silicon substrate includes any one of a Czochralski single crystal and a cast single crystal.

3. The hybrid passivated back contact cell according to claim 1, characterized in that: The reflectivity of the pyramid velvet surface is 9%-12%, the pyramid height is 0.8μm-5μm, and the pyramid width is 1μm-5μm; The reflectivity of the alkali-polished tower base morphology is 35%-45%, and the size of the tower base is 5μm-15μm.

4. The hybrid passivated back contact cell according to claim 1, characterized in that: The passivation anti-reflection layer comprises any one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, and hydrogenated amorphous silicon; The thickness of the passivation anti-reflection layer is 50-200 nm, and the refractive index is 1.8-2.

2.

5. The hybrid passivated back contact cell according to claim 1, characterized in that: The insulating material isolation region includes a tunneling oxide layer disposed on one side of the backlight surface and an insulating material disposed on one side of the transparent conductive film layer; The insulating material comprises one or more combinations of silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, and silicon oxynitride, and the resistivity of the insulating material is greater than 10 10 Ω·m; The thickness of the insulating material is 100nm-300nm, the width of the insulating material isolation region is 50μm-100μm, and the back deposition area accounts for 5%-10%.

6. The hybrid passivated back contact cell according to claim 1, characterized in that: The first semiconductor region includes a tunneling oxide layer disposed on the backlight side and a phosphorus-doped polysilicon layer disposed on the transparent conductive film layer side; The width of the first semiconductor region is 200 μm-400 μm, the thickness ratio of the tunneling oxide layer to the phosphorus-doped polysilicon layer is 1:50-1:200, and the backside deposition area accounts for 20%-45%; The thickness of the tunnel oxide layer is 0.5nm-3nm, the thickness of the phosphorus-doped polysilicon layer is 50nm-200nm, and the effective doping concentration is 5×10 19 / cm 3 ~1×10 22 / cm 3 .

7. The hybrid passivated back contact cell according to claim 1, characterized in that: The second semiconductor region is sequentially stacked with an intrinsic hydrogenated amorphous silicon layer, a boron-doped amorphous silicon layer and a boron-doped carbon-oxidized silicon microcrystalline layer from the backlight side; Wherein, the width of the second semiconductor region is 300-500 μm, and the back side deposition area accounts for 45%-75%; The thickness of the intrinsic hydrogenated amorphous silicon layer is 3nm-10nm, the thickness of the boron-doped amorphous silicon layer is 3nm-10nm, and the doping concentration is 1×10 19 / cm 3 ~5×10 19 / cm 3 The thickness of the boron-doped carbon-doped silicon oxide microcrystalline layer is 10nm-30nm, and the doping concentration is 5×10 19 / cm 3 ~2×10 20 / cm 3 , and the thickness ratio of the three layers is 1:1:1 to 1:1:

3.

8. The hybrid passivated back contact cell according to claim 1, characterized in that: The opening width of the transparent conductive film layer is 10 μm-50 μm.

9. The hybrid passivated back contact cell according to claim 1, characterized in that: The area ratio of the first semiconductor region, the second semiconductor region and the insulating material isolation region is 4:9:1 to 9:15:

2.

10. A method for preparing a hybrid passivated back contact cell according to any one of claims 1 to 9, characterized in that: The steps include: Step S1, providing a clean double-sided polished silicon wafer; Step S2, sequentially preparing a tunneling oxide layer (2), an intrinsic amorphous silicon layer (3) and a doped amorphous silicon layer (4) on the backlight surface of the silicon wafer; Step S3, preparing a first opening region (5) on the doped amorphous silicon layer (4) to expose the intrinsic amorphous silicon layer (3); Step S4, depositing phosphorus-doped amorphous silicon (6) and a silicon oxide mask (7) in sequence on the backlight surface of the silicon wafer; Step S5, preparing a pyramid velvet surface morphology on the light-receiving surface of the silicon wafer, and removing the silicon oxide mask (7) on the backlight surface; Step S6, preparing a first semiconductor region (8) in the first opening region (5), and preparing an insulating material isolation region (9) in a region outside the first semiconductor region (8) of the doped amorphous silicon layer (6); Step S7, preparing a second opening region (11) on the insulating material isolation region (9); Step S8, preparing a second semiconductor region (10) in the second opening region (11); Step S9, preparing a third opening region (12) to expose the first semiconductor region (8) and a portion of the insulating material isolation region (9); Step S10, depositing a transparent conductive film layer (13) on the backlight side of the silicon wafer; Step S11, sequentially preparing a FSF front surface passivation field (14) and a passivation anti-reflection layer (15) on the light-receiving side of the silicon wafer; Step S12, preparing a fourth opening region (16) on the transparent conductive film layer (13) to expose a portion of the insulating material isolation region (9); Step S13: metallizing the first semiconductor region (8) and the second semiconductor region (9) to prepare metal electrodes (17) to form ohmic contacts.

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