Sensor package with low aspect ratio through silicon vias

Abstract

An electronic device (100) includes: a semiconductor substrate (112) having a first conductive wiring structure (121) on a first side (115) of the semiconductor substrate (112); and a low aspect ratio via opening (117) extending from the first side (115) to an opposite second side (116). The electronic device (100) includes a transparent cover (124) over a portion of the first side (115) and covering the patterned first conductive wiring structure (121); and an insulator layer (131) comprising a light imageable material on the second side (116) and along a sidewall (118) of the via opening (117); and a second conductive wiring structure (132) on an outer side of the insulator layer (131) and extending through the via opening (117) and directly contacting a portion of the first conductive wiring structure (121).

Description

Background Art

[0001] Ambient light sensors and CMOS image sensors are electronic devices for detecting light and typically include a wafer chip scale package (WCSP) with a semiconductor die with a sensing area facing up on a host printed circuit board (PCB). Through silicon vias (TSVs, also known as through chip vias) route signals from the top side of the die to solder balls or other signal routing at the bottom of the device to help reduce package size. The isolation layer on the back side of the die and the semiconductor sidewalls of the TSV isolates the bottom terminal contacts and is typically made of silicon dioxide (SiO2) deposited by chemical vapor deposition (CVD). 2 However, bottom-side processing is complex and costly due to the long process time of etching through silicon to form TSVs and the CVD deposition and patterning of silicon dioxide which typically requires multiple photolithography process steps. Summary of the invention

[0002] In one aspect, an electronic device includes: a semiconductor substrate having opposing first and second sides; a first conductive wiring structure on the first side; and a through-hole opening extending from the first side to the second side. A portion of the first conductive wiring structure extends above the through-hole opening, and the semiconductor substrate has a thickness distance of about 20 μm or more and less than 150 μm between the first and second sides. The electronic device includes a transparent cover, an insulator layer, and a second conductive wiring structure. The transparent cover extends over a portion of the first side of the semiconductor substrate and covers the patterned first conductive wiring structure. The insulator layer extends on the second side of the semiconductor substrate and along the sidewalls of the through-hole opening, and the insulator layer includes a photoimageable material. The second conductive wiring structure extends on the outside of the insulator layer and through the through-hole opening and directly contacts the portion of the first conductive wiring structure.

[0003] In another aspect, an electronic device includes: a semiconductor substrate having opposing first and second sides; a first conductive wiring structure on the first side; and a through-hole opening extending from the first side to the second side. A portion of the first conductive wiring structure extends above the through-hole opening. The electronic device includes a transparent cover, an insulator layer, and a second conductive wiring structure. The transparent cover extends over a portion of the first side of the semiconductor substrate and covers the patterned first conductive wiring structure. The insulator layer extends on the second side of the semiconductor substrate and along the sidewalls of the through-hole opening, and the insulator layer includes a photoimageable material. The second conductive wiring structure extends on the outside of the insulator layer and through the through-hole opening and directly contacts the portion of the first conductive wiring structure.

[0004] In another aspect, a method for manufacturing an electronic device includes: forming a patterned first conductive wiring structure on a first side of a semiconductor substrate; attaching a transparent cover over a portion of the first side of the semiconductor substrate, the transparent cover covering the patterned first conductive wiring structure; grinding the second side of the semiconductor substrate to reduce the thickness distance between the first and second sides; forming a through-hole opening extending from the first side of the semiconductor substrate to the second side of the semiconductor substrate, a portion of the first conductive wiring structure extending over the through-hole opening; forming an insulator layer on the second side of the semiconductor substrate and along the sidewall of the through-hole opening; and forming a second conductive wiring structure on the outer side of the insulator layer, the second conductive wiring structure extending through the through-hole opening and directly contacting the portion of the first conductive wiring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a top perspective view of the sensor electronics.

[0006] Figure 1A yes Figure 1 A bottom perspective view of an electronic device.

[0007] Figure 1B It is along Figure 1 A partial cross-sectional side view of the electronic device taken along line 1B-1B.

[0008] Figure 2 is a flow chart of a method of manufacturing an electronic device.

[0009] Figures 3 to 16 It is based on experience Figure 2 Method of manufacturing a process Figures 1 to 1B A partial cross-sectional side view of an electronic device.

[0010] Fig.17 is a partial cross-sectional side view of another electronic device.

[0011] Fig.18 is a partial cross-sectional side view of another electronic device.

[0012] Fig.19 is a cross-sectional side view of another electronic device. DETAILED DESCRIPTION

[0013] In the drawings, the same reference numerals refer to the same elements throughout the text, and the various features are not necessarily drawn to scale. In addition, the term "coupling" includes indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled to a second device, the connection may be by direct electrical connection or by indirect electrical connection via one or more intervening devices and connections. The following describes one or more operating characteristics of various circuits, systems and / or components in the context of functions, which in some cases are generated by the configuration and / or interconnection of various structures when the circuit system is powered on and operated. Unless otherwise stated, the "about", "approximately" or "substantially" in front of the value means + / -10% of the stated value.

[0014] Figures 1 to 1B The electronic device 100 is shown having a small form factor. Figure 1 and 1A show the corresponding top and bottom perspectives, and Figure 1B Show along Figure 1 1B-1B is a cross-sectional side view of the electronic device 100.

[0015] The electronic device 100 has a generally rectangular shape, including respective opposite first and second sides 101 and 102 (e.g., bottom and top sides), and respective lateral third, fourth, fifth, and sixth sides 103, 104, 105, and 106. In one example, the electronic device 100 has a WCSP package structure. Figures 1 to 1B 1 is shown in an example position or orientation in a three-dimensional space having a first direction X, a perpendicular (orthogonal) second direction Y, and a third direction Z perpendicular (orthogonal) to the respective first direction X and second direction Y, and structures or features along any two of these respective directions are orthogonal to each other. In the illustrated orientation, the respective first side 101 and the second side 102 are spaced apart from each other along the third direction Z, the respective third side 103 and the fourth side 104 are spaced apart from each other along the first direction X, and the respective fifth side 105 and the sixth side 106 are spaced apart from each other along the second direction Y.

[0016] The electronic device 100 includes a thin semiconductor substrate 112, such as a die that is or includes silicon or other suitable semiconductor material, having low aspect ratio through silicon vias to facilitate cost-effective insulator formation, such as by spin coating using a photoimageable material in certain embodiments. In one example, the semiconductor substrate 112 has a thickness distance 113 of less than 150 μm between respective first and second sides 115 and 116, where larger values ​​may make subsequent TSV formation more difficult and / or more expensive. In this or another example, the semiconductor thickness distance 113 is about 20 μm or more, and smaller values ​​may be difficult to manufacture.

[0017] like Figure 1B As shown, the semiconductor substrate 112 has an optional sensing region 114 exposed along an upper first side 115 of the semiconductor substrate 112. The semiconductor substrate 112 has an opposite (e.g., lower) second side 116. In one example, the sensing region 114 is sensitive to light, and the internal circuit system of the semiconductor substrate 112 provides external terminal connections for the light sensor to interface the light sensor to the main PCB. Figure 1B As shown, the sensing region 114 can be slightly elevated from the first side 115 of the semiconductor substrate 112, or in other embodiments, the sensing region 114 can be substantially flush with the first side 115 of the semiconductor substrate 112. In another example, the sensing region 114 is omitted.

[0018] The semiconductor substrate 112 has low aspect ratio via openings 117 that individually extend from a first side 115 of the semiconductor substrate 112 to a second side 116 of the semiconductor substrate 112. The via openings 117 include at least one sidewall 118. In one example, the via openings 117 have a curved shape, such as a circular or oval shape, but this is not required in all embodiments.

[0019] The first conductive wiring structure 121 extends on the first side 115 of the semiconductor substrate 112, and the first conductive wiring structure 121 is laterally spaced apart from the sensing region 114 (eg, along a first direction X, such as Figure 1B ). A portion of each first conductive wiring structure 121 extends over an associated via opening 117 to allow electrical connection to a bottom side of a circuit system or component of the semiconductor substrate 112. In one example, the first conductive wiring structure 121 is or includes copper.

[0020] Wafer bonding material 122 extends over all or part of first side 115 of semiconductor die 112. Transparent cover 124 extends over a portion of first side 115 of semiconductor substrate 112 and provides top side or second side 102 of electronic device 100. Transparent cover 124 covers sensing region 114 and patterned first conductive wiring structure 121 and allows light to pass from second side 102 to sensing region 114 of semiconductor substrate 112. In one example, transparent cover 124 is or includes glass. Transparent cover 124 has a thickness dimension 125 between lower side or bottom side 126 and upper side or top side 127 along third direction Z.

[0021] In one example, the wafer bonding material 122 is a cured adhesive that bonds the transparent cover 124 to the first side 115 of the semiconductor substrate 112. Figure 1BIn the illustrated example, the wafer bonding material 122 is patterned to extend over the first conductive wiring structure 121 and a portion of the first side 115 of the semiconductor substrate 112 without extending over the sensing area 114. This example allows for the use of a semi-transparent or opaque wafer bonding material 122 while allowing light to enter the sensing area 114 from the transparent cover 124. In another example, the wafer bonding material 122 is at least partially transparent. In one example, the wafer bonding material 122 is unpatterned, at least partially transparent, and extends over any included sensing area 114. In the illustrated example, the wafer bonding material 122 is patterned and leaves a gap 128 between the sensing area 114 and the bottom side 126 of the transparent cover 124, as shown. Figure 1B shown.

[0022] like Figure 1A and 1B As further shown in FIG. 1 , the electronic device 100 includes an insulator layer 131 on the second side 116 of the semiconductor substrate 112 and along the sidewalls 118 of the through hole opening 117. In one example, the insulator layer 131 includes a photoimageable material. In one example, the insulator layer 131 is or includes a polyimide material. In another example, the insulator layer 131 is or includes a polybenzoxazole (PBO) material. In another example, the insulator layer 131 is or includes a solder mask material. In one example, the insulator layer 131 is a single layer. In another embodiment, the insulator layer 131 is a multilayer structure, for example, including a second photoimageable material,

[0023] The electronic device 100 further includes a second conductive wiring structure 132 on the outer side of the insulator layer 131, such as Figure 1A and 1B As shown. The second conductive routing structure 132 extends through the through-hole opening 117 and directly contacts a portion of the corresponding first conductive routing structure 121. In one embodiment, the first and second conductive routing structures 121 and 132 are or include copper. In this or another example, the first conductive routing structure 121 and the second conductive routing structure 132 are formed by electroplating, for example, using an associated redistribution layer (RDL) or active circuit bonding (BOAC) process. The thickness of the second conductive routing structure 132 on the insulator layer 131 is set to a final device height 134 (not shown) for mounting the electronic device 100 on a host system PCB (not shown). Figure 1B ).

[0024] like Figure 1A and 1BAs shown, in one example, the electronic device 100 further includes a solder structure 136 that is attached to the corresponding second conductive routing structure 132 to allow the electronic device 100 to be soldered to the host PCB. The solder structure 136 extends outward (e.g., downward) from the bottom side 101 of the electronic device 100 along the third direction Z. In the example shown, the solder structure 136 is a solder ball having a slightly spherical shape, such as Figure 1A and 1B In another example, the solder structures 136 are printed solder features (not shown) of any suitable shape and are attached to corresponding ones of the second conductive wiring structures 132 .

[0025] Reference now Figures 2 to 16 , Figure 2 A method 200 of manufacturing an electronic device is shown, and Figures 3 to 16 A device that undergoes a manufacturing process according to method 200 is shown. Figures 1 to 1B In one example, the method 200 includes: Figure 2 The front-end wafer at 201 is processed to form a circuit system, such as a light sensing circuit, having a sensing region along a top side or a first side in each of a plurality of unit regions of a starting wafer. Figure 3 An example is shown in which a front-end wafer fabrication process 300 is performed to form light sensing circuitry (e.g., transistors, diodes, etc., not shown) in a unit area 301 of a starting semiconductor wafer 302 (also referred to herein as a semiconductor substrate). In the example shown, the wafer 302 includes the intended semiconductor substrate 112 of the ultimately formed packaged electronic device 100, which is separated after certain described process steps, and the following description refers to the wafer 302 relative to the intended semiconductor substrate 112.

[0026] Method 200 Figure 2 The process continues at 202 with forming a patterned first conductive wiring structure on a first side of the wafer. Figure 4 An example is shown in which a redistribution layer (RDL) or bonding on active circuit (BOAC) process 400 is performed to form a patterned first conductive wiring structure 121 in each unit area 301 on the first side 115 of the wafer 302. In one example, a titanium and copper seed layer is deposited (e.g., by sputtering or other deposition techniques) on the first side 115 and patterned to extend over an area spaced apart from the corresponding sensing area 114, followed by electroplating to form the first conductive wiring structure 121 in each unit area 301, and Figure 2 Any remaining portion of the seed layer is removed at 202 .

[0027] exist Figure 2At 204 , method 200 continues with forming a layer of wafer bonding material on the first side of the wafer. Figure 5 An example is shown in which a coating process 500 is performed that coats the wafer bonding material 122 as a layer on the first side 115 of the wafer 302 , thereby covering the patterned first conductive wiring structure 121 and any included sensing region 114 in each unit area 301 .

[0028] In one embodiment, the method 200 includes, at 205 , optionally patterning the wafer bonding material 122 . Figure 6 An example is shown in which an exposure step is performed using a photolithography machine, and a development process 600 is performed to remove the wafer bonding material 122 above the sensing region 114. In another embodiment, for example, using a transparent wafer bonding material 122, the patterning at 205 is omitted.

[0029] exist Figure 2 At 206, a glass carrier or other suitable transparent cover is attached. Figure 7 An example is shown in which an attachment process 700 is performed to attach a transparent cover 124 to the wafer bonding material 112 over the first side 115 of the wafer 302 so that the transparent cover 112 covers the sensing area 114 and the patterned first conductive wiring structure 121 in each unit area 301. Figure 7 As shown, in one example, the attached transparent cover 124 has a starting thickness 702 that is significantly greater than the above combined Figure 1B The final thickness dimension 125 is depicted between the lower side or bottom side 126 and the upper side or top side 127 of the transparent cover 124 along the third direction Z. In the illustrated example, the process 700 attaches the attached transparent cover 124 to the wafer 302 via the wafer bonding material 122, and in the case of a patterned wafer bonding material 122 embodiment, may include a gap 128, such as Figure 7 In one example, the attachment process 700 mounts a single transparent cover 124 on the wafer bonding material 122 to cover the entire processed wafer, such as Figure 7 In another example, an automated pick-and-place device (not shown) attaches a respective transparent cover 124 to each unit area 301 (not shown). In these or other examples, the attachment process 700 includes a curing step to cure the wafer bonding material 122, for example, using heat, UV exposure, or other suitable techniques.

[0030] The method 200 continues at 208 with grinding a second side (eg, backside or bottom side) of the wafer 302 . Figure 8An example is shown in which a grinding process 800 is performed to remove material from the second side 116 of the wafer 302, such as by mechanical grinding, chemical mechanical polishing (CMP), or other suitable material removal techniques. In one example, the grinding process 800 reduces the thickness distance 113 between the first side 115 and the second side 116 to less than 150 μm, such as to about 20 μm or more and less than 150 μm. This reduces the thickness of the resulting through-hole opening (e.g., above Figure 1B 117), which in turn facilitates the spin coating process and simplifies the patterning when forming the insulator layer 131 using a photoimageable material to help reduce manufacturing time, complexity, and cost. In addition, the grinding process 800 helps reduce the overall finished device height (e.g., Figure 1B The final device height 134 shown in FIG. 1 is preferably selected to accommodate high density circuit boards and system designs using the finished electronic device 100.

[0031] Figure 2 The method 200 in continues with through silicon via (TSV) formation at 210, 212, and 214. At 210, a patterned photoresist is formed on the bottom side of the wafer. Fig. 9 An example is shown in which a process 900 is performed to form a patterned photoresist 902 on the second side 116 of the wafer 302, including depositing a resist material, exposing selected portions of the resist to light and removing the exposed portions to provide Fig. 9 The patterned photoresist 902 is shown. Figure 2 At 212, via openings are etched through the exposed portions of the wafer. Fig.10 An example is shown in which the etching process 1000 is performed using the patterned resist 902 as an etching mask. The etching process 1000 forms a via opening 117 extending from the first side 115 of the wafer 302 to the second side 116 of the wafer 302. Fig.10 As shown, in addition, the etching process 1000 extends the via opening to expose a portion of the corresponding first conductive wiring structure 121 in the corresponding via opening 117. Figure 2 214 of them, for example, through Fig.11 The stripping process 1100 shown in FIG. 1 removes the patterned resist.

[0032] exist Figure 2 At 216 , the method 200 continues with forming a patterned insulator layer on the second side 116 of the via sidewalls and the bottom side of the wafer. Fig.12An example is shown in which a deposition process 1200 is performed to form an insulator layer 131 on the second side 116 of the semiconductor substrate 112 and along the sidewalls 118 of the via openings 117 using any suitable material deposition techniques and equipment. The deposited insulator layer 131 can extend onto and cover the exposed portions of the first conductive wiring structures 121 in the corresponding via openings 117, but this is not required in all embodiments.

[0033] Sidewall coverage facilitates insulating the semiconductor material of the wafer 302 from the subsequently formed conductive RDL or BOAC metal within the via opening 117. Continued exposure of portions of the first conductive wiring structure 121 in the respective via openings 117 can alleviate the need for a patterning step prior to metal formation to form the TSVs, in which case the spin-on deposition at 216 provides a patterned insulating layer 131 without further processing time and expense.

[0034] In one example, the deposition process 1200 includes spin coating a photoimageable (e.g., photosensitive definable material) material on the second side 116 of the semiconductor substrate 112 and along the sidewalls 118 of the via opening 117. In this or another example, the deposited photoimageable material 131 includes a polyimide material. In the above or another example, the deposited photoimageable material 131 includes a polybenzoxazole (PBO) material. In the above or another example, the deposited material 131 includes a solder mask material. An example spin coating process includes dispensing a photoimageable material, such as a resin fluid, onto a wafer surface, spinning or rotating the wafer at high speed to thin the fluid, and a drying step for removing excess solvent from the resulting film. Different embodiments may include static dispensing or dynamic dispensing.

[0035] In one example, a patterning step is performed at 216 to expose portions of the first conductive wiring structures 121 in corresponding via openings 117 . Fig.13An example is shown in which a patterning process 1300 is performed, which patterns the photoimageable material 131 to expose a portion of the patterned first conductive wiring structure 121 in the corresponding through-hole opening 117. In one embodiment, the patterning process 1300 includes exposure or other photo exposure processes. In one example, a photosensitive definable material layer 131 is deposited at 216, such as spin coating or other formation, and the patterning process 1300 includes exposing a portion of the layer 131 to light for development. In another embodiment, the coating is formed from a solution on the layer at 216, and the solvent evaporates from the coating. In this embodiment, a positive photoresist is applied over the coating and exposed to a light pattern by the patterning process 1300, and the exposed portion of the photoresist and the exposed portion of the polyamic acid coating thereunder are removed, and then the remaining photoresist is removed, and the polyamic acid coating is imidized to leave a polyimide patterned insulating layer 131.

[0036] exist Figure 2 At 218 , a patterned second conductive wiring feature is formed on the bottom side of the wafer and on the patterned insulating layer 131 in the via openings 117 to contact portions of the first conductive wiring structure 121 in the corresponding via openings 117 . Fig.14 One example of an RDL implementation is shown in which a process 1400 is performed that forms second conductive wiring structures 132 on the outside of the insulator layer 131 such that the second conductive wiring structures 132 extend through respective via openings 117 and directly contact exposed portions of respective first conductive wiring structures 121 .

[0037] In one example, method 200 includes Figure 2 Optionally, a patterned photoimageable material is formed on the second side of the wafer at 219, for example, as a second layer of the multilayer insulator 131. In another example, the material formation at 219 is omitted. In one example, the method 200 includes Figure 2 A transparent cover is optionally ground at 220 in the embodiment. Fig.15 An example is shown in which a second grinding process 1500 is performed that removes material from the top side 127 of the transparent cover 124 to remove material from its original starting thickness (eg, above 100 mm). Figure 7 The transparent cover 124 thickness distance 125 is reduced from the starting thickness distance 702 in FIG. 1 . In another embodiment, grinding the transparent cover at 220 is omitted. Embodiments that include grinding at 220 advantageously allow for easy handling of thicker transparent covers at 220 during attachment at 206, particularly for attaching a single transparent cover over the entire wafer 302 at 220, while helping to reduce the overall finished device height (e.g., above Figure 1BThe final device height 134 in the embodiment of the present invention can be increased to accommodate high density circuit boards and system designs using the finished electronic device 100.

[0038] Figure 2 The method 200 in also includes an optional solder ball dropping or solder printing operation at 221. Fig.16 An example is shown in which a solder ball dropping process 1600 is performed that forms a substantially spherical solder structure 136 (eg, a solder ball) on the second conductive wiring structure 132 , wherein the solder structure 136 extends outward from the bottom side or first side 101 of the electronic device 100 .

[0039] exist Figure 2 At 222 , method 200 further includes device or die separation. Fig.17 An example is shown in which a dicing process 1700 is performed, for example using a saw, laser cutting, chemical etching, or a combination thereof, to cut the starting wafer along the boundaries between rows and columns of the unit area 301. The dicing process 1700 separates multiple instances of the finished electronic device 100 from the starting wafer.

[0040] Fig.18 A cross-sectional side view of another example electronic device 1800 is shown having a low aspect ratio through silicon via to facilitate cost-effective insulator formation, such as by spin coating using a photoimageable material in certain embodiments. Figure 1-1B The structures and features 112-118, 121, 124-127, 131, 132, 134, and 136 are described. In this example, the electronic device 1800 includes an unpatterned transparent or substantially transparent wafer bonding material 1822 (e.g., omitting Figure 2 ). In this example, the wafer bonding material 1822 extends over the sensing region 114 of the semiconductor substrate 112 and portions of the first conductive wiring structure 121 and the first side 115 of the semiconductor substrate 112 .

[0041] Fig.19 A cross-sectional side view of another electronic device example 1900 having a low aspect ratio through silicon via is shown. The electronic device 1900 includes the Figure 1-1B The structures and features 112-118, 121, 122, 126-128, 131, 132 and 136 described herein. In this example, the wafer bonding material 122 is patterned and may be transparent or even opaque. In another embodiment, a patterned transparent wafer bonding material (e.g., Fig.18 in 1822). Fig.19The electronic device 1900 has a thicker transparent cover 1924 that extends over a portion of the first side 115 of the semiconductor substrate 112 and provides a top side or second side 102 of the electronic device 1900. The device 1900 has a device height dimension 1934 that is larger than the electronic devices 100 and 1800 described above. The transparent cover 1924 covers the sensing area 114 and the patterned first conductive wiring structure 121, and allows light to pass from the second side 102 to the sensing area 114 of the semiconductor substrate 112. In one example, the transparent cover 124 is or includes glass. The transparent cover 124 has a thickness dimension 125 between a lower side or bottom side 126 and an upper side or top side 127 along a third direction Z. In this example, the transparent cover 124 has a thickness 702 between its bottom side 126 and top side 127 along the third direction Z, for example, corresponding to the above combined Figure 7 In one embodiment, during the manufacture of Fig.19 Electronic device 1900 is omitted Figure 2 A second back grinding operation at 219 is performed.

[0042] Unlike higher aspect ratio TVS devices, the described electronic device examples 100, 1800, and 1900 provide low profile device shapes and smaller device height dimensions, as well as manufacturing cost savings. Because the example semiconductor substrate 112 or wafer 302 is back ground to less than 150 μm prior to TVS formation, the etch time to form the via opening 117 is significantly less than the etch time required to form an opening through a thicker semiconductor wafer (e.g., 200 to 300 μm). In addition, the lower aspect ratio of the via opening 117 facilitates cost-effective spin-on deposition of the insulator layer 131 using a photoimageable material that can be patterned without adding additional masks to the manufacturing process. Compared to the method used for forming the via with SiO 2 This further saves cost and manufacturing time compared to CVD or other slower deposition processes for filling higher aspect ratio TSV openings. In some instances, the combination of the top-facing light sensing region 114 and the bottom-side TSVs for electrical terminal connection to the host PCB allows top-side optical light sensing without the need for holes through the host PCB while providing the compact form factor benefits of wafer chip-scale packaging using redistribution layers or BOAC signal routing and interconnection techniques.

[0043] Modifications are possible in the described examples and other implementations are possible within the scope of the claims.

Claims

1. An electronic device, include: A semiconductor substrate having: first and second opposite sides, a first conductive wiring structure on the first side of the semiconductor substrate, and a via opening extending from the first side of the semiconductor substrate to the second side of the semiconductor substrate, a portion of the first conductive wiring structure extending over the via opening, the semiconductor substrate having a thickness distance of about 20 μm or more and less than 150 μm between the first and second sides; a transparent cover over a portion of the first side of the semiconductor substrate, the transparent cover covering the patterned first conductive wiring structure; an insulator layer on the second side of the semiconductor substrate and along sidewalls of the via opening, the insulator layer comprising a photoimageable material; as well as A second conductive wiring structure is on an outer side of the insulator layer, the second conductive wiring structure extending through the via opening and directly contacting the portion of the first conductive wiring structure.

2. The electronic device of claim 1, wherein the first and second conductive wiring structures comprise copper. The electronic device of claim 1 , wherein the transparent cover comprises glass. The electronic device of claim 1 , wherein the insulator layer comprises a polyimide material.

5. The electronic device of claim 1, wherein the insulator layer comprises a polybenzoxazole (PBO) material. The electronic device of claim 1 , wherein the insulator layer comprises a solder mask material.

7. The electronic device of claim 1, further comprising a solder structure attached to the second conductive routing structure and extending outwardly from a bottom side of the electronic device. 8 . The electronic device of claim 1 , wherein the semiconductor substrate comprises a sensing region that is exposed along the first side of the semiconductor substrate and is spaced apart from the first conductive wiring structure.

9. An electronic device, include: A semiconductor substrate having first and second opposite sides, a a first conductive wiring structure and a via opening extending from the first side of the semiconductor substrate to the second side of the semiconductor substrate, a portion of the first conductive wiring structure extending over the via opening; a transparent cover over a portion of the first side of the semiconductor substrate, the transparent cover covering the patterned first conductive wiring structure; an insulator layer on the second side of the semiconductor substrate and along sidewalls of the via opening, the insulator layer comprising a polyimide material; as well as A second conductive wiring structure is on an outer side of the insulator layer, the second conductive wiring structure extending through the via opening and directly contacting the portion of the first conductive wiring structure. 10 . The electronic device of claim 9 , wherein the semiconductor substrate has a thickness distance of approximately 20 μm or more and less than 150 μm between the first and second sides.

11. The electronic device of claim 9, wherein the first and second conductive wiring structures comprise copper.

12. The electronic device of claim 9, wherein the transparent cover comprises glass.

13. The electronic device of claim 9, further comprising a solder structure attached to the second conductive routing structure and extending outwardly from a bottom side of the electronic device. 14 . The electronic device of claim 9 , wherein the semiconductor substrate comprises a sensing region that is exposed along the first side of the semiconductor substrate and is spaced apart from the first conductive wiring structure.

15. A method for manufacturing an electronic device, the method include: forming a patterned first conductive wiring structure on a first side of a semiconductor substrate; attaching a transparent cover over a portion of the first side of the semiconductor substrate, the transparent cover covering the patterned first conductive wiring structure; grinding the second side of the semiconductor substrate to reduce a thickness distance between the first and second sides to about 20 μm or more and less than 150 μm; forming a via opening extending from the first side of the semiconductor substrate to the second side of the semiconductor substrate, a portion of the first conductive wiring structure extending over the via opening; forming an insulator layer on the second side of the semiconductor substrate and along sidewalls of the via opening; as well as A second conductive wiring structure is formed on an outer side of the insulator layer, the second conductive wiring structure extending through the via opening and directly contacting the portion of the first conductive wiring structure.

16. The method of claim 15, wherein forming an insulator layer comprises spin coating a photoimageable material on the second side of the semiconductor substrate and along the sidewalls of the via opening.

17. The method of claim 16, wherein forming an insulator layer further comprises patterning the photoimageable material to expose a portion of the patterned first conductive wiring structure in the via opening.

18. The method of claim 16, wherein the photoimageable material comprises a polyimide material. The method of claim 15 , wherein the insulator layer comprises a polyimide material.

20. The method of claim 15, wherein the insulator layer comprises a polybenzoxazole material.

21. The method of claim 15, wherein the insulator layer comprises a solder mask material.

22. The method according to claim 15, further comprising: include: A solder structure is formed on the second conductive wiring structure extending outwardly from the bottom side of the electronic device.

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