Semiconductor device, semiconductor device manufacturing method, and electronic apparatus

Abstract

The present disclosure relates to a semiconductor device capable of improving image quality, a semiconductor device manufacturing method, and an electronic apparatus. The semiconductor device includes: a first semiconductor chip; a second semiconductor chip which is bonded to the first semiconductor chip by means of CoW bonding; and a high stress film that generates stress to counteract stress that may be generated in the first semiconductor chip or the second semiconductor chip during the CoW bonding. The high stress film is provided in an arrangement pattern having a high density in a region near four corners of the first semiconductor chip or the second semiconductor chip, and having a low density in a region near a center of the first semiconductor chip or the second semiconductor chip. The present technology is applicable, for example, to a stacked CMOS image sensor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device, and more particularly, to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device capable of improving image quality. Background Art

[0002] In recent years, a technology for making semiconductor devices using 3D (three-dimensional) integrated circuits by bonding semiconductor wafers together using WoW (wafer on wafer) bonding or bonding semiconductor chips to semiconductor wafers using CoW (chip on wafer) bonding has been developed. This technology makes it possible to manufacture, for example, a highly functional semiconductor device obtained by bonding a plurality of chips having various functions together.

[0003] However, in the step of bonding semiconductor wafers to each other by WoW bonding, or in the step of bonding a semiconductor wafer and a semiconductor chip to each other by CoW bonding, stress generated by pressing during bonding may cause a device pattern of a semiconductor device to be distorted (strained).

[0004] For example, Patent Document 1 discloses a semiconductor device in which propagation of stress is interrupted by grooves formed in the outer periphery of a chip region on a bonding surface of a support substrate, thereby alleviating distortion caused by wafer bonding. [Citation list] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Publication No. 2012-204543 Summary of the invention [Technical issues to be solved]

[0006] Although Patent Document 1 discloses a technique for alleviating distortion during WoW bonding, it does not disclose a technique for CoW bonding. For example, in a solid-state imaging element, when the device pattern is distorted due to CoW bonding, light entering the photodiode from the lens is blocked. This leads to concerns that image quality may deteriorate.

[0007] The present disclosure has been made in view of the above-described circumstances, and the present disclosure aims to improve the quality of a semiconductor device manufactured by CoW bonding. [Technical solution to the problem]

[0008] A semiconductor device according to one aspect of the present disclosure includes: a first semiconductor chip; a second semiconductor chip bonded to the first semiconductor chip by CoW bonding; and a high-stress film that generates stress to offset stress that would be generated in the first semiconductor chip or the second semiconductor chip during CoW bonding.

[0009] A semiconductor device manufacturing method according to one aspect of the present disclosure includes forming a high stress film that generates stress to offset stress that would be generated in a first semiconductor chip or a second semiconductor chip during CoW bonding when attaching a second semiconductor chip to a first semiconductor chip.

[0010] An electronic device according to one aspect of the present invention includes a semiconductor device, which includes: a first semiconductor chip; a second semiconductor chip, which is bonded to the first semiconductor chip through CoW bonding; and a high stress film, which generates stress to offset the stress that will be generated in the first semiconductor chip or the second semiconductor chip during CoW bonding.

[0011] In one aspect of the present disclosure, a high stress film is provided in a semiconductor device, the high stress film generating stress to offset stress generated in the first semiconductor chip or the second semiconductor chip during CoW bonding when attaching the second semiconductor chip to the first semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 : is a block diagram showing a configuration example of a first embodiment of an image pickup element to which the present technology is applied. Figure 2 FIG. 5 is a diagram showing simulation results of stress generated by CoW bonding and an example of a high stress film. Figure 3 It is a diagram showing a cross-sectional view of a structural example of a sensor chip. Figure 4 It is a figure for demonstrating the manufacturing method of an imaging element. Figure 5 It is a figure for demonstrating the manufacturing method of an imaging element. Figure 6 It is a figure for demonstrating the manufacturing method of an imaging element. Figure 7 It is a diagram showing a modified example of the sensor chip. Figure 8 It is a diagram for explaining a second embodiment of the imaging element. Fig. 9 It is a diagram for explaining a third embodiment of an image pickup element. Fig.10It is a diagram for explaining a fourth embodiment of an image pickup element. Fig.11 It is used to illustrate Fig.10 FIG. 1 is a diagram of a method for manufacturing an imaging element. Fig.12 It is a flow chart of the design process of the imaging element. Fig.13 is a cross-sectional view of a second structural example of the sensor chip. Fig.14 It is shown Fig.13 FIG. 5 is a diagram of a modified example of the sensor chip in FIG. Fig.15 is a cross-sectional view of a third structural example of the sensor chip. Fig.16 It is shown Fig.15 FIG. 5 is a diagram of a modified example of the sensor chip in FIG. Fig.17 It is a diagram for explaining the fifth embodiment of the imaging element. Fig.18 It is a diagram for explaining a sixth embodiment of an image pickup element. Fig.19 It is used to illustrate Fig.18 FIG. 1 is a diagram of a method for manufacturing an imaging element. Fig. 20 It is used to illustrate Fig.18 FIG. 1 is a diagram of a method for manufacturing an imaging element. Fig.21 This is a diagram for explaining a case where the influence of chip steps is significant. Fig. 22 It is used to illustrate Fig.18 FIG. 1 is a diagram of a first variation of the imaging element in FIG. Fig.23 It is used to illustrate Fig.18 FIG. 2 is a diagram of a second variation of the imaging element in FIG. Fig.24 is a block diagram showing a configuration example of an imaging device. Fig.25 This is a diagram showing an example of use of an image sensor. DETAILED DESCRIPTION

[0013] Hereinafter, specific embodiments to which the present technology is applicable will be described in detail with reference to the accompanying drawings.

[0014] <First structural example of imaging element> Will refer to Figures 1 to 7 A first embodiment of an imaging element as a semiconductor device to which the present technology is applied will be described.

[0015] like Figure 1As shown in the figure, first, a logic chip 12 on which a logic circuit for driving pixels is formed and a semiconductor wafer 13 that has not yet been cut into a plurality of sensor chips 14 are bonded together by CoW bonding. Then, dicing is performed on the semiconductor wafer 13 along the dotted lines in the figure to form individual sensor chips 14. Thus, an imaging element 11 is manufactured. For example, the imaging element 11 is a stacked CMOS (Complementary Metal Oxide Semiconductor) image sensor obtained by stacking a logic chip 12 and a sensor chip 14 having the same chip size.

[0016] The imaging element 11 has a structure including a high stress film 15 (see FIG. 1 ) provided on the bonding surface of the sensor chip 14 with the logic chip 12. Figure 2 B) to suppress distortion that may occur in the device pattern of the sensor chip 14 due to stress generated during CoW bonding when the logic chip 12 is pressed onto the semiconductor wafer 13.

[0017] exist Figure 2 In A of FIG. 1 , an example of a simulation result obtained by simulating the stress that will be generated in the logic chip 12 during the CoW bonding when the logic chip 12 is pressed onto the semiconductor wafer 13 is shown. Figure 2 In A, each arrow indicates the direction and magnitude of stress generated at each point on the logic chip 12 , and the rectangular frame line indicates the outer shape of the logic chip 12 .

[0018] like Figure 2 As shown in FIG. 1 , during the CoW bonding period when the logic chip 12 is pressed onto the semiconductor wafer 13, stress is generated that stretches the logic chip 12. Therefore, stress is generated in the sensor chip 14 in the opposite direction to the stress that contracts the sensor chip 14. In addition, the stress generated by the CoW bonding is larger at positions closer to the four corners of the logic chip 12 and the sensor chip 14, and is symmetrical in the left and right directions and in the top and bottom directions with respect to the rectangular shapes of the logic chip 12 and the sensor chip 14.

[0019] Therefore, the high stress film 15 provided on the sensor chip 14 generates stress to offset the stress causing the sensor chip 14 to shrink, and the high stress film 15 is formed in an arrangement pattern having a higher density as it is closer to the four corners of the sensor chip 14 and being symmetrical left-right and top-bottom with respect to the rectangular shape of the sensor chip 14 .

[0020] For example, Figure 2As shown in FIG. 1B , by adjusting the arrangement density using an arrangement pattern in which slits and openings (white blank portions) are provided in the high stress film 15, the stress that causes the sensor chip 14 to shrink due to the CoW bonding can be adaptively offset. That is, the high stress film 15 is formed in an arrangement pattern with a difference in density, wherein the density is high in the regions near the four corners where the stress that causes the sensor chip 14 to shrink is large, and the density is low in the region near the center where the stress that causes the sensor chip 14 to shrink is small. Therefore, the high stress film 15 is formed so that a large stress that causes the sensor chip 14 to stretch is generated in the regions near the four corners, and a small stress that causes the sensor chip 14 to stretch is generated in the region near the center.

[0021] In addition, in the imaging element 11 including the logic chip 12 and the sensor chip 14 having the same chip size, the high stress film 15 having the same size as the logic chip 12 and the sensor chip 14 is provided.

[0022] Note that the direction and magnitude of the stress to be generated vary depending on the bonding method of the logic chip 12 and the sensor chip 14, but the stress is necessarily high in density at the four corners of the logic chip 12 and the sensor chip 14, and is symmetrical left and right and vertically with respect to the rectangular shape. Therefore, the arrangement pattern for providing the high stress film 15 with a density difference needs to have a higher density in the areas near the four corners, and be symmetrical left and right and vertically with respect to the rectangular shape.

[0023] Figure 3 2 is a diagram showing a cross-sectional view of a structural example of the sensor chip 14 .

[0024] like Figure 3 As shown, the sensor chip 14 is formed by laminating a wiring layer 22 on a semiconductor substrate 21 provided with a photodiode and the like. In the wiring layer 22, a plurality of layers (three layers in the example in the figure) of wiring 32 are provided inside an interlayer insulating film 31, and a high stress film 15 is provided in a layer different from the wiring 32. In addition, a bonding pad 33 for bonding with the logic chip 12 is provided so as to be exposed from the surface of the wiring layer 22, and the bonding pad 33 is connected to a prescribed wiring 32.

[0025] In this way, the sensor chip 14 can have the high stress film 15 inside the wiring layer 22 on the bonding surface side of the logic chip 12. Therefore, the high stress film 15 can alleviate the occurrence of distortion caused by the stress generated in the sensor chip 14 during the CoW bonding, and the occurrence of distortion in the device pattern of the sensor chip 14 can be suppressed.

[0026] Therefore, in the imaging element 11, it is possible to suppress distortion occurring in the device pattern of the sensor chip 14. As a result, for example, it is possible to form a lens provided for each pixel on the sensor surface of the sensor chip 14 in a manner consistent with the arrangement of the photodiode provided for each pixel in the sensor chip 14. Therefore, it is possible to avoid obstruction of light entering from the lens to the photodiode, and thus it is possible to further improve the image quality of the imaging element 11.

[0027] Furthermore, the accuracy of bonding alignment between the logic chip 12 and the sensor chip 14 is improved in the imaging element 11. Therefore, for example, it is possible to improve conduction failure.

[0028] Will refer to Figures 4 to 6 The steps for manufacturing the sensor chip 14 provided with the high stress film 15 in the method for manufacturing the imaging element 11 will be described.

[0029] In the first step, if Figure 4 As shown in the upper figure in FIG. 2 , an interlayer insulating film 31 is stacked on the surface of the semiconductor substrate 21 , and a plurality of wirings 32 are formed inside the interlayer insulating film 31 .

[0030] In the second step, if Figure 4 As shown in the middle figure in FIG. 1 , by dry-etching the surface of the interlayer insulating film 31 , a recessed portion 41 conforming to the arrangement pattern of the high stress film 15 is formed.

[0031] In the third step, if Figure 4 As shown in the lower figure in FIG. , a material that will become the high stress film 15 (for example, silicon nitride) is formed on the surface of the interlayer insulating film 31 and inside the recess 41, thereby forming a nitride film 42 on the entire surface of the interlayer insulating film 31.

[0032] In the fourth step, if Figure 5 As shown in the upper figure in FIG. 1 , the nitride film 42 formed on the surface of the interlayer insulating film 31 is removed by chemical mechanical polishing (CMP) to form the high stress film 15 .

[0033] In the fifth step, if Figure 5 As shown in the middle figure in FIG. 2 , the interlayer insulating film 31 is deposited until the thickness reaches the wiring layer 22 .

[0034] In the sixth step, if Figure 5 As shown in the lower figure in FIG. 1 , by dry etching the surface of the interlayer insulating film 31 , a recess 43 conforming to the shape of the bonding pad 33 is formed.

[0035] In the seventh step, if Figure 6 As shown in the upper figure in FIG. , a metal material (eg, copper) that will become a bonding pad 33 is formed on the surface of the interlayer insulating film 31 and inside the recess 43 , thereby forming a metal film 44 on the entire surface of the interlayer insulating film 31 .

[0036] In the eighth step, if Figure 6 As shown in the lower figure in FIG. 4 , the metal film 44 formed on the surface of the interlayer insulating film 31 is removed by CMP to form the bonding pad 33 .

[0037] As a result of the above steps, the sensor chip 14 having the high stress film 15 provided inside the wiring layer 22 can be manufactured.

[0038] Figure 7 It is a diagram showing a modified example of the sensor chip 14 .

[0039] Figure 7 A is a cross-sectional view showing a configuration example of a sensor chip 14 a as a first modification example. The sensor chip 14 a is formed by providing a high stress film 15 a on the outermost surface of the wiring layer 22 , for example.

[0040] Figure 7 B is a cross-sectional view showing a configuration example of a sensor chip 14 b as a second modification example. For example, the sensor chip 14 b is formed by providing a part and another part of the high stress film 15 b in different layers inside the wiring layer 22 .

[0041] <Second Structural Example of Imaging Element> Will refer to Figure 8 A second embodiment of the image pickup element will be described.

[0042] like Figure 8 As shown in the cross-sectional layout in A of FIG. 1 , the imaging element 11A is formed by bonding a logic chip 12A and a sensor chip 14A having a larger chip size than the logic chip 12A by a CoW bonding method.

[0043] For example, when CoW bonding is performed while the logic chip 12A is pressed onto the sensor chip 14A, stress due to the applied pressure causes distortion to occur in the sensor chip 14A in a range larger than the chip size of the logic chip 12A. In view of this, in order to suppress distortion occurring in a range larger than the chip size of the logic chip 12A, the imaging element 11A has a structure in which a high stress film 15A larger than the logic chip 12A is provided on the logic chip 12A bonding surface side of the sensor chip 14A.

[0044] For example, Figure 8The dotted rectangular frame line 51 in B shows the outer shape of the logic chip 12A, and the high stress film 15A is provided on the sensor chip 14A in a larger range than the logic chip 12A. Figure 2 Like the high stress film 15 in , the high stress film 15A is formed in an arrangement pattern having a higher density in regions closer to the four corners of the sensor chip 14A and being symmetrical left-right and top-bottom with respect to the rectangular shape of the sensor chip 14A.

[0045] In the imaging element 11A having the above-described configuration, Figure 1 As with the imaging element 11 in FIG. 1 , the distortion occurring in the device pattern of the sensor chip 14A can be suppressed. Therefore, for example, the image quality can be further improved, and the conduction failure can be further improved.

[0046] <Third Structural Example of Imaging Element> Will refer to Fig. 9 A third embodiment of the image pickup element will be described.

[0047] like Fig. 9 As shown in the planar layout in A, the imaging element 11B is formed by bonding four logic chips 12B-1 to 12B-4 to a sensor chip 14B having a larger chip size than the logic chips 12B-1 to 12B-4 in a CoW bonding manner. That is, the imaging element 11B can adopt a stacked structure in which a plurality of logic chips 12B are stacked on the sensor chip 14B.

[0048] For example, when CoW bonding is performed while the logic chips 12B-1 to 12B-4 are pressed onto the sensor chip 14B, stress due to the applied pressure causes distortion to occur in the sensor chip 14B in a range larger than the chip size of the logic chips 12B-1 to 12B-4. In view of this, in order to suppress distortion occurring in a range larger than the chip size of the logic chips 12B-1 to 12B-4, the imaging element 11B has a configuration in which a high stress film 15B is provided on the entire surface of the sensor chip 14B.

[0049] For example, Fig. 9 The dotted rectangular frame lines 51-1 to 51-4 in B represent the outer shapes of the logic chips 12B-1 to 12B-4, respectively. The high stress film 15B is provided on the sensor chip 14B in a larger range than the logic chips 12B-1 to 12B-4. Figure 2Like the high stress film 15 in the figure, the high stress film 15B is formed in the following arrangement pattern: the arrangement pattern has a higher density in the area closer to the four corners of each of the logic chips 12B-1 to 12B-4, and is symmetrical left-right and top-bottom relative to the rectangular shape of each of the logic chips 12B-1 to 12B-4.

[0050] In the imaging element 11B having the above-described configuration, Figure 1 As with the imaging element 11 in FIG. 1 , the distortion occurring in the device pattern of the sensor chip 14B can be suppressed. Therefore, for example, the image quality can be further improved, and the conduction failure can be further improved.

[0051] <Fourth Structural Example of Imaging Element> Will refer to Fig.10 and Fig.11 A fourth embodiment of the image pickup element will be described.

[0052] like Fig.10 As shown in the cross-sectional layout in FIG, the imaging element 11C is formed by bonding a logic chip 12C and a sensor chip 14C having a chip size larger than the logic chip 12C by CoW bonding. In addition, in the imaging element 11C, a high stress film 15C is provided to cover the logic chip 12C in a larger range than the logic chip 12C, and an insulating film 16 is provided to be stacked on the sensor chip 14C and the high stress film 15C.

[0053] For example, Figure 8 The imaging element 11A in the embodiment has a structure in which the high stress film 15A provided on the bonding surface side of the sensor chip 14A with the logic chip 12A alleviates the occurrence of distortion inside the sensor chip 14A. In contrast, the imaging element 11C has a structure in which the high stress film 15C provided to cover the logic chip 12C after the CoW bonding of the logic chip 12C and the sensor chip 14C alleviates the occurrence of distortion from the outside of the sensor chip 14C.

[0054] Note that although the arrangement pattern is not shown, Figure 8 Like the high stress film 15A shown in FIG. 1B , the high stress film 15C is formed in an arrangement pattern having a higher density in regions closer to the four corners of the sensor chip 14C and being symmetrical left-right and top-bottom with respect to the rectangular shape of the sensor chip 14C.

[0055] In addition, in Fig. 9When CoW bonding of a plurality of logic chips 12C and a sensor chip 14C is performed like the imaging element 11B in FIG. 1 , the high stress film 15C is provided to cover the plurality of logic chips 12C.

[0056] In the imaging element 11C having the above-described configuration, Figure 1 As with the imaging element 11 in FIG. 1 , the distortion occurring in the device pattern of the sensor chip 14C can be suppressed. Therefore, for example, the image quality can be further improved.

[0057] Fig.11 An example of a method for manufacturing the image pickup element 11C is shown.

[0058] In the eleventh step, if Fig.11 As shown in the upper figure in FIG. 1 , the CoW bonding of the logic chip 12C and the sensor chip 14C is performed. During the CoW bonding, the sensor chip 14C is deformed in the region surrounded by the double-dashed line, that is, in a region larger than the logic chip 12C.

[0059] In the twelfth step, if Fig.11 As shown in the middle figure in FIG. 1 , the thickness of the logic chip 12C is reduced by, for example, grinding the logic chip 12C.

[0060] In the thirteenth step, if Fig.11 As shown in the lower figure in FIG. 1 , a high stress film 15C is formed to cover the logic chip 12C.

[0061] Subsequently, the insulating film 16 is formed. Thus, it is possible to manufacture Fig.10 The imaging element 11C is shown.

[0062] <Image Pickup Element Design Process> Will refer to Fig.12 The design process of the imaging element 11 is explained with reference to the flowchart in FIG.

[0063] For example, when the design process of the image pickup element 11 is started, it is determined in step S11 whether the image pickup element 11 is to be manufactured by CoW bonding.

[0064] If it is determined in step S11 that the image pickup element 11 is not manufactured by CoW bonding, the process ends. If it is determined that the image pickup element 11 is manufactured by CoW bonding, the process proceeds to step S12.

[0065] In step S12, a simulation is performed to find the stress that will be generated in the sensor chip 14, and the position and size of the distortion that will occur in the sensor chip 14 are confirmed based on the simulation result. In this step, for example, a configuration in which the logic chip 12 and the sensor chip 14 have the same chip size (see Figure 1 ), the logic chip 12 and the sensor chip 14 have different chip sizes (see Figure 8 ), or a structure where a plurality of logic chips 12 are bonded to a sensor chip 14 (see Fig. 9 ) etc. were simulated as structures to be manufactured.

[0066] In step S13, the size and design of the high stress film 15 are determined based on the position and size of the distortion confirmed in step S12. For example, the size and design of the high stress film 15 are determined so that the density is higher at the position where the distortion is larger and the density is lower at the position where the distortion is smaller.

[0067] In step S14, it is determined which of the arrangement on the outermost surface of the wiring layer 22, the arrangement inside the wiring layer 22, and the arrangement covering the logic chip 12 is the arrangement of the high stress film 15 according to the structure of the imaging element 11 to be manufactured.

[0068] If it is determined in step S14 that the high stress film 15 is arranged on the outermost surface of the wiring layer 22, the process proceeds to step S15, and in this step S15 it is determined that the high stress film 15 is arranged on the outermost surface of the wiring layer 22. That is, in this case, the imaging element 11 is used Figure 7 The configuration of the sensor chip 14a shown in A is manufactured.

[0069] On the other hand, if it is determined in step S14 that the high stress film 15 is arranged in a manner inside the wiring layer 22, the process proceeds to step S16, and in this step S16 it is determined that the high stress film 15 is arranged inside the wiring layer 22. That is, in this case, the imaging element 11 is used Figure 3 The sensor chip 14 is manufactured with the structure shown.

[0070] On the other hand, if it is determined in step S15 that the high stress film 15 is arranged so as to cover the logic chip 12, the process proceeds to step S17, and in this step S17 it is determined that the high stress film 15 is arranged so as to cover the logic chip 12. That is, in this case, the high stress film 15 is manufactured. Fig.10 The imaging element 11C is shown.

[0071] Then, after the processing of steps S15 to S17 , the design process of the image pickup element 11 is completed, and then the manufacturing of the image pickup element 11 is performed according to the decision made in the design process.

[0072] As described above, according to the design process of the structure of the imaging element 11 to be manufactured, it is possible to manufacture the imaging element 11 capable of appropriately suppressing the distortion occurring in the device pattern.

[0073] <Second structural example of sensor chip> Will refer to Fig.13 The sensor chip 14D as the second configuration example is described below. Fig.13 In the sensor chip 14D shown, Figure 3 Configurations similar to those in the illustrated sensor chip 14 will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0074] like Fig.13 As shown, Figure 3 Similar to the sensor chip 14 in FIG. 1 , the sensor chip 14D has the following structure: wherein the sensor chip 14D is formed by stacking a wiring layer 22D on a semiconductor substrate 21, the wiring 32 is arranged inside the wiring layer 22D, and the bonding pad 33 is arranged to be exposed from the surface of the wiring layer 22D.

[0075] In addition, Figure 3 The sensor chip 14D has the high stress film 15D provided in the wiring layer 22D in a layer different from the layers of the wiring 32, but the sensor chip 14D is different from the sensor chip 14D in FIG. Figure 3 The difference from the sensor chip 14 in FIG. 1 is that the high stress film 15D includes at least two or more types of materials.

[0076] exist Fig.13 In the example shown, the high stress film 15D includes a high stress film 61a made of a first material and a high stress film 61b made of a second material. For example, silicon nitride (Si 2+) can be used as the material of the high stress film 61a and the high stress film 61b. 3 N 4 ), silicon carbide (SiC), silicon carbonitride (SiCN), or silicon oxide containing carbon, hydrogen or nitrogen. In another case, aluminum oxide (Al2O3) can be used as the material of the high stress film 61a and the high stress film 61b. 2 O 3 ), aluminum nitride (AlN), tantalum, tantalum nitride (TaN), titanium, titanium nitride (TiN), tungsten, or tungsten nitride (WN), etc.

[0077] Furthermore, in the high stress film 15D, in consideration of the distortion caused by the CoW bonding, for example, a high stress film 61a and a high stress film 61b are provided in a region where a stress is applied during the CoW bonding to offset the contraction stress generated after the CoW bonding. For example, in the high stress film 15D, a high stress film 61a made of a material having a relatively strong force to offset the stress is provided in a region where a stress caused by the CoW bonding to shrink the sensor chip 14D is large, and a high stress film 61b made of a material having a relatively weak force to offset the stress is provided in a region where a stress caused by the CoW bonding to shrink the sensor chip 14D is small.

[0078] Therefore, the high stress film 15D in the sensor chip 14D effectively alleviates the occurrence of distortion due to the stress generated during the CoW bonding period, thereby further improving the quality.

[0079] In addition, the high stress film 15D including a plurality of materials can be obtained by, for example, repeating the previously referenced Figures 4 to 6 The method is formed by performing the second to fifth steps in the manufacturing method described above.

[0080] Note that Fig.13 In the example shown, the sensor chip 14D is configured to have the high stress film 15D provided on the outermost surface of the wiring layer 22D, but may be configured to have the high stress film 15D provided at a position other than the outermost surface of the wiring layer 22D. Fig.14 As in the modified example shown, even if the sensor chip 14D has the high stress film 15D provided inside the wiring layer 22D, it is possible to improve the quality.

[0081] <Third Structure Example of Sensor Chip> Will refer to Fig.15 The sensor chip 14E as the third structural example is described below. Fig.15 In the sensor chip 14E shown, Figure 3 Configurations similar to the configuration of the illustrated sensor chip 14 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0082] like Fig.15 As shown, Figure 3 Similar to the sensor chip 14 in FIG. 1 , the sensor chip 14E has a structure in which a wiring layer 22E is stacked on the semiconductor substrate 21 , wirings 32 are provided inside the wiring layer 22E, and bonding pads 33 are provided to be exposed from the surface of the wiring layer 22E.

[0083] On the other hand, Figure 3The sensor chip 14E is different from the sensor chip 14 in that an air gap layer 17 is provided in a layer different from the wiring 32 in the wiring layer 22E instead of the high stress film 15 .

[0084] exist Fig.15 In the example shown, since the void layer 17 is provided on the outermost surface of the wiring layer 22E, the void 62 constituting the void layer 17 is formed as a recessed portion. In addition, the void layer 17 has a configuration in which, for example, in a region where pressure is applied during CoW bonding, the void 62 is provided to release the contraction stress generated after CoW bonding (thereby preventing such stress from being applied to the sensor chip 14E).

[0085] Therefore, the gap layer 17 in the sensor chip 14E effectively alleviates the occurrence of distortion caused by the stress generated during the CoW bonding period, thereby further improving the quality.

[0086] In addition, the gap layer 17 can be formed by the following steps: For example, in reference Figures 4 to 6 In the manufacturing method described above, the recessed portion 41 is formed in the second step, and then the embedding of the material to be the high stress film 15 is not performed.

[0087] It should be noted that Fig.15 The sensor chip 14E in the illustrated example is configured to have the gap layer 17 provided on the outermost surface of the wiring layer 22E, but may be configured to have the gap layer 17 provided at a position other than the outermost surface of the wiring layer 22E. Fig.16 Even if the sensor chip 14E has a structure in which the air gap layer 17 is provided inside the wiring layer 22E as in the illustrated modification example, the quality can still be improved.

[0088] <Fifth Structural Example of Imaging Element> Will refer to Fig.17 A fifth embodiment of the image pickup element will be described.

[0089] like Fig.17 As shown in the cross-sectional layout in FIG, the imaging element 11F is formed by bonding the logic chip 12F and the sensor chip 14F having a larger chip size than the logic chip 12F by CoW bonding. In addition, in the imaging element 11F, the high stress film 15F-1 is provided in the logic chip 12F, and the high stress film 15F-2 is provided in the sensor chip 14F. That is, the imaging element 11F is formed by providing the high stress film 15F in both the logic chip 12F and the sensor chip 14F.

[0090] For example, the high stress film 15F-1 is provided so as to suppress the outward expansion of the logic chip 12F due to the pressure during the CoW bonding. Similarly, the high stress film 15F-2 is provided so as to suppress the outward expansion of the sensor chip 14F due to the pressure during the CoW bonding. In this way, since the outward expansion during the CoW bonding is suppressed by the high stress film 15F-1 and the high stress film 15F-2, the generation of the contraction stress in the logic chip 12F and the sensor chip 14F after the CoW bonding can be suppressed.

[0091] Therefore, in the imaging element 11F, the generation of contraction stress in the logic chip 12F and the sensor chip 14F due to the CoW bonding is suppressed, and thus, for example, the generation of distortion in the sensor surface can be suppressed. Therefore, the image quality can be further improved.

[0092] Note that the imaging element 11F may be configured such that, instead of the high stress films 15F-1 and 15F-2, the imaging element 11F may be configured such that Fig.15 The void layer 17 described above alleviates the occurrence of strain caused by stress generated during CoW bonding.

[0093] <Sixth Structural Example of Imaging Element> Will refer to Figures 18 to 23 A sixth embodiment of the image pickup element will be described.

[0094] Fig.18 It is a cross-sectional view showing a structural example of an imaging element 101 as a semiconductor device to which the present technique is applied.

[0095] like Fig.18 As shown in FIG. 1 , the imaging element 101 is formed by stacking a sensor chip 102 , a logic chip 103 , a distortion adjustment film 104 , and a supporting substrate 105 .

[0096] The sensor chip 102 is formed by laminating a wiring layer 112 on a semiconductor substrate 111 on which a photodiode and the like are arranged.

[0097] The logic chip 103 is formed by stacking the wiring layer 121, the semiconductor substrate 122, the wiring layer 123, the wiring layers 124-1 and 124-2, the semiconductor substrates 125-1 and 125-2, and the buried layer 126. That is, the logic chip 103 is formed by attaching a small chip including the wiring layer 124-1 and the semiconductor substrate 125-1 and a small chip including the wiring layer 124-2 and the semiconductor substrate 125-2 to a large chip including the wiring layer 121, the semiconductor substrate 122, and the wiring layer 123. Therefore, the logic chip 103 has a shape in which a step protruding toward the wiring layer 123 is provided between the wiring layer 124-1 and the semiconductor substrate 125-1 and the wiring layer 124-2 and the semiconductor substrate 125-2. In addition, in the logic chip 103, a buried layer 126 for burying the above-mentioned step is formed, so that the surface ( Fig.18 The downward-facing surface in the middle is flattened.

[0098] Here, the buried layer 126 is formed by forming the buried layer 126 by chemical vapor deposition (CVD) or the like on the surface of a small chip including the wiring layer 124-1 and the semiconductor substrate 125-1, on the surface of a small chip including the wiring layer 124-2 and the semiconductor substrate 125-2, and between the two small chips, and then planarizing the surface of the buried layer 126 by CMP. However, due to the above-mentioned step protruding toward the wiring layer 123, even if planarization is performed by CMP, unevenness (hereinafter referred to as chip step) is generated on the surface of the buried layer 126.

[0099] Then, when the embedded layer 126 is bonded to the support substrate 105 in a state where the surface has a chip step, for example, the influence of the chip step may act on the surface after the semiconductor substrate 111 is thinned. If so, distortion occurs in the longitudinal and lateral directions of the sensor surface of the sensor chip 102. Such distortion may cause misalignment or defocus in the photolithography step after WoW bonding. This causes the influence of color mixing in terms of device characteristics and a decrease in yield due to abnormalities in pattern formation.

[0100] The distortion adjustment film 104 is provided to suppress the influence of the chip step on the surface of such an embedded layer 126 and to adjust the distortion occurring in the sensor surface of the sensor chip 102. For example, before the logic chip 103 is bonded to the support substrate 105, the SFQR (Site Front least sQuare Range) value of the surface of the embedded layer 126 is measured, and a concavoconvex surface 131 for canceling the concavoconvexity of the surface of the embedded layer 126 is formed on the distortion adjustment film 104 according to the SFQR flatness value. That is, the logic chip 103 bonding surface of the distortion adjustment film 104 is a concavoconvex surface 131 that protrudes according to the concave portion in the surface of the embedded layer 126 and is concave according to the convex portion on the surface of the embedded layer 126. Since the concavoconvex surface 131 is provided on the distortion adjustment film 104 in this way, the influence of the chip step on the surface of the embedded layer 126 can be canceled.

[0101] The support substrate 105 is a base for supporting the sensor chip 102 and the logic chip 103 .

[0102] Since the imaging element 101 has the above-described structure, the influence of the chip step on the surface of the buried layer 126 is offset by the distortion adjustment film 104, so that the generation of distortion in the surface of the thinned semiconductor substrate 111 can be suppressed. As a result, it is possible to avoid degradation of device characteristics and degradation of the yield of the imaging element 101. Therefore, the quality can be further improved.

[0103] Will refer to Fig.19 and Fig. 20 A method for manufacturing the image pickup element 101 will be described.

[0104] In the twenty-first step, if Fig.19 As shown in the upper figure in FIG. 1 , a supporting substrate 105 is prepared.

[0105] In the twenty-second step, if Fig.19 As shown in the middle figure in FIG, a distortion adjustment film 104 is formed on a supporting substrate 105. Examples of the film forming material of the distortion adjustment film 104 include silicon nitride (SiN), silicon oxide (SiO), silicon carbonitride (SiCN), silicon carbide (SiC), titanium nitride (TiN), and amorphous carbon. Note that the silicon-based film can be adjusted to the extension side and the contraction side depending on the film forming conditions.

[0106] In the twenty-third step, if Fig.19 As shown in the lower figure in FIG. 1 , the surface of the strain adjustment film 104 is partially etched to form the uneven surface 131. For example, the uneven surface 131 is formed in a manner to cancel the influence of the chip step according to the SFQR flatness value of the surface of the buried layer 126.

[0107] In the twenty-fourth step, if Fig. 20 As shown in the upper figure in FIG. 1 , the strain adjustment film 104 stacked on the support substrate 105 is set as a bonding surface, and bonding with the buried layer 126 on the logic chip 103 is performed. Here, the semiconductor substrate 111 of the sensor chip 102 is in a state before thinning.

[0108] In the twenty-fifth step, if Fig. 20 As shown in the lower figure in FIG. 1 , the thickness of the semiconductor substrate 111 is reduced. Thus, the imaging element 101 is manufactured.

[0109] In this manner, since the concavoconvex surface 131 is formed on the surface of the distortion adjustment film 104 according to the SFQR flatness value measured before the logic chip 103 is bonded to the support substrate 105, it is possible to suppress distortion generated in the surface of the thinned semiconductor substrate 111. Therefore, it is possible to manufacture a higher quality imaging element 101.

[0110] Will refer to Fig.21 The case where the chip step has a significant influence on the surface of the buried layer 126 will be described.

[0111] For example, when the SFQR flatness value of the surface of the buried layer 126 is large, if the strain adjustment film 104 is over-etched to form a deeper recessed portion, there is a possibility that the strain correction effect may be deteriorated.

[0112] Therefore, if Fig.21 As shown in A, a second strain adjustment film 106 having a smaller stress is additionally formed on the strain adjustment film 104 having the uneven surface 131, and the second strain adjustment film 106 is etched, so that an uneven surface 132 that is more depressed than the uneven surface 131 can be formed. Therefore, even when the chip step has a large influence on the surface of the buried layer 126, the influence of the chip step can be more reliably offset.

[0113] Or, if Fig.21 As shown in FIG. 1B , the support substrate 105 is etched in consideration of the chip size to form the concave-convex surface 133, and the distortion adjustment film 104 is formed on the concave-convex surface 133, thereby forming a more deeply recessed concave-convex surface 131. Therefore, even when the chip step has a large influence on the surface of the buried layer 126, the effect of more reliably offsetting the influence of the chip step can be obtained.

[0114] Will refer to Fig. 22 A first modification of the image pickup element 101 will be described. It should be noted that Fig. 22 The imaging element 101A shown in FIG. Fig.18Components similar to those of the imaging element 101 in FIG. 1 will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0115] like Fig. 22 As shown in the lower figure, Fig.18 Similar to the imaging element 101 in FIG. 1 , the imaging element 101A has a configuration in which a sensor chip 102 and a logic chip 103 are stacked.

[0116] On the other hand, the imaging element 101A has a structure in which a support substrate 105A is stacked on the logic chip 103, and a distortion adjustment film 104A is stacked on the surface of the support substrate 105A opposite to the bonding surface of the logic chip 103. This structure is different from Fig.18 The structure of the imaging element 101 in FIG.

[0117] That is, Fig. 22 As shown in the upper figure of FIG. 1 , when the support substrate 105A is bonded to the logic chip 103, the surface of the support substrate 105A on which the distortion adjustment film 104A is not stacked is pressed against the buried layer 126, so that the support substrate 105A is bonded to the logic chip 103. Here, pressure is applied to the concavoconvex surface 131 of the distortion adjustment film 104A. Therefore, the front surface of the distortion adjustment film 104A becomes flat, and the concavoconvex surface 131 is provided on the back surface of the distortion adjustment film 104A. Therefore, a concavoconvex surface 134 that conforms to the shape of the concavoconvex surface 131 is formed on the bonding surface of the support substrate 105A to the logic chip 103.

[0118] As described above, the concavo-convex surface 131 is formed to offset the surface concavo-convexity of the buried layer 126 , and the concavo-convex surface 134 formed on the supporting substrate 105 also has a shape to offset the surface concavo-convexity of the buried layer 126 .

[0119] Therefore, with Fig.18 Like the imaging element 101 in FIG. 1 , the imaging element 101A can suppress the occurrence of distortion in the surface of the already thinned semiconductor substrate 111. Therefore, the quality can be further improved.

[0120] That is, in Fig.18 The structure in which the distortion adjustment film 104 is formed on the bonding surface of the logic chip 103 of the support substrate 105A as in the imaging element 101 in FIG. Fig. 22 In a structure where the distortion adjustment film 104A is formed on the surface of the support substrate 105A opposite to the bonding surface with the logic chip 103, as in the imaging element 101A in FIG. 1 , the influence of the chip step on the surface of the buried layer 126 can be eliminated.

[0121] Will refer to Fig.23A second modification of the imaging element 101 will be described. It should be noted that Fig.23 The image pickup element 101B shown in FIG. Fig.18 The same components as those of the image pickup element 101 in FIG. 1 will be denoted by the same reference numerals, and detailed description thereof will be omitted.

[0122] like Fig.23 As shown in the lower figure, Fig.18 Like the imaging element 101 in , the imaging element 101B has a configuration in which a sensor chip 102 and a logic chip 103B are stacked.

[0123] On the other hand, the image pickup element 101B has a configuration in which the distortion adjustment film 127 is provided on the logic chip 103B, and the support substrate 105 is bonded to the distortion adjustment film 127. This configuration is different from Fig.18 The structure of the imaging element 101 in FIG.

[0124] That is, Fig.23 As shown in the upper figure of FIG. 1 , in the stage before bonding with the support substrate 105, the logic chip 103B has a two-layer structure in which a buried layer 126 and a distortion adjustment film 127 are provided. The buried layer 126 is provided to bury the step protruding toward the wiring layer 123. The distortion adjustment film 127 is formed on the buried layer 126. Fig.18 Like the distortion adjustment film 104 in FIG. 1 , the distortion adjustment film 127 is also provided to improve the flatness of the bonding surface of the support substrate 105 by eliminating the chip step on the surface of the buried layer 126, and to relieve the distortion (stress) after the WoW bonding. For example, the distortion adjustment film 127 may be partially etched so that the semiconductor substrate 111 is flat after being thinned.

[0125] Then, the buried layer 126 and the distortion adjustment film 127 include film types and film properties having respective characteristics suitable for respective uses. Examples of the film forming material of the distortion adjustment film 104 include silicon nitride (SiN), silicon oxide (SiO), silicon carbonitride (SiCN), silicon carbide (SiC), titanium nitride (TiN), and amorphous carbon. Note that the silicon-based film can be adjusted to the extension side and the contraction side depending on the film forming conditions.

[0126] and Fig.18 Like the imaging element 101 in FIG. 1 , the imaging element 101B having such a structure can also suppress the generation of distortion in the surface of the already thinned semiconductor substrate 111. Therefore, the quality can be further improved.

[0127] Note that in the present embodiment, a configuration example in which the high stress film 15 is provided in the sensor chip 14 has been described, but for example, in order to alleviate the distortion of the device pattern of the logic chip 12, the high stress film 15 may also be provided in the logic chip 12. Needless to say, the high stress film 15 may be provided in both the logic chip 12 and the sensor chip 14.

[0128] In addition, the present technology is not limited to the image pickup element 11, and is also applicable to various semiconductor devices manufactured by CoW bonding. With the present technology, the quality of these semiconductor devices can be improved.

[0129] Note that the various techniques described herein can be implemented independently and separately, as long as no contradiction occurs. Needless to say, the various techniques can also be optionally combined and implemented. For example, part or all of the techniques described in any embodiment can be implemented by combining with part or all of the techniques described in another embodiment. In addition, part or all of any of the aforementioned techniques can be implemented by combining with any other techniques not described herein.

[0130] <Structure Example of Electronic Equipment> For example, the above-described imaging element 11 is applicable to various electronic devices, examples of which include: imaging systems such as digital cameras and digital video cameras; mobile phones equipped with an imaging function; and any other devices equipped with an imaging function.

[0131] Fig.24 : is a block diagram showing a configuration example of an imaging device installed in an electronic device.

[0132] like Fig.24 As shown, the imaging device 101 includes an optical system 102, an imaging element 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and videos.

[0133] The optical system 102 includes one or more lenses, and guides image light (incident light) from a subject toward the imaging element 103 , and forms an image on a light receiving surface (sensor portion) of the imaging element 103 .

[0134] The imaging element 11 is used as the imaging element 103. In the imaging element 103, electrons are accumulated for a certain period of time according to the imaging on the light receiving surface via the optical system 102. Then, a signal corresponding to the electrons accumulated in the imaging element 103 is supplied to the signal processing circuit 104.

[0135] The signal processing circuit 104 performs various signal processing on the pixel signal output from the imaging element 103. The image (image data) generated by the signal processing performed by the signal processing circuit 104 is supplied to the monitor 105 to be displayed on the monitor, or supplied to the memory 106 to be stored (recorded) therein.

[0136] For example, when the above-described image pickup element 11 is applied to the image pickup device 101 having the above-described configuration, a picture with higher image quality can be obtained.

[0137] <Examples of using image sensors> Fig.25 This is a diagram showing an example of use of the above-mentioned image sensor (imaging element).

[0138] The above-mentioned image sensor may be used in various situations of sensing visible light, infrared light, ultraviolet light, X-rays, etc. as described below.

[0139] - Equipment used to capture images for viewing, such as digital cameras or portable devices with camera functions - Equipment for traffic, such as on-board cameras that capture images of the front, rear, surroundings, and interior of a car, surveillance cameras that monitor moving vehicles and roads, and distance-measuring sensors that measure the distance between vehicles, etc., in order to achieve safe driving such as automatic parking or recognize the driver's status - Devices for home appliances, such as televisions, refrigerators, or air conditioners, that capture user gestures and operate the device based on the gestures - Equipment used in medical care, such as endoscopes or equipment for angiography by receiving infrared light, etc. - Equipment used for security, such as surveillance cameras for crime prevention or cameras for personal identification, etc. - Equipment used for beauty treatments, such as skin measurement equipment for photographing the skin or microscopes for photographing the scalp, etc. - Equipment for sports, such as action cameras or wearable cameras for sports use, etc. -Equipment used in agriculture, such as cameras that monitor the status of fields and crops

[0140] <Combination example> It should be noted that the present technology can also have the following technical solutions. (1) Semiconductor devices, including: a first semiconductor chip; A second semiconductor chip bonded to the first semiconductor chip by CoW (Chip On Wafer) bonding; and A high stress film generates stress to offset stress that would be generated in the first semiconductor chip or the second semiconductor chip during CoW bonding. (2) The semiconductor device according to (1) above, wherein: The high stress film is provided in an arrangement pattern having high density in regions near four corners of the first semiconductor chip or the second semiconductor chip and having low density in a region near the center of the first semiconductor chip or the second semiconductor chip. (3) The semiconductor device according to (1) or (2) above, wherein: The high stress film is provided in a layout pattern that is bilaterally symmetrical and vertically symmetrical with respect to a rectangular shape of the first semiconductor chip or the second semiconductor chip. (4) The semiconductor device according to any one of (1) to (3) above, wherein: When contraction stress is applied to the first semiconductor chip during the CoW bonding period, the high stress film provided on the first semiconductor chip generates stress that stretches the first semiconductor chip. (5) The semiconductor device according to any one of (1) to (4) above, wherein: The high stress film is provided on the inner part or the outermost surface of a wiring layer which is the second semiconductor chip bonding surface side of the first semiconductor chip. (6) The semiconductor device according to (5) above, wherein: A portion and another portion of the high stress film are provided in different layers inside the wiring layer. (7) The semiconductor device according to any one of (1) to (6) above, wherein: In the case where the first semiconductor chip and the second semiconductor chip have the same chip size, the high stress film having the same size as the first semiconductor chip and the second semiconductor chip is provided. (8) The semiconductor device according to any one of (1) to (6) above, wherein: In the case of performing CoW bonding of the second semiconductor chip with the first semiconductor chip having a chip size larger than that of the second semiconductor chip, the high stress film is provided on the first semiconductor chip over a larger range than that of the second semiconductor chip. (9) The semiconductor device according to any one of (1) to (6) above, wherein: In the case where CoW bonding of a plurality of the second semiconductor chips to the first semiconductor chip is performed, the high stress film is provided on the first semiconductor chip in a larger range than that of each of the second semiconductor chips. (10) The semiconductor device according to any one of (1) to (9) above, wherein: The high stress film is provided so as to cover the second semiconductor chip after the CoW bonding of the second semiconductor chip and the first semiconductor chip. (11) The semiconductor device according to any one of (1) to (10) above, wherein: The high stress film includes at least two materials. (12) The semiconductor device according to (11) above, wherein: The high stress film is formed of a material having a relatively strong force for offsetting the stress in a region where the first semiconductor chip or the second semiconductor chip is subjected to a large stress caused by the CoW bonding and shrinking. For a region where the stress that would be generated by CoW bonding and cause the first semiconductor chip or the second semiconductor chip to shrink is small, the high stress film is formed using a material having a relatively weak force for counteracting the stress. (13) The semiconductor device according to (11) or (12) above, wherein: In the region to which stress is applied during CoW bonding, a void for releasing the contraction stress generated after CoW bonding is provided instead of the high stress film. (14) The semiconductor device according to any one of (11) to (13) above, wherein: The high stress film is provided in both the first semiconductor chip and the second semiconductor chip. (15) A method for manufacturing a semiconductor device, comprising: A high stress film is formed which generates stress to offset stress generated in the first semiconductor chip or the second semiconductor chip during CoW (Chip On Wafer) bonding when attaching the second semiconductor chip to the first semiconductor chip. (16) Electronic equipment, including: A semiconductor device comprising: a first semiconductor chip; A second semiconductor chip bonded to the first semiconductor chip by CoW (Chip On Wafer) bonding; and A high stress film generates stress to offset stress that would be generated in the first semiconductor chip or the second semiconductor chip during CoW bonding. (17) Semiconductor devices, including: a first semiconductor chip; a second semiconductor chip bonded to the first semiconductor chip by CoW (chip on wafer) bonding; a distortion adjustment film that suppresses the influence of unevenness of the surface of the second semiconductor chip on the side opposite to the bonding surface of the first semiconductor chip; and A support substrate supports the first semiconductor chip and the second semiconductor chip. (18) The semiconductor device according to (17) above, wherein: The strain adjustment film is provided with an uneven surface that cancels unevenness of the surface according to a SFQR (Site Front leasts Quare Range) value of the surface of the second semiconductor chip located on the side opposite to the bonding surface of the first semiconductor chip. (19) The semiconductor device according to (17) or (18) above, wherein: The distortion adjustment film is formed on the second semiconductor chip bonding surface of the support substrate or on a surface of the support substrate on the opposite side to the second semiconductor chip bonding surface. (20) The semiconductor device according to (17) or (18) above, wherein: The distortion adjustment film is formed so as to improve the flatness of the support substrate bonding surface of the second semiconductor chip with respect to a buried layer for burying a chip step provided inside the second semiconductor chip.

[0141] It should be noted that the embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications can be made within the scope of the gist of the present disclosure. In addition, the effects described in this specification are only examples and are not restrictive, but any other effects can also be provided. [reference numerals list]

[0142] 11: Camera element 12: Logic chip 13: Semiconductor wafer 14: Sensor chip 15: High stress film 16: Insulation film 21: Semiconductor substrate 22: Wiring layer 31: Interlayer insulation film 32: Wiring 33: Bonding pad

Claims

1. Semiconductor devices, include: a first semiconductor chip; a second semiconductor chip bonded to the first semiconductor chip by CoW (chip on wafer) bonding; and A high stress film generates stress to offset stress that would be generated in the first semiconductor chip or the second semiconductor chip during CoW bonding.

2. The semiconductor device according to claim 1, in, The high stress film is provided in an arrangement pattern having high density in regions near four corners of the first semiconductor chip or the second semiconductor chip and having low density in a region near the center of the first semiconductor chip or the second semiconductor chip.

3. The semiconductor device according to claim 1, in, The high stress film is provided in a layout pattern that is bilaterally symmetrical and vertically symmetrical with respect to a rectangular shape of the first semiconductor chip or the second semiconductor chip.

4. The semiconductor device according to claim 1, in, When contraction stress is applied to the first semiconductor chip during the CoW bonding period, the high stress film provided on the first semiconductor chip generates stress that stretches the first semiconductor chip.

5. The semiconductor device according to claim 1, in, The high stress film is provided on the inner part or the outermost surface of a wiring layer which is the second semiconductor chip bonding surface side of the first semiconductor chip.

6. The semiconductor device according to claim 5, in, A portion and another portion of the high stress film are provided in different layers inside the wiring layer.

7. The semiconductor device according to claim 1, in, In the case where the first semiconductor chip and the second semiconductor chip have the same chip size, the high stress film having the same size as the first semiconductor chip and the second semiconductor chip is provided.

8. The semiconductor device according to claim 1, in, In the case of performing CoW bonding of the second semiconductor chip with the first semiconductor chip having a chip size larger than that of the second semiconductor chip, the high stress film is provided on the first semiconductor chip over a larger range than that of the second semiconductor chip.

9. The semiconductor device according to claim 1, in, In the case where CoW bonding of a plurality of the second semiconductor chips to the first semiconductor chip is performed, the high stress film is provided on the first semiconductor chip in a larger range than that of each of the second semiconductor chips.

10. The semiconductor device according to claim 1, in, The high stress film is provided so as to cover the second semiconductor chip after the CoW bonding of the second semiconductor chip and the first semiconductor chip.

11. The semiconductor device according to claim 1, in, The high stress film includes at least two materials.

12. The semiconductor device according to claim 11, in, The high stress film is formed of a material having a relatively strong force for offsetting the stress in a region where the first semiconductor chip or the second semiconductor chip is subjected to a large stress caused by the CoW bonding and shrinking. For a region where the stress that would be generated by CoW bonding and cause the first semiconductor chip or the second semiconductor chip to shrink is small, the high stress film is formed using a material having a relatively weak force for counteracting the stress.

13. The semiconductor device according to claim 11, in, In a region to which stress is applied during CoW bonding, a void for releasing the contraction stress generated after CoW bonding is provided instead of the high stress film.

14. The semiconductor device according to claim 11, in, The high stress film is provided in both the first semiconductor chip and the second semiconductor chip.

15. Semiconductor device manufacturing method, include: A high stress film is formed that generates stress to offset stress that would be generated in the first semiconductor chip or the second semiconductor chip during CoW (chip on wafer) bonding when attaching the second semiconductor chip to the first semiconductor chip.

16. Electronic equipment, include: A semiconductor device comprising: a first semiconductor chip; A second semiconductor chip bonded to the first semiconductor chip by CoW (Chip On Wafer) bonding; and A high stress film generates stress to offset stress that would be generated in the first semiconductor chip or the second semiconductor chip during CoW bonding.

17. Semiconductor devices, include: a first semiconductor chip; a second semiconductor chip bonded to the first semiconductor chip by CoW (chip on wafer) bonding; a distortion adjustment film that suppresses the influence of unevenness of the surface of the second semiconductor chip on the side opposite to the bonding surface of the first semiconductor chip; as well as A support substrate supports the first semiconductor chip and the second semiconductor chip.

18. The semiconductor device according to claim 17, in, The distortion adjustment film is provided with an uneven surface that cancels unevenness of the surface according to a SFQR (Site Front leasts Quare Range) value of the surface of the second semiconductor chip located on the side opposite to the bonding surface of the first semiconductor chip.

19. The semiconductor device according to claim 17, in, The distortion adjustment film is formed on the second semiconductor chip bonding surface of the support substrate or on a surface of the support substrate on the opposite side to the second semiconductor chip bonding surface.

20. The semiconductor device according to claim 17, in, The distortion adjustment film is formed so as to improve the flatness of the support substrate bonding surface of the second semiconductor chip with respect to a buried layer for burying a chip step provided inside the second semiconductor chip.

Images