Monolithic integrated silicon optical device structure and manufacturing method thereof
By integrating electrical devices and optical devices on the same silicon substrate, the process problem of monolithic integrated silicon optical receiving chips in the prior art is solved, and low-cost and high-performance silicon optical device integration is achieved.
Patent Information
- Application Number
- CN202311596997.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-27
- Publication Date
- 2025-06-10
AI Technical Summary
The prior art is difficult to realize a monolithic integrated silicon optical receiving chip, resulting in parasitic effects at the photoelectric interface, high power consumption, complex process and high cost.
The interconnection of the photodetection device and the electrical device is achieved by integrating electrical devices and optical devices on the same silicon substrate, using the CMOS process to define the active region and forming passive devices outside the active region, such as end-face coupling trenches and optical waveguides.
Reduces process complexity and cost, reduces power consumption, improves bandwidth and product performance, and realizes interconnection on the same substrate of the optoelectronic structure.
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Figure CN120122274A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuit processes, and particularly to a monolithic integrated silicon optical device structure and a manufacturing method thereof. Background Art
[0002] Silicon-based optoelectronic processes focus on nanoscale optoelectronic devices. By leveraging the CMOS process platform and using an SOI substrate, the conversion and processing of optical and electrical signals are achieved on the same chip, which has excellent performance such as high bandwidth, low power consumption, anti-interference, and high reliability. Currently, it has been applied in many fields such as data centers, quantum computing, lidar, and biosensing, and has broad development prospects.
[0003] Silicon optical devices usually include passive devices and active devices. Passive devices are used for processing optical signals, and active devices are used for converting optical and electrical signals. According to different devices, silicon optical chips can be divided into optical emission chips, optical reception chips, optical emission and reception integrated chips, etc. Among them, the main optical device included in the optical emission chip is an optical modulator, which is used to convert an electrical signal into an optical signal and then introduce it into the optical fiber for transmission; the main optical device included in the optical reception chip is an optical receiver, which is used to convert the optical signal introduced by the optical fiber into an electrical signal.
[0004] The optical reception chip involves both the optical device (chip) part and the electrical device (chip) part. In the current mainstream process, due to process differences, optical chips and electrical chips usually need to be separately manufactured on different process platforms and then form signal connections through packaging methods. In this solution, due to the limitations of packaging technology for signal wiring, the following impacts on product performance will occur: 1) There are significant parasitic effects at the optoelectronic interface, affecting performance; 2) The overly long optoelectronic wiring increases the product power consumption; 3) The optoelectronic packaging process is relatively complex, increasing costs.
[0005] Therefore, monolithic optoelectronic integrated structures have also been widely studied. In this solution, optical chips and electrical chips are completed on the same process platform. Since the mainstream silicon optical process relies on SOI wafers and the requirements for the top silicon and buried oxide layer thickness in it are different from those in general CMOS processes, the current monolithic integration ideas are mainly divided into the following two types: one is to conduct research and development on silicon optical device processes based on the existing SOI CMOS process; the other is to conduct research and development on CMOS device processes based on the existing SOI silicon optical platform process. However, as mentioned above, even on the SOI process platform, the requirements of CMOS processes and silicon optical device processes for substrates, manufacturing processes, etc. are quite different, making it very difficult to develop the process of monolithic integrated optical reception chips, that is, to simultaneously perform the processes of optical devices and electrical devices on a single silicon wafer. Summary of the Invention
[0006] The object of the present invention is to overcome the above-mentioned defects existing in the prior art, and to provide a monolithic integrated silicon optical device structure and a manufacturing method thereof.
[0007] To achieve the above object, the technical solution of the present invention is as follows:
[0008] The present invention provides a monolithic integrated silicon optical device structure, including:
[0009] An electrical device and an optical device disposed on the first surface of a substrate;
[0010] The optical device includes an active device and a passive device. The active device is connected to the substrate. The passive device includes a first passive device and a second passive device. The first passive device is located in the substrate below the first surface. The second passive device is plural, and each of the second passive devices is isolated above the first surface, and one of the second passive devices is located above the first passive device.
[0011] Further, the electrical device and the active device are located in the active region on the substrate, and the passive device is located on the substrate outside the active region.
[0012] Further, the electrical device includes a transistor, and / or, the active device includes a photodetector device.
[0013] Further, the photodetector device includes an intrinsic absorption layer located above the first surface and heterogeneous with the substrate, and a contact region disposed on the top of the intrinsic absorption layer facing away from the first surface. The photodetector device is led out through the contact region to be interconnected with the electrical device; or, the photodetector device includes an intrinsic absorption layer located above the first surface and heterogeneous with the substrate, and a contact region located below the first surface and connected to the intrinsic absorption layer. The photodetector device is led out through the contact region to be interconnected with the electrical device.
[0014] Further, the first passive device includes an end-face coupling trench filled with a first dielectric. The second passive device includes an end-face coupler located above and aligned with the end-face coupling trench, and at least one optical waveguide. The end-face coupler and the optical waveguide are also isolated above the first surface by the first dielectric.
[0015] Further, the second passive device is heterogeneous with the substrate.
[0016] The present invention also provides a manufacturing method of a monolithic integrated silicon optical device structure, including:
[0017] Providing a substrate;
[0018] Form electrical devices and optical devices on a first surface of the substrate, such that the formed optical devices include active devices and passive devices, the active devices are connected to the substrate, the passive devices include a first passive device and a second passive device, the first passive device is in the substrate below the first surface, the second passive devices are multiple, each of the second passive devices is isolated above the first surface, and one of the second passive devices is above the first passive device.
[0019] Further, forming the electrical devices and optical devices on the first surface of the substrate specifically includes:
[0020] Adopt a CMOS process to define an active region on the first surface of the substrate, form a first doping region and a second doping region below the first surface of the active region, and form a transistor as an electrical device on the first surface corresponding to the first doping region;
[0021] Form a trench in the substrate below the first surface outside the active region;
[0022] Form a first dielectric layer on the first surface and fill the trench to form an end-face coupling trench as a passive device and as the first passive device in the substrate below the first surface;
[0023] Form an end-face coupler as a passive device and as one of the second passive devices and at least one optical waveguide on the surface of the first dielectric layer outside the active region, such that the end-face coupler and the optical waveguide are isolated above the first surface through the first dielectric layer, and the end-face coupler is above and aligned with the end-face coupling trench;
[0024] Form a second dielectric layer on the surface of the first dielectric layer to cover the end-face coupler and the optical waveguide;
[0025] Form a window communicating with the second doping region on the surface of the second dielectric layer, and form a photodetector device as an active device in the window, thereby forming an optical device including the active device and the passive device.
[0026] Further, forming the photodetector device as an active device in the window specifically includes:
[0027] Form an intrinsic absorption layer heterogeneous with the substrate in the window;
[0028] A third doped region serving as a contact region is formed on top of the intrinsic absorption layer, thereby forming a photodetector device serving as an active device in the window, which is composed of the second doped region, the intrinsic absorption layer, and the third doped region;
[0029] And a metal interconnection layer is formed on the surface of the second dielectric layer, and contact holes connected to the metal interconnection layer are respectively formed on the contact region and the first doped region, so that the photodetector device is interconnected with the electrical device.
[0030] Further, forming the photodetector device serving as an active device in the window specifically includes:
[0031] An intrinsic absorption layer heterogeneous with the substrate is formed in the window, thereby forming a photodetector device serving as an active device in the window, which is composed of the second doped region and the intrinsic absorption layer;
[0032] And a metal interconnection layer is formed on the surface of the second dielectric layer, and contact holes connected to the metal interconnection layer are simultaneously formed on the second doped region and the first doped region, so that the photodetector device is interconnected with the electrical device.
[0033] It can be seen from the above technical solutions that the present invention integrates the electrical device and the optical device in the silicon photonic device structure on the same substrate. Compared with the traditional method of using SOI optical wafers and Si electrical wafers and encapsulating them, the cost is greatly reduced, and the process complexity is also reduced synchronously, thereby reducing the process risk, and the photoelectric structure can be interconnected on the same substrate. Therefore, the power consumption can be reduced, the bandwidth can be increased, and the product performance can be significantly improved. At the same time, compared with the current mainstream monolithic electrical chip and optical chip integration process, the present invention also has the following obvious advantages:
[0034] (1) It is basically unnecessary to adjust the CMOS process to realize the integration of electrical devices and optical devices on a monolithic substrate.
[0035] (2) Passive devices such as end face couplers and optical waveguides in the optical device are made of materials heterogeneous with the substrate (for example, high-quality SiN process can be used to make silicon photonic passive devices). While meeting the performance requirements, it also gets rid of the limitations of SOI wafers. And, an end face coupling trench is formed on the substrate by using a trench and dielectric filling method, which can effectively avoid the problem of optical signal transmission loss in the optical device.
[0036] (3) Active devices such as photodetector devices in the optical device are made of materials heterogeneous with the substrate on the substrate (for example, a germanium photodetector (GEPD) solution can be used to make the photodetector device). While not affecting the performance, it also achieves the effect of being fully compatible with the CMOS process. Brief Description of the Drawings
[0037] Figures 1-2 Schematic diagram of a monolithic integrated silicon photonic device structure according to a preferred embodiment of the present invention;
[0038] Figures 3-8 Process flow chart of a method for fabricating a monolithic integrated silicon photonic device structure according to a preferred embodiment of the present invention. Detailed Description of the Embodiments
[0039] In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items.
[0040] The following will further elaborate on the specific embodiments of the present invention with reference to the accompanying drawings.
[0041] Reference Figure 1 A monolithic integrated silicon photonic device structure of the present invention includes: an electrical device and an optical device of a silicon photonic device (chip) disposed on a substrate 100.
[0042] Among them, the substrate 100 may be a conventional semiconductor substrate 100. For example, the substrate 100 may be a silicon substrate 100, but is not limited thereto. And, the substrate 100 is a monolithic substrate 100, such as a monolithic silicon wafer substrate 100, to be distinguished from the conventional SOI substrate used to form silicon photonic devices. However, the substrate 100 of the present invention may be formed using the top silicon or bottom silicon of a conventional SOI substrate. In this case, the electrical device and the optical device will be all integrated on the same exposed surface of the top silicon or bottom silicon of the conventional SOI substrate 100.
[0043] Reference Figure 1 The electrical device and the optical device are disposed on the first surface (shown as the upper surface) of the substrate 100 in a monolithic integrated manner.
[0044] An electrical device (chip) area and an optical device (chip) area may be defined on the first surface of the substrate 100. The electrical device is disposed in the electrical device (chip) area, and the optical device is disposed in the optical device (chip) area.
[0045] The optical device includes an active device (such as the photodetector device 1051) and passive devices (such as the end-face coupling trench 101, the end-face coupler 103, and the optical waveguide 104). Among them, the active device is connected to the substrate 100. The passive devices further include a first passive device (such as the end-face coupling trench 101) and a second passive device (such as the end-face coupler 103 and the optical waveguide 104). The first passive device is located in the substrate 100 below the first surface; the second passive devices are multiple, each second passive device is isolated above the first surface, and one of the multiple second passive devices is located above the first passive device.
[0046] An active region is provided on the substrate 100, and the range of the active region can be defined by the shallow trench isolation 109. The electrical device region is located in the active region; and both the electrical devices in the electrical device region and the active devices in the optical devices in the optical device region are located in the active region and can be separated by the shallow trench isolation 109. The passive devices in the optical device are located on the substrate 100 outside the active region.
[0047] In some embodiments, the electrical devices of the silicon photonics device include transistors 108, and transimpedance amplifiers (TIAs), clock and data recovery circuits (CDRs), etc. can be formed by using these transistors 108 and the like.
[0048] In some embodiments, the active device in the optical device of the silicon photonics device includes the photodetector device 1051.
[0049] In some embodiments, the photodetector device 1051 includes an intrinsic absorption layer 105 located above the first surface of the substrate 100 and heterogeneous with the substrate 100 material, and a top contact region 1052 provided on the top of the intrinsic absorption layer 105 facing away from the first surface. For example, when the substrate 100 material is a silicon substrate 100, the intrinsic absorption layer 105 material can be germanium, so that a germanium photodetector device 1051 (Ge PD) can be formed.
[0050] Reference Figure 1 In some embodiments, the first passive device in the optical device includes an end-face coupling trench 101 filled with a first dielectric; the second passive device includes an end-face coupler 103 located above the end-face coupling trench 101 and vertically aligned with the end-face coupling trench 101, and at least one optical waveguide 104.
[0051] A first dielectric is also provided on the first surface of the substrate 100. The first dielectric on the first surface of the substrate 100 and the first dielectric in the end-face coupling trench 101 can be two closely contacting layer structures, or can be formed into an integral structure by the same layer structure. The end-face coupler 103 and the optical waveguide 104 are isolated above the first surface by the first dielectric. The first dielectric can extend to cover the first surface of the substrate 100 covering the active region and cover the top of the electrical device to form the first dielectric layer 102 (refer to Figure 4 the first dielectric layer 102). Alternatively, the first dielectric can be connected to other dielectrics covering the top of the electrical device on the first surface of the substrate 100 covering the active region.
[0052] In some embodiments, the second passive device material is a material heterogeneous to the substrate 100. For example, when the substrate 100 material is a silicon substrate 100, the second passive device material can be silicon nitride, so that a silicon nitride end-face coupler 103 and a silicon nitride optical waveguide 104 can be formed.
[0053] In some embodiments, the second passive device material can also be a material homogeneous to the substrate 100.
[0054] In some embodiments, the second passive devices (such as the end-face coupler 103 and the optical waveguide 104) can also be formed of materials heterogeneous to each other
[0055] In some embodiments, the optical waveguide 104 can be disposed on the same layer as the end-face coupler 103.
[0056] In some embodiments, the optical waveguide 104 can be disposed on a different layer from the end-face coupler 103.
[0057] In some embodiments, when multiple optical waveguides 104 are provided, among the multiple optical waveguides 104, there are both optical waveguides 104 disposed on the same layer as the end-face coupler 103 and optical waveguides 104 disposed on a different layer from the end-face coupler 103.
[0058] In some embodiments, the optical waveguide 104 can be at least one of a strip waveguide, a ridge waveguide, a parallel waveguide, a gate waveguide, a slot waveguide, a window waveguide, etc.
[0059] Reference Figure 1。In some embodiments, the optoelectronic detection device 1051 is led out through the top contact region 1052 to form an interconnection with the electrical device. For example, on the first surface of the substrate 100, one or more interlayer dielectric layers 200 including a first dielectric (and other dielectrics) are provided to cover the optical waveguide 104, the end face coupler 103, the optoelectronic detection device 1051, and the electrical device. And, a metal interconnection layer 106 is provided in the interlayer dielectric layer 200; the optoelectronic detection device 1051 is connected to the metal interconnection layer 106 through a first contact hole 1071 provided on the top contact region 1052, and each transistor 108 is connected to the metal interconnection layer 106 through a second contact hole 1072 provided on the first surface of the substrate 100 and connected to its source / drain 1081, thereby realizing the interconnection between the optoelectronic detection device 1051 and the electrical device.
[0060] Reference Figure 2 。In some embodiments, the above-mentioned top contact region 1052 located on the top of the intrinsic absorption layer 105 can also be moved below the first surface of the substrate 100 and connected to the bottom of the intrinsic absorption layer 105 to form a bottom contact region 1053. The optoelectronic detection device 1051 and each transistor 108 are respectively connected to the metal interconnection layer 106 through third contact holes 1073 corresponding to the bottom contact region 1053 and the source / drain 1081, thereby realizing the interconnection between the optoelectronic detection device 1051 and the electrical device.
[0061] The above-mentioned monolithic integrated silicon photonic device structure of the present invention can be a silicon photonic optical receiver chip (device) structure.
[0062] The following further details the manufacturing method of the monolithic integrated silicon photonic device structure of the present invention through specific embodiments and in combination with the drawings.
[0063] Reference Figures 3-7 。The manufacturing method of the monolithic integrated silicon photonic device structure of the present invention can be used to manufacture, for example Figure 1 a monolithic integrated silicon photonic device structure as shown, and may include the following steps:
[0064] Provide a substrate 100;
[0065] Form electrical devices and optical devices on the first surface of the substrate 100, so that the formed optical devices include active devices and passive devices. The active devices are connected to the substrate 100. The passive devices include a first passive device and a second passive device. The first passive device is in the substrate 100 below the first surface. The second passive devices are multiple, each second passive device is isolated above the first surface, and one of the second passive devices is above the first passive device.
[0066] The above steps specifically include the following steps:
[0067] Step S1: Using the CMOS process, define an active region on the first surface of the substrate 100, form a first doped region 110 and a second doped region 111 below the first surface of the active region, and form a transistor 108 as an electrical device on the first surface corresponding to the first doped region 110.
[0068] As Figure 3 shown, a monocrystalline silicon wafer substrate 100 suitable for performing the CMOS process is used to integrate the silicon optical device structure of the present invention.
[0069] First, perform the related processes of conventional CMOS devices on the silicon substrate 100. Specifically, it includes:
[0070] Define an active region on the first surface (upper surface) of the silicon substrate 100. Perform the related processes of the shallow trench isolation (STI) process on the silicon substrate 100 layer of the active region to form a shallow trench isolation 109 structure.
[0071] Perform well implantation patterning and ion implantation processes in the designated area of the active region to form a first doped region 110 and a second doped region 111 below the first surface of the silicon substrate 100 in the active region.
[0072] Perform a gate oxide layer process on the first surface of the silicon substrate 100 corresponding to the first doped region 110 to form a gate oxide. Perform the related processes of the gate process to form, for example, a polysilicon gate 1082 and its sidewall structure. Perform the related implantation processes of the post-gate 1082 process to form the source-drain 1081, lightly doped drain (LDD), and other structures required for a conventional MOS transistor. A transistor in the form of a back-gate structure can also be formed.
[0073] The above steps are all conventional CMOS processes, and a transistor 108 as an electrical device can be formed on the first surface of the silicon substrate 100 corresponding to the first doped region 110. At the same time, during the ion implantation process, the ion implantation required for the active device (photoelectric detection device 1051) in the optical device is also synchronously completed in the second doped region 111.
[0074] Step S2: Form a trench 1011 in the substrate 100 below the first surface outside the active region.
[0075] As Figure 4 shown, using the deep trench process, form a deep trench 1011 in the silicon substrate 100 below the first surface outside the active region. The deep trench 1011 is used to form an end-face coupling trench 101 as the first passive device in the optical device. By performing the deep trench process in the end-face coupler 103 region, the signal loss during fiber optic signal coupling can be reduced. This step specifically includes:
[0076] In a specific area corresponding to the position of the end face coupler, a photolithography and etching process is carried out to etch a deep trench 1011 structure in the silicon substrate 100. Among them, the depth of the deep trench 1011 is preferably greater than 3 μm, and the width of the deep trench 1011 needs to be greater than the conventional optical fiber optical mode size, such as greater than 6 μm.
[0077] Step S3: Form a first dielectric layer 102 on the first surface and fill the trench 1011 to form an end face coupling trench 101 that serves as a passive device and as the first passive device in the substrate 100 below the first surface.
[0078] As Figure 4 shown, using a dielectric deposition process, a first dielectric layer 102 is formed on the first surface of the silicon substrate 100, and the deep trench 1011 is filled with the material of the first dielectric layer 102 (the first dielectric), so as to form an end face coupling trench 101 that serves as the first passive device in the silicon substrate 100 below the first surface. The material of the first dielectric layer 102 is usually SiO 2 . A planarization process is performed on the surface of the filled first dielectric layer 102 to make the surface flat. The thickness of the first dielectric layer 102 needs to meet the requirements of the optical waveguide 104 device, such as greater than 1 μm, so that the silicon material of the silicon substrate 100 will not affect the optical device.
[0079] Step S4: Form an end face coupler 103 and at least one optical waveguide 104 that serve as passive devices and as the second passive device on the surface of the first dielectric layer 102 outside the active region, so that the end face coupler 103 and the optical waveguide 104 are isolated above the first surface through the first dielectric layer 102, and the end face coupler 103 is located above the end face coupling trench 101 and is aligned.
[0080] As Figure 5 shown, using a dielectric deposition process, a functional layer for fabricating the end face coupler 103 and the optical waveguide 104 is formed on the surface of the first dielectric layer 102. Taking the formation of the end face coupler 103 and the optical waveguide 104 made of silicon nitride material as an example, a silicon nitride functional layer can be formed on the surface of the first dielectric layer 102.
[0081] On the silicon substrate 100 formed with the silicon nitride functional layer, relevant processes of silicon nitride optical passive devices are carried out. Specifically include:
[0082] A photolithography process and a silicon nitride etching process are performed on the silicon nitride functional layer to form a second passive device morphology, such as an end coupler 103, an optical waveguide 104 (the figure shows an end coupler 103 and an optical waveguide 104 formed as an example). As required, etching steps can be added when etching silicon nitride to form a variety of optical passive devices. Among them, it is necessary to make the formed end coupler 103 located above the vertical position of the end coupling groove 101 and surrounded by the projection area of the end coupling groove 101.
[0083] Step S5 : forming a second dielectric layer 201 on the surface of the first dielectric layer 102 to cover the end face coupler 103 and the optical waveguide 104 .
[0084] like Figure 5 As shown, a second dielectric layer 201 is formed on the surface of the first dielectric layer 102 by using a dielectric deposition process, and covers the end face coupler 103 and the optical waveguide 104 .
[0085] Step S6: forming a window connected to the second doping region 111 on the surface of the second dielectric layer 201, and forming a photoelectric detection device 1051 as an active device in the window, thereby forming an optical device including an active device and a passive device.
[0086] On the silicon substrate 100 after the above steps, processes such as germanium photodetector (Ge PD) are performed. Specifically, the processes include:
[0087] like Figure 6 As shown, photolithography, dielectric etching and other processes are performed on the second dielectric layer 201 to open the germanium epitaxial window and expose the first surface of the silicon substrate 100, so that the bottom of the window is connected to the second doped region 111 located on the silicon substrate 100.
[0088] The germanium intrinsic absorption layer 105 is epitaxially grown in the window on the silicon substrate 100. After the epitaxial germanium intrinsic absorption layer 105 is formed, a germanium intrinsic absorption layer 105 structure whose top surface is flush with the surface of the second dielectric layer 201 is formed in the window through processes such as planarization.
[0089] Then, a dielectric deposition process is adopted to form a third dielectric layer 202 on the surface of the second dielectric layer 201 to protect the top surface of the germanium intrinsic absorption layer 105 .
[0090] like Figure 7As shown, an ion implantation process is used to form a third doped region as the top contact region 1052 on the top of the germanium intrinsic absorption layer 105. Thus, a germanium photodetector device 1051 serving as an active device is formed in the window, which is composed of the second doped region 111, the germanium intrinsic absorption layer 105, and the top contact region 1052. In this way, an optical device including an active device (germanium photodetector device 1051) and passive devices (end-face coupling trench 101, end-face coupler 103, and optical waveguide 104), as well as an electrical device including a transistor 108, are integrated on a monolithic silicon substrate 100.
[0091] Then, a dielectric deposition process is used to form a fourth dielectric layer 203 on the surface of the third dielectric layer 202 to cover the optical device and the electrical device.
[0092] On the surface of the fourth dielectric layer 203, a contact hole patterning and metal filling process is used to form a first contact hole 1071 on the top contact region 1052 of the germanium photodetector device 1051. Then, using the same process, a second contact hole 1072 of the MOS device is formed on the source / drain 1081 of the transistor 108.
[0093] Next, a dielectric deposition process is used to form a fifth dielectric layer 204 on the surface of the fourth dielectric layer 203, and a metal interconnect layer 106 structure connecting the first contact hole 1071 and the second contact hole 1072 is formed on the fifth dielectric layer 204 using the conventional back-end metal process of CMOS. Thus, the photodetector device 1051 is interconnected with the electrical device through the first contact hole 1071, the metal interconnect layer 106, and the second contact hole 1072.
[0094] The advantage of this embodiment is that the third dielectric layer 202 and the fourth dielectric layer 203 that need to be etched when fabricating the first contact hole 1071 are relatively thin, and the electric field distribution of the silicon optical device formed in this way is more matched with the optical mode, which can improve performance such as responsivity and response speed. However, the possible disadvantage is that when forming the first contact hole 1071, damage is likely to occur on the germanium layer, which will increase the dark current.
[0095] The above first dielectric layer 102 to fifth dielectric layer 204 together form, for example, Figure 1 the interlayer dielectric layer 200 in
[0096] Refer to Figures 3-6 and Figure 8 , which is used to reflect another implementation manner of a method for fabricating a monolithic integrated silicon optical device structure of the present invention, and can be used to fabricate, for example, Figure 2 a monolithic integrated silicon optical device structure shown in Figure 1A method for a monolithic integrated silicon photonics device structure only differs in the step of forming the germanium photodetector device 1051 as the active device, so the previous steps will not be elaborated here. Among them, the different steps of forming the germanium photodetector device 1051 as the active device specifically include:
[0097] As Figure 8 shown, a germanium intrinsic absorption layer 105 heteroepitaxial with the silicon substrate 100 is formed in the window. For this process, when forming the second doped region 111 (refer to Figure 3 ), a bottom contact region 1053 is formed in the second doped region 111 below the first surface of the substrate 100, so that the bottom of the subsequently formed germanium intrinsic absorption layer 105 can be connected to the bottom contact region 1053. Thus, a germanium photodetector device 1051 as the active device composed of the bottom contact region 1053 (second doped region 111) and the germanium intrinsic absorption layer 105 is formed in the window.
[0098] Then, after forming the fourth dielectric layer (refer to Figure 7 , the same hereinafter), a contact hole patterning and metal filling process is used to simultaneously form third contact holes 1073 corresponding to the bottom contact region 1053 of the germanium photodetector device 1051 and the source / drain 1081 of each transistor 108. Using the same process again, a fifth dielectric layer 204 is formed on the surface of the fourth dielectric layer 203, and a metal interconnect layer 106 is formed in the fifth dielectric layer 204, so that the germanium photodetector device 1051 and each transistor 108 are respectively connected to the metal interconnect layer 106 through the third contact holes 1073 corresponding to the bottom contact region 1053 and the source / drain 1081, thereby realizing the interconnection between the germanium photodetector device 1051 and the electrical devices.
[0099] The advantage of this embodiment is that the contact holes (third contact holes 1073) required for leading out the germanium photodetector device 1051 and the contact holes (third contact holes 1073) required for leading out the MOS device are formed simultaneously, which can save costs and reduce process complexity. However, the possible disadvantage is that when the required thickness of the germanium intrinsic absorption layer 105 is relatively large, its electric field and optical mode may not be easily matched, which will affect the responsivity and response speed. Therefore, in actual fabrication, according to the performance bias of the germanium photodetector device 1051, the above two different fabrication methods for the contact holes (first contact hole 1071 / third contact hole 1073) of the germanium photodetector device 1051 can be selected.
[0100] In summary, the present invention realizes a novel monolithic integrated silicon optical device structure (such as an optical receiver) and its manufacturing process, which can form an integrated process solution that is compatible with the CMOS process and integrates an optical receiving device (photoelectric detection device 1051), optical passive devices (end-face coupling trench 101, end-face coupler 103, and optical waveguide 104), and CMOS devices (TIA, CDR, etc. including transistor 108) on the same substrate 100. Therefore, the process difficulty is reduced, the process risk is decreased, the product cost is lowered, and the product quality is improved.
[0101] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.
Claims
1. A monolithic integrated silicon photonic device structure, characterized in that, comprising: An electrical device and an optical device disposed on the first surface of a substrate; The optical device includes an active device and a passive device, the active device is connected to the substrate, the passive device includes a first passive device and a second passive device, the first passive device is in the substrate below the first surface, the second passive device is plural, each of the second passive devices is isolated above the first surface, and one of the second passive devices is above the first passive device.
2. The monolithic integrated silicon photonic device structure according to claim 1, characterized in that, The electrical device and the active device are located in the active region on the substrate, and the passive device is located on the substrate outside the active region.
3. The monolithic integrated silicon photonic device structure according to claim 1, characterized in that, The electrical device includes a transistor, and / or, the active device includes a photodetector device.
4. The monolithic integrated silicon photonic device structure according to claim 3, characterized in that, The photodetector device includes an intrinsic absorption layer located above the first surface and heterogeneous with the substrate, and a contact region disposed on the top of the intrinsic absorption layer facing away from the first surface, and the photodetector device is led out through the contact region to be interconnected with the electrical device; or, the photodetector device includes an intrinsic absorption layer located above the first surface and heterogeneous with the substrate, and a contact region located below the first surface and connected to the intrinsic absorption layer, and the photodetector device is led out through the contact region to be interconnected with the electrical device.
5. The monolithic integrated silicon photonic device structure according to claim 1, characterized in that, The first passive device includes an end-face coupling trench filled with a first dielectric, the second passive device includes an end-face coupler located above and aligned with the end-face coupling trench, and at least one optical waveguide, and the end-face coupler and the optical waveguide are also isolated above the first surface by the first dielectric.
6. The monolithic integrated silicon photonic device structure according to claim 1, characterized in that, The second passive device is heterogeneous with the substrate.
7. A method for fabricating a monolithic integrated silicon photonic device structure, characterized in that, comprising: Providing a substrate; Forming an electrical device and an optical device on the first surface of the substrate, such that the formed optical device includes an active device and a passive device, the active device is connected to the substrate, the passive device includes a first passive device and a second passive device, the first passive device is in the substrate below the first surface, the second passive device is plural, each of the second passive devices is isolated above the first surface, and one of the second passive devices is above the first passive device.
8. The method for fabricating a monolithic integrated silicon photonic device structure according to claim 7, characterized in that, The forming an electrical device and an optical device on the first surface of the substrate specifically includes: Using a CMOS process, an active region is defined on a first surface of the substrate, a first doped region and a second doped region are formed below the first surface of the active region, and a transistor serving as an electrical device is formed on the first surface corresponding to the first doped region; A trench is formed in the substrate below the first surface outside the active region; A first dielectric layer is formed on the first surface and fills the trench to form an end-face coupled trench serving as a passive device and a first passive device in the substrate below the first surface; An end-face coupler serving as a passive device and a second passive device and at least one optical waveguide are formed on a surface of the first dielectric layer outside the active region, such that the end-face coupler and the optical waveguide are isolated above the first surface through the first dielectric layer, and the end-face coupler is located above and aligned with the end-face coupled trench; A second dielectric layer is formed on the surface of the first dielectric layer to cover the end-face coupler and the optical waveguide; A window communicating with the second doped region is formed on the surface of the second dielectric layer, and a photodetector serving as an active device is formed in the window, thereby forming an optical device including the active device and the passive device.
9. The method for fabricating a monolithic integrated silicon optical device structure according to claim 8, wherein, the forming of the photodetector serving as an active device in the window specifically includes: forming an intrinsic absorption layer heteroepitaxial with the substrate in the window; forming a third doped region serving as a contact region on a top of the intrinsic absorption layer, thereby forming a photodetector serving as an active device composed of the second doped region, the intrinsic absorption layer, and the third doped region in the window; and forming a metal interconnection layer on the surface of the second dielectric layer, and forming contact holes connecting to the metal interconnection layer on the contact region and the first doped region respectively, such that the photodetector is interconnected with the electrical device.
10. The method for fabricating a monolithic integrated silicon optical device structure according to claim 8, wherein, the forming of the photodetector serving as an active device in the window specifically includes: forming an intrinsic absorption layer heteroepitaxial with the substrate in the window, thereby forming a photodetector serving as an active device composed of the second doped region and the intrinsic absorption layer in the window; and forming a metal interconnection layer on the surface of the second dielectric layer, and simultaneously forming contact holes connecting to the metal interconnection layer on the second doped region and the first doped region, such that the photodetector is interconnected with the electrical device.