Preparation method for mass production of transverse silicon-based photonic device

Abstract

The invention relates to the technical field of semiconductor preparation, in particular to a preparation method for mass production of a transverse silicon-based photonic device, transverse wet etching is carried out on a monocrystalline silicon strip, and a {1 < 1 >} crystal face can be formed through wet etching. After the treatment is finished, quickly putting into MOCVD (Metal Organic Chemical Vapor Deposition) to grow a III-V compound structure; the method comprises the following steps: by taking a {1 < 1 >} surface of SI as a seed layer, growing 20 nm InAs below the seed layer, and selectively nucleating on the {1 < 1 >} surface of SI; and then growing a 500nm InGaAs main body structure, and adopting InGaAs or being matched with other III-V structures. According to the invention, process integration is carried out on the basis of the existing mature silicon-based process in combination with the requirements of the III-V compound integration process, and a new idea of integration of the silicon-based photoelectric device is provided; and the III-V compound and the silicon layer can be arranged in a coplanar manner, so that efficient coupling between the III-V compound and the silicon waveguide can be realized.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor manufacturing, and particularly to a preparation method for mass production of lateral silicon-based photonic devices. Background Art

[0002] Silicon-based photonic devices have the cost advantage of being compatible with CMOS processes and can achieve high-density optoelectronic integration. They are one of the most promising integration platforms in the future. Heterogeneously integrating group III-V semiconductor light-emitting materials on the silicon-based photonic platform will greatly unleash the application potential of silicon-based photonic devices and is expected to play an important role in information interconnection technologies with large capacity, large bandwidth, and low cost.

[0003] In the future, with the continuous in-depth research, the group III-V compound integrated silicon-based technology is expected to be more widely applied in frontier fields such as next-generation data communication, heterogeneous computing, and quantum technology. The research team of Professor Xue Ying and Liu Jimei at the Hong Kong University of Science and Technology designed this selective direct epitaxial growth technology, which can laterally and selectively grow group III-V materials on an insulating silicon substrate (SOI) without the need for a thick buffer layer. Based on this technology, the team fabricated a group III-V distributed feedback laser on an SOI wafer, which can be configured coplanarly with the silicon layer to achieve efficient coupling between the group III-V laser and the silicon waveguide.

[0004] Based on this technology, large-scale mass production can be carried out on 6 / 8 / 12-inch silicon-based wafers in the future. However, industrial mass production will involve issues of compatibility with existing technologies, and at the same time, high efficiency and low cost are required during the production process. For photon devices with sizes ranging from dozens of nanometers to several micrometers, different silicon-based node technologies should be adopted for adaptation. Taking the relatively mature 28nm / 40nm / 65nm silicon-based technology nodes as the carrier, the present invention provides a process route for silicon-based integrated photonic devices, providing a feasible solution for subsequent introduction. Summary of the Invention

[0005] In order to achieve mass production of silicon-based integrated photonic devices, this application provides a preparation method for mass production of lateral silicon-based photonic devices.

[0006] The preparation method for mass production of lateral silicon-based photonic devices provided by this application adopts the following technical solutions: A preparation method for mass production of lateral silicon-based photonic devices includes the following steps: S1. Thermally oxidize to generate a lower silicon dioxide layer on the substrate; S2. Chemically vapor deposit and grow a single-crystalline silicon layer on the upper surface of the silicon dioxide layer; S3. Thermally grow an upper silicon dioxide layer on the upper surface of the single-crystalline silicon layer; S4. Sequentially grow a silicon nitride layer and an amorphous silicon layer on the upper surface of the upper silicon dioxide layer by chemical vapor deposition; S5. Lithograph the entire stacked structure to expose the line - space pattern, and after exposure, transfer the pattern to the amorphous silicon layer through plasma etching; S6. Use self - aligned etching to transfer the pattern on the amorphous silicon layer to the silicon nitride layer; S7. Remove the amorphous silicon layer by rinsing with a mixed solution of nitric acid and hydrofluoric acid; S8. Transfer the pattern on the silicon nitride layer to the upper silicon dioxide layer through etching, and then etch down the single - crystal silicon layer. The etching stops at the lower silicon dioxide layer, and the pattern is transferred to the single - crystal silicon layer to form several single - crystal silicon strips; S9. Perform thermal oxidation on the single - crystal silicon layer to form a middle silicon dioxide layer, and the middle silicon dioxide layer wraps outside the pattern of the single - crystal silicon layer; S10. Remove the silicon nitride layer by a mixed solution of hydrofluoric acid and phosphoric acid; S11. Partially etch the upper silicon dioxide layer through lithography and development, so that one end of the single - crystal silicon strip is exposed; S12. Perform lateral wet etching on the single - crystal silicon strip, and retain a part of the single - crystal silicon at the other end of the single - crystal silicon strip to form a {1 11} crystal plane; S13. Place the entire structure into MOCVD for the growth of the III - V compound structure. Using the {1 1 1} crystal plane of the single - crystal silicon as the seed layer, after nucleation, grow the main structure; S14. Use alignment etching to remove the upper silicon dioxide layer, exposing the single - crystal silicon layer and the III - V compound structure.

[0007] By adopting the above technical solutions, currently, the III - V compound and silicon - based integration mass - production solutions are still on the silicon substrate through hybrid integration or heterogeneous integration methods. However, these integration methods all have certain problems. For example, the inter - chip hybrid integration technology cannot integrate large - scale light sources; the on - chip flip - chip technology needs to solve the problem of high - precision coupling; the on - chip bonding heterogeneous integration technology has development potential, but currently only a few companies have achieved productization, and this technical route requires the organic combination of the traditional CMOS process line and the heterogeneous material process line, which is difficult. The present invention designs a III - V compound growth template directly on the silicon substrate, directly integrates the III - V compound on the silicon substrate through MOCVD, and at the same time, the III - V compound can be coplanarly configured with the silicon layer, solving the problem of the organic combination of the traditional CMOS process line and the heterogeneous material process line.

[0008] Preferably, in S13, using the {1 1 1} crystal plane of the single - crystal silicon as the seed layer, grow an InAs layer on the side of the seed layer at 550 °C. The InAs layer selectively nucleates on the {1 1 1} crystal plane of the single - crystal silicon, and then grow the InGaAs main structure.

[0009] Preferably, in S11, the upper silicon dioxide layer is etched by dry etching, with an over-etching of 10%.

[0010] By adopting the above technical solution, over-etching means etching 10% of the single-crystalline silicon layer. The purpose is to ensure that the single-crystalline silicon layer is completely exposed and prevent the upper silicon dioxide layer from remaining. Since the single-crystalline silicon layer will be basically etched away by wet etching in the next step, over-etching here will not have too much impact.

[0011] Preferably, in S12, wet etching is carried out using a 10% KOH solution.

[0012] By adopting the above technical solution, the 10% KOH solution has a very slow etching rate for silicon dioxide, so as to prevent the upper silicon dioxide layer from being etched synchronously when etching the single-crystalline silicon layer.

[0013] Preferably, in S14, dry ICP etching is adopted, and the gases used are C 4 F 8 、He and H 2 .

[0014] By adopting the above technical solution, dry etching can remove silicon dioxide cleanly without damaging the underlying group III-V compound.

[0015] Preferably, the thickness of the single-crystalline silicon layer in S2 is 150 nm, and after S3 is completed, the thickness of the single-crystalline silicon is not less than 100 nm.

[0016] By adopting the above technical solution, when growing the upper silicon dioxide layer, the single-crystalline silicon layer will be somewhat lost. To ensure the thickness of the single-crystalline silicon layer, the thickness of the single-crystalline silicon layer grown in the previous process is relatively thick to ensure the subsequent processes.

[0017] Preferably, the thickness of the upper silicon dioxide layer and the lower silicon dioxide layer is 50 nm.

[0018] Preferably, in S12, after etching to form the {1 1 1} crystal plane, the {1 1 1} crystal plane is treated with a mixed solution of 45% KOH and isopropyl alcohol at 70 °C, then washed with 10% HCI for 1 minute, and then washed and dried with deionized water.

[0019] In summary, the present application includes at least one of the following beneficial technical effects: 1. It is a process integration based on the current mature silicon-based process combined with the requirements of the group III-V compound integration process, and a process flow for silicon-based optoelectronic device integration is given; 2. The group III-V compound can be configured coplanarly with the silicon layer, and efficient coupling between the group III-V compound and the silicon waveguide can be achieved. Brief Description of the Drawings

[0020] Figure 1 It is a schematic structural diagram of the entire stacked structure after the end of step S4 in the embodiment; Figure 2 It is a schematic structural diagram of the stacked structure from step S5 to step S7 in the embodiment; Figure 3 It is a schematic structural diagram of the stacked structure from step S8 to step S9 in the embodiment; Figure 4 It is a schematic structural diagram for showing a single-crystalline silicon strip in the stacked structure in step S11 of the embodiment; Figure 5 It is a schematic structural diagram for showing the growth process of the group III-V compound in the stacked structure from step S12 to S14 in the embodiment.

[0021] Explanation of reference numerals: 1. Substrate; 2. Lower silicon dioxide layer; 3. Single-crystalline silicon layer; 4. Middle silicon dioxide layer; 5. InAs layer; 6. InGaAs main structure; 7. Upper silicon dioxide layer; 8. Silicon nitride layer; 9. Amorphous silicon layer. Detailed implementation manners

[0022] The following further elaborates on the present application in conjunction with all the attached drawings.

[0023] Embodiment: The embodiment of the present application discloses a preparation method for mass production of a lateral silicon-based photonic device. Referring to Figures 1 to 5 , it includes the following steps: S1. Thermally oxidize 50 nm thick silicon dioxide on the substrate 1 wafer silicon to form the lower silicon dioxide layer 2.

[0024] S2. Then, chemically vapor deposit and grow 150 nm of single-crystalline silicon on the lower silicon dioxide layer 2 to form the single-crystalline silicon layer 3; the purpose of thermally oxidizing 50 nm thick silicon dioxide here is to form a pad oxide layer, which protects the upper single-crystalline silicon and is also the lower surface of the subsequent growth template for the group III-V compound.

[0025] S3. Next, thermally grow a thin layer of silicon dioxide about 50 nm on the surface of the single-crystalline silicon layer 3 to form the upper silicon dioxide layer 7; the purpose of this layer is to protect the underlying single-crystalline silicon and is also the etch stop layer for subsequent etching to prevent damage to the single-crystalline silicon in subsequent steps. At this time, the thermally grown 50 nm of silicon dioxide will reduce the thickness of the single-crystalline silicon from 150 nm to 100 nm.

[0026] S4. Then, a 90-nm-thick silicon nitride and a 100-nm-thick amorphous silicon α-Si are successively deposited by chemical vapor deposition on the silicon dioxide layer 7, forming a silicon nitride layer 8 and an amorphous silicon layer 9 in sequence. Here, the silicon nitride serves as a hard mask for etching, used to define the final 100-nm-thick single-crystalline silicon to be etched; while the role of the amorphous silicon α-Si is that of dummy Si, a sacrificial layer for pattern transfer, and it is finally removed.

[0027] S5. Lithography is performed on the entire stacked structure, and pattern transfer is carried out using line-space pattern exposure. After exposure, the pattern is transferred to the underlying amorphous silicon layer 9 through plasma etching; the line-space pattern is used to define the position and size of the future silicon strips. The etching stops at the upper surface of the silicon nitride, and finally the remaining photoresist is removed to complete the pattern transfer from PR to the amorphous silicon layer 9. Finally, a number of amorphous silicon strips with dimensions of 1000 nm * 150 nm * 100 nm are formed.

[0028] S6. Then, self-aligned etching is adopted to transfer the pattern of the amorphous silicon layer 9 to the underlying silicon nitride layer 8. Here, α-Si is sacrificed for the transfer, and part of the α-Si will be lost during the etching process; the selectivity ratio of Si to silicon nitride should be adjusted during the etching process. After the silicon nitride etching is completed, the remaining amount of α-Si is about 20 nm. S7. The remaining α-Si is removed by rinsing with a mixed solution of nitric acid and hydrofluoric acid.

[0029] S8. Using the silicon nitride as a hard mask, the pattern on the silicon nitride layer 8 is transferred to the upper silicon dioxide layer 7 through etching, and then the underlying 100-nm single-crystalline silicon is etched. The etching stops at the lower silicon dioxide layer 2, and the pattern is transferred to the single-crystalline silicon layer 3, forming a number of single-crystalline silicon strips.

[0030] S9. After cleaning, 50-nm-thick silicon dioxide is thermally oxidized to form the middle silicon dioxide layer 4. At this time, since the single-crystalline silicon has been thermally oxidized on both the top and bottom, and at the same time the 50-nm upper silicon dioxide layer 7 on the top is protected by silicon nitride, so the thermal oxidation only occurs in the four directions of the front, back, left, and right of the single-crystalline silicon; therefore, the middle silicon dioxide layer 4 wraps around the outside of the pattern of the single-crystalline silicon layer 3; the single-crystalline silicon strips change from 1000 nm * 150 nm * 100 nm in length, width, and height to 900 nm * 50 nm * 100 nm after thermal oxidation. Thus, the thermal growth of the middle silicon dioxide layer 4 surrounding the single-crystalline silicon strips is completed, and at the same time, the top is protected by the silicon nitride layer 8.

[0031] S10. The silicon nitride layer 8 is removed by a mixed solution of hydrofluoric acid and phosphoric acid, and at the same time, the upper silicon dioxide layer 7 above the single-crystalline silicon is not damaged.

[0032] S11. After lithography and development, one end of the single-crystalline silicon strip is exposed with a width of 200 nm. Then, the silicon dioxide layer 7 at the end is opened by dry etching to expose the underlying single-crystalline silicon, and over-etching can be 10% because the single-crystalline silicon will be completely etched away by wet etching in the next step.

[0033] S12. Then, transverse wet etching of the single-crystalline silicon strip is carried out. Etching is performed with a 10% KOH solution at room temperature. KOH etches silicon but has a very slow etching rate for silicon dioxide, and the etching rate ratio of silicon to silicon dioxide is 100:1. Stop 200 nm away from the other end of the single-crystalline silicon strip. The wet etching will form a {1 1 1} crystal plane. After etching, the {1 1 1} crystal plane is treated briefly in a mixed solution of 45% KOH and isopropyl alcohol at 70 °C. Finally, it is cleaned with 10% HCl for 1 minute, and finally cleaned and dried with deionized water.

[0034] S13. After processing, it is quickly placed in MOCVD for the growth of the III-V compound structure. Using the {1 1 1} plane of Si as the seed layer, first grow 20 nm of InAs at 550 °C, and they will selectively nucleate on the Si {111} plane. Then grow the 500 nm InGaAs main structure 6. The present invention uses InGaAs and can also be paired with other III-V structures.

[0035] S14. Finally, self-aligned etching is used to remove the silicon dioxide layer 7 on the surface of the III-V compound structure. The etching process uses dry ICP etching, and the gas used is a mixed gas of C 4 F 8 , He and H 2 . The etching requirement is to completely remove the silicon dioxide without damaging the underlying InGaAs structure. Thus, the process of integrating the III-V compound on the silicon substrate is completely completed.

[0036] The above are all preferred embodiments of this application, and the protection scope of this application is not limited thereby. Therefore, all equivalent changes made according to the structure, shape, and principle of this application should be covered within the protection scope of this application.

Claims

1. A method for mass production of lateral silicon-based photonic devices, characterized in that: The following steps are involved: S1, thermally oxidizing a substrate (1) to form a lower silicon dioxide layer (2); S2, growing a single crystal silicon layer (3) by chemical vapor deposition on the upper surface of the silicon dioxide layer; S3, thermally growing an upper silicon dioxide layer (7) on the upper surface of the single crystal silicon layer (3); S4, sequentially growing a silicon nitride layer (8) and an amorphous silicon layer (9) on the upper surface of the upper silicon dioxide layer (7) by chemical vapor deposition; S5, performing photolithography on the entire stacked structure to expose the line-space pattern, and after exposure, transferring the pattern to the amorphous silicon layer (9) through plasma etching; S6, using self-aligned etching to transfer the pattern on the amorphous silicon layer (9) to the silicon nitride layer (8); S7, removing the amorphous silicon layer (9) by rinsing with a mixture of nitric acid and hydrofluoric acid; S8, transferring the pattern on the silicon nitride layer (8) to the upper silicon dioxide layer (7) by etching, and then etching downwards the single crystal silicon layer (3), stopping the etching at the lower silicon dioxide layer (2), and transferring the pattern to the single crystal silicon layer (3), thereby forming a plurality of single crystal silicon strips; S9, performing thermal oxidation on the single crystal silicon layer (3) to form a middle silicon dioxide layer (4), wherein the middle silicon dioxide layer (4) wraps around the outer side of the pattern of the single crystal silicon layer (3); S10, removing the silicon nitride layer (8) by using a mixture of hydrofluoric acid and phosphoric acid; S11, partially etching the upper silicon dioxide layer (7) through photolithography and development, so that one end of the single crystal silicon strip is exposed; S12, performing lateral wet etching on the single crystal silicon strip, retaining a portion of single crystal silicon at the other end of the single crystal silicon strip to form a {1 1 1} crystal plane; S13, placing the entire structure into MOCVD to grow a III-V compound structure, using the {1 1 1} crystal plane of single crystal silicon as a seed layer, and growing the main structure after nucleation; S14, using aligned etching to remove the upper silicon dioxide layer (7), exposing the single crystal silicon layer (3) and the III-V compound structure.

2. The method for mass production of lateral silicon-based photonic devices according to claim 1, characterized in that: In S13, the {1 1 1} crystal plane of the single crystal silicon is used as a seed layer, and an InAs layer (5) is grown on the side of the seed layer at 550° C. The InAs layer (5) is selectively nucleated on the {1 1 1} crystal plane of the single crystal silicon, and then an InGaAs main structure (6) is grown.

3. The method for mass production of lateral silicon-based photonic devices according to claim 1, characterized in that: In S11, the upper silicon dioxide layer (7) is etched by dry etching and overetched by 10%.

4. The method for mass production of lateral silicon-based photonic devices according to claim 1, characterized in that: In S12, wet etching is performed using a 10% KOH solution.

5. The method for mass production of lateral silicon-based photonic devices according to claim 1, characterized in that: In S14, dry ICP etching is adopted, and the gases used are C4F8, He and H2.

6. The method for mass production of lateral silicon-based photonic devices according to claim 1, characterized in that: In S2, the thickness of the single crystal silicon layer (3) is 150 nm. After S3 is completed, the thickness of the single crystal silicon is not less than 100 nm.

7. The method for mass production of lateral silicon-based photonic devices according to claim 1, characterized in that: The thickness of the upper silicon dioxide layer (7) and the lower silicon dioxide layer (2) is 50 nm.

8. The method for mass production of lateral silicon-based photonic devices according to claim 1, characterized in that: In S12, after etching to form the {1 1 1} crystal plane, the {1 1 1} crystal plane was treated with a mixed solution of 45% KOH and isopropanol at 70°C, then cleaned with 10% HCI for 1 minute, and then cleaned with deionized water and blown dry.

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