Power optimization methods, devices, electronic devices, and storage media in chip design

Abstract

This invention provides a power consumption optimization method, apparatus, electronic device, and storage medium in chip design. First, it filters out paths from the chip design diagram that cannot be optimized by the standard optimization process. When these paths contain both high-power standard cells and slow standard cells, the slow standard cell closest to the path's starting point is replaced with a new standard cell, allowing the path to gain a time margin. Finally, the standard power consumption optimization process replaces the corresponding high-power standard cells based on this time margin, significantly improving the power consumption optimization effect of timing paths composed of a mixture of high-power and slow standard cells, and further reducing the power consumption of the chip design diagram.

Description

Technical Field

[0001] This invention belongs to the field of chip design technology, and particularly relates to a power consumption optimization method, apparatus, electronic device and storage medium in chip design. Background Technology

[0002] Today, power consumption has become one of the key metrics for evaluating chip design, and low-power design has begun to be implemented in many chip designs.

[0003] Existing power optimization processes rely on EDA tools, typically performed during the ECO phase of the chip back-end design cycle. Power consumption is reduced by switching standard cells to lower drive strengths or higher threshold voltages. During the power optimization process, EDA tools perform time margin checks. When a timing path has time margin, optimization is performed: higher-power standard cells are replaced with lower-power standard cells. However, for timing paths composed of a mix of high-power and slow standard cells, the slow cells may have already occupied all the time margin. Therefore, EDA tools cannot replace the standard cells because the increased latency of the replaced standard cells would lead to timing violations. Consequently, existing power optimization methods are less effective. Summary of the Invention

[0004] Based on this, and in response to the aforementioned technical problems, a power consumption optimization method, apparatus, electronic device, and storage medium in chip design are provided.

[0005] The technical solution adopted in this invention is as follows:

[0006] As a first aspect of the present invention, a power consumption optimization method in chip design is provided, characterized in that it includes:

[0007] S101. Determine the timing paths with time margins in the chip design diagram, and filter out the timing paths with time margins less than a threshold to form a path set.

[0008] S102. Determine whether there is at least one high-power standard unit in each timing path of the path set. If yes, proceed to the next step; otherwise, ignore the path. The high-power standard unit is a standard unit whose threshold voltage is equal to the lowest threshold voltage of the process standard unit library and whose drive strength is greater than D10.

[0009] S103. Further determine whether there is a slow standard unit in the timing path where there is at least one high-power standard unit. If so, take the slow standard unit closest to the start point of the path as the unit to be replaced, and determine the position of the unit to be replaced in the chip design diagram and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced.

[0010] The slow standard unit is defined as a standard unit whose threshold voltage is equal to the highest threshold voltage in the process standard unit library, whose drive strength is equal to the lowest drive strength in the process standard unit library, and whose delay is greater than twice the standard delay. The threshold voltage and drive strength of the new standard unit are determined as follows:

[0011] The threshold voltage of the new standard unit is determined by the following method: First, the threshold voltage of the next lower level of the threshold voltage level provided by the process standard unit library is lower than the threshold voltage of the unit to be replaced. Second, the driving strength of the new standard unit is the same as the driving strength of the unit to be replaced. Third, the driving strength of the new standard unit is determined by the following method: The ...

[0012] S104. Based on the position of the unit to be replaced in the chip design diagram and the threshold voltage and driving strength of the new standard unit used to replace the unit to be replaced, replace all the units to be replaced in the chip design diagram with the corresponding new standard units.

[0013] S105. Update the timing of each timing path in the chip design diagram;

[0014] S106. Optimize the power consumption of the chip design using the standard power consumption optimization process.

[0015] As a second aspect of the present invention, a power consumption optimization device for chip design is provided, characterized in that it comprises:

[0016] The first module is used to determine the timing paths with time margin in the chip design diagram, and filter out the timing paths with time margin less than a threshold to form a path set.

[0017] The second module is used to determine whether there is at least one high-power standard unit in each timing path of the path set. If so, proceed to the next step; otherwise, ignore the path. The high-power standard unit is a standard unit whose threshold voltage is equal to the lowest threshold voltage of the process standard unit library and whose drive strength is greater than D10.

[0018] The third module is used to further determine whether there is a slow standard unit in the timing path where there is at least one high-power standard unit. If so, the slow standard unit closest to the start point of the path is taken as the unit to be replaced, and the position of the unit to be replaced in the chip design diagram and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced are determined.

[0019] The slow standard unit is defined as a standard unit whose threshold voltage is equal to the highest threshold voltage in the process standard unit library, whose drive strength is equal to the lowest drive strength in the process standard unit library, and whose delay is greater than twice the standard delay. The threshold voltage and drive strength of the new standard unit are determined as follows:

[0020] The threshold voltage of the new standard unit is determined by the following method: First, the threshold voltage of the next lower level of the threshold voltage level provided by the process standard unit library is lower than the threshold voltage of the unit to be replaced. Second, the driving strength of the new standard unit is the same as the driving strength of the unit to be replaced. Third, the driving strength of the new standard unit is determined by the following method: The ...

[0021] The fourth module is used to replace all the units to be replaced in the chip design with the corresponding new standard units according to the position of the unit to be replaced in the chip design and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced.

[0022] The fifth module is used to update the timing of each timing path in the chip design diagram;

[0023] The sixth module is used to optimize the power consumption of the chip design using a standard power optimization process.

[0024] As a third aspect of the present invention, an electronic device is provided, characterized in that it includes a storage module, the storage module including instructions loaded and executed by a processor, the instructions causing the processor to perform a power optimization method in a chip design according to the first aspect described above when executed.

[0025] As a fourth aspect of the present invention, a computer-readable storage medium is provided that stores one or more programs, characterized in that, when the one or more programs are executed by a processor, they implement a power consumption optimization method in chip design as described in the first aspect.

[0026] This invention first identifies paths in the chip design that cannot be optimized by the standard optimization process. When these paths contain both high-power standard cells and slow standard cells, the slow standard cell closest to the path start point is replaced with a new standard cell, allowing the path to gain a time margin. Finally, the standard power optimization process replaces the corresponding high-power standard cells based on this time margin, greatly improving the power optimization effect of timing paths composed of a mixture of high-power and slow standard cells, and further reducing the power consumption of the chip design. Attached Figure Description

[0027] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments:

[0028] Figure 1 A flowchart illustrating a power consumption optimization method in chip design, provided as an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a power consumption optimization device in chip design provided by an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of an electronic device provided in an embodiment of the present invention;

[0031] Figure 4 (a) and (b) are schematic diagrams of the timing paths before and after power consumption optimization in the embodiments of the present invention. Detailed Implementation

[0032] The embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the embodiments described in this specification are not exhaustive and do not represent the only embodiments of the present invention. The corresponding embodiments below are only for clearly illustrating the inventive content of this patent and are not intended to limit its implementation. For those skilled in the art, different variations and modifications can be made based on the embodiments described. Any variations or modifications that fall within the technical concept and inventive content of this invention and are obvious are also within the protection scope of this invention.

[0033] This application embodiment is based on the Static Timing Analysis (STA) tool of EDA tools. In this embodiment, the Static Timing Analysis tool adopts Synopsys' PrimeTime (PT), which has power optimization function.

[0034] like Figure 1 As shown in the figure, this application provides a power consumption optimization method in chip design, the specific process of which is as follows:

[0035] S101. Start PT. Use PT to determine the timing paths with time margin in the chip design diagram. Filter out the timing paths with time margin less than the threshold to form a path set.

[0036] Here, the slack of each timing path in the chip design diagram is calculated using PT. Here, slack = data required time - data arrival time. Data required time is the time it takes for the data to reach the register clock pin from the clock source, i.e., the time the data needs to arrive. Data arrival time is the time it takes for the data to arrive at this level register after passing through the functional logic of the previous level register, i.e., the actual time the data arrives. Successfully converged timing is represented by a positive number, while timing violations are represented by a negative number. Therefore, when slack is positive, it means that the corresponding timing path has time margin, and when slack is negative, it means that the corresponding timing path has no time margin.

[0037] Among them, timing paths with a time margin less than the threshold are paths that cannot be optimized by the subsequent standard optimization process, while timing paths with a time margin greater than or equal to the threshold can be optimized by the subsequent standard optimization process. Therefore, they are ignored by the threshold, which can be set to 5 ps (picosecond).

[0038] It should be noted that in chip design, timing path mainly refers to the signal propagation path from timing source (such as the output of a register) to timing end (the input of the next level register), and this path usually contains multiple standard cells.

[0039] S102. Determine whether there is at least one high-power standard unit in each timing path of the path set. If so, proceed to the next step; otherwise, ignore the path.

[0040] Among them, the high-power standard cell is a standard cell whose threshold voltage is equal to the lowest threshold voltage in the process standard cell library and whose drive strength is greater than D10. Assume the threshold voltage levels of the standard cells provided by the process standard cell library are as follows:

[0041] HVT (High Threshold Voltage)

[0042] SVT (Standard Threshold Voltage)

[0043] LVT (Low Threshold Voltage)

[0044] ULVT (Ultra-Low Threshold Voltage)

[0045] Assuming there exists a standard cell with a threshold voltage of ULVT and a drive strength of D12 in the worst-case path, since the lower the threshold voltage, the larger the leakage current and the higher the power consumption, this standard cell is a high-power standard cell.

[0046] S103. Further determine whether there is a slow standard cell in the worst path where there is at least one high-power standard cell. If so, take the slow standard cell closest to the start point of the path as the cell to be replaced, and determine the position of the cell to be replaced in the chip design diagram, as well as the threshold voltage and drive strength of the new standard cell used to replace the cell to be replaced.

[0047] Among them, the slow standard cell is a standard cell whose threshold voltage is equal to the highest threshold voltage of the process standard cell library, whose drive strength is equal to the lowest drive strength of the process standard cell library, and whose delay is greater than twice the standard delay. The higher the threshold voltage, the slower the switching speed and the longer the delay time of the standard cell. The lower the drive strength, the longer the delay time of the standard cell.

[0048] Standard delay refers to the normal delay of a standard cell under the current PVT (Process, Voltage, and Temperature) conditions. Of course, the normal delay of a standard cell may be different under different PVT conditions.

[0049] The threshold voltage and drive strength of the new standard unit are determined as follows: First, it is determined whether there is a next-level threshold voltage in the threshold voltage level provided by the process standard unit library that is lower than the threshold voltage of the unit to be replaced. If so, the next-level threshold voltage is used as the threshold voltage of the new standard unit, and the drive strength of the new standard unit is the same as the drive strength of the unit to be replaced. Otherwise, the next-level drive strength in the drive strength level provided by the process standard unit library that is higher than the drive strength of the unit to be replaced is used as the drive strength of the new standard unit, and the threshold voltage of the new standard unit is the same as the threshold voltage of the unit to be replaced.

[0050] Assume the threshold voltage level and drive level of the standard cells provided by the process standard cell library are as follows:

[0051] HVT (High Threshold Voltage)

[0052] SVT (Standard Threshold Voltage)

[0053] LVT (Low Threshold Voltage)

[0054] ULVT (Ultra-Low Threshold Voltage)

[0055] D1, D2, D4, D6…

[0056] For the replacement cell of D2 SVT, the corresponding new standard cell of D2 LVT is used; for the replacement cell of D2 ULVT, the corresponding new standard cell of D4 ULVT is used.

[0057] It can be seen that when replacing standard cells, the threshold voltage level should be reduced first. Only when the threshold voltage level cannot be reduced further should the drive strength be increased. The purpose of this is that replacing the threshold voltage yields the greatest benefit in the later stages of the design (usually the ECO phase). Different threshold voltages of the same standard cell have the same area and pin locations, so this type of replacement has minimal physical impact (wiring, DRC, etc.), and delay is almost halved under ideal conditions. Of course, when replacing standard cells, the above preferred method can be abandoned, and instead, the threshold voltage can be reduced and / or the drive strength increased, i.e.:

[0058] The threshold voltage of the new standard unit is determined by the following method: First, the threshold voltage of the next lower level of the threshold voltage level provided by the process standard unit library is lower than the threshold voltage of the unit to be replaced. The driving strength of the new standard unit is the same as the driving strength of the unit to be replaced. Alternatively, the threshold voltage of the new standard unit is the same as the threshold voltage of the unit to be replaced, and the driving strength of the next lower level of the driving strength level provided by the process standard unit library is higher than the driving strength of the unit to be replaced. Or, the threshold voltage of the new standard unit is determined by the following method: First, the threshold voltage of the next lower level of the threshold voltage level provided by the process standard unit library is lower than the threshold voltage of the unit to be replaced. Simultaneously, the driving strength of the next lower level of the driving strength level provided by the process standard unit library is higher than the driving strength of the unit to be replaced.

[0059] In this embodiment, after determining the position of the unit to be replaced in the chip design diagram and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced, a unit replacement script is generated based on this information.

[0060] Glitches occur in cells with two or more input pins because signal transmission has a delay; signals from different pins pass through different logic paths and arrive at different times, causing unnecessary signal changes at the cell's output. This glitch phenomenon propagates down the cell hierarchy, with cells closer to the timing endpoint receiving more glitch signals. Dynamic power consumption is linked to the cell's output signal switching; more glitch signals result in higher switching times and thus higher dynamic power consumption. Therefore, selecting the slowest standard cell closest to the start of the path as the replacement cell minimizes the impact of glitch signals and avoids increased dynamic power consumption.

[0061] S104. Based on the position of the cell to be replaced in the chip design diagram and the threshold voltage and drive strength of the new standard cell used to replace the cell to be replaced, replace all the cells to be replaced in the chip design diagram with the corresponding new standard cells.

[0062] Here, PT is restarted, and PT reads the cell replacement script to replace the standard cells.

[0063] S105. Update the timing of each timing path in the chip design diagram.

[0064] S106. The power consumption of the chip design is optimized using a standard power consumption optimization process based on PT.

[0065] Since the standard cells in the chip design have been replaced (upsized), the timing path where the replacement occurred has enough time leeway for the standard power optimization process to downsize the high-power standard cells, thereby reducing power consumption.

[0066] by Figure 4 Taking the timing path shown in (a) as an example, assuming the highest threshold voltage of the standard cell library in this example is SVT and the lowest threshold voltage is ULV, the maximum delay requirement of this timing path is 360ps. It contains two high-power standard cells (cells 4 and 6) and four slow standard cells (cells 1-3 and 5). The slowest standard cell (cell 1) closest to the start of the path is selected as the cell to be replaced (delay: 80ps). The threshold voltage of the corresponding new standard cell is LVT (delay: 40ps). After replacement and timing updates, see [link to relevant documentation]. Figure 4 (b) shows that the path has a time margin of 40ps. Based on this, the standard power optimization process can replace the two high-power standard units (4 and 6) with LVT standard units respectively. The timing path can still meet the maximum delay requirement of 360ps. However, in the prior art, it is not possible to replace the two high-power standard units (4 and 6) of the timing path with LVT standard units respectively through the standard power optimization process, because this would directly lead to timing violations.

[0067] It should be noted that upsizing the cell to be replaced actually increases its power consumption. However, since the high-power standard cell we want to optimize needs to meet the requirement of a drive strength greater than D10, the power reduction of this level of standard cell after downsizing is greater than the power increase of the slow cell after upsizing. Therefore, the solution in this application will not result in zero optimization or negative optimization.

[0068] Furthermore, with the STA tool supporting parallel operation, this embodiment can perform operations on multiple paths in parallel, thereby improving efficiency.

[0069] As can be seen from the above, the power consumption optimization method in chip design provided by this application first filters out paths that cannot be optimized by the standard optimization process from the chip design diagram. When there are both high-power standard cells and slow standard cells in these paths, the slow standard cell closest to the starting point of the path is replaced with a new standard cell, so that the path can obtain a time margin (relaxing the time margin of the path). Finally, the standard power consumption optimization process replaces the corresponding high-power standard cells according to the time margin, which greatly improves the power consumption optimization effect of the timing path composed of a mixture of high-power standard cells and slow standard cells, and further reduces the power consumption of the chip design diagram.

[0070] The following describes in detail one or more embodiments of the present invention a power optimization device in a chip design. Those skilled in the art will understand that these optimization devices can be configured using commercially available hardware components through the steps taught in this solution. Figure 2 This invention illustrates a power consumption optimization device in chip design, as provided in an embodiment of the present invention. Figure 2 As shown, the optimization device includes a first module 11, a second module 12, a third module 13, a fourth module 14, a fifth module 15, and a sixth module 16.

[0071] The first module 11 is used to start PT, which determines the timing paths with time margin in the chip design diagram through PT, and filters out the timing paths with time margin less than the threshold to form a path set.

[0072] Here, the slack of each timing path in the chip design diagram is calculated using PT. Here, slack = data required time - data arrival time. Data required time is the time it takes for the data to reach the register clock pin from the clock source, i.e., the time the data needs to arrive. Data arrival time is the time it takes for the data to arrive at this level register after passing through the functional logic of the previous level register, i.e., the actual time the data arrives. Successfully converged timing is represented by a positive number, while timing violations are represented by a negative number. Therefore, when slack is positive, it means that the corresponding timing path has time margin, and when slack is negative, it means that the corresponding timing path has no time margin.

[0073] Among them, timing paths with a time margin less than the threshold are paths that cannot be optimized by the subsequent standard optimization process, while timing paths with a time margin greater than or equal to the threshold can be optimized by the subsequent standard optimization process. Therefore, they are ignored by the threshold, which can be set to 5 ps (picosecond).

[0074] It should be noted that in chip design, timing path mainly refers to the signal propagation path from timing source (such as the output of a register) to timing end (the input of the next level register), and this path usually contains multiple standard cells.

[0075] The second module 12 is used to determine whether there is at least one high-power standard unit in each timing path in the path set. If so, proceed to the next step; otherwise, ignore the path.

[0076] Among them, the high-power standard cell is a standard cell whose threshold voltage is equal to the lowest threshold voltage in the process standard cell library and whose drive strength is greater than D10. Assume the threshold voltage levels of the standard cells provided by the process standard cell library are as follows:

[0077] HVT (High Threshold Voltage)

[0078] SVT (Standard Threshold Voltage)

[0079] LVT (Low Threshold Voltage)

[0080] ULVT (Ultra-Low Threshold Voltage)

[0081] Assuming there exists a standard cell with a threshold voltage of ULVT and a drive strength of D12 in the worst-case path, since the lower the threshold voltage, the larger the leakage current and the higher the power consumption, this standard cell is a high-power standard cell.

[0082] The third module 13 is used to further determine whether there is a slow standard unit in the worst path where there is at least one high-power standard unit. If so, the slow standard unit closest to the start point of the path is taken as the unit to be replaced. The slow standard unit closest to the start point of the path is less affected by glitches. The module also determines the position of the unit to be replaced in the chip design and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced.

[0083] Among them, the slow standard cell is a standard cell whose threshold voltage is equal to the highest threshold voltage of the process standard cell library, whose drive strength is equal to the lowest drive strength of the process standard cell library, and whose delay is greater than twice the standard delay. The higher the threshold voltage, the slower the switching speed and the longer the delay time of the standard cell. The lower the drive strength, the longer the delay time of the standard cell.

[0084] Standard delay refers to the normal delay of a standard cell under the current PVT (Process, Voltage, and Temperature) conditions. Of course, the normal delay of a standard cell may be different under different PVT conditions.

[0085] The threshold voltage and drive strength of the new standard unit are determined as follows: First, it is determined whether there is a next-level threshold voltage in the threshold voltage level provided by the process standard unit library that is lower than the threshold voltage of the unit to be replaced. If so, the next-level threshold voltage is used as the threshold voltage of the new standard unit, and the drive strength of the new standard unit is the same as the drive strength of the unit to be replaced. Otherwise, the next-level drive strength in the drive strength level provided by the process standard unit library that is higher than the drive strength of the unit to be replaced is used as the drive strength of the new standard unit, and the threshold voltage of the new standard unit is the same as the threshold voltage of the unit to be replaced.

[0086] Assume the threshold voltage level and drive level of the standard cells provided by the process standard cell library are as follows:

[0087] HVT (High Threshold Voltage)

[0088] SVT (Standard Threshold Voltage)

[0089] LVT (Low Threshold Voltage)

[0090] ULVT (Ultra-Low Threshold Voltage)

[0091] D1, D2, D4, D6…

[0092] For the replacement cell of D2 SVT, the corresponding new standard cell of D2 LVT is used; for the replacement cell of D2 ULVT, the corresponding new standard cell of D4 ULVT is used.

[0093] It can be seen that when replacing standard cells, the threshold voltage level should be reduced first. Only when the threshold voltage level cannot be reduced further should the drive strength be increased. The purpose of this is that replacing the threshold voltage yields the greatest benefit in the later stages of the design (usually the ECO phase). Different threshold voltages of the same standard cell have the same area and pin locations, so this type of replacement has minimal physical impact (wiring, DRC, etc.), and delay is almost halved under ideal conditions. Of course, when replacing standard cells, the above preferred method can be abandoned, and instead, the threshold voltage can be reduced and / or the drive strength increased, i.e.:

[0094] The threshold voltage of the new standard unit is determined by the following method: First, the threshold voltage of the next lower level of the threshold voltage level provided by the process standard unit library is lower than the threshold voltage of the unit to be replaced. The driving strength of the new standard unit is the same as the driving strength of the unit to be replaced. Alternatively, the threshold voltage of the new standard unit is the same as the threshold voltage of the unit to be replaced, and the driving strength of the next lower level of the driving strength level provided by the process standard unit library is higher than the driving strength of the unit to be replaced. Or, the threshold voltage of the new standard unit is determined by the following method: First, the threshold voltage of the next lower level of the threshold voltage level provided by the process standard unit library is lower than the threshold voltage of the unit to be replaced. Simultaneously, the driving strength of the next lower level of the driving strength level provided by the process standard unit library is higher than the driving strength of the unit to be replaced.

[0095] In this embodiment, after determining the position of the unit to be replaced in the chip design diagram and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced, a unit replacement script is generated based on this information.

[0096] Glitches occur in cells with two or more input pins because signal transmission has a delay; signals from different pins pass through different logic paths and arrive at different times, causing unnecessary signal changes at the cell's output. This glitch phenomenon propagates down the cell hierarchy, with cells closer to the timing endpoint receiving more glitch signals. Dynamic power consumption is linked to the cell's output signal switching; more glitch signals result in higher switching times and thus higher dynamic power consumption. Therefore, selecting the slowest standard cell closest to the start of the path as the replacement cell minimizes the impact of glitch signals and avoids increased dynamic power consumption.

[0097] The fourth module 14 is used to replace all the cells to be replaced in the chip design with the corresponding new standard cells according to the position of the cell to be replaced in the chip design and the threshold voltage and drive strength of the new standard cell used to replace the cell to be replaced.

[0098] Here, PT is restarted, and PT reads the cell replacement script to replace the standard cells.

[0099] Module 5, 15, is used to update the timing of each timing path in the chip design diagram.

[0100] Module 6, 16, is used to optimize the power consumption of the chip design using a standard power optimization process based on PT.

[0101] Since the standard cells in the chip design have been replaced (upsized), the timing path where the replacement occurred has enough time leeway for the standard power optimization process to downsize the high-power standard cells, thereby reducing power consumption.

[0102] by Figure 4 Taking the timing path shown in (a) as an example, assuming the highest threshold voltage of the standard cell library in this example is SVT and the lowest threshold voltage is ULV, the maximum delay requirement of this timing path is 360ps. It contains two high-power standard cells (cells 4 and 6) and four slow standard cells (cells 1-3 and 5). The slowest standard cell (cell 1) closest to the start of the path is selected as the cell to be replaced (delay: 80ps). The threshold voltage of the corresponding new standard cell is LVT (delay: 40ps). After replacement and timing updates, see [link to relevant documentation]. Figure 4 (b) shows that the path has a time margin of 40ps. Based on this, the standard power optimization process can replace the two high-power standard units (4 and 6) with LVT standard units respectively. The timing path can still meet the maximum delay requirement of 360ps. However, in the prior art, it is not possible to replace the two high-power standard units (4 and 6) of the timing path with LVT standard units respectively through the standard power optimization process, because this would directly lead to timing violations.

[0103] It should be noted that upsizing the cell to be replaced actually increases its power consumption. However, since the high-power standard cell we want to optimize needs to meet the requirement of a drive strength greater than D10, the power reduction of this level of standard cell after downsizing is greater than the power increase of the slow cell after upsizing. Therefore, the solution in this application will not result in zero optimization or negative optimization.

[0104] Furthermore, with the STA tool supporting parallel operation, this embodiment can perform operations on multiple paths in parallel, thereby improving efficiency.

[0105] In summary, the power optimization device in the chip design provided in the above embodiments can execute the power optimization method in the chip design provided in the foregoing embodiments.

[0106] Similar to the above concept, the above Figure 2 The power optimization device in the chip design shown can be implemented as an electronic device. Figure 3 A schematic block diagram of the structure of an electronic device provided by an embodiment of the present invention is shown.

[0107] For example, the electronic device includes a storage module 21 and a processor 22. The storage module 21 includes instructions loaded and executed by the processor 22, which, when executed, cause the processor 22 to perform the steps described in the section on power optimization methods in a chip design described above in this specification, according to various exemplary embodiments of the present invention.

[0108] It should be understood that processor 22 can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, the general-purpose processor can be a microprocessor or any conventional processor.

[0109] This invention also provides a computer-readable storage medium that stores one or more programs, which, when executed by a processor, implement the steps described in the section on power optimization methods in chip design according to various exemplary embodiments of the invention.

[0110] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer-readable storage media (or non-transitory media) and communication media (or transient media).

[0111] As is known to those skilled in the art, the term computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0112] For example, the computer-readable storage medium may be an internal storage unit of the electronic device described in the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc., provided on the electronic device.

[0113] The electronic devices and computer-readable storage media provided in the foregoing embodiments first screen out paths that cannot be optimized by the standard optimization process from the chip design diagram. When there are both high-power standard cells and slow standard cells in these paths, the slow standard cell closest to the start of the path is replaced with a new standard cell, so that the path can obtain a time margin. Finally, the standard power optimization process replaces the corresponding high-power standard cells according to the time margin, which greatly improves the power optimization effect of the timing path composed of a mixture of high-power standard cells and slow standard cells, and further reduces the power consumption of the chip design diagram.

[0114] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A power consumption optimization method in chip design, characterized in that, include: S101. Determine the timing paths with time margins in the chip design diagram, and filter out the timing paths with time margins less than a threshold to form a path set. S102. Determine whether there is at least one high-power standard unit in each timing path of the path set. If yes, proceed to the next step; otherwise, ignore the path. The high-power standard unit is a standard unit whose threshold voltage is equal to the lowest threshold voltage of the process standard unit library and whose drive strength is greater than D10. S103. Further determine whether there is a slow standard unit in the timing path where there is at least one high-power standard unit. If so, take the slow standard unit closest to the start point of the path as the unit to be replaced, and determine the position of the unit to be replaced in the chip design diagram and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced. The slow standard unit is defined as a standard unit whose threshold voltage is equal to the highest threshold voltage in the process standard unit library, whose drive strength is equal to the lowest drive strength in the process standard unit library, and whose delay is greater than twice the standard delay. The threshold voltage and drive strength of the new standard unit are determined as follows: The threshold voltage of the new standard unit is determined by the following method: First, the threshold voltage of the next lower level of the threshold voltage level provided by the process standard unit library is lower than the threshold voltage of the unit to be replaced. Second, the driving strength of the new standard unit is the same as the driving strength of the unit to be replaced. Third, the threshold voltage of the new standard unit is the same as the threshold voltage of the unit to be replaced. Fourth, the driving strength of the new standard unit is determined by the following method: First, the driving strength of the new standard unit is determined by the following method: Second, the driving strength of the new standard unit is determined by the following method: Third, the driving strength of the new standard unit is determined by the following method: Fourth, the driving strength of the new standard unit is determined by the following method: Fifth, the driving strength of the new standard unit is determined by the following method: Sixth ... S104. Based on the position of the unit to be replaced in the chip design diagram and the threshold voltage and driving strength of the new standard unit used to replace the unit to be replaced, replace all the units to be replaced in the chip design diagram with the corresponding new standard units. S105. Update the timing of each timing path in the chip design diagram; S106. Optimize the power consumption of the chip design using the standard power consumption optimization process.

2. The power consumption optimization method in chip design according to claim 1, characterized in that, The determination of timing paths with time margins in the chip design diagram further includes: The slack of each timing path in the chip design is calculated using a static timing analysis tool. When the slack is positive, the corresponding timing path is a timing path with time margin.

3. The power consumption optimization method in chip design according to claim 1, characterized in that, The method for determining the threshold voltage and driving strength of the new standard unit further includes: First, determine whether there is a next-level threshold voltage in the threshold voltage levels provided by the process standard unit library that is lower than the threshold voltage of the unit to be replaced. If so, the next-level threshold voltage is used as the threshold voltage of the new standard unit, and the driving strength of the new standard unit is the same as the driving strength of the unit to be replaced. Otherwise, the next-level driving strength in the driving strength levels provided by the process standard unit library that is higher than the driving strength of the unit to be replaced is used as the driving strength of the new standard unit, and the threshold voltage of the new standard unit is the same as the threshold voltage of the unit to be replaced.

4. The power consumption optimization method in chip design according to claim 1, characterized in that, S104 further includes: A unit replacement script is generated based on the position of the unit to be replaced in the chip design diagram and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced.

5. The power consumption optimization method in chip design according to claim 4, characterized in that, S105 further includes: The static timing analysis tool reads the cell replacement script and replaces all the cells to be replaced in the chip design with the corresponding new standard cells.

6. The power consumption optimization method in chip design according to claim 1, characterized in that, The threshold is 5 ps.

7. The power consumption optimization method in chip design according to claim 1, characterized in that, The standard power consumption optimization process is a standard power consumption optimization process based on EDA tools.

8. A power consumption optimization device in chip design, characterized in that, include: The first module is used to determine the timing paths with time margin in the chip design diagram, and filter out the timing paths with time margin less than a threshold to form a path set. The second module is used to determine whether there is at least one high-power standard unit in each timing path of the path set. If so, proceed to the next step; otherwise, ignore the path. The high-power standard unit is a standard unit whose threshold voltage is equal to the lowest threshold voltage of the process standard unit library and whose drive strength is greater than D10. The third module is used to further determine whether there is a slow standard unit in the timing path where there is at least one high-power standard unit. If so, the slow standard unit closest to the start point of the path is taken as the unit to be replaced, and the position of the unit to be replaced in the chip design diagram and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced are determined. The slow standard unit is defined as a standard unit whose threshold voltage is equal to the highest threshold voltage in the process standard unit library, whose drive strength is equal to the lowest drive strength in the process standard unit library, and whose delay is greater than twice the standard delay. The threshold voltage and drive strength of the new standard unit are determined as follows: The threshold voltage of the new standard unit is determined by the following method: First, the threshold voltage of the next lower level of the threshold voltage level provided by the process standard unit library is lower than the threshold voltage of the unit to be replaced. Second, the driving strength of the new standard unit is the same as the driving strength of the unit to be replaced. Third, the threshold voltage of the new standard unit is the same as the threshold voltage of the unit to be replaced. Fourth, the driving strength of the new standard unit is determined by the following method: First, the driving strength of the new standard unit is determined by the following method: Second, the driving strength of the new standard unit is determined by the following method: Third, the driving strength of the new standard unit is determined by the following method: Fourth, the driving strength of the new standard unit is determined by the following method: Fifth, the driving strength of the new standard unit is determined by the following method: Sixth ... The fourth module is used to replace all the units to be replaced in the chip design with the corresponding new standard units according to the position of the unit to be replaced in the chip design and the threshold voltage and drive strength of the new standard unit used to replace the unit to be replaced. The fifth module is used to update the timing of each timing path in the chip design diagram; The sixth module is used to optimize the power consumption of the chip design using a standard power optimization process.

9. An electronic device, characterized in that, The device includes a storage module comprising instructions loaded and executed by a processor, which, when executed, cause the processor to perform a power optimization method in a chip design according to any one of claims 1-7.

10. A computer-readable storage medium storing one or more programs, characterized in that, When the one or more programs are executed by the processor, they implement the power consumption optimization method in chip design as described in any one of claims 1-7.

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