Abnormal tracing method and system for chip test, computer equipment and storage medium

Abstract

The invention relates to the technical field of chip testing, and discloses a chip testing abnormity tracing method and system, computer equipment and a storage medium, and the method comprises the steps: comparing the recorded coding information of a testing socket corresponding to a Site position during testing with the coding information of the testing socket determined through code scanning in advance; whether inconsistency exists or not can be judged in time, so that manual input errors are avoided, the corresponding test socket can be accurately positioned when the chip has test abnormity, abnormity analysis or abnormity clarification can be accurately carried out, and the method is suitable for large-scale popularization and application.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular, to an abnormal traceability method, system, computer device, and storage medium for chip testing. Background Art

[0002] The Site location refers to a specific test location or station during the chip testing process. Each Site location usually corresponds to a specific test socket, and each test socket is matched with a specific test circuit design for specific test items of the finished chip.

[0003] Currently, during the process of detecting a finished chip using a test socket, the conventional process followed is that an operator manually enters the test socket code corresponding to the Site location where the test is being conducted as the on-machine information of the test socket and saves it to the server. Once any abnormality occurs during the test of the finished chip, the test socket code corresponding to the Site location where the abnormal chip was tested can be quickly retrieved from the saved on-machine information of the test socket through the server, so as to locate the specific test socket for subsequent abnormal analysis and problem clarification work.

[0004] However, this manual entry method is inevitably affected by adverse factors such as human negligence, resulting in the inability to fully guarantee the accuracy of the entry of the test socket code, and thus there are errors in the on-machine information of the test socket. When quality problems occur in the finished chip, it is difficult to accurately trace the specific test socket for in-depth abnormal analysis and problem clarification, which not only increases the difficulty of problem-solving but also easily leads to customer complaints and subsequent compensation issues.

[0005] In view of the existence of the above problems, it is particularly important to make necessary improvements and optimizations to the current technology.

[0006] The above information is given as background information only to assist in understanding the present disclosure, and does not determine or admit whether any of the above content can be used as prior art relative to the present disclosure. Summary of the Invention

[0007] The present invention provides an abnormal traceability method, system, computer device, and storage medium for chip testing to solve the problems existing in the prior art.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] In a first aspect, the present invention provides an abnormal traceability method for chip testing, and the method includes:

[0010] S1. Receive the encoded information of the test socket corresponding to the Site location during testing entered, and compare it with the encoded information of the test socket determined by pre-scanning the code. Determine whether they are consistent. If they are consistent, execute S2; if they are not consistent, first execute S3, and then return to execute S1;

[0011] S2. The entry is successful and saved as the on-machine information of the test socket for anomaly tracing when the chip test result is abnormal;

[0012] S3. The entry fails and prompts to re-enter.

[0013] Further, in the anomaly tracing method for chip testing, before S1, the method further includes:

[0014] S0. Scan the QR code of the Site location and the QR code of the test socket corresponding to the Site location to obtain the encoded information of the test socket and the encoded information of the Site location.

[0015] Further, in the anomaly tracing method for chip testing, S0 includes:

[0016] S0.1. Scan the QR code of the Site location and the QR code of the test socket corresponding to the Site location to obtain two scanned code information;

[0017] S0.2. Respectively determine whether the two scanned code information can be retrieved in the test socket list, and determine the scanned code information that can be retrieved as the encoded information of the test socket, and determine the other scanned code information that cannot be retrieved as the encoded information of the Site location.

[0018] Further, in the anomaly tracing method for chip testing, S0.1 includes:

[0019] S0.1.1. Scan the QR code of the Site location and the QR code of the test socket corresponding to the Site location to obtain two scanned code information;

[0020] S0.1.2. Use a separator to separate the two scanned code information.

[0021] Further, in the anomaly tracing method for chip testing, S0.1.1 includes:

[0022] When setting up the test product environment, scan the QR codes of all Site locations and the QR codes of the test sockets corresponding to each of the Site locations to obtain several groups of information. Each group of information includes two scanned information. One of the scanned information comes from the QR code of one of the Site locations, and the other scanned information comes from the QR code of the test socket corresponding to the Site location.

[0023] Alternatively, when replacing a certain test socket, scan the QR code of the Site location corresponding to the test socket and the QR code of the test socket to obtain two scanned information.

[0024] Further, in the method for abnormal traceability of chip testing, after S2, the method further includes:

[0025] S4. Detect whether the encoded information of the test socket in the saved on-machine information is a null value; if so, execute S5; if not, execute S6.

[0026] S5. The saving fails, and a prompt is given to save again.

[0027] S6. The saving is successful.

[0028] Further, in the method for abnormal traceability of chip testing, S2 includes:

[0029] S2.1. The input is successful, and the on-machine information of the test socket is saved to the server to retrieve the on-machine information from the server for abnormal traceability when the chip test result is abnormal.

[0030] In a second aspect, the present invention provides a system for abnormal traceability of chip testing. The system includes:

[0031] An information comparison module, configured to receive the encoded information of the test socket corresponding to the Site location where the test is conducted during input, and compare it with the encoded information of the test socket determined by pre-scanning to determine whether they are consistent.

[0032] A result execution module, configured to, if they are consistent, the input is successful, and the on-machine information of the test socket is saved for abnormal traceability when the chip test result is abnormal; if they are inconsistent, the input fails, and a prompt is given to re-enter.

[0033] In a third aspect, the present invention provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the method for abnormal traceability of chip testing provided in the first aspect above is implemented.

[0034] Fourthly, the present invention provides a computer-readable storage medium, on which computer-executable instructions are stored, and the computer-executable instructions are executed by a computer processor to implement the abnormal traceability method for chip testing provided in the first aspect as described above.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] An abnormal traceability method, system, computer device and storage medium for chip testing provided by the present invention can timely determine whether there is an inconsistent situation by comparing the encoded information of the test socket corresponding to the Site position where the test is performed during entry with the encoded information of the test socket determined by pre-scanning the code, so as to avoid manual entry errors, which is beneficial to accurately locate the corresponding test socket when a chip test anomaly occurs, so as to accurately perform anomaly analysis or anomaly clarification, and is suitable for wide promotion and application.

[0037] The present invention has other characteristics and advantages, which will be obvious from the accompanying drawings incorporated herein and the subsequent detailed description, or will be described in detail in the accompanying drawings incorporated herein and the subsequent detailed description. These accompanying drawings and detailed description are used together to explain the specific principles of the present invention. Description of the Drawings

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 is a schematic flowchart of an abnormal traceability method for chip testing provided in Embodiment 1 of the present invention;

[0040] Figure 2 is a schematic diagram of the functional modules of an abnormal traceability system for chip testing provided in Embodiment 2 of the present invention;

[0041] Figure 3 is a schematic diagram of the structure of a computer device provided in Embodiment 3 of the present invention. Detailed Description of the Embodiments

[0042] To illustrate in detail the possible application scenarios, technical principles, specific implementable solutions, achievable purposes and effects of the present application, the following will be described in detail in combination with the specific embodiments listed and the accompanying drawings. The embodiments described herein are only used to more clearly illustrate the technical solutions of the present application, so they are only examples and cannot be used to limit the protection scope of the present application.

[0043] As used herein, the mention of "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment may be included in at least one embodiment of the present application. The term "embodiment" appearing at various positions in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or relevance to other embodiments. In principle, in the present application, as long as there is no technical contradiction or conflict, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.

[0044] Unless otherwise defined, the meanings of the technical terms used herein are the same as those commonly understood by those skilled in the technical field to which the present application belongs; the use of the relevant terms herein is only for describing specific embodiments and is not intended to limit the present application.

[0045] In the description of the present application, the phrase "and / or" is an expression used to describe the logical relationship between objects, indicating that three relationships may exist. For example, A and / or B means: there is A, there is B, and there is both A and B at the same time. In addition, the character " / " in this article generally represents an "or" logical relationship between the associated objects before and after.

[0046] In the present application, terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantitative, primary or secondary, or sequential relationship between these entities or operations.

[0047] Without further limitation, in the present application, the use of "including", "comprising", "having" or other similar expressions in a statement is intended to cover non-exclusive inclusion. These expressions do not exclude the possibility that there may be additional elements in the process, method or product including the said elements, so that the process, method or product including a series of elements may include not only those defined elements, but also other elements not explicitly listed, or elements inherent to such process, method or product.

[0048] In the present application, expressions such as "greater than", "less than", "exceeding" are understood not to include the number itself; expressions such as "above", "below", "within" are understood to include the number itself. In addition, in the description of the embodiments of the present application, the meaning of "a plurality of" is two or more (including two), and similar expressions related to "many" are understood in the same way, such as "multiple groups", "multiple times", etc., unless otherwise specifically defined.

[0049] In the description of the embodiments of the present application, the spatially related expressions used, such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "perpendicular", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the specific embodiment or the accompanying drawings. It is only for the convenience of describing the specific embodiments of the present application or for the reader's understanding, rather than indicating or implying that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, it should not be construed as a limitation on the embodiments of the present application.

[0050] Unless otherwise clearly specified or limited, in the description of the embodiments of the present application, the terms "installed", "connected", "connected", "fixed", "set", etc. should be understood in a broad sense. For example, the "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication inside two components or the interaction relationship between two components. For those skilled in the art to which the present application pertains, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0051] Embodiment 1

[0052] Please refer to Figure 1 , which is a schematic flowchart of an abnormal traceability method for chip testing provided by Embodiment 1 of the present invention. The method specifically includes the following steps:

[0053] S1. Receive the coding information of the test socket corresponding to the Site position during the test entered, and compare it with the coding information of the test socket determined by pre-scanning the code to determine whether they are consistent; if they are consistent, execute S2; if they are not consistent, first execute S3, and then return to execute S1.

[0054] It should be noted that during chip testing, the operator will enter the coding information of the test socket used at the current test Site position. This coding information is unique and is used to identify a specific test socket.

[0055] Before the test starts, the coding information of the test socket has been pre-recorded and stored by means such as scanning the code. In S1, the system will compare the coding information entered by the operator with the pre-stored coding information. If the entered coding information is exactly the same as the pre-stored coding information, it indicates that the entry is correct and the next step, that is, S2, can be continued. If they are not consistent, it indicates that the entry is incorrect and S3 needs to be executed.

[0056] S2. The entry is successful and saved as the on-machine information of the test socket for anomaly tracing when the chip test result is abnormal.

[0057] It should be noted that the system will save the successful entry information as the on-machine information of the test socket. These information usually include the code of the test socket, the test time, the test Site location, etc.

[0058] These on-machine information will be used for anomaly tracing when the subsequent chip test result is abnormal. By searching for the on-machine information of the test socket associated with the abnormal chip test, the source of the problem can be quickly located for further analysis and processing.

[0059] S3. The entry fails and prompts to re-enter.

[0060] It should be noted that the system will prompt the operator to re-enter the correct test socket code information. The tester needs to operate according to the prompt until the entry is successful.

[0061] After the tester re-enters the correct code information, the system will execute step S1 again for comparison until the comparison is successful and step S2 is executed.

[0062] In summary, the anomaly tracing method for this chip test ensures the accuracy and traceability of the test socket information through strict code information comparison and entry processes, providing strong support for subsequent anomaly analysis and processing.

[0063] In a specific and detailed implementation manner of this embodiment, before step S1 of the entire anomaly tracing method for chip testing, there is also a crucial preparatory step, namely S0. The main task of step S0 is to comprehensively enter and initialize the information of the test environment to ensure the smooth progress of subsequent steps.

[0064] S0. Scan the QR code of the Site location and the QR code of the test socket corresponding to the Site location to obtain the code information of the test socket and the code information of the Site location.

[0065] It should be noted that before the test starts, it is first necessary to accurately locate the Site location where the test is conducted. For this purpose, we use the modern method of scanning the QR code on the Site location to quickly and accurately obtain the code information of this Site. This step ensures that the specific location of the test environment is clearly identified, laying a solid foundation for subsequent information comparison and anomaly tracing.

[0066] Next, we also need to scan the QR code on the test socket associated with the current Site location. This operation aims to obtain the unique coding information of the test socket, which is crucial for ensuring the accuracy of the test process and the accuracy of subsequent anomaly tracing.

[0067] Through the above two scans, we have successfully obtained the coding information of the Site location and the coding information of the test socket. These information will be stored by the system and used in subsequent comparison and tracing processes.

[0068] The introduction of the S0 step not only improves the informatization level of the test environment, but also provides comprehensive and accurate data support for subsequent anomaly tracing work. It ensures that the information of each key node in the test process is effectively recorded and saved, thus greatly enhancing the reliability and traceability of the test results.

[0069] In summary, the S0 step, as an indispensable part of this embodiment, provides a solid foundation and guarantee for the anomaly tracing method of the entire chip test. After completing the S0 step, the system can smoothly enter the S1 step to compare and judge the coding information.

[0070] In a carefully designed implementation manner of this embodiment, the S0 step is further refined into two specific sub-steps, namely S0.1 and S0.2, to ensure the accurate positioning of the test environment and the accuracy of the test socket information.

[0071] S0.1: Scan the QR code of the Site location and the QR code of the test socket corresponding to the Site location to obtain two scanning information;

[0072] It should be noted that first, we use advanced scanning technology to scan the QR code of the Site location where the test is located. This operation aims to obtain the unique identification information of the Site location, providing a key basis for subsequent information comparison and anomaly tracing.

[0073] Next, we also use scanning technology to scan the QR code of the test socket installed at the current Site location. This step aims to obtain the coding information of the test socket, which is crucial for ensuring the accuracy of the test process and the accuracy of subsequent anomaly tracing.

[0074] Through the above two scans, we have successfully obtained two important scanning information: one is the scanning information of the Site location, and the other is the scanning information of the test socket. These two information will be used in subsequent information retrieval and confirmation processes.

[0075] S0.2. Determine whether each of the two scanned code information can be retrieved from the test socket list respectively, and determine the scanned code information that can be retrieved as the coding information of the test socket, and determine the other scanned code information that cannot be retrieved as the coding information of the Site location.

[0076] It should be noted that after obtaining the two scanned code information, we need to perform a search in the test socket list next. This step aims to verify the accuracy of the attribution of the scanned code information, that is, to determine which scanned code information corresponds to the test socket and which corresponds to the Site location.

[0077] Specifically, if the search is successful, it means that the scanned code information does correspond to a valid test socket, that is, it indeed belongs to the test socket; if the search fails, it means that the scanned code information may not belong to the test socket.

[0078] According to the above search results, we can determine which of the two scanned code information corresponds to the coding information of the test socket and which corresponds to the coding information of the Site location. Specifically:

[0079] If the scanned code information of the test socket is successfully retrieved from the test socket list, it is determined as the coding information of the test socket.

[0080] If the scanned code information of the Site location is successfully retrieved from the corresponding list or database, it is determined as the coding information of the Site location.

[0081] The introduction of steps S0.1 and S0.2 not only improves the informatization level of the test environment, but also ensures the accuracy of the test socket and Site location information. Through the combination of code scanning and information retrieval, we can quickly and accurately obtain the key information of the test environment, providing comprehensive and reliable data support for subsequent anomaly traceability work. This design greatly enhances the reliability and traceability of test results.

[0082] In a more detailed and meticulous implementation manner of this embodiment, step S0.1 is further decomposed into two specific sub-steps, namely S0.1.1 and S0.1.2, to ensure the accurate acquisition and effective processing of the scanned code information.

[0083] S0.1.1. Scan the two-dimensional code of the Site location and the two-dimensional code of the test socket corresponding to the Site location to obtain two scanned code information;

[0084] It should be noted that first, we use a high-precision code scanning device to scan the two-dimensional code of the Site location where the test is located. This operation aims to accurately obtain the unique identification information of the Site location, laying a solid foundation for subsequent information comparison and anomaly traceability.

[0085] Immediately afterwards, we also adopt the barcode scanning technology to scan the two-dimensional code of the test socket configured at the current Site location. This step aims to obtain the coding information of the test socket, which is crucial for ensuring the accuracy of the test process, improving the test efficiency, and the accuracy of subsequent anomaly tracing.

[0086] Through the above two scans, we have successfully obtained two key barcode scanning information: one is the barcode scanning information of the Site location, which represents the specific location of the test environment; the other is the barcode scanning information of the test socket, which represents the specific device used in the current test. These two pieces of information will be used in the subsequent information processing and confirmation process.

[0087] S0.1.2. Use a separator to separate the two pieces of barcode scanning information.

[0088] It should be noted that after obtaining the two pieces of barcode scanning information, in order to avoid information confusion and misreading, we use a specific separator (such as a comma, semicolon, or space, etc.) to effectively separate the two pieces of information. This step aims to ensure that the barcode scanning information can be correctly identified and distinguished in the subsequent processing process, thereby improving the accuracy and efficiency of information processing.

[0089] Specifically, we will place the barcode scanning information of the Site location and the barcode scanning information of the test socket on both sides of the separator respectively to form a clear and easily recognizable information string. In this way, in the subsequent information retrieval, comparison, and confirmation process, the system can quickly and accurately identify these two pieces of barcode scanning information and then perform corresponding processing.

[0090] The introduction of steps S0.1.1 and S0.1.2 not only improves the acquisition efficiency and accuracy of the barcode scanning information but also ensures the clarity and recognizability of the barcode scanning information in the subsequent processing process. By combining barcode scanning and information separation processing, we can quickly and accurately obtain the key information of the test environment. This design greatly enhances the automation and intelligence level of the test process.

[0091] In a more detailed and flexible implementation manner of this embodiment, step S0.1.1 is given higher adaptability and practicality to meet the requirements of different test scenarios. Specifically, step S0.1.1 is designed into two operation modes, which are respectively applicable to the scenarios of setting up the test product environment and replacing the test socket, that is:

[0092] When setting up the test product environment, scan the QR codes of all Site locations and the QR codes of the test sockets corresponding to each of the Site locations to obtain several groups of information groups. Each group of information groups includes two scanned code information, where one of the scanned code information comes from the QR code of one of the Site locations, and the other scanned code information comes from the QR code of the test socket corresponding to the Site location;

[0093] Or, when replacing a certain test socket, scan the QR code of the Site location corresponding to the test socket and the QR code of the test socket to obtain two scanned code information.

[0094] It should be noted that at the beginning of setting up the test product environment, we will scan the QR codes of all test Site locations. This operation aims to ensure that each test location has an accurate and unique identifier, providing basic data for subsequent information comparison and anomaly tracing.

[0095] Immediately afterwards, for each Site location, we will scan the QR code on the corresponding test socket. This step aims to obtain the coding information of each test socket, which is crucial for ensuring the accuracy of the test process, improving the test efficiency, and the accuracy of subsequent anomaly tracing.

[0096] Through the above two scans, we have successfully obtained several groups of information groups. Each group of information groups includes two scanned code information: one is the scanned code information of the Site location, which represents the specific location of the test environment; the other is the scanned code information of the test socket, which represents the specific device used at the current test location. These information groups will be used in the subsequent information processing and confirmation process.

[0097] When a certain test socket needs to be replaced during the test process, we first need to scan the QR code of the Site location corresponding to the test socket. This operation aims to ensure that we can still accurately identify the specific location of the test environment, providing a basis for subsequent information comparison.

[0098] Immediately afterwards, we will scan the QR code on the newly replaced test socket to obtain its coding information. This step is crucial for ensuring the continuity of the test process, improving the test efficiency, and avoiding information confusion.

[0099] Through the above two scans, we have successfully obtained two key scanned code information: one is the scanned code information of the Site location, and the other is the scanned code information of the newly replaced test socket. These two pieces of information will be used in the subsequent information update and confirmation process.

[0100] The design of these two operation modes in step S0.1.1 not only improves the acquisition efficiency and accuracy of the scanned code information, but also ensures the clarity and recognizability of the scanned code information during subsequent processing. By flexibly selecting the applicable operation mode, we can quickly and accurately obtain the key information of the test environment, providing strong guarantee for subsequent information comparison, anomaly tracing, and the reliability of test results. This design greatly enhances the flexibility and adaptability of the test process, providing solid technical support for the smooth progress of chip testing.

[0101] In a more complete and detailed implementation manner of this embodiment, in order to further improve the reliability and accuracy of the test process, we added an additional detection and saving process after step S2, namely steps S4, S5, and S6. This process aims to ensure the integrity of the coding information of the test socket in the information uploaded to the machine, thereby avoiding test errors or difficulties in anomaly tracing caused by missing information, that is:

[0102] S4. Detect whether the coding information of the test socket in the saved information uploaded to the machine is a null value; if so, execute S5; if not, execute S6;

[0103] It should be noted that after step S2, the system will obtain and detect the saved information uploaded to the machine. These information usually contain various key data required during the test process, such as test time, test personnel, test equipment (i.e., test socket), etc.

[0104] During the detection process, the system will pay special attention to the coding information of the test socket. This information is crucial for ensuring the accuracy of the test process and the accuracy of subsequent anomaly tracing. Therefore, the system will determine whether this coding information is a null value, that is, whether it has not been correctly filled or obtained.

[0105] If it is detected that the coding information of the test socket is a null value, it means that the information uploaded to the machine is incomplete, and the system will execute step S5; if the coding information is not a null value, it means that the information uploaded to the machine is complete and accurate, and the system will execute step S6.

[0106] S5. Save failed and prompt to save again;

[0107] It should be noted that when the system determines that the coding information of the test socket is a null value, it will immediately stop the current saving operation and mark it as a failed save.

[0108] At the same time, the system will send a clear prompt message to the user, informing that the coding information of the test socket in the information uploaded to the machine is a null value, and the user needs to re-fill or obtain this information and try to save again.

[0109] S6. Save successfully.

[0110] It should be noted that when the system determines that the coding information of the test socket is not a null value, it will continue to perform the save operation and mark it as saved successfully. At this time, all key data in the on-machine information (including the coding information of the test socket) have been correctly filled in and saved to the system.

[0111] The introduction of steps S4, S5, and S6 not only improves the reliability and accuracy of the test process but also ensures the integrity and traceability of the on-machine information. By detecting whether the coding information of the test socket is a null value and performing corresponding operations based on the judgment result, we can effectively avoid test errors or difficulties in abnormal traceability caused by missing information.

[0112] In a more detailed implementation manner of this embodiment, the specific content of step S2, that is, how to process and save the on-machine information of the test socket, is described in detail. The following is the detailed breakdown of step S2:

[0113] S2.1. The input is successful, and the on-machine information of the test socket is saved to the server to retrieve the on-machine information from the server for abnormal traceability when the chip test result is abnormal.

[0114] It should be noted that the system will save the sorted on-machine information to a specified location or database of the server. The server is usually a system for centralized storage and management of data, which provides reliable data storage and access capabilities.

[0115] An important purpose of saving this information is to be able to quickly and accurately retrieve the relevant on-machine information from the server for abnormal traceability when the chip test result is abnormal. Abnormal traceability means analyzing various parameters and data in the test process to find out the reasons for the abnormal test results. By retrieving the on-machine information, technicians can understand the specific conditions and environment during the test, thus more effectively locating the problem.

[0116] The detailed implementation of step S2.1 not only ensures the accuracy and integrity of the on-machine information of the test socket but also provides important data support for subsequent abnormal traceability. By saving the information to the server, the system realizes the centralized management and long-term storage of data, enabling quick and convenient access to this information when needed. This design greatly improves the reliability and traceability of the test process.

[0117] At the same time, the implementation of step S2.1 also reflects the automation and intelligent level of the system design. By automatically inputting and saving information, the system reduces human operation errors and omissions, improving work efficiency and accuracy.

[0118] Although terms such as chips and test sockets are used more frequently in this application, the possibility of using other terms is not excluded. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitation is contrary to the spirit of the present invention.

[0119] An abnormal traceability method for chip testing provided by an embodiment of the present invention can timely determine whether there is an inconsistent situation by comparing the encoded information of the test socket corresponding to the Site position where the test is performed, which is entered, with the encoded information of the test socket determined by pre-scanning the code, so as to avoid manual entry errors, facilitate accurately positioning the corresponding test socket when a chip test is abnormal, and accurately perform abnormal analysis or abnormal clarification, and is suitable for wide promotion and application.

[0120] Embodiment 2

[0121] Please refer to Figure 2 , an abnormal traceability system for chip testing provided by Embodiment 2 of the present invention, the system includes:

[0122] An information comparison module 201, configured to receive the encoded information of the test socket corresponding to the Site position where the test is performed, and compare it with the encoded information of the test socket determined by pre-scanning the code to determine whether they are consistent;

[0123] A result execution module 202, configured to, if they are consistent, the entry is successful, and save it as the on-machine information of the test socket for abnormal traceability when the chip test result is abnormal; if they are inconsistent, the entry fails, and prompt to re-enter.

[0124] Preferably, the system further includes a code scanning module, configured to:

[0125] S0. Scan the two-dimensional code of the Site position and the two-dimensional code of the test socket corresponding to the Site position to obtain the encoded information of the test socket and the encoded information of the Site position.

[0126] Preferably, the code scanning module is specifically configured to:

[0127] S0.1. Scan the two-dimensional code of the Site position and the two-dimensional code of the test socket corresponding to the Site position to obtain two code scanning information;

[0128] S0.2. Respectively determine whether the two code scanning information can be retrieved in the test socket list, and determine the one code scanning information that can be retrieved as the encoded information of the test socket, and determine the other code scanning information that cannot be retrieved as the encoded information of the Site position.

[0129] Preferably, the code scanning module is specifically configured to:

[0130] S0.1.1. Scan the QR code at the Site location and the QR code of the test socket corresponding to the Site location to obtain two scanned code messages;

[0131] S0.1.2. Use a separator to separate the two scanned code messages.

[0132] 5. The method for abnormal traceability of chip testing according to claim 4, wherein S0.1.1 includes:

[0133] When setting up the test product environment, scan the QR codes at all Site locations and the QR codes of the test sockets corresponding to each Site location to obtain several groups of information groups. Each group of information groups includes two scanned code messages, one of which comes from the QR code of a Site location and the other comes from the QR code of the test socket corresponding to the Site location;

[0134] Or, when replacing a certain test socket, scan the QR code of the Site location corresponding to the test socket and the QR code of the test socket to obtain two scanned code messages.

[0135] Preferably, the system further includes a detection and saving module for, after S2:

[0136] S4. Detect whether the encoded information of the test socket in the saved on-machine information is a null value; if so, execute S5; if not, execute S6;

[0137] S5. Saving fails and prompts to save again;

[0138] S6. Saving is successful.

[0139] Preferably, the result execution module is specifically used for:

[0140] S2.1. The entry is successful and saved as the on-machine information of the test socket to the server so as to retrieve the on-machine information from the server for abnormal traceability when the chip test result is abnormal.

[0141] The above system can execute the method provided in any embodiment of the present invention and has the corresponding functional modules and beneficial effects of the executed method.

[0142] Embodiment III

[0143] Figure 3 It is a schematic structural diagram of a computer device provided in Embodiment III of the present invention. Figure 3 It shows a block diagram of an exemplary computer device 12 suitable for implementing the embodiments of the present invention. Figure 3The computer device 12 shown is merely an example and should not impose any limitation on the functions and scope of use of the embodiments of the present invention.

[0144] As Figure 3 shown, the computer device 12 appears in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that connects different system components (including the system memory 28 and the processing unit 16).

[0145] The bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus structures. By way of example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0146] The computer device 12 typically includes a variety of computer system-readable media. These media can be any available media that can be accessed by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0147] The system memory 28 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 can be used to read and write non-removable, non-volatile magnetic media ( Figure 3 not shown, typically referred to as a "hard disk drive"). Although Figure 3 not shown in the figure, a disk drive for reading and writing removable non-volatile disks (such as "floppy disks") and an optical disk drive for reading and writing removable non-volatile optical disks (such as CD-ROM, DVD-ROM, or other optical media) can be provided. In these cases, each drive can be connected to the bus 18 through one or more data media interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the embodiments of the present invention.

[0148] A program / utilities 40 having a set (at least one) of program modules 42 can be stored, for example, in a memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 42 generally execute the functions and / or methods in the embodiments described in the present invention.

[0149] The computer device 12 can also communicate with one or more external devices 14 (such as a keyboard, a pointing device, a display 24, etc.), and can also communicate with one or more devices that enable a user to interact with the computer device 12, and / or communicate with any device that enables the computer device 12 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through an input / output (I / O) interface 22. Moreover, the computer device 12 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the computer device 12 through a bus 18. It should be understood that although Figure 3 not shown in the figure, other hardware and / or software modules can be used in combination with the computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0150] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the abnormal traceback method for chip testing provided in the embodiments of the present invention.

[0151] Embodiment 4

[0152] Embodiment 4 of the present invention provides a computer-readable storage medium, on which computer-executable instructions are stored. When the instructions are executed by a processor, the abnormal traceback method for chip testing provided in all the invention embodiments of the present application is implemented.

[0153] Any combination of one or more computer-readable media may be employed. The computer-readable media may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0154] A computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which the computer-readable program code is carried. Such a propagated data signal may take any of a variety of forms, including—but not limited to—electromagnetic signals, optical signals, or any suitable combination of the foregoing. The computer-readable signal medium may also be any computer-readable medium that is not a computer-readable storage medium and that can send, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0155] The program code embodied on the computer-readable medium may be transmitted using any appropriate medium, including—but not limited to—wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0156] The computer program code for carrying out operations of the present invention may be written in one or more programming languages, or combinations thereof, including object-oriented programming languages such as Java, Smalltalk, C++, as well as conventional procedural programming languages such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0157] Finally, it should be noted that although the above embodiments have been described in the text of the specification and the drawings of this application, the patent protection scope of this application cannot be limited thereby. Any technical solutions resulting from equivalent structural or equivalent process substitutions or modifications made based on the essential concept of this application and using the content recorded in the text of the specification and the drawings of this application, as well as those directly or indirectly implementing the technical solutions of the above embodiments in other related technical fields, etc., are all included within the patent protection scope of this application.

Claims

1. A chip test abnormality tracing method, characterized in that: The method comprises: S1, receiving the coding information of the test socket corresponding to the site location at the time of the test, and comparing it with the coding information of the test socket determined by scanning the code in advance to determine whether they are consistent; if they are consistent, executing S2; if they are inconsistent, executing S3 first, and then returning to execute S1; S2. The data is successfully entered and saved as the on-machine information of the test socket, so as to perform abnormal tracing when abnormal chip test results are found; S3. The input fails and prompts you to input again.

2. The abnormality tracing method for chip testing according to claim 1, characterized in that: Before S1, the method further includes: S0. Scan the QR code of the Site location and the QR code of the test socket corresponding to the Site location to obtain the coding information of the test socket and the coding information of the Site location.

3. The abnormality tracing method for chip testing according to claim 2, characterized in that: The S0 includes: S0.

1. Scan the QR code of the site location and the QR code of the test socket corresponding to the site location to obtain two scanned code information; S0.

2. Determine whether the two scan code information can be retrieved in the test socket list respectively, and determine the scan code information that can be retrieved as the coding information of the test socket, and determine the other scan code information that cannot be retrieved as the coding information of the Site location.

4. The abnormality tracing method for chip testing according to claim 3, characterized in that: The S0.1 includes: S0.1.

1. Scan the QR code of the site location and the QR code of the test socket corresponding to the site location to obtain two scanned code information; S0.1.

2. Use a separator to separate the two scanned code information.

5. The abnormality tracing method for chip testing according to claim 4, characterized in that: S0.1.1 includes: When setting up a test product environment, scan the QR codes of all site locations and the QR codes of the test sockets corresponding to each site location to obtain several groups of information, each of which includes two scanned code information, one of which comes from the QR code of one site location, and the other comes from the QR code of the test socket corresponding to the site location; Or, when replacing a test socket, scan the QR code of the Site location corresponding to the test socket and the QR code of the test socket to obtain two scanned code information.

6. The abnormality tracing method for chip testing according to claim 1, characterized in that: After S2, the method further includes: S4, detecting whether the coding information of the test socket in the saved on-machine information is a null value; if so, executing S5; if not, executing S6; S5, saving fails, and prompts to save again; S6. Save successfully.

7. The abnormality tracing method for chip testing according to claim 1, characterized in that: The S2 includes: S2.

1. The input is successful and saved as the on-machine information of the test socket to the server, so that when an abnormality occurs in the chip test result, the on-machine information can be retrieved from the server for abnormality tracing.

8. A chip test abnormality tracing system, characterized in that: The system comprises: An information comparison module is used to receive the coding information of the test socket corresponding to the site location at the time of the test, and compare it with the coding information of the test socket determined by scanning the code in advance to determine whether they are consistent; The result execution module is used to record successfully if they are consistent and save it as the machine information of the test socket to trace the abnormality when the chip test result is abnormal; if they are inconsistent, the recording fails and prompts to re-enter.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the abnormality tracing method for chip testing according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that: The computer executable instructions are executed by a computer processor to implement the abnormality tracing method for chip testing as described in any one of claims 1-7.

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