Display panel driving method and display device

Abstract

The invention discloses a display panel driving method and a display device.The display panel driving method comprises the steps that a refresh frequency switching instruction is received, and the refresh frequency switching instruction is an instruction for controlling a display panel to be switched from a first refresh frequency to a second refresh frequency; generating an input first video signal with a first image resolution and a first frame rate into a second video signal with a second image resolution and a second frame rate according to the refresh frequency switching instruction; and outputting a scanning driving signal corresponding to the second refresh frequency and the second video signal to a plurality of pixels of the display panel. According to the invention, frequency multiplication driving can be realized in display panels with different driving architectures.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a method for driving a display panel and a display device. Background Art

[0002] Most of the existing display panels adopt a 1G1D (One Gate line One Data line) driving architecture, and the number of source driver chips is 12, resulting in a relatively high cost. To reduce the cost, a UHD (Ultra High Definition) Tri-gate driving architecture is now adopted. Under this driving architecture, the number of source driver chips of the display panel is reduced to 4, significantly reducing the cost. However, the existing frequency doubling driving technology (doubling from 60Hz to 120Hz) cannot be applied to the Tri-gate driving architecture, which causes the Tri-gate driving architecture to only operate in the 60Hz mode and cannot achieve a high refresh rate display of 120Hz.

[0003] In summary, the existing frequency doubling driving technology cannot be applied to display panels with different driving architectures.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0005] The present application provides a method for driving a display panel and a display device, which can achieve frequency doubling driving in display panels with different driving architectures.

[0006] The present application provides a method for driving a display panel. The method for driving a display panel includes: receiving a refresh frequency switching instruction, where the refresh frequency switching instruction is an instruction for controlling the display panel to switch from a first refresh frequency to a second refresh frequency; generating a second video signal with a second image resolution and a second frame rate according to the refresh frequency switching instruction from the input first video signal with a first image resolution and a first frame rate; and outputting a scan driving signal corresponding to the second refresh frequency and the second video signal to a plurality of pixels of the display panel.

[0007] In the above method for driving a display panel, the generating a second video signal with a second image resolution and a second frame rate according to the refresh frequency switching instruction from the input first video signal with a first image resolution and a first frame rate includes: generating a third video signal with the first image resolution and the second frame rate according to the refresh frequency switching instruction; and generating the second video signal from the third video signal.

[0008] In the above display panel driving method, the second refresh frequency is twice the first refresh frequency, and the second frame rate is twice the first frame rate; the generating the third video signal with the first image resolution and the second frame rate from the first video signal according to the refresh frequency switching instruction includes: generating two first video signals from one first video signal according to the refresh frequency switching instruction; combining the two first video signals into the third video signal, wherein the (2L - 1)-th frame image and the 2L-th frame image in the third video signal are the same and are the same as the L-th frame image in the first video signal, where L is a positive integer; the generating the second video signal from the third video signal includes: extracting the image data of the odd columns in the M-th frame image in the third video signal and the image data of the even columns in the (M + 1)-th frame image in the third video signal, where M is a positive integer; generating the second video signal according to the image data of the odd columns in the M-th frame image and the image data of the even columns in the (M + 1)-th frame image, wherein the image data of the M-th frame image in the second video signal includes the image data of the odd columns in the M-th frame image in the third video signal, and the image data of the (M + 1)-th frame image in the second video signal includes the image data of the even columns in the (M + 1)-th frame image in the third video signal.

[0009] In the above display panel driving method, the outputting the scan driving signal corresponding to the second refresh frequency and the second video signal to the multiple pixels of the display panel includes: according to the second refresh frequency, outputting the image data of the P columns in the N-th frame image in the second video signal to the P pixels of the odd columns of the display panel during the driving period of the N-th frame image, and outputting a common voltage to the P pixels of the even columns of the display panel during the driving period of the N-th frame image; outputting the image data of the P columns in the (N + 1)-th frame image in the second video signal to the P pixels of the even columns of the display panel during the driving period of the (N + 1)-th frame image and outputting the common voltage to the P pixels of the odd columns of the display panel during the driving period of the (N + 1)-th frame image; wherein, both N and P are positive integers.

[0010] In the above display panel driving method, the output of the scan driving signal corresponding to the second refresh frequency and the second video signal to multiple pixels of the display panel includes: according to the second refresh frequency, within the driving period of the Nth frame image, output the P-column image data of the Nth frame image in the second video signal to the pixels of P odd-numbered columns of the display panel, and disconnect the current path between the source driving circuit of the display panel and the pixels of P even-numbered columns of the display panel within the driving period of the Nth frame image; within the driving period of the (N + 1)th frame image, output the P-column image data of the (N + 1)th frame image in the second video signal to the pixels of P even-numbered columns of the display panel, and disconnect the current path between the source driving circuit and the pixels of P odd-numbered columns of the display panel within the driving period of the (N + 1)th frame image; where N and P are both positive integers.

[0011] In the above display panel driving method, the generation of the second video signal with the second image resolution and the second frame rate from the input first video signal with the first image resolution and the first frame rate according to the refresh frequency switching instruction includes: according to the refresh frequency switching instruction, scale the first video signal to a fourth video signal with the second image resolution and the first frame rate; generate two fourth video signals from one fourth video signal; and composite the two fourth video signals into the second video signal, where the (2L - 1)th frame image and the 2Lth frame image in the second video signal are the same and are the same as the Lth frame image in the fourth video signal, and L is a positive integer.

[0012] In the above display panel driving method, the output of the scan driving signal corresponding to the second refresh frequency and the second video signal to multiple pixels of the display panel includes: copy the P-column image data of the Qth frame image in the second video signal into 2P-column image data; within the driving period of the Qth frame image, output the 2P-column image data to the pixels of 2P columns of the display panel, where the two identical columns of the 2P-column image data obtained after copying are output to the adjacent two columns of pixels of the display panel, and P and Q are both positive integers.

[0013] The present application further provides a display device, which includes a display panel and a control chip. The display panel includes a gate driving circuit, a source driving circuit, and a plurality of pixels. The control chip is electrically connected to the gate driving circuit and the source driving circuit of the display panel, and both the gate driving circuit and the source driving circuit are electrically connected to the plurality of pixels. The control chip is configured to receive a refresh frequency switching instruction, and is configured to generate a second video signal with a second image resolution and a second frame rate from the input first video signal with a first image resolution and a first frame rate according to the refresh frequency switching instruction, and is configured to output the scanning driving signal corresponding to the second refresh frequency and the second video signal to the plurality of pixels of the display panel through the gate driving circuit and the source driving circuit. Wherein, the refresh frequency switching instruction is an instruction for controlling the display panel to switch from a first refresh frequency to a second refresh frequency.

[0014] In the above display device, the second refresh frequency is twice the first refresh frequency, and the second frame rate is twice the first frame rate. The control chip is configured to generate two first video signals from one first video signal according to the refresh frequency switching instruction, and is configured to combine the two first video signals into the third video signal, and is configured to extract the image data of the odd-numbered columns in the Mth frame image of the third video signal and the image data of the even-numbered columns in the (M + 1)th frame image of the third video signal, and is configured to generate the second video signal according to the image data of the odd-numbered columns in the Mth frame image and the image data of the even-numbered columns in the (M + 1)th frame image. Wherein, the (2L - 1)th frame image in the third video signal is the same as the 2Lth frame image and is the same as the Lth frame image in the first video signal, L and M are both positive integers, the image data of the Mth frame image in the second video signal includes the image data of the odd-numbered columns in the Mth frame image of the third video signal, and the image data of the (M + 1)th frame image in the second video signal includes the image data of the even-numbered columns in the (M + 1)th frame image of the third video signal.

[0015] In the above display device, the source driver circuit includes a data register and a latch. The data register is electrically connected to the latch, and the latch is electrically connected to multiple columns of pixels of the display panel. The data register is configured to output the P-column image data of the Nth frame image in the second video signal to the pixels of the P odd-numbered columns of the display panel during the driving period of the Nth frame image according to the second refresh frequency, and is configured to output a common voltage to the pixels of the P even-numbered columns of the display panel during the driving period of the Nth frame image, and is configured to output the P-column image data of the (N + 1)th frame image in the second video signal to the pixels of the P even-numbered columns of the display panel during the driving period of the (N + 1)th frame image, and is configured to output the common voltage to the pixels of the P odd-numbered columns of the display panel during the driving period of the (N + 1)th frame image; or, the data register or the latch is configured to output the P-column image data of the Nth frame image in the second video signal to the pixels of the P odd-numbered columns of the display panel during the driving period of the Nth frame image according to the second refresh frequency, and is configured to disconnect the current path between the source driver circuit of the display panel and the pixels of the P even-numbered columns of the display panel during the driving period of the Nth frame image, and is configured to output the P-column image data of the (N + 1)th frame image in the second video signal to the pixels of the P even-numbered columns of the display panel during the driving period of the (N + 1)th frame image, and is configured to disconnect the current path between the source driver circuit and the pixels of the P odd-numbered columns of the display panel during the driving period of the (N + 1)th frame image; where N and P are both positive integers.

[0016] In the above display device, the source driver circuit includes an output controller, and the output controller is electrically connected to multiple columns of pixels. The output controller is configured to turn on the current path between the source driver circuit and the pixels of the P odd-numbered columns of the display panel during the driving period of the Nth frame image, and disconnect the current path between the source driver circuit and the pixels of the P even-numbered columns of the display panel, and to turn on the current path between the source driver circuit and the pixels of the P even-numbered columns of the display panel during the driving period of the (N + 1)th frame image, and disconnect the current path between the source driver circuit and the pixels of the P odd-numbered columns of the display panel.

[0017] In the above display device, the control chip is configured to scale the first video signal into a fourth video signal having a second image resolution and a first frame rate according to the refresh frequency switching instruction, and is configured to generate two fourth video signals from one fourth video signal, and is configured to combine the two fourth video signals into the second video signal; wherein, the (2L - 1)-th frame image in the second video signal is the same as the 2L-th frame image and is the same as the L-th frame image in the fourth video signal, and L is a positive integer.

[0018] In the above display device, the source driver circuit is configured to copy the P-column image data of the Q-th frame image in the second video signal into 2P-column image data, and is configured to output the 2P-column image data to the pixels of 2P columns of the display panel within the driving period of the Q-th frame image; wherein, two identical columns of the copied 2P-column image data are output to the pixels of two adjacent columns of the display panel, and both P and Q are positive integers.

[0019] The technical solution of this application reconstructs the input low-frame-rate video signal according to the refresh frequency switching instruction to generate a high-frame-rate video signal that matches the high refresh frequency, and controls the gate driver circuit to output a scan driving signal that matches the high refresh frequency according to the high refresh frequency, and controls the source driver circuit to output the reconstructed video signal to the display panel in a high refresh frequency manner. In this way, regardless of the driving architecture adopted by the display panel, the switching from a low refresh rate to a high refresh rate can be achieved without changing the hardware circuit. For example, the display panel based on the DLG driving technology with a 1G1D driving architecture can be switched from 60Hz to 120Hz, or the display panel with a three-gate driving architecture can be switched from 60Hz to 120Hz without changing the wiring of the display panel. This technical solution overcomes the problem that it is difficult for panels with different driving methods to be compatible with frequency doubling driving, realizes the effect of frequency doubling display in display panels with different driving architectures, and improves the compatibility and applicability of frequency doubling display. Description of the Drawings

[0020] Figure 1 It is a schematic diagram of a display panel with a three-gate driving architecture in the related art.

[0021] Figure 2 It is a schematic diagram of the display device provided by this application.

[0022] Figure 3 It is a schematic diagram of the scan driving timing of the display device in the related art at the normal refresh frequency.

[0023] Figure 4 It is a schematic diagram of the scan driving timing of the display device provided by this application at the frequency doubling refresh frequency.

[0024] Figure 5 This is a schematic diagram of the first working principle of the display device provided by this application.

[0025] Figure 6 It is Figure 5 a block diagram of the source driver circuit shown.

[0026] Figure 7 This is a schematic diagram of the second working principle of the display device provided by this application.

[0027] Figure 8 It is Figure 7 a block diagram of the source driver circuit shown.

[0028] Figure 9 This is a schematic diagram of the third working principle of the display device provided by this application.

[0029] Figure 10 It is Figure 9 a block diagram of the source driver circuit shown. Detailed implementation manners

[0030] Next, the technical solutions in the embodiments of this application will be described with reference to the accompanying drawings in the embodiments of this application. The technical solutions described below are only used to explain and illustrate the idea of this application, and should not be regarded as a limitation on the protection scope of this application.

[0031] In addition, terms such as "first" and "second" do not indicate any order, quantity, or importance, but are only used to distinguish different technical features. Terms such as "multiple" and similar words mean two or more, unless otherwise clearly defined.

[0032] Currently, display panels using Dual Line Gate (DLG) technology meet the demand for high refresh rates. Display panels using DLG technology can achieve high refresh rate displays such as 120Hz on the basis of a conventional one-gate-one-source (1G1D) architecture.

[0033] In an Ultra High Definition (UHD) display panel, the drive architecture with the lowest cost is the Tri-gate drive architecture, as Figure 1 shown. Compared with the 1G1D drive architecture that requires 12 source driver chips, the Tri-gate drive architecture only requires 4 source driver chips. Therefore, the Tri-gate drive architecture is expected to replace the DLG drive technology based on the 1G1D drive architecture and become the mainstream drive architecture for UHD display panels.

[0034] However, the traditional three-gate drive architecture has such a defect: pixels in adjacent rows are pixels of different colors, and directly applying the DLG drive technology in the display panel of the three-gate drive architecture will lead to serious display problems. In other words, the DLG technology is not suitable for display panels of the three-gate drive architecture. At present, there is no solution in the industry that can achieve switching between 60Hz refresh rate and 120Hz refresh rate in a display device of the three-gate drive architecture.

[0035] In order to reduce costs while taking into account the high refresh rate display, it is urgent to study a technical solution to achieve the switch between 60Hz refresh rate (conventional refresh rate) and 120Hz high refresh rate in a display device with a three-gate drive architecture. This is an important technical problem facing current display technology.

[0036] In view of this, a first embodiment of the present application provides a display panel driving method and a display device. The display panel driving method is operated in the display device provided by the present application. Figure 2 As shown, the display device includes a display panel 400 and a control chip, the display panel includes a gate driving circuit, a source driving circuit and a plurality of pixels, the control chip is electrically connected to the gate driving circuit and the source driving circuit of the display panel, and the gate driving circuit and the source driving circuit are both electrically connected to the plurality of pixels.

[0037] The display panel 400 may be, for example, one of LCD, OLED, Mini-LED, Micro-LED, etc. The gate driving circuit 200 may be integrated in the display panel 400. The column resolution of the display panel 400 is 2P, that is, the display panel 400 includes 2P columns of pixels, where P is a positive integer.

[0038] The display panel 400 includes multiple pixels (multiple rows of pixels, multiple columns of pixels), multiple scan lines and multiple data lines. One scan line is electrically connected to a row of pixels, and one data line is electrically connected to a column of pixels. The start control signal (STV), the reset signal (Reset), and the clock signal (CK1-CK12) are input into the gate drive circuit 200 to control the gate drive circuit 200 to scan multiple rows of pixels.

[0039] The display panel driving method of this embodiment includes the following steps:

[0040] The control chip receives a refresh frequency switching instruction, where the refresh frequency switching instruction is an instruction for controlling the display panel 400 to switch from a first refresh frequency to a second refresh frequency. The refresh frequency switching instruction can be generated according to the action of the user operating a hardware button on the electronic device, or can be generated according to the action of the user operating a software button on the display interface, or can be generated according to a voice instruction, a gesture instruction, etc. issued by the user.

[0041] The control chip generates a second video signal with a second image resolution and a second frame rate from the input first video signal with a first image resolution and a first frame rate according to the refresh frequency switching instruction.

[0042] The control chip outputs the scan driving signal corresponding to the second refresh frequency and the second video signal to a plurality of pixels of the display panel through the gate driving circuit and the source driving circuit.

[0043] Specifically, the gate driving circuit 200 outputs a scan driving signal corresponding to the second refresh frequency to multiple rows of pixels of the display panel 400 according to a timing control signal corresponding to the second refresh frequency. The source driving circuit 300 outputs the second video signal to multiple columns of pixels of the display panel 400 according to a timing control signal corresponding to the second refresh frequency.

[0044] The gate driving circuit 200 outputs a scan driving signal according to the refresh frequency switching instruction, and the scan driving signal is a signal for progressive scanning. For example, when the refresh frequency switching instruction is to switch the refresh frequency of the display panel 400 from the second refresh frequency to the first refresh frequency, the gate driving circuit 200 outputs a first scan driving signal corresponding to the first refresh frequency according to the refresh frequency switching instruction. When the refresh frequency switching instruction is to switch the refresh frequency of the display panel 400 from the first refresh frequency to the second refresh frequency, the gate driving circuit 200 of the display panel 400 outputs a second scan driving signal corresponding to the second refresh frequency according to the refresh frequency switching instruction.

[0045] A high-potential signal for the refresh frequency switching instruction indicates that the user needs to switch the refresh frequency of the display panel 400 from the first refresh frequency to the second refresh frequency; a low-potential signal for the refresh frequency switching instruction indicates that the user needs the refresh frequency of the display panel 400 to switch from the second refresh frequency to the first refresh frequency. Vice versa.

[0046] Wherein, the second refresh frequency is twice, three times, four times, and so on of the first refresh frequency.

[0047] Such asFigure 3 As shown, the display device further includes a power management chip, the model of which is CS602, integrating three functions of power management, generating gamma voltage, and level conversion. The level converter or level shift IC of the display device has a model number of 50138B. In order to reduce the temperature rise and power consumption at a 120Hz refresh rate, the display device adopts a technical solution of using the power management chip of CS602 in combination with the level conversion chip of 50138B.

[0048] Among them, the power management chip provides the required power supply voltage for the gate driving circuit 200, the source driving circuit 300, the control chip 100, and the display panel 400. The level conversion chip provides the corresponding high potential (VGH) and low potential (VGL) for the gate driving circuit 200.

[0049] Among them, CS602 / CK1 and CS602 / CK2 are two clock signals in the power management chip. 50138B / CK1 and 50138B / CK2 are two clock signals in the level conversion chip.

[0050] The time corresponding to the first rising edge of the clock signal CS602 / CK1 is the same as the time corresponding to the first rising edge of CK1, and the time corresponding to the second rising edge of the clock signal CS602 / CK1 is the same as the time corresponding to the first rising edge of CK3. The time corresponding to the first falling edge of the clock signal CS602 / CK2 is the same as the time corresponding to the first falling edge of CK1, and the time corresponding to the second falling edge of the clock signal CS602 / CK2 is the same as the time corresponding to the first falling edge of CK3.

[0051] The time corresponding to the first rising edge of the clock signal 50138B / CK1 is the same as the time corresponding to the first rising edge of CK2, and the time corresponding to the second rising edge of the clock signal 50138B / CK1 is the same as the time corresponding to the first rising edge of CK4. The time corresponding to the first rising edge of the clock signal 50138B / CK2 is the same as the time corresponding to the first falling edge of CK2, and the time corresponding to the second rising edge of the clock signal 50138B / CK2 is the same as the time corresponding to the first falling edge of CK4.

[0052] The interval time between the rising edge of the first pulse of one of the start control signal (STV) and the reset signal (Reset) and the rising edge of the first pulse of CK1 is 5.4H. The period of each clock signal (CK1 - CK12) is 12H, the pulse duration is 5.16H, and the duty cycle of each clock signal is 43%. The interval time between the rising edges of two adjacent clock signals in CK1 - CK12 is 1H.

[0053] The pulse durations of the start control signal (STV) and the reset signal (Reset) are both 10.4H, where H is the unit time. As shown, in the mode of 60Hz refresh rate, 1H = 2.47us. Figure 3 As shown, in the mode of 60Hz refresh rate, 1H = 2.47us.

[0054] The high potential (VGH) of one of the start control signal (STV) and the reset signal (Reset) is the same as that of each clock signal. Therefore, by controlling the high potential of one of the start control signal (STV) and the reset signal (Reset), the high potential of each clock signal can be controlled. In the mode of 60Hz refresh rate, the high potential VGH is set to 28.5V to save power under the charging condition corresponding to the 60Hz refresh rate.

[0055] As Figure 6 shown, the source driver circuit 300 may include a shift register (ShiftRegister), a data register (Data Register), a line latch (Line Latch), a level shifter (LevelShifter), a digital-to-analog converter (R-DAC), and an output buffer (Output Buffer) that are electrically connected in sequence. The above devices all include n transmission channels for outputting n data signals, and the source driver circuit 300 has n output pins. n may be equal to 966, that is, the source driver circuit 300 can output 966 data signals Y1 - Y966.

[0056] As Figure 4 shown, the refresh rate is increased from 60Hz to 120Hz. In the mode of 120Hz doubled refresh rate, 1H = 1.24us, the periods of each clock signal still remain the same, that is, 12H, and the duty cycles of each clock signal remain the same, that is, 43%. In order to maximize the charging rate of the sub-pixels, the high potential VGH is further increased to 33V.

[0057] As Figure 3 、 Figure 4 shown, the duty cycle of the scan driving signal corresponding to the second refresh rate is equal to the duty cycle of the scan driving signal corresponding to the first refresh rate. That is, the duty cycle of the scan driving signal of the gate driver circuit 200 of the display panel 400 in the mode of the first refresh rate is equal to the duty cycle of the scan driving signal of the gate driver circuit 200 of the display panel 400 in the mode of the second refresh rate (the actual difference does not exceed 5%).

[0058] The pulse amplitude of the scan driving signal corresponding to the second refresh rate is greater than the pulse amplitude of the scan driving signal corresponding to the first refresh rate.

[0059] The pulse amplitude of the scan driving signal corresponding to the second refresh frequency is in the range of 29V to 39V. For example, the pulse amplitude of the driving signal is 29V, 29.5V, 30V, 30.5V, 31V, 31.5V, 32V, 32.5V, 33V, 33.5V, 34V, 34.5V, 35V, 35.5V, 36V, 36.5V, 37V, 37.5V, 38V, 38.5V, 39V.

[0060] The high-level duration of the scan driving signal of the gate driving circuit 200 of the display panel 400 in the mode of the first refresh frequency is twice the high-level duration of the scan driving signal of the gate driving circuit 200 of the display panel 400 in the mode of the second refresh frequency.

[0061] Generating the first video signal with the first image resolution and the first frame rate into the second video signal with the second image resolution and the second frame rate according to the refresh frequency switching instruction includes:

[0062] The control chip generates the first video signal into a third video signal with the first image resolution and the second frame rate according to the refresh frequency switching instruction.

[0063] The control chip generates the third video signal into the second video signal.

[0064] The second refresh frequency is twice the first refresh frequency, and the second frame rate is twice the first frame rate.

[0065] Generating the first video signal into a third video signal with the first image resolution and the second frame rate according to the refresh frequency switching instruction includes:

[0066] The control chip generates one first video signal into two first video signals according to the refresh frequency switching instruction.

[0067] The control chip combines the two first video signals into the third video signal, where the (2L - 1)-th frame image and the 2L-th frame image in the third video signal are the same and the same as the L-th frame image in the first video signal, where L is a positive integer.

[0068] Generating the third video signal into the second video signal includes:

[0069] The control chip extracts the image data of the odd columns in the Mth frame image in the third video signal and the image data of the even columns in the (M + 1)th frame image in the third video signal, where M is a positive integer.

[0070] The control chip generates the second video signal according to the image data of the odd columns in the Mth frame image and the image data of the even columns in the (M + 1)th frame image. The image data of the Mth frame image in the second video signal includes the image data of the odd columns in the Mth frame image in the third video signal, and the image data of the (M + 1)th frame image in the second video signal includes the image data of the even columns in the (M + 1)th frame image in the third video signal.

[0071] The source driver circuit includes a data register, and the data register is electrically connected to multiple columns of pixels.

[0072] The outputting the scan driving signal corresponding to the second refresh frequency and the second video signal to multiple pixels of the display panel includes:

[0073] According to the second refresh frequency, the data register outputs the image data of the P columns in the Nth frame image in the second video signal to the P odd-column pixels of the display panel 400 during the driving period of the Nth frame image.

[0074] The data register outputs the image data of the P columns in the (N + 1)th frame image in the second video signal to the P even-column pixels of the display panel 400 during the driving period of the (N + 1)th frame image, where N and P are both positive integers.

[0075] The outputting the scan driving signal corresponding to the second refresh frequency and the second video signal to multiple pixels of the display panel further includes:

[0076] The data register outputs a common voltage to the P even-column pixels of the display panel 400 during the driving period of the Nth frame image.

[0077] The data register outputs the common voltage to the P odd-column pixels of the display panel 400 during the driving period of the (N + 1)th frame image.

[0078] Specifically, the control chip 100 adjusts the first video signal with the first frame rate to the second video signal with the second frame rate.

[0079] The control chip retains the image data corresponding to the odd-numbered column pixels of the display panel 400 in the image data of odd frames, and eliminates the image data corresponding to the even-numbered column pixels of the display panel 400, and retains the image data corresponding to the even-numbered column pixels of the display panel 400 in the image data of even frames, and eliminates the image data corresponding to the odd-numbered column pixels of the display panel 400.

[0080] The data register assigns the voltage of the image data corresponding to the even-numbered column pixels of the display panel 400 to the voltage of the common electrode of the display panel 400 (black insertion processing) in the image data of odd frames, and assigns the voltage of the image data corresponding to the odd-numbered column pixels of the display panel 400 to the voltage of the common electrode of the display panel 400 in the image data of even frames.

[0081] That is, for odd-frame images, the data register sets the voltage of the image data output from the even channels to the black insertion voltage (BS), that is, the voltage of the common electrode. For even-frame images, the data register sets the voltage of the image data output from the odd channels to the black insertion voltage.

[0082] Specifically, as Figure 5As shown, the UHD (4K2K) 60Hz display device defaults to display in a 60Hz (first refresh rate) mode. When receiving a display requirement (refresh rate switching instruction) for the 120Hz (second refresh rate) mode of frequency doubling, the SoC (control chip 100) in the display device issues an instruction to the gate driving circuit 200, and the gate driving circuit 200 outputs a scanning driving signal of 4K2K 120Hz (second refresh rate) to the display panel 400. The SoC (control chip 100) generates a third video signal of 4K2K (first image resolution) 120Hz (second frame rate) from the input first video signal of 4K2K (first image resolution) 60Hz (first frame rate), and then performs data decimation processing on this third video signal. Among them, for the odd frames in this third video signal, the image data of the even columns is extracted, and for the even frames in this third video signal, the image data of the odd columns is extracted, or, for the odd frames in this third video signal, the image data of the odd columns is extracted, and for the even frames in this third video signal, the image data of the even columns is extracted, so as to obtain a second video signal of 2K2K (second image resolution) 120Hz (second frame rate) (the signals of the odd frames and even frames after decimation processing are different), and output this second video signal to the source driving circuit 300. The data register performs data blanking processing on the display panel 400 according to the second video signal. The blanking method is to set the voltage of the pixel columns corresponding to the data extracted in one frame of the second video signal in the display panel 400 to the common voltage (the voltage value is equal to the voltage value input to the common electrode on the counter substrate), that is, to make the voltage difference between the pixel columns in the thin film transistor array substrate where the data set to the common voltage is input and the counter substrate zero. The data of the even columns is supplemented and blanked in the odd frame images of the second video signal, and the data of the odd columns is supplemented and blanked in the even frames of the second video signal.

[0083] Finally, the display panel 400 displays an image of 2K2K (second image resolution) 120Hz (second frame rate), achieving the goal of 120Hz (second refresh rate) of frequency doubling.

[0084] Taking the display panel 400 with a Tri-gate driving architecture as an example, for the image FD1 of odd frames, the first, second, and third pixels in the first column all display color images, the fourth, fifth, and sixth pixels in the first column all display black, the first, second, and third pixels in the second column all display black, the fourth, fifth, and sixth pixels in the second column all display color images, the first, second, and third pixels in the third column all display color images, the fourth, fifth, and sixth pixels in the third column all display black, the first, second, and third pixels in the fourth column all display black, and the fourth, fifth, and sixth pixels in the fourth column all display color images; for the image FD2 of even frames, the first, second, and third pixels in the first column all display black, the fourth, fifth, and sixth pixels in the first column all display color images, the first, second, and third pixels in the second column all display color images, the fourth, fifth, and sixth pixels in the second column all display black, the first, second, and third pixels in the third column all display black, the fourth, fifth, and sixth pixels in the third column all display color images, the first, second, and third pixels in the fourth column all display color images, and the fourth, fifth, and sixth pixels in the fourth column all display black.

[0085] Among them, FS1 refers to the image data of odd frames, and FS2 refers to the image data of even frames. FD1 refers to the image data of odd frames, and FD2 refers to the image data of even frames. Among them, FS1, FS2, FD1, and FD2 are all images of the second video signal.

[0086] The driving period (1F) of one frame of image includes an effective display period (T1) and a blank display period (T2).

[0087] The second embodiment of the present application is similar to the above first embodiment, the difference lies in:

[0088] The step of outputting the scanning driving signal corresponding to the second refresh frequency and the second video signal to the multiple pixels of the display panel further includes:

[0089] The data register of the source driving circuit 300 disconnects the current path between the source driving circuit 300 and the pixels of the P even columns of the display panel 400 during the driving period of the Nth frame of image.

[0090] During the driving period of the (N + 1)-th frame image, the data register disconnects the current path between the source driver circuit 300 and the pixels of P odd-numbered columns of the display panel 400.

[0091] Alternatively, before the data register outputs the image data of the N-th frame to the display panel 400, the latch of the source driver circuit 300 disconnects the transmission channel of the corresponding even-numbered column pixels between the data register and the display panel 400, and before the data register outputs the image data of the (N + 1)-th frame to the display panel 400, disconnects the transmission channel of the corresponding odd-numbered column pixels between the data register and the display panel 400.

[0092] Alternatively, the source driver circuit 300 further includes an output controller. A plurality of input terminals of the output controller are electrically connected to a plurality of output terminals of an output buffer of the source driver circuit 300, and a plurality of output terminals of the output controller are electrically connected to multiple columns of pixels. The output controller includes a plurality of transistor switches (for example, 966 transistor switches). Among them, all odd transistor switches among the plurality of transistor switches are turned on or off simultaneously, and all even transistor switches are turned on or off simultaneously, but when the odd transistors are on, the even transistors are off, and when the even transistors are on, the odd transistors are off. The output controller turns on the current path between the source driver circuit 300 and the pixels of P odd-numbered columns of the display panel 400 during the driving period of the N-th frame image, and disconnects the current path between the source driver circuit 300 and the pixels of P even-numbered columns of the display panel 400, and during the driving period of the (N + 1)-th frame image, turns on the current path between the source driver circuit 300 and the pixels of P even-numbered columns of the display panel 400, and disconnects the current path between the source driver circuit 300 and the pixels of P odd-numbered columns of the display panel 400.

[0093] Specifically, as Figure 7 、 Figure 8As shown in the figure, the UHD (4K2K) 60Hz display device defaults to display in the 60Hz (first refresh rate) mode. When receiving a display requirement (refresh rate switching instruction) for the 120Hz (second refresh rate) mode of double frequency, the SoC (control chip 100) in the display device issues an instruction to the gate driving circuit 200, and the gate driving circuit 200 outputs a scanning driving signal of 4K2K 120Hz (second refresh rate) to the display panel 400. The SoC (control chip 100) generates (repeats) the input first video signal of 4K2K (first image resolution) 60Hz (first frame rate) into a third video signal of 4K2K (first image resolution) 120Hz (second frame rate), and then performs data decimation processing on this third video signal. Among them, for the odd frames in this third video signal, the image data of the even columns is extracted, for the even frames in this third video signal, the image data of the odd columns is extracted, or for the odd frames in this third video signal, the image data of the odd columns is extracted, for the even frames in this third video signal, the image data of the even columns is extracted, so as to obtain a second video signal of 2K2K (second image resolution) 120Hz (second frame rate) (the signals of the odd frames and even frames after decimation processing are different), and output this second video signal to the source driving circuit 300. The source driving circuit 300 performs signal disconnection processing / signal floating processing on the display panel 400 according to the second video signal. The signal disconnection processing / signal floating processing is to disconnect the current path between the pixel columns corresponding to the extracted data in one frame of the second video signal in the display panel 400 and the source driving circuit 300. For example, for the Nth frame in this third video signal, the source driving circuit 300 disconnects / floats the current path between the pixel columns corresponding to the image data of the even columns in the Nth frame in the display panel 400 and the source driving circuit 300. For the (N + 1)th frame in this third video signal, the source driving circuit 300 disconnects / floats the current path between the pixel columns corresponding to the image data of the odd columns in the (N + 1)th frame in the display panel 400 and the source driving circuit 300. Specifically, as Figure 8 shown, the source driving circuit 300 disconnects the even transmission channel (F) between the data register and the latch during the transmission of the image data of the odd frames, so that the pixels electrically connected to the even transmission channel do not receive data signals; the source driving circuit 300 also disconnects the odd transmission channel between the data register and the latch during the transmission of the image data of the even frames, so that the pixels electrically connected to the odd transmission channel do not receive data signals.

[0094] Finally, the display panel 400 displays an image of 2K2K (second image resolution) 120Hz (second frame rate), achieving the goal of 120Hz (second refresh rate) of double frequency.

[0095] Compared with the technical solution of the black insertion process in the above-mentioned first embodiment, in this embodiment, the pixels electrically connected to the even transmission channels and the pixels electrically connected to the odd transmission channels do not display black, but display the original color with a darker brightness.

[0096] The third embodiment of the present application is similar to the above-mentioned first embodiment or second embodiment, and the differences are as follows:

[0097] The generating the second video signal with the second image resolution and the second frame rate from the input first video signal with the first image resolution and the first frame rate according to the refresh frequency switching instruction includes:

[0098] The image scaling module of the control chip is used to scale the first video signal into a fourth video signal with the second image resolution and the first frame rate according to the refresh frequency switching instruction.

[0099] The control chip generates two of the fourth video signals from one of the fourth video signals.

[0100] The control chip composites the two fourth video signals into the second video signal, wherein the (2L - 1)-th frame image in the second video signal is the same as the 2L-th frame image and is the same as the L-th frame image in the fourth video signal, where L is a positive integer.

[0101] The outputting the scan driving signal corresponding to the second refresh frequency and the second video signal to the multiple pixels of the display panel includes:

[0102] The source driving circuit copies the P-column image data of the Q-th frame image in the second video signal into 2P-column image data.

[0103] The source driving circuit outputs the 2P-column image data to the pixels of 2P columns of the display panel 400 within the driving period of the Q-th frame image, wherein the two identical columns of the 2P-column image data obtained after copying are output to the adjacent two columns of pixels of the display panel 400, and both P and Q are positive integers.

[0104] Specifically, the control chip 100 includes an image scaling module, and the image scaling module is used to adjust the first image resolution of the first video signal to the second image resolution to generate a fourth video signal, and is used to adjust the first frame rate of the fourth video signal to the second frame rate to generate the second video signal.

[0105] Every two output channels of the data register of the source driving circuit 300 share the same column data signal in one frame of image.

[0106] Specifically, the UHD (4K2K) 60Hz display device defaults to display in the 60Hz (first refresh rate) mode. When receiving a display requirement (refresh rate switching instruction) for the 120Hz (second refresh rate) mode of double frequency, the SoC (control chip 100) in the display device issues an instruction to the gate driving circuit 200, and the gate driving circuit 200 outputs a scan driving signal of 4K2K 120Hz (second refresh rate) to the display panel 400. As Figure 9 , Figure 10 shown, the SoC (control chip 100) generates a fourth video signal of 2K2K (second image resolution) 60Hz (first frame rate) from the input first video signal of 4K2K (first image resolution) 60Hz (first frame rate) through an image scaling module (Scaler), then copies the fourth video signal, and combines the two copied fourth video signals into a second video signal of 2K2K (second image resolution) 120Hz (second frame rate). The signals of the odd and even frames of the combined second video signal are the same (consistent), and the second video signal is output to the source driving circuit 300. As Figure 10 shown, the source driving circuit 300 copies each column of image data in any one frame of the second video signal to obtain twice the column image data. The implementation method is as follows: for the display panel 400 with a 1G1D driving architecture and a Tri-gate driving architecture, the source driving circuit 300 performs data copying of adjacent odd and even channels (Channels) internally. For the display panel 400 with a DLS driving architecture, the source driving circuit outputs one column of image data to two columns of pixels through a data line connected to two columns of pixels. As Figure 9 , Figure 10 shown, the image scaling module is used to adjust the first video signal with 2*N columns of image data to a fourth video signal with N columns of image data, and adjust the first frame rate of the fourth video signal to the second frame rate to obtain the second video signal. Every two output channels of the data register share the same column of image data. Finally, the display panel 400 displays an image of 2K2K (second image resolution) 120Hz (second frame rate), achieving the high refresh rate target of 120Hz (second refresh rate) of double frequency.

[0107] The features in the above-mentioned first embodiment, second embodiment, and third embodiment can be combined with each other.

[0108] The working steps or functions of the control chip, source driving circuit, and gate driving circuit in the display device provided by this application correspond to the steps or functions in the above-mentioned display panel driving method.

[0109] In the display panel driving method and display device provided in the above embodiments of the present application, since the gate driving circuit 200 is controlled according to a refresh frequency switching instruction (doubling control instruction) to adjust the timing of the scan driving signal, and the control chip 100 and the source driving circuit 300 are controlled according to the refresh frequency switching instruction to adjust the image resolution and frame rate of the video signal, the display effect of doubling the refresh frequency of the display panel 400 can be achieved in a variety of different pixel driving architectures, getting rid of the limitation of different pixel driving architectures on the display effect of doubling the refresh frequency of the display panel 400. In addition, since the function of the timing controller or the timing control chip 100 is integrated into the control chip 100, a separate timing controller or timing control chip 100 is not required, simplifying the driving system of the display device and reducing the cost.

[0110] In the technical solution of the present application, the control chip 100 reconstructs the input low-frame-rate video signal according to the refresh frequency switching instruction to generate a high-frame-rate video signal matching the high refresh frequency, and outputs a timing control signal for controlling the gate driving circuit 200 according to the high refresh frequency, so that the gate driving circuit 200 outputs a scan driving signal matching the high refresh frequency. At the same time, the source driving circuit 300 is controlled to output the reconstructed video signal to the display panel 400 at the high refresh frequency. In this way, regardless of the driving architecture adopted by the display panel 400, the switching from a low refresh rate to a high refresh rate can be achieved without changing the hardware circuit. For example, the display panel 400 based on the DLG driving technology of the 1G1D driving architecture can be switched from 60Hz to 120Hz, or the display panel 400 of the triple-gate driving architecture can be switched from 60Hz to 120Hz without changing the wiring of the display panel 400. This technical solution overcomes the problem that it is difficult for panels with different driving methods to be compatible with doubling driving, and realizes doubling display in display panels 400 with different driving architectures, improving the compatibility and applicability of doubling display.

[0111] The above description has explained the display panel driving method and display device provided in the embodiments of the present application. The above description is only used to help understand the technical solution and its core idea of the present application. Modifications or replacements made by those of ordinary skill in the art to some of the technical features do not cause the essence of the corresponding technical solution to deviate from the protection scope of the claims of the present application.

Claims

1. A display panel driving method, characterized in that, the display panel driving method includes: receiving a refresh frequency switching instruction, wherein the refresh frequency switching instruction is an instruction for controlling the display panel to switch from a first refresh frequency to a second refresh frequency; generating a second video signal with a second image resolution and a second frame rate from the input first video signal with a first image resolution and a first frame rate according to the refresh frequency switching instruction; outputting a scan driving signal corresponding to the second refresh frequency and the second video signal to a plurality of pixels of the display panel.

2. The display panel driving method according to claim 1, characterized in that, the generating a second video signal with a second image resolution and a second frame rate from the input first video signal with a first image resolution and a first frame rate according to the refresh frequency switching instruction includes: generating a third video signal with the first image resolution and the second frame rate from the first video signal according to the refresh frequency switching instruction; generating the second video signal from the third video signal.

3. The display panel driving method according to claim 2, characterized in that, the second refresh frequency is twice the first refresh frequency, and the second frame rate is twice the first frame rate; the generating a third video signal with the first image resolution and the second frame rate from the first video signal according to the refresh frequency switching instruction includes: generating two first video signals from one first video signal according to the refresh frequency switching instruction; combining the two first video signals into the third video signal, wherein the (2L - 1)-th frame image in the third video signal is the same as the 2L-th frame image and the same as the L-th frame image in the first video signal, where L is a positive integer; the generating the second video signal from the third video signal includes: extracting the image data of odd columns in the M-th frame image in the third video signal and the image data of even columns in the (M + 1)-th frame image in the third video signal, where M is a positive integer; generating the second video signal according to the image data of odd columns in the M-th frame image and the image data of even columns in the (M + 1)-th frame image, wherein the image data of the M-th frame image in the second video signal includes the image data of odd columns in the M-th frame image in the third video signal, and the image data of the (M + 1)-th frame image in the second video signal includes the image data of even columns in the (M + 1)-th frame image in the third video signal.

4. The display panel driving method according to claim 3, characterized in that, the outputting a scan driving signal corresponding to the second refresh frequency and the second video signal to a plurality of pixels of the display panel includes: According to the second refresh frequency, within the driving period of the Nth frame image, output the P-column image data of the Nth frame image in the second video signal to the pixels of P odd-numbered columns of the display panel, and output a common voltage to the pixels of P even-numbered columns of the display panel within the driving period of the Nth frame image; Within the driving period of the (N + 1)th frame image, output the P-column image data of the (N + 1)th frame image in the second video signal to the pixels of P even-numbered columns of the display panel and output the common voltage to the pixels of P odd-numbered columns of the display panel within the driving period of the (N + 1)th frame image; wherein both N and P are positive integers.

5. The display panel driving method according to claim 3, characterized in that the outputting the scan driving signal corresponding to the second refresh frequency and the second video signal to multiple pixels of the display panel includes: According to the second refresh frequency, within the driving period of the Nth frame image, output the P-column image data of the Nth frame image in the second video signal to the pixels of P odd-numbered columns of the display panel, and disconnect the current path between the source driving circuit of the display panel and the pixels of P even-numbered columns of the display panel within the driving period of the Nth frame image; Within the driving period of the (N + 1)th frame image, output the P-column image data of the (N + 1)th frame image in the second video signal to the pixels of P even-numbered columns of the display panel, and disconnect the current path between the source driving circuit and the pixels of P odd-numbered columns of the display panel within the driving period of the (N + 1)th frame image; wherein both N and P are positive integers.

6. The display panel driving method according to claim 1, characterized in that the generating the second video signal with a second image resolution and a second frame rate from the input first video signal with a first image resolution and a first frame rate according to the refresh frequency switching instruction includes: According to the refresh frequency switching instruction, scale the first video signal to a fourth video signal with a second image resolution and a first frame rate; Generate two fourth video signals from one fourth video signal; Composite the two fourth video signals into the second video signal, wherein the (2L - 1)th frame image and the 2Lth frame image in the second video signal are the same and are the same as the Lth frame image in the fourth video signal, and L is a positive integer.

7. The display panel driving method according to claim 6, characterized in that the outputting the scan driving signal corresponding to the second refresh frequency and the second video signal to multiple pixels of the display panel includes: Copy the P-column image data of the Qth frame image in the second video signal into 2P-column image data; Within the driving period of the Qth frame image, output the 2P-column image data to the pixels of 2P columns of the display panel, wherein two identical columns of the copied 2P-column image data are output to adjacent two columns of pixels of the display panel, and both P and Q are positive integers.

8. A display device, characterized in that The display device includes a display panel and a control chip. The display panel includes a gate driving circuit, a source driving circuit, and a plurality of pixels. The control chip is electrically connected to the gate driving circuit and the source driving circuit of the display panel, and both the gate driving circuit and the source driving circuit are electrically connected to the plurality of pixels; The control chip is configured to receive a refresh frequency switching instruction, and is configured to generate a second video signal having a second image resolution and a second frame rate from the input first video signal having a first image resolution and a first frame rate according to the refresh frequency switching instruction, and is configured to output a scan driving signal corresponding to the second refresh frequency and the second video signal to the plurality of pixels of the display panel through the gate driving circuit and the source driving circuit; Wherein, the refresh frequency switching instruction is an instruction for controlling the display panel to switch from a first refresh frequency to a second refresh frequency.

9. The display device according to claim 8, wherein, the second refresh frequency is twice the first refresh frequency, and the second frame rate is twice the first frame rate; The control chip is configured to generate two first video signals from one first video signal according to the refresh frequency switching instruction, and is configured to combine the two first video signals into the third video signal, and is configured to extract the image data of the odd columns in the Mth frame image of the third video signal and the image data of the even columns in the (M + 1)th frame image of the third video signal, and is configured to generate the second video signal according to the image data of the odd columns in the Mth frame image and the image data of the even columns in the (M + 1)th frame image; Wherein, the (2L - 1)th frame image in the third video signal is the same as the 2Lth frame image and is the same as the Lth frame image in the first video signal, L and M are both positive integers, the image data of the Mth frame image in the second video signal includes the image data of the odd columns in the Mth frame image of the third video signal, and the image data of the (M + 1)th frame image in the second video signal includes the image data of the even columns in the (M + 1)th frame image of the third video signal.

10. The display device according to claim 9, wherein, the source driving circuit includes a data register and a latch. The data register is electrically connected to the latch, and the latch is electrically connected to multiple columns of pixels of the display panel; The data register is configured to output, according to the second refresh frequency, the P-column image data of the Nth frame image in the second video signal to the pixels of P odd-numbered columns of the display panel during the driving period of the Nth frame image, and is configured to output a common voltage to the pixels of P even-numbered columns of the display panel during the driving period of the Nth frame image, and is configured to output, during the driving period of the (N + 1)th frame image, the P-column image data of the (N + 1)th frame image in the second video signal to the pixels of P even-numbered columns of the display panel, and is configured to output the common voltage to the pixels of P odd-numbered columns of the display panel during the driving period of the (N + 1)th frame image; or, The data register or the latch is configured to output, according to the second refresh frequency, the P-column image data of the Nth frame image in the second video signal to the pixels of P odd-numbered columns of the display panel during the driving period of the Nth frame image, and is configured to disconnect the current path between the source driver circuit of the display panel and the pixels of P even-numbered columns of the display panel during the driving period of the Nth frame image, and is configured to output, during the driving period of the (N + 1)th frame image, the P-column image data of the (N + 1)th frame image in the second video signal to the pixels of P even-numbered columns of the display panel, and is configured to disconnect the current path between the source driver circuit and the pixels of P odd-numbered columns of the display panel during the driving period of the (N + 1)th frame image; wherein both N and P are positive integers.

11. The display device according to claim 9, wherein: The source driver circuit includes an output controller, and the output controller is electrically connected to multiple columns of pixels; The output controller is configured to turn on the current path between the source driver circuit and the pixels of P odd-numbered columns of the display panel during the driving period of the Nth frame image, and disconnect the current path between the source driver circuit and the pixels of P even-numbered columns of the display panel, and to turn on the current path between the source driver circuit and the pixels of P even-numbered columns of the display panel during the driving period of the (N + 1)th frame image, and disconnect the current path between the source driver circuit and the pixels of P odd-numbered columns of the display panel.

12. The display device according to claim 8, wherein: The control chip is configured to scale the first video signal into a fourth video signal having a second image resolution and a first frame rate according to the refresh frequency switching instruction, and is configured to generate two fourth video signals from one fourth video signal, and is configured to composite the two fourth video signals into the second video signal; wherein the (2L - 1)th frame image and the 2Lth frame image in the second video signal are the same and are the same as the Lth frame image in the fourth video signal, and L is a positive integer.

13. The display device according to claim 12, wherein: The source driving circuit is used to copy the P-column image data of the Q-th frame image in the second video signal into 2P-column image data, and is used to output the 2P-column image data to the pixels of 2P columns of the display panel during the driving period of the Q-th frame image; Among them, two identical columns of the 2P-column image data obtained after copying are output to the pixels of two adjacent columns of the display panel, and both P and Q are positive integers.

Images