A Phase-Locked Loop Control Method and Related Devices

Abstract

The present invention relates to the technical field of power supply or power distribution, and in particular to a phase-locked loop control method and related device, including obtaining the grid voltage #imgabs0#-axis and #imgabs1#-axis voltage components, and respectively performing multiple notch filtering processing, equivalent virtual capacitance processing, second-order generalized integral processing, and positive and negative sequence separation processing in sequence to obtain the positive sequence #imgabs2# component of the grid voltage and the positive sequence #imgabs3# component of the grid voltage; performing coordinate transformation and PI regulation on the positive sequence #imgabs4# component of the grid voltage and the positive sequence #imgabs5# component of the grid voltage, and outputting the phase angle to complete the phase-locked loop control. Through the synergistic effect of multiple notch filtering processing, equivalent virtual capacitance processing, second-order generalized integral processing, and positive and negative sequence separation processing, the present invention ensures that accurate phase-locked voltages can be obtained under the conditions of unbalanced grid voltage, grid voltage harmonics, and DC bias of the grid voltage, realizes the stable operation of the phase-locked loop, and solves the problem that the existing phase-locked loop control cannot operate stably under the conditions of unbalanced grid voltage, grid voltage harmonics, and DC bias of the grid voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply or power distribution, and specifically to a phase-locked loop control method and related device. Background Art

[0002] A phase-locked loop (PLL) is a feedback control circuit widely used in electronic circuits and systems, which is used to achieve precise control and tracking of the frequency and phase of a signal. In a grid-connected inverter, in order to ensure that the current output by the inverter is phase-synchronized with the grid voltage, the PLL will monitor the phase of the grid voltage in real time and adjust the phase of the inverter output current to match it. It is an important link for the phase orientation of the grid-connected inverter output voltage and plays a key role in the stable operation of the grid-connected inverter.

[0003] When a grid voltage fault occurs, it generally causes grid voltage imbalance and generates a negative sequence voltage component. Since the PLL depends on the symmetry of three-phase voltages or currents for phase locking, when the grid voltage is unbalanced, the symmetry of the three-phase voltages or currents is destroyed, resulting in difficulty for the PLL to accurately lock the phase, thereby reducing the control accuracy of the system. At the same time, grid voltage harmonics also appear in the grid, mainly including the 3rd, 5th, and 7th harmonics. The harmonics will interfere with the performance of the PLL, leading to misjudgment or failure of the PLL. In addition, grid faults are often accompanied by the generation of voltage DC offsets, and the generation of voltage DC offsets will also have a great impact on the normal operation of the PLL, thereby affecting the stable operation of the grid-connected inverter.

[0004] Currently, the mainstream phase-locked loop control methods mainly focus on solving the problems of grid voltage imbalance and eliminating single harmonics. To eliminate the influence of grid voltage imbalance on the PLL, mainly by extracting the positive sequence component of the grid voltage to eliminate the influence of the negative sequence component, generally implemented by low-pass filtering or second-order generalized integrators, and the effect is good. The means to eliminate harmonics is to filter out high-order harmonics through a low-pass filter. However, the delay effect of the low-pass filter is obvious, which may cause too large an output error of the PLL and cannot solve the influence of grid voltage DC offset on the stability of the PLL. Therefore, the existing phase-locked loop control methods cannot achieve stable operation under the three working conditions of grid voltage imbalance, grid voltage harmonics, and grid voltage DC offset. Summary of the Invention

[0005] Aiming at the problem that the phase-locked loop control in the prior art cannot operate stably when the grid voltage is unbalanced, there are grid voltage harmonics, and there is a grid voltage DC offset, the present invention provides a phase-locked loop control method and related device.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] The present invention provides a phase-locked loop control method, including:

[0008] Obtaining the grid voltage axis and axis voltage components;

[0009] Performing multiple notch filtering processing, equivalent virtual capacitance processing, second-order generalized integral processing, and positive and negative sequence separation processing on the grid voltage axis and axis voltage components in sequence, respectively obtaining the positive sequence component of the grid voltage and the positive sequence component of the grid voltage;

[0010] Performing coordinate transformation on the positive sequence component of the grid voltage and the positive sequence component of the grid voltage to obtain the positive sequence d-q axis voltage components;

[0011] Performing PI regulation on the positive sequence d-q axis voltage components and outputting the phase angle to complete the phase-locked loop control.

[0012] Furthermore, the transfer function of the multiple notch filtering processing is:

[0013]

[0014] Wherein, represents the multiple notch filtering transfer function of the axis; represents the multiple notch filtering transfer function of the axis; represents different frequency harmonics; represents the damping ratio; represents the summation index variable.

[0015] Furthermore, the transfer function of the equivalent virtual capacitance processing is:

[0016]

[0017] Wherein, is the equivalent virtual capacitance transfer function of the axis; is the equivalent virtual capacitance; represents the differential operator.

[0018] Furthermore, the transfer function of the second-order generalized integral processing is:

[0019]

[0020] Among them, represents the direct channel transfer function; represents the quadrature channel transfer function; represents the proportional coefficient of the second-order generalized integrator; represents the input quantity; represents the output quantity; represents the quadrature output quantity of; represents the actual value of the angular frequency; represents the differential operator.

[0021] Furthermore, the method for positive and negative sequence separation processing is:

[0022]

[0023] Among them, represents the positive sequence voltage in the stationary two-phase coordinate system; represents the negative sequence voltage in the stationary two-phase coordinate system; represents the original voltage in the stationary coordinate system; represents the positive sequence component of the grid voltage; represents the positive sequence component of the grid voltage; represents the negative sequence component of the grid voltage; represents the negative sequence component of the grid voltage; represents the lagging phase shift operator.

[0024] Furthermore, the method for performing PI regulation on the positive sequence components of the d-q axis voltages, outputting the phase angle, and completing the phase-locked loop control is:

[0025]

[0026] Among them, represents the second derivative of the phase angle output by the phase-locked loop; represents the integral coefficient of the PI regulation of the phase-locked loop; represents the proportional coefficient of the PI regulation of the phase-locked loop; represents the positive sequence component of the q-axis voltage; represents the phase angle output by the phase-locked loop.

[0027] Furthermore, the positive sequence component of the q-axis voltage is:

[0028]

[0029] Among them, represents the positive sequence of the grid voltage Component; Indicating the positive sequence of the grid voltage Component; Indicating the output phase angle of the phase-locked loop.

[0030] The present invention provides a phase-locked loop control system, comprising:

[0031] Voltage component acquisition module: for acquiring the grid voltage axis and axis voltage components;

[0032] Voltage component processing module: for respectively performing multiple trap filtering processing, equivalent virtual capacitance processing, second-order generalized integral processing and positive and negative sequence separation processing on the grid voltage axis and axis voltage components in sequence, and respectively obtaining the positive sequence component of the grid voltage and the positive sequence component of the grid voltage;

[0033] Coordinate transformation module: for performing coordinate transformation on the positive sequence component of the grid voltage and the positive sequence component of the grid voltage to obtain the positive sequence d-q axis voltage components;

[0034] Phase angle output module: for performing PI regulation on the positive sequence d-q axis voltage components and outputting the phase angle to complete the phase-locked loop control.

[0035] A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the phase-locked loop control method as described above are implemented.

[0036] A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the steps of the phase-locked loop control method as described above are implemented.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] The present invention provides a phase-locked loop control method, which uses the grid voltage axis and Taking the axis voltage component as the input, multiple notch filtering processing, equivalent virtual capacitance processing, second-order generalized integral processing, positive and negative sequence separation processing, and coordinate transformation are sequentially performed to obtain the positive sequence components of the d-q axis voltage; the positive sequence components of the d-q axis voltage are adjusted by proportional integral (PI) to output the phase angle, completing the phase-locked loop control. Among them, multiple notch filtering processing can effectively filter out the harmonics in the grid voltage, especially the interference of harmonics with specific frequencies (such as low-order harmonics), and obtain the grid voltage component without harmonics. Using the band-pass characteristic of multiple notch filtering to filter for specific harmonic frequencies will not introduce excessive phase delay. Compared with the existing method of eliminating harmonics by low-pass filtering, the overall phase delay of the signal is smaller, which can greatly reduce the error of the phase-locked loop output; the equivalent virtual capacitance processing utilizes the characteristic of capacitors blocking direct current and passing alternating current, which can effectively eliminate the direct current component in the grid voltage component to ensure that the output grid voltage component contains no harmonic components and no direct current component, thereby effectively reducing the influence of the grid voltage DC bias on the phase-locked loop and further improving the accuracy of the phase-locked loop output; the second-order generalized integral processing can quickly extract the positive sequence component of the grid voltage, has good dynamic response characteristics, can quickly track the frequency and phase changes of the grid voltage, and improves the dynamic response speed of the system; the positive and negative sequence separation processing can effectively separate the positive and negative sequence components in the grid voltage, ensuring that the phase-locked loop only tracks the positive sequence component and avoiding the interference of the negative sequence component on the phase-locked loop, further improving the dynamic performance of the system; by adjusting the positive sequence components of the d-q axis voltage through PI regulation, the output phase angle of the phase-locked loop can be accurately controlled to ensure the output accuracy of the phase-locked loop; this method can effectively improve the anti-interference ability, dynamic response speed, and phase-locking accuracy of the phase-locked loop, can adapt to complex grid environments, has strong robustness and practicality, and can achieve the accurate output of the phase-locked loop under the coexistence conditions of three working conditions: unbalanced grid voltage, grid voltage harmonics, and grid voltage DC bias.

[0039] The present invention also provides a phase-locked loop control system, including a voltage component acquisition module, a voltage component processing module, a coordinate transformation module, and a phase angle output module; among them, the voltage component acquisition module is responsible for acquiring the grid voltage axis and axis voltage components as the input of the phase-locked loop; the voltage component processing module is responsible for effectively filtering out the harmonics, negative sequence components, and direct current components in the grid voltage component to avoid interference with the phase-locked loop; the coordinate transformation module is used to transform the two-phase stationary coordinates into two-phase rotating coordinates; the phase angle output module is used to accurately control the output phase angle of the phase-locked loop; this system has strong anti-interference ability, fast dynamic response, high calculation and processing ability, low development and maintenance costs, and high reliability and small robustness, and can adapt to different grid environments and control requirements.

[0040] The present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above-mentioned phase-locked loop control method are implemented; the processor can quickly execute processes such as the above-mentioned multiple notch filtering processing, equivalent virtual capacitance processing, second-order generalized integral processing, and positive and negative sequence separation processing, ensuring the real-time performance and accuracy of the phase-locked loop control; the computer program in the memory can be modified and optimized according to actual requirements to adapt to different power grid environments and control requirements.

[0041] A computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the steps of the above-mentioned phase-locked loop control method are implemented; the computer-readable storage medium (such as a solid-state drive (SSD) and a Flash memory) has a high-speed reading ability and can quickly load the computer program into the processor for execution, ensuring the real-time performance of the phase-locked loop control. It has characteristics such as flexibility and portability, high reliability and stability, support for large-scale data storage, easy integration and expansion, reduction of development and maintenance costs, high security, energy conservation and environmental protection, support for multiple application scenarios, and promotion of standardization and normalization, providing strong support for the implementation and popularization of the phase-locked loop control technology and having a wide range of application prospects. Brief Description of the Drawings

[0042] Figure 1 It is a schematic flowchart of a phase-locked loop control method of the present invention.

[0043] Figure 2 It is a phase-locked loop control schematic diagram in a specific embodiment of the present invention.

[0044] Figure 3 It is a comparison diagram of the separation effect of a mixed signal after multiple notch filtering processing in a specific embodiment of the present invention; among them, a is a diagram of the mixed signal before multiple notch filtering processing; b is a diagram of the signal after multiple notch filtering processing.

[0045] Figure 4 It is a second-order generalized integral control block diagram in a specific embodiment of the present invention.

[0046] Figure 5 It is a second-order generalized integral Bode diagram in a specific embodiment of the present invention; a is an amplitude-frequency characteristic diagram; b is a phase-frequency characteristic diagram.

[0047] Figure 6Phase trajectory comparison diagram of the phase-locked loop control method of the present invention; wherein, a is the phase trajectory comparison diagram of the phase-locked loop control method of the present invention when the grid voltage is unbalanced; b is the phase trajectory comparison diagram of the phase-locked loop control method of the present invention when the grid voltage contains harmonics; c is the phase trajectory comparison diagram of the phase-locked loop control method of the present invention when the grid voltage contains a DC bias.

[0048] Figure 7 It is a comparison simulation diagram of the phase-locked loop control method of the present invention when the grid voltage is unbalanced; wherein, a is the simulation waveform diagram when the grid voltage is unbalanced; b is the phase-locked loop performance simulation diagram after only equivalent virtual capacitor processing, second-order generalized integral processing, and positive and negative sequence separation processing; c is the phase-locked loop performance simulation diagram after only second-order generalized integral processing and positive and negative sequence separation processing; d is the phase-locked loop performance simulation diagram after being processed by the phase-locked loop control method of the present invention.

[0049] Figure 8 It is a performance comparison simulation diagram of the phase-locked loop control method of the present invention and the comparative example when the grid voltage contains harmonics; wherein, a is the simulation waveform diagram when the grid voltage contains harmonics; b is the phase-locked loop performance simulation diagram after only equivalent virtual capacitor processing, second-order generalized integral processing, and positive and negative sequence separation processing; c is the phase-locked loop performance simulation diagram after only second-order generalized integral processing and positive and negative sequence separation processing; d is the phase-locked loop performance simulation diagram after being processed by the phase-locked loop control method of the present invention.

[0050] Figure 9 It is a performance comparison simulation diagram of the phase-locked loop control method of the present invention and the comparative example when the grid voltage contains a DC bias; wherein, a is the simulation waveform diagram when the grid voltage contains a DC bias; b is the phase-locked loop performance simulation diagram after only equivalent virtual capacitor processing, second-order generalized integral processing, and positive and negative sequence separation processing; c is the phase-locked loop performance simulation diagram after only second-order generalized integral processing and positive and negative sequence separation processing; d is the phase-locked loop performance simulation diagram after being processed by the phase-locked loop control method of the present invention.

[0051] Figure 10 Structural diagram of a phase-locked loop control system of the present invention. Specific implementation mode

[0052] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0053] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices.

[0054] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0055] See Figure 1 , the present invention provides a phase-locked loop control method, including:

[0056] S1: Obtain the grid voltage axis and axis voltage components, specifically:

[0057] Obtain the grid voltage axis and axis voltage components, and use the grid voltage axis and axis voltage components as the input of the phase-locked loop.

[0058] S2: Perform multiple notch filtering processing, equivalent virtual capacitance processing, second-order generalized integral processing, and positive and negative sequence separation processing on the grid voltage axis and axis voltage components in sequence, and respectively obtain the positive sequence component of the grid voltage and the positive sequence component of the grid voltage, specifically:

[0059] Set a multiple notch filter group composed of several virtual notch filters after the grid voltage axis and axis voltage components, and perform multiple notch filtering processing on the grid voltage axis and axis voltage components respectively to filter out the harmonics existing in the grid voltage, and obtain the grid voltage axis and axis voltage components without harmonics;

[0060] Among them, the transfer function of the multiple notch filtering processing is:

[0061]

[0062] The grid voltage without harmonics Axis and The axis voltage component is:

[0063]

[0064] Wherein, Represents The multi-notch filter transfer function of the axis; Represents The multi-notch filter transfer function of the axis; Represents different frequency harmonics; Represents the total number of different frequency harmonics; Represents the differential operator; Represents the damping ratio; Indicates the grid voltage Axis voltage component; Indicates the grid voltage Axis voltage component; Indicates the grid voltage without harmonics Axis voltage component; Indicates the grid voltage without harmonics Axis voltage component; Represents the index variable for summation, which is the th different frequency harmonic;

[0065] The grid voltage without harmonics Axis and After the axis voltage components are respectively connected in series with equivalent virtual capacitors, the grid voltage without harmonics Axis and The axis voltage components are respectively processed with equivalent virtual capacitors. Utilizing the characteristic of the equivalent virtual capacitor to block direct current and pass alternating current, the direct current components in the grid voltage Axis and The axis voltage components are eliminated, and the grid voltage without harmonics and direct current components Axis and Axis voltage components are obtained;

[0066] Wherein, the transfer function of the equivalent virtual capacitor processing is:

[0067]

[0068] The grid voltage without harmonics and direct current components Axis and The axis voltage component is:

[0069]

[0070] Wherein, is the equivalent virtual capacitance transfer function of the axis; is the equivalent virtual capacitance transfer function of the axis; represents the equivalent virtual capacitance; represents the grid voltage without harmonic and DC components axis voltage component; represents the grid voltage without harmonic and DC components axis voltage component;

[0071] The grid voltage without harmonic and DC components axis and axis voltage components are set with a second-order generalized integrator. For the grid voltage without harmonic and DC components axis and axis voltage components are respectively subjected to second-order generalized integration and positive and negative sequence separation processing, and the positive sequence of the grid voltage component and the positive sequence of the grid voltage component are obtained respectively.

[0072] The transfer function of the second-order generalized integration processing is:

[0073]

[0074] After the second-order generalized integration processing, we get:

[0075]

[0076] The positive sequence of the grid voltage component and the positive sequence of the grid voltage component are respectively:

[0077]

[0078] The method of the positive and negative sequence separation processing is:

[0079]

[0080] Among them, represents the direct channel transfer function; represents the quadrature channel transfer function; represents the proportional coefficient of the second-order generalized integrator; represents the input quantity; represents the output quantity; represents the quadrature output quantity of; represents the actual value of the angular frequency; represents the differential operator; Represents the positive-sequence voltage in the stationary two-phase coordinate system; Represents the negative-sequence voltage in the stationary two-phase coordinate system; Represents the original voltage in the stationary coordinate system; Represents the positive sequence of the grid voltage component; Represents the positive sequence of the grid voltage component; Represents the negative sequence of the grid voltage component; Represents the negative sequence of the grid voltage component; Represents the lagging phase-shifting operator; and respectively represent the grid voltage after passing through the second-order generalized integrator in the two-phase stationary coordinate system, and are 90° out of phase with each other and are a pair of orthogonal components; and respectively represent the grid voltage after passing through the second-order generalized integrator in the two-phase stationary coordinate system, and are 90° out of phase with each other and are a pair of orthogonal components;

[0081] S3: Perform coordinate transformation on the positive-sequence component of the grid voltage component and the positive-sequence component of the grid voltage to obtain the positive-sequence d-q axis voltage components;

[0082] Perform two-phase stationary coordinate transformation on the positive-sequence component of the grid voltage component and the positive-sequence component of the grid voltage to the two-phase rotating coordinate to obtain the positive-sequence d-q axis voltage components; among them, the positive-sequence component of the grid voltage is transformed into the positive-sequence d-axis voltage component , and the positive-sequence component of the grid voltage is transformed into the positive-sequence q-axis voltage component ;

[0083] The positive-sequence q-axis voltage component is:

[0084]

[0085] where, represents the positive-sequence component of the grid voltage component; represents the positive-sequence component of the grid voltage component; represents the phase angle output by the phase-locked loop.

[0086] S4: Perform PI regulation on the positive-sequence components of the d-q axis voltages, output the phase angle, and complete the phase-locked loop control, specifically as follows:

[0087] Control the phase of the positive-sequence voltage component of the q axis on the q axis through a virtual PI regulator, output the phase angle, and complete the phase-locked loop control;

[0088]

[0089] Among them, represents the second derivative of the phase angle output by the phase-locked loop; represents the integral coefficient of the PI regulation of the phase-locked loop; represents the proportional coefficient of the PI regulation of the phase-locked loop; represents the positive-sequence component of the q-axis voltage; represents the phase angle output by the phase-locked loop;

[0090] Substitute formulas (2), (4), (6), (7), and (9) into formula (10) to obtain the phase angle. This control method can ensure that the correct voltage for phase locking can be accurately obtained under the conditions of unbalanced grid voltage, grid voltage harmonics, and DC offset of the grid voltage, and realize the stable operation of the phase-locked loop.

[0091] To further illustrate the beneficial effects of the phase-locked loop control method of the present invention, taking a certain grid voltage with harmonic angular frequencies of 3rd, 5th, and 7th as an example, and there are unbalanced grid voltage and DC offset of the grid voltage, the phase-locked loop control method provided by the present invention is used for control and stability analysis.

[0092] Refer to Figure 2 , then the grid voltage axis and axis voltage components are obtained. Taking the grid voltage axis and axis voltage components as the input of the phase-locked loop, and setting a multiple trap filter group composed of 3 virtual trap filters after the grid voltage axis and axis voltage components, then its transfer function is:

[0093]

[0094] Among them, represents the 3rd harmonic; represents the 5th harmonic; represents the 7th harmonic;

[0095] Refer to Figure 3 , taking the mixed signal of low-frequency 10Hz and power frequency 50Hz as an example, after the multiple trap filtering process, the power frequency 50Hz and the low-frequency 10Hz can be effectively separated, proving the effectiveness of the multiple trap filter proposed by the present invention.

[0096] By performing virtual notch filtering on the grid voltage axis and axis voltage components, a grid voltage without 3rd, 5th, and 7th harmonics is obtained axis and axis voltage components are:

[0097]

[0098] Then, equivalent virtual capacitance processing is performed. The transfer function is shown in Equation (3), and grid voltages without harmonic and DC components are obtained respectively axis and axis voltage components;

[0099] For the grid voltage axis and axis voltage components without harmonic and DC components, second-order generalized integration processing is carried out, that is, the grid voltage axis and axis voltage components are set with a second-order generalized integrator. See Figure 4 , and a pair of orthogonal voltage components are obtained through the direct channel and the quadrature channel of the second-order generalized integrator. The transfer function is shown in Equation (5); when , in Equation (5), and Bode plots are shown in Figure 5 . It can be seen that the second-order generalized integrator can generate two orthogonal signals with the same amplitude and a phase difference of . The main function of this part is to generate orthogonal output quantities, providing reliable input quantities for subsequent positive and negative sequence separation; using the orthogonal output quantities generated by the second-order generalized integrator as the input quantities for positive and negative sequence separation, positive and negative sequence separation is carried out. Specifically, see Equation (8). The lagging phase shift operator in Equation (8) is a phase shift operator lagging by , representing the generation of orthogonal signals.

[0100] Finally, the positive sequence component of the grid voltage and the positive sequence component of the grid voltage obtained after positive and negative sequence separation are converted from two-phase stationary coordinates to two-phase rotating coordinates to obtain the positive sequence d-q axis voltage components, and the phase of the positive sequence voltage component on the q-axis is controlled by a virtual PI regulator to output the phase angle, completing the phase-locked loop control. Specifically, see Equation (10). Substituting (12), (4), (6), (7), and (9) into Equation (10), the correct phase angle is output.

[0101] See Figure 6, it can be seen from the phase trajectory comparison diagram that when the grid voltage is unbalanced, only the PLL outputs of the second-order generalized integral processing and the positive and negative sequence separation processing have divergent phase angles, and the PLL becomes unstable. After adding the equivalent virtual capacitor, the PLL still cannot operate stably, and the PLL still diverges. This is due to the harmonics generated during grid faults. However, the PLL control method of the present invention can quickly restore the stability of the PLL output; when the grid voltage contains 3rd, 5th, and 7th harmonics, only the PLL outputs of the second-order generalized integral processing and the positive and negative sequence separation processing have divergent phase angles, and the PLL becomes unstable. After adding the equivalent virtual capacitor, the PLL still cannot operate stably. However, the PLL control method of the present invention can quickly restore the stability of the PLL output; when there is a DC bias in the grid voltage, the PLL without adding the equivalent virtual capacitor directly diverges, while the PLL control method of the present invention can quickly restore the stability of the PLL output phase angle, further indicating that the control method of the present invention can effectively improve the stability of the PLL under three working conditions: unbalanced grid voltage, grid voltage with harmonics, and DC bias of grid voltage; it should be noted that "the method of the present invention" in the figure refers to the PLL control method provided by the present invention, and "without equivalent virtual capacitor" in the figure means that only the grid voltage axis and axis voltage components are successively subjected to multiple trap filtering processing, second-order generalized integral processing, and positive and negative sequence separation processing. "Without filtering and equivalent virtual capacitor" in the figure means that only the grid voltage axis and axis voltage components are successively subjected to second-order generalized integral processing and positive and negative sequence separation processing.

[0102] The PLL controls under three working conditions of unbalanced grid voltage, grid voltage with harmonics, and DC bias of grid voltage are respectively simulated and compared. The simulation results are shown in Figures 7 to 9 . It can be seen that when the grid voltage is unbalanced, contains grid voltage harmonics, or contains DC bias of grid voltage, after only being processed by the equivalent virtual capacitor, second-order generalized integral processing, and positive and negative sequence separation processing and after only being processed by second-order generalized integral processing and positive and negative sequence separation processing, the stability of the PLL output cannot be guaranteed. The PLL processed by the PLL control method of the present invention can realize the stable operation of the PLL, further indicating that the PLL control method provided by the present invention can ensure that the correct voltage for phase locking can be accurately obtained under unbalanced grid voltage, grid voltage harmonics, and DC bias of grid voltage, and realize the stable operation of the PLL, which plays a positive role in the stable operation of the grid-connected inverter.

[0103] See Figure 10 . The present invention also provides a PLL control system, including:

[0104] Voltage component acquisition module: used to acquire the grid voltage axis and axis voltage components;

[0105] Voltage component processing module: used to perform multiple trap filtering, equivalent virtual capacitance processing, second-order generalized integral processing, and positive and negative sequence separation processing on the grid voltage axis and axis voltage components in sequence, respectively obtaining the positive sequence component of the grid voltage and the positive sequence component of the grid voltage;

[0106] Coordinate transformation module: used to perform coordinate transformation on the positive sequence component of the grid voltage and the positive sequence component of the grid voltage to obtain the positive sequence d-q axis voltage components;

[0107] Phase angle output module: used to perform PI regulation on the positive sequence d-q axis voltage components and output the phase angle to complete the phase-locked loop control.

[0108] This system has strong anti-interference ability, fast dynamic response, high computing and processing ability, low development and maintenance costs, and high reliability and small robustness, and can adapt to different grid environments and control requirements.

[0109] The present invention provides a terminal device including: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps in the above-mentioned various method embodiments are implemented. Alternatively, when the processor executes the computer program, the functions of each module / unit in the above-mentioned various device embodiments are implemented.

[0110] The computer program can be divided into one or more modules / units, and the one or more modules / units are stored in the memory and executed by the processor to complete the present invention.

[0111] The terminal device can be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server. The terminal device may include, but is not limited to, a processor and a memory.

[0112] The processor may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0113] The memory can be used to store the computer program and / or module. By running or executing the computer program and / or module stored in the memory, and invoking the data stored in the memory, the processor implements various functions of the terminal device.

[0114] If the module / unit integrated in the terminal device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such understanding, to implement all or part of the processes in the above-mentioned embodiment methods of the present invention, it can also be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0115] The above are only the preferred embodiments of the present invention, and are not used to limit the technical solutions of the present invention. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solutions can be subject to several simple modifications and substitutions, and these modifications and substitutions also fall within the protection scope covered by the claims.

Claims

1. A phase-locked loop control method, characterized in that, Including: Obtain grid voltage Axis and Axis voltage component; The grid voltage axis and the axis voltage components are successively subjected to multiple notch filtering, equivalent virtual capacitance processing, second-order generalized integral processing, and positive and negative sequence separation processing, respectively, to obtain the positive sequence component and the positive sequence component of the grid voltage; The positive sequence component of the grid voltage and the positive sequence component of the grid voltage are subjected to coordinate transformation to obtain the positive sequence components of the d-q axis voltages; Performing PI regulation on the positive-sequence component of the d-q axis voltage to output a phase angle and complete the phase-locked loop control; Among them, the transfer function of the multiple trap filtering process is: The transfer function of the equivalent virtual capacitance process is: The transfer function of the second-order generalized integral process is: The method for positive and negative sequence separation processing is: The method for performing PI regulation on the positive-sequence component of the d-q axis voltage to output a phase angle and complete the phase-locked loop control is: Among them, represents the multiple trap filter transfer function of the axis; represents the multiple trap filter transfer function of the axis; represents the index variable for summation; represents the differential operator; represents the damping ratio; is the equivalent virtual capacitance transfer function of the axis; is the equivalent virtual capacitance transfer function of the axis; represents the direct channel transfer function; represents the quadrature channel transfer function; represents the proportional coefficient of the second-order generalized integrator; represents the input quantity; represents the output quantity; represents the orthogonal output quantity of represents the actual value of the angular frequency; represents the differential operator; represents the positive-sequence voltage in the stationary two-phase coordinate system; represents the negative-sequence voltage in the stationary two-phase coordinate system; represents the original voltage in the stationary coordinate system; represents the positive-sequence component of the grid voltage; represents the positive-sequence component of the grid voltage; represents the negative-sequence component of the grid voltage; represents the negative-sequence component of the grid voltage; represents the lagging phase shift operator; represents the second derivative of the phase angle output by the phase-locked loop; represents the integral coefficient of the phase-locked loop PI regulation; represents the proportional coefficient of the phase-locked loop PI regulation; represents the positive-sequence component of the q-axis voltage; represents the phase angle output by the phase-locked loop.

2. The phase-locked loop control method according to claim 1, wherein The positive-sequence component of the q-axis voltage is: Among them, represents the positive-sequence component of the grid voltage; represents the positive-sequence component of the grid voltage; represents the phase angle output by the phase-locked loop.

3. A phase-locked loop control system based on the phase-locked loop control method according to claim 1 or 2, characterized in that, Including: Voltage component acquisition module: used to acquire grid voltage axis and axis voltage component; Voltage component processing module: used to perform multiple trap filtering processing, equivalent virtual capacitance processing, second-order generalized integral processing, and positive and negative sequence separation processing on the grid voltage axis and axis voltage components in sequence, respectively obtaining the positive sequence component and the positive sequence component of the grid voltage; Coordinate transformation module: used to perform coordinate transformation on the positive-sequence component of the grid voltage and the positive-sequence component of the grid voltage to obtain the positive-sequence components of the d-q axis voltage; component and the positive-sequence component of the grid voltage component to obtain the positive-sequence components of the d-q axis voltage; Phase angle output module: used to perform PI regulation on the positive-sequence component of the d-q axis voltage to output a phase angle and complete the phase-locked loop control.

4. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the phase-locked loop control method as described in claim 1 or 2.

5. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the phase-locked loop control method as described in claim 1 or 2.

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