A diode and a manufacturing method thereof

Abstract

The present application provides a diode and a manufacturing method thereof, relating to the field of semiconductor technology. The diode includes a terminal region and an active region located on the surface of an epitaxial wafer; the active region includes a composite structure and a plurality of P pillars, and the plurality of P pillars are arranged at intervals. The composite structure includes a first P region, a second P region and a third P region located on both sides of the first P region. The first P region, the second P region and the third P region are arranged at intervals. The width of the first P region is greater than the widths of the second P region, the third P region and the P pillars. The bottoms of the second P region and the third P region are set in a stepped shape, and the depths of the second P region and the third P region are greater than the depth of the first P region. Among them, when the diode is in a surge current condition, the first P region is used to provide a main surge current channel, and the second P region and the third P region are used to share part of the surge current. The present application has the advantage of achieving a balance among the nominal forward conduction ability, the surge current handling ability and the unit chip cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a diode and a manufacturing method thereof. Background Art

[0002] In order to improve the surge reliability of devices, on the basis of conventional SBD (Schottky Barrier Diode) and JBS (Junction Barrier Schottky), an MPS diode (Merged PiN Schottky) has been designed and developed. Under high forward current density (such as in the case of large surge current conditions), the large-size PN junction in the MPS diode will turn on and inject minority carriers (holes) into the drift region of the diode. The resulting conductance modulation effect will greatly reduce the resistance of the device and take over the current conduction of the Schottky junction. Therefore, at high current density, the MPS has better forward surge current handling ability than conventional SBD and JBS diodes.

[0003] However, introducing a large-size PN area, if the chip area is to be kept unchanged (the unit chip cost remains unchanged), it will lead to a reduction in the Schottky contact area. When the bipolar structure is not yet working, this will cause an increase in the "on-resistance" under the nominal forward current, increasing the power loss of the device when operating under the nominal forward current. Similarly, if the Schottky contact area is to be kept unchanged, it will increase the chip area, resulting in an increase in the unit chip cost.

[0004] In summary, there is a problem in the prior art that it is difficult to balance the nominal forward conduction ability, surge current handling ability, and unit chip cost of a diode. Summary of the Invention

[0005] The purpose of the present application is to provide a diode and a manufacturing method thereof to solve the problem in the prior art that it is difficult to balance the nominal forward conduction ability, surge current handling ability, and unit chip cost of a diode.

[0006] To achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] On the one hand, an embodiment of the present application provides a diode, which includes:

[0008] An N-type epitaxial wafer;

[0009] A terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein, the active region includes a composite structure and a plurality of P-columns, the plurality of P-columns are spaced apart from each other, and the composite structure is also spaced apart from the P-columns on both sides;

[0010] The composite structure includes a first P region, a second P region, and a third P region located on both sides of the first P region. The first P region, the second P region, and the third P region are arranged at intervals. The width of the first P region is greater than the widths of the second P region, the third P region, and the P pillar. The bottoms of the second P region and the third P region are set in a stepped shape, and the depths of the second P region and the third P region are greater than the depth of the first P region. When the diode is in the surge current condition, the first P region is used to provide the main surge current channel, and the second P region and the third P region are used to share part of the surge current.

[0011] An ohmic contact layer located on the surfaces of the first P region, the second P region, and the third P region;

[0012] A passivation protection layer located on the surface of the terminal region;

[0013] A first metal layer located on the surface of the active region;

[0014] A second metal layer located on the back surface of the epitaxial wafer.

[0015] Optionally, the first P region includes a first P-type sub-region and a second P-type sub-region. The second P-type sub-region is located at the bottom of the first P-type sub-region, and the middle region of the second P-type sub-region is in contact with the first P-type sub-region. The second P-type sub-region is set in an arc shape.

[0016] Optionally, a first groove is provided on the surface of the first P-type sub-region, and the ohmic contact layer is in contact with the surface of the first groove and the mesa of the first P-type sub-region.

[0017] Optionally, both the second P region and the third P region include a third P-type sub-region, a fourth P-type sub-region, a fifth P-type sub-region, and a sixth P-type sub-region. The depth of the third P-type sub-region is equal to the depth of the P pillar. The fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region are all located at the bottom of the third P-type sub-region. The fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region are in contact in sequence, and the surfaces of the fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region are in contact with the bottom surface of the third P-type sub-region;

[0018] The depths of the fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region decrease in sequence, and the depth of the sixth P-type sub-region is greater than the depth of the first P region.

[0019] Optionally, the sizes of the fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region satisfy the formula:

[0020] H1 = 1 / 3H0;

[0021] H2 = 1 / 3(H0 - H1) = 2 / 9H0;

[0022] H1 > H2 > H3 > H4;

[0023] L0 = L1 = L2 = 1 / 3W1;

[0024] Among them, H0 represents the thickness of the fourth P-type sub-region, H1 represents the depth difference between the fourth P-type sub-region and the fifth P-type sub-region, H2 represents the depth difference between the fifth P-type sub-region and the sixth P-type sub-region, H3 represents the depth difference between the sixth P-type sub-region and the seventh P-type sub-region, H4 represents the depth difference between the seventh P-type sub-region and the eighth P-type sub-region, L0 represents the width of the fourth P-type sub-region, L1 represents the width of the fifth P-type sub-region, L2 represents the width of the sixth P-type sub-region, and W1 represents the width of the third P-type sub-region.

[0025] Optionally, both the second P-region and the third P-region further include a seventh P-type sub-region and an eighth P-type sub-region, and the surfaces of the seventh P-type sub-region and the eighth P-type sub-region are flush with the surface of the third P-type sub-region; the depths of the fourth P-type sub-region, the fifth P-type sub-region, the sixth P-type sub-region, the seventh P-type sub-region, and the eighth P-type sub-region decrease in sequence, and the depth of the eighth P-type sub-region is flush with the depth of the first P-region.

[0026] Optionally, a second trench and a third trench are further provided on the surface of the active region, the second trench is located at the central position between the first P-region and the second P-region, and the third trench is located at the central position between the first P-region and the third P-region.

[0027] Optionally, the dimensions of the composite structure satisfy the formula:

[0028] H0 > 2Hz;

[0029] (H0 + Hz - H5):(2W2 + W3) > 2;

[0030] Among them, H0 represents the thickness of the fourth P-type sub-region, Hz represents the thickness of the third P-type sub-region, H5 represents the depth of the second trench, W2 represents the distance between the side wall of the second trench and the eighth P-type sub-region, or the distance between the side wall of the second trench and the first P-region, and W3 represents the width of the second trench.

[0031] Optionally, the dimensions of the composite structure satisfy the formula:

[0032] (H0 + Hz):(W1 + L3 + L4) > 2.5;

[0033] H5 > 2W2;

[0034] Wherein, H0 represents the thickness of the fourth P-type sub-region, Hz represents the thickness of the third P-type sub-region, W1 represents the width of the third P-type sub-region, L3 represents the width of the seventh P-type sub-region, L4 represents the width of the eighth P-type sub-region, H5 represents the depth of the second trench, and W2 represents the distance between the sidewall of the second trench and the eighth P-type sub-region.

[0035] Optionally, the doping concentrations of the third P-type sub-region, the fourth P-type sub-region, the fifth P-type sub-region, the sixth P-type sub-region, the seventh P-type sub-region, and the eighth P-type sub-region are all different.

[0036] On the other hand, an embodiment of the present application also provides a method for manufacturing a diode for manufacturing the above-mentioned diode, and the method includes:

[0037] Providing an N-type epitaxial wafer;

[0038] Defining a terminal region and an active region based on the surface of the N-type epitaxial wafer; wherein, the active region includes a composite structure and a plurality of P-columns, the plurality of P-columns are arranged at intervals, and the composite structure is also arranged at intervals with the P-columns on both sides;

[0039] The composite structure includes a first P-region and second P-regions and third P-regions located on both sides of the first P-region, the first P-region, the second P-regions, and the third P-regions are arranged at intervals, the width of the first P-region is greater than the widths of the second P-regions, the third P-regions, and the P-columns, the bottoms of the second P-regions and the third P-regions are set in a stepped shape, and the depths of the second P-regions and the third P-regions are greater than the depth of the first P-region; wherein, when the diode is in a surge current condition, the first P-region is used to provide a main surge current channel, and the second P-regions and the third P-regions are used to share part of the surge current;

[0040] Manufacturing an ohmic contact layer based on the surfaces of the first P-region, the second P-regions, and the third P-regions;

[0041] Manufacturing a first metal layer on the surface of the active region;

[0042] Manufacturing a passivation protection layer based on the surface of the terminal region;

[0043] Manufacturing a second metal layer based on the back surface of the epitaxial wafer.

[0044] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0045] An embodiment of the present application provides a diode and a manufacturing method thereof. The diode includes an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein, the active region includes a composite structure and a plurality of P pillars, the plurality of P pillars are arranged at intervals, and there is also an interval between the composite structure and the P pillars on both sides; the composite structure includes a first P region, a second P region and a third P region located on both sides of the first P region, the first P region, the second P region and the third P region are arranged at intervals, the width of the first P region is greater than the widths of the second P region, the third P region and the P pillars, the bottoms of the second P region and the third P region are set in a stepped shape, and the depths of the second P region and the third P region are greater than the depth of the first P region; wherein, when the diode is in a surge current working condition, the first P region is used to provide a main surge current channel, and the second P region and the third P region are used to share part of the surge current; an ohmic contact layer located on the surfaces of the first P region, the second P region and the third P region; a passivation protection layer located on the surface of the terminal region; a first metal layer located on the surface of the active region; a second metal layer located on the back surface of the epitaxial wafer.

[0046] On the one hand, since the composite structure is added in the diode provided by the present application, and the composite structure can provide a main surge current channel under the action of the first P region, while the second P region and the third P region can share part of the surge current, the surge current handling capacity of the device is improved. On the other hand, since the depths of the second P region and the third P region are relatively deep, when the device is in reverse bias, it shields the high electric field, reduces the reverse leakage current, and improves the reverse breakdown voltage of the device.

[0047] To make the above objects, features and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, the detailed description is as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0049] Figure 1 It is a schematic cross-sectional structure diagram of the diode provided by the embodiment of the present application.

[0050] Figure 2 It is a schematic cross-sectional view of the composite structure provided by the embodiment of the present application.

[0051] Figure 3 It is a parameter schematic diagram of the composite structure provided by the embodiment of the present application.

[0052] Figure 4 It is another schematic cross-sectional view of the composite structure provided by the embodiment of the present application.

[0053] Figure 5 This is a schematic cross-sectional view of the epitaxial wafer provided by the embodiment of the present application.

[0054] Figure 6 This is a corresponding schematic cross-sectional view after ion implantation on the first epitaxial layer provided by the embodiment of the present application.

[0055] Figure 7 This is a corresponding schematic cross-sectional view after growing the second epitaxial layer on the surface of the first epitaxial layer provided by the embodiment of the present application.

[0056] Figure 8 This is a corresponding schematic cross-sectional view after ion implantation on the second epitaxial layer provided by the embodiment of the present application.

[0057] Figure 9 This is a corresponding schematic cross-sectional view after etching the active region provided by the embodiment of the present application.

[0058] In the figure:

[0059] 110 - N-type epitaxial wafer; 120 - P pillar; 130 - first P region; 140 - second P region; 150 - third P region; 160 - ohmic contact layer; 170 - terminal region; 180 - passivation protection layer; 190 - first metal layer; 200 - second metal layer; 210 - first trench; 220 - second trench; 230 - third trench; P1 - first P-type sub-region; P2 - second P-type sub-region; P3 - third P-type sub-region; P4 - fourth P-type sub-region; P5 - fifth P-type sub-region; P6 - sixth P-type sub-region; P7 - seventh P-type sub-region; P8 - eighth P-type sub-region. Detailed implementation manners

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0062] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, further definition and explanation thereof is not required in subsequent figures. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0063] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0064] The following will, with reference to the accompanying drawings, elaborate on some embodiments of the present application. Without conflict, the embodiments and features in the embodiments below may be combined with each other.

[0065] As described in the background art, there is a problem in the prior art that it is difficult to balance the nominal forward conduction ability, the surge current handling ability, and the unit chip cost of a diode.

[0066] In view of this, the present application provides a diode, which realizes the balance of the nominal forward conduction ability, the surge current handling ability, and the unit chip cost by adding a composite structure in the device to improve the reverse breakdown voltage, the surge current handling ability, and the nominal forward conduction ability of the device.

[0067] The following gives an exemplary description of the diode provided by the present application:

[0068] As an implementation manner, please refer to Figure 1 and Figure 2, the diode includes: an N-type epitaxial wafer 110; a terminal region 170 and an active region located on the surface of the N-type epitaxial wafer 110; wherein, the active region includes a composite structure and a plurality of P pillars 120, the plurality of P pillars 120 are arranged at intervals, and the composite structure is also arranged at intervals with the P pillars 120 on both sides; the composite structure includes a first P region 130, a second P region 140 and a third P region 150 located on both sides of the first P region 130, the first P region 130, the second P region 140 and the third P region 150 are arranged at intervals, the width of the first P region 130 is greater than the widths of the second P region 140, the third P region 150 and the P pillars 120, the bottoms of the second P region 140 and the third P region 150 are arranged in a stepped shape, and the depths of the second P region 140 and the third P region 150 are greater than the depth of the first P region 130; wherein, when the diode is in the surge current working condition, the first P region 130 is used to provide a main surge current channel, and the second P region 140 and the third P region 150 are used to share part of the surge current; an ohmic contact layer 160 located on the surfaces of the first P region 130, the second P region 140 and the third P region 150; a passivation protection layer 180 located on the surface of the terminal region 170; a first metal layer 190 located on the surface of the active region; a second metal layer 200 located on the back surface of the epitaxial wafer.

[0069] On the one hand, since a composite structure is added in the diode provided by the present application, and the composite structure can provide a main surge current channel under the action of the first P region 130, and at the same time the second P region 140 and the third P region 150 can share part of the surge current, the surge current handling ability of the device is improved. On the other hand, since the depths of the second P region 140 and the third P region 150 are relatively deep, a high electric field is shielded when the device is reverse-biased, the reverse leakage current is reduced, and the reverse breakdown voltage of the device is increased.

[0070] As an implementation manner, for the first P region 130, the first P region 130 includes a first P-type sub-region P1 and a second P-type sub-region P2, the second P-type sub-region P2 is located at the bottom of the first P-type sub-region P1, and the middle region of the second P-type sub-region P2 is in contact with the first P-type sub-region P1; the second P-type sub-region P2 is arranged in an arc shape.

[0071] For the MPS diode, the size of the first P-type sub-region P1 is the largest, that is, the size of the first P region 130 is the widest, so that a PN junction with a large area size can be formed in the epitaxial layer, the bipolar conduction ability of the device is improved, and further the surge current handling ability of the device is improved, ensuring the reliability and robustness of the device under short-time overload conditions.

[0072] Moreover, the width of the second P-type sub-region P2 is smaller than the width of the first P-type sub-region P1, and the second P-type sub-region P2 is arranged in an arc shape, which can buffer the electric field, increase the reverse breakdown voltage of the device, and improve the avalanche reliability and robustness of the device.

[0073] In addition, a first trench 210 is provided on the surface of the first P-type sub-region P1, and the ohmic contact layer 160 is in surface contact with the surface of the first trench 210 and the mesa of the first P-type sub-region P1.

[0074] By providing the first trench 210 on the surface of the first P-type sub-region P1, a P+ ohmic contact region with a larger area size can be formed on the sidewall of the trench, thereby enhancing the surge current handling capacity of the device. That is, by providing the first trench 210, the traditional planar ohmic contact region is converted into a three-dimensional ohmic contact region, and the area of the ohmic contact region is increased. On this basis, the chip area can be significantly reduced and the chip cost can be significantly reduced under the same surge current handling capacity of the device. The saved area can also be used to fabricate a larger Schottky region, thereby enhancing the unipolar conduction performance (nominal forward conduction capacity) of the device, that is, obtaining a lower forward conduction resistance and forward conduction voltage drop VF.

[0075] It should be noted that the nominal forward conduction capacity described in this application refers to the current handling capacity when the device is operating normally; the surge current handling capacity described in this application refers to the surge current conduction channel improved by the composite structure when a surge current is input to the diode, thereby avoiding damage to the device by the surge current. In addition, the composite structure provided in this application refers to the collection of the first P-region 130, the second P-region 140, and the third P-region 150. When the diode is operating normally, the current does not flow through the composite structure but through the Schottky region of the diode; when a surge current occurs, the surge current flows through the first P-region 130, the second P-region 140, and the third P-region 150.

[0076] In one implementation, to achieve the best comprehensive effect of the diode, the entire composite structure is symmetrically arranged, that is, the left and right sides of the first P-region 130 are symmetric about the midline, the second P-region 140 and the third P-region 150 are also symmetric about the midline, and the second P-region 140 and the third P-region 150 have the same structure.

[0077] As one implementation, the second P-region 140 and the third P-region 150 each include a third P-type sub-region P3, a fourth P-type sub-region P4, a fifth P-type sub-region P5, and a sixth P-type sub-region P6. The depth of the third P-type sub-region P3 is equal to the depth of the P pillar 120. The fourth P-type sub-region P4, the fifth P-type sub-region P5, and the sixth P-type sub-region P6 are all located at the bottom of the third P-type sub-region P3. The fourth P-type sub-region P4, the fifth P-type sub-region P5, and the sixth P-type sub-region P6 are in contact in sequence, and the surfaces of the fourth P-type sub-region P4, the fifth P-type sub-region P5, and the sixth P-type sub-region P6 are in contact with the bottom surface of the third P-type sub-region P3. The depths of the fourth P-type sub-region P4, the fifth P-type sub-region P5, and the sixth P-type sub-region P6 decrease in sequence, and the depth of the sixth P-type sub-region P6 is greater than the depth of the first P-region 130.

[0078] By setting multiple P-type sub-regions, the P+ region can penetrate deep into the epitaxial layer, shielding the high electric field when the device is reverse-biased, reducing the reverse leakage current, and increasing the reverse breakdown voltage of the device.

[0079] Meanwhile, to enhance the ability of the second P-region 140 and the third P-region 150 to share surge current, both the second P-region 140 and the third P-region 150 further include a seventh P-type sub-region P7 and an eighth P-type sub-region P8. The surfaces of the seventh P-type sub-region P7 and the eighth P-type sub-region P8 are flush with the surface of the third P-type sub-region P3; the depths of the fourth P-type sub-region P4, the fifth P-type sub-region P5, the sixth P-type sub-region P6, the seventh P-type sub-region P7, and the eighth P-type sub-region P8 decrease in sequence, and the depth of the eighth P-type sub-region P8 is flush with the depth of the first P-region 130, that is, the bottom surface of the eighth P-type sub-region P8 is flush with the bottom surface of the second P-type sub-region P2.

[0080] After setting the seventh P-type sub-region P7 and the eighth P-type sub-region P8, the seventh P-type sub-region P7, the eighth P-type sub-region P8, and the third P-type sub-region P3 can jointly form a P+ region with a relatively large area. Although the area of this region is still smaller than that of the first P-region 130, it can assist and cooperate with the first P-region 130, and effectively share part of the surge current, further improving the device's surge current handling ability and the thermal reliability and robustness under high current density.

[0081] In addition, by integrally setting the bottoms of the second P-region 140 and the third P-region 150 as a stepped shape, the PN junction formed between the composite structure and the epitaxial layer can be equivalently regarded as an arc-shaped structure as a whole, thereby increasing the area that the power lines of the depletion region can cover. The power lines are more dispersed, the electric field intensity distribution is gentle, the peak electric field is reduced, and the breakdown voltage, device reliability, and robustness can be improved.

[0082] Meanwhile, for the second P-region 140 and the third P-region 150, the doping concentrations of the third P-type sub-region P3, the fourth P-type sub-region P4, the fifth P-type sub-region P5, the sixth P-type sub-region P6, the seventh P-type sub-region P7, and the eighth P-type sub-region P8 are all different.

[0083] On this basis, when the diode is applied to a specific circuit, it is equivalent to introducing an equivalent resistance capacitance of the PN junction depletion region with an automatic buffering and suppressing effect in the current path. When an abnormal working condition occurs, the device can automatically and flexibly expand the PN depletion regions at different positions, and then automatically generate equivalent resistance capacitances of different sizes of the depletion layers, automatically suppressing problems such as EMI electromagnetic interference, oscillation, and surge. Finally, the device has better anti-electromagnetic interference, oscillation, surge, voltage and current overshoot capabilities, stronger short-circuit withstand capability SCWT, and high device reliability.

[0084] In addition, as an implementation, a second trench 220 and a third trench 230 are also provided on the surface of the active region. The second trench 220 is located at the central position between the first P region 130 and the second P region 140, and the third trench 230 is located at the central position between the first P region 130 and the third P region 150.

[0085] It can be understood that by providing the second trench 220 and the third trench 230, the planar Schottky region can be converted into a three-dimensional Schottky region, and then a Schottky contact region with a larger area size can be formed, thereby enhancing the unipolar conduction performance (nominal forward conduction ability) of the device, and obtaining a lower forward conduction resistance and forward conduction voltage drop VF.

[0086] Meanwhile, on the basis of setting the composite structure, since the size of the first P region 130 is larger than that of other regions, and the first P region 130 is in a non-conducting state during the normal operation of the device, the distribution of the nominal forward current flowing through the inside and outside of the composite structure region is uneven when the diode is operating normally. By providing the second trench 220 and the third trench 230, the overall distribution of the nominal forward current can be made more uniform, improving the reliability and robustness of the device. And it can make the entire device significantly reduce the chip area and significantly reduce the chip cost under the same unipolar conduction performance, and the saved area can be used to fabricate a P+ ohmic contact region with a larger area size, thereby enhancing the surge current handling ability of the device.

[0087] In order to improve the overall performance of the diode, the parameters of the composite structure are described below:

[0088] As an implementation, please refer to Figure 3 , the sizes of the fourth P-type sub-region P4, the fifth P-type sub-region P5, and the sixth P-type sub-region P6 satisfy the formula:

[0089] H1 = 1 / 3H0;

[0090] H2 = 1 / 3(H0 - H1) = 2 / 9H0;

[0091] H1 > H2 > H3 > H4;

[0092] L0 = L1 = L2 = 1 / 3W1;

[0093] Wherein, H0 represents the thickness of the fourth P-type sub-region P4, H1 represents the depth difference between the fourth P-type sub-region P4 and the fifth P-type sub-region P5, H2 represents the depth difference between the fifth P-type sub-region P5 and the sixth P-type sub-region P6, H3 represents the depth difference between the sixth P-type sub-region P6 and the seventh P-type sub-region P7, H4 represents the depth difference between the seventh P-type sub-region P7 and the eighth P-type sub-region P8, L0 represents the width of the fourth P-type sub-region, L1 represents the width of the fifth P-type sub-region P5, L2 represents the width of the sixth P-type sub-region P6, and W1 represents the width of the third P-type sub-region.

[0094] Through this implementation method, the PN junction of the overall composite structure can form a more uniform equivalent arc surface structure, increasing the area that the power lines of the depletion region can cover, making the power lines more dispersed, the electric field intensity distribution gentle, reducing the peak electric field, and improving the breakdown voltage, device reliability and robustness. At the same time, setting the widths of the fourth P-type sub-region P4, the fifth P-type sub-region P5, and the sixth P-type sub-region P6 to be equal is more conducive to achieving the equivalent arc surface effect of the PN junction, thereby achieving the best effect. In addition, since the second P-type sub-region P2 is set to be arc-shaped, the PN junction of the overall composite structure can form an equivalent arc surface structure with a buffer region at the top, flexibly adjusting the electric field distribution under high voltage, and further reducing the peak electric field.

[0095] It should be noted that the depth mentioned in this application refers to the position where the bottom surface of the P-type sub-region is located on the epitaxial wafer; the thickness mentioned in this application refers to the height difference between the bottom surface and the surface of the P-type sub-region.

[0096] And, as an implementation method, please combine Figure 3 with Figure 4 , the dimensions of the composite structure satisfy the formula:

[0097] H0 > 2Hz;

[0098] (H0 + Hz - H5) : (2W2 + W3) > 2;

[0099] Wherein, H0 represents the thickness of the fourth P-type sub-region, Hz represents the thickness of the third P-type sub-region P3, H5 represents the depth of the second trench 220, W2 represents the distance between the side wall of the second trench 220 and the eighth P-type sub-region P8, or the distance between the side wall of the second trench 220 and the first P-region 130, and W3 represents the width of the second trench 220. With this parameter setting, on the basis of ensuring that the second trench 220 and the third trench 230 can increase the Schottky contact area, it can achieve the best buffering and shielding effects on the high-voltage electric field, greatly reduce the device peak electric field, greatly reduce the reverse leakage current, greatly improve the device reverse breakdown voltage, and greatly improve the avalanche reliability and robustness of the device.

[0100] Moreover, in the present application, the dimensions of the composite structure satisfy the formula:

[0101] (H0 + Hz) : (W1 + L3 + L4) > 2.5;

[0102] H5 > 2W2;

[0103] Wherein, H0 represents the thickness of the fourth P-type sub-region, Hz represents the thickness of the third P-type sub-region, W1 represents the width of the third P-type sub-region, L3 represents the width of the seventh P-type sub-region, L4 represents the width of the eighth P-type sub-region, H5 represents the depth of the second trench, and W2 represents the distance between the side wall of the second trench and the eighth P-type sub-region.

[0104] By setting these parameters, it is easier to achieve charge balance in the device, thereby realizing the super junction effect, further increasing the reverse breakdown voltage of the device, and further improving the avalanche reliability and robustness of the device.

[0105] It should be noted that, in one implementation, the widths of the fourth P-type sub-region P4, the fifth P-type sub-region P5, the sixth P-type sub-region P6, the seventh P-type sub-region P7, and the eighth P-type sub-region P8 are all equal; in another implementation, the widths of the seventh P-type sub-region P7 and the eighth P-type sub-region P8 may also be unequal to the widths of the fourth P-type sub-region P4, the fifth P-type sub-region P5, and the sixth P-type sub-region P6, and no limitation is made here.

[0106] Meanwhile, setting H5 > 2W2 is more conducive to the device to exert the electrical performance and reliability advantages brought by the Schottky contact region with a larger area size. Moreover, setting H6 > 2W4, where H6 represents the depth of the first trench and W4 represents the mesa width of the first P-type sub-region P1 on one side of the first trench, is more conducive to the device to exert the electrical performance and reliability advantages brought by the P+ ohmic contact region with a larger area size.

[0107] Generally speaking, by setting the above composite structure (including different ion implantation regions and trench regions) and flexibly adjusting the dimensions and concentrations of each region, the forward conduction characteristics (such as nominal forward conduction ability, surge current handling ability), reverse blocking characteristics (such as reverse breakdown voltage), reliability and robustness (such as thermal, avalanche, surge, etc.), and the unit chip cost of the device can be flexibly adjusted and balanced.

[0108] Based on the above implementation, an embodiment of the present application provides a method for manufacturing a diode for manufacturing the above diode, and the method includes

[0109] S102, providing an N-type epitaxial wafer.

[0110] S104. Define the terminal region and the active region based on the surface of the N-type epitaxial wafer. Among them, the active region includes a composite structure and multiple P-columns, and the multiple P-columns are arranged at intervals, and there is also an interval between the composite structure and the P-columns on both sides.

[0111] The composite structure includes a first P-region and second P-regions and third P-regions located on both sides of the first P-region. The first P-region, the second P-regions, and the third P-regions are arranged at intervals. The width of the first P-region is greater than the widths of the second P-regions, the third P-regions, and the P-columns. The bottoms of the second P-regions and the third P-regions are set in a stepped shape, and the depths of the second P-regions and the third P-regions are greater than the depth of the first P-region. Among them, when the diode is in the surge current condition, the first P-region is used to provide the main surge current channel, and the second P-regions and the third P-regions are used to share part of the surge current.

[0112] S106. Fabricate an ohmic contact layer based on the surfaces of the first P-region, the second P-regions, and the third P-regions.

[0113] S108. Fabricate a first metal layer based on the surface of the active region.

[0114] S110. Fabricate a passivation protection layer based on the surface of the terminal region.

[0115] S112. Fabricate a second metal layer based on the back surface of the epitaxial wafer.

[0116] Next, in conjunction with the accompanying drawings, an exemplary description is given of the diode manufacturing method provided by the present application. It should be noted that in order to more clearly show the manufacturing process of the composite structure in the following drawings, only the region including the composite structure is shown, and other regions of the active region and the terminal region 170 are omitted.

[0117] As Figure 5 shown, the epitaxial wafer provided by the present application includes a substrate and a first epitaxial layer, and both the substrate and the first epitaxial layer can be made of SiC material.

[0118] The steps of S104 are as Figure 6 shown. First, ion implantation is performed at a set position on the first epitaxial layer, and the implantation parameters are adjusted, and then a second P-type sub-region P2, a fourth P-type sub-region P4, a fifth P-type sub-region P5, and a sixth P-type sub-region P6 are formed on the first epitaxial layer.

[0119] Next, please refer to Figure 7 , a second epitaxial layer is grown on the surface of the first epitaxial layer, and the second epitaxial layer has the same material as the first epitaxial layer. And the doping concentration of the second epitaxial layer can be the same as or different from the doping concentration of the first epitaxial layer. When the second epitaxial layer has a different doping concentration from the first epitaxial layer, the unipolar conduction performance (nominal forward conduction ability) of the device can be flexibly adjusted, that is, the forward conduction resistance and the forward conduction voltage drop VF of the device can be flexibly adjusted.

[0120] After growing the second epitaxial layer, refer to Figure 8 , based on the surface of the second epitaxial layer, adjust the implantation parameters and perform ion implantation at the specified positions. Thereby, a first P-type sub-region P1, a third P-type sub-region P3, a seventh P-type sub-region P7, an eighth P-type sub-region P8, and spaced P-columns 120 are formed on the second epitaxial layer. Among them, the seventh P-type sub-region P7 and the eighth P-type sub-region P8 need to penetrate into the first epitaxial layer.

[0121] Refer to Figure 9 , after ion implantation, etch the active region to form trenches. Among them, etch the middle region of the first P-type sub-region P1 to form a first trench 210; etch the second epitaxial layer between the first P-type sub-region P1 and the second P-region 140 to form a second trench 220; etch the second epitaxial layer between the first P-type sub-region P1 and the third P-region 150 to form a third back trench.

[0122] After that, perform ion implantation on the terminal region 170 and perform high-temperature furnace annealing. Then deposit ohmic contact metal Ni on the surfaces of the first P-region 130, the second P-region 140, and the third P-region 150, and perform ohmic contact annealing. Finally, fabricate a first metal layer 190 (aluminum metal), a passivation protection layer 180, and a second metal layer 200 on the back surface to complete the fabrication of the diode.

[0123] In summary, the embodiments of the present application provide a diode and a manufacturing method thereof. The diode includes an N-type epitaxial wafer; a terminal region and an active region located on the surface of the N-type epitaxial wafer. Among them, the active region includes a composite structure and a plurality of P pillars, and the plurality of P pillars are arranged at intervals, and the composite structure is also arranged at intervals with the P pillars on both sides; the composite structure includes a first P region, a second P region and a third P region located on both sides of the first P region, and the first P region, the second P region and the third P region are arranged at intervals. The width of the first P region is greater than the widths of the second P region, the third P region and the P pillars. The bottoms of the second P region and the third P region are set in a stepped shape, and the depths of the second P region and the third P region are greater than the depth of the first P region. Among them, when the diode is in the surge current condition, the first P region is used to provide the main surge current channel, and the second P region and the third P region are used to share part of the surge current; an ohmic contact layer located on the surfaces of the first P region, the second P region and the third P region; a passivation protection layer located on the surface of the terminal region; a first metal layer located on the surface of the active region; a second metal layer located on the back surface of the epitaxial wafer. On the one hand, since a composite structure is added to the diode provided by the present application, and the composite structure can provide the main surge current channel under the action of the first P region, and at the same time the second P region and the third P region can share part of the surge current, the surge current handling capacity of the device is improved. On the other hand, since the depths of the second P region and the third P region are relatively deep, high electric fields are shielded when the device is reverse-biased, the reverse leakage current is reduced, and the reverse breakdown voltage of the device is increased.

[0124] The foregoing is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0125] For those skilled in the art, it is obvious that the present application is not limited to the details of the above-described exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, it is intended to include all changes falling within the meaning and scope of the equivalent elements of the claims in the present application. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. A diode, characterized in that, The diode includes: An N-type epitaxial wafer; A terminal region and an active region located on the surface of the N-type epitaxial wafer; wherein, the active region includes a composite structure and a plurality of P pillars, the plurality of P pillars are arranged at intervals, and the composite structure is also arranged at intervals with the P pillars on both sides; The composite structure includes a first P region, a second P region, and a third P region located on both sides of the first P region, the first P region, the second P region, and the third P region are arranged at intervals, the width of the first P region is greater than the widths of the second P region, the third P region, and the P pillars, the bottoms of the second P region and the third P region are set in a stepped shape, and the depths of the second P region and the third P region are greater than the depth of the first P region; wherein, when the diode is in a surge current condition, the first P region is used to provide a main surge current channel, and the second P region and the third P region are used to share part of the surge current; An ohmic contact layer located on the surfaces of the first P region, the second P region, and the third P region; A passivation protection layer located on the surface of the terminal region; A first metal layer located on the surface of the active region; A second metal layer located on the back surface of the epitaxial wafer.

2. The diode according to claim 1, wherein The first P region includes a first P-type sub-region and a second P-type sub-region, the second P-type sub-region is located at the bottom of the first P-type sub-region, and the second P-type sub-region is in contact with the middle region of the first P-type sub-region; the second P-type sub-region is set in an arc shape.

3. The diode according to claim 2, wherein A first groove is provided on the surface of the first P-type sub-region, and the ohmic contact layer is in contact with the surface of the first groove and the mesa of the first P-type sub-region.

4. The diode according to claim 1, characterized in that, Both the second P region and the third P region include a third P-type sub-region, a fourth P-type sub-region, a fifth P-type sub-region, and a sixth P-type sub-region, the depth of the third P-type sub-region is equal to the depth of the P pillar, the fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region are all located at the bottom of the third P-type sub-region, the fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region are in contact in sequence, and the surfaces of the fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region are in contact with the bottom surface of the third P-type sub-region; The depths of the fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region decrease in sequence, and the depth of the sixth P-type sub-region is greater than the depth of the first P region.

5. The diode according to claim 4, wherein Both the second P region and the third P region further include a seventh P-type sub-region and an eighth P-type sub-region, the surfaces of the seventh P-type sub-region and the eighth P-type sub-region are flush with the surface of the third P-type sub-region; the depths of the fourth P-type sub-region, the fifth P-type sub-region, the sixth P-type sub-region, the seventh P-type sub-region, and the eighth P-type sub-region decrease in sequence, and the depth of the eighth P-type sub-region is flush with the depth of the first P region.

6. The diode according to claim 5, characterized in that, The sizes of the fourth P-type sub-region, the fifth P-type sub-region, and the sixth P-type sub-region satisfy the formula: H1 = 1 / 3H0; H2 = 1 / 3(H0 - H1) = 2 / 9H0; H1 > H2 > H3 > H4; L0 = L1 = L2 = 1 / 3W1; Wherein, H0 represents the thickness of the fourth P-type sub-region, H1 represents the depth difference between the fourth P-type sub-region and the fifth P-type sub-region, H2 represents the depth difference between the fifth P-type sub-region and the sixth P-type sub-region, H3 represents the depth difference between the sixth P-type sub-region and the seventh P-type sub-region, H4 represents the depth difference between the seventh P-type sub-region and the eighth P-type sub-region, L0 represents the width of the fourth P-type sub-region, L1 represents the width of the fifth P-type sub-region, L2 represents the width of the sixth P-type sub-region, and W1 represents the width of the third P-type sub-region.

7. The diode according to claim 6, wherein A second trench and a third trench are further provided on the surface of the active region. The second trench is located at the central position between the first P region and the second P region, and the third trench is located at the central position between the first P region and the third P region.

8. The diode according to claim 7, characterized in that, The size of the composite structure satisfies the formula: H0 > 2Hz; (H0 + Hz - H5):(2W2 + W3) > 2; Wherein, H0 represents the thickness of the fourth P-type sub-region, Hz represents the thickness of the third P-type sub-region, H5 represents the depth of the second trench, W2 represents the distance between the side wall of the second trench and the eighth P-type sub-region, or the distance between the side wall of the second trench and the first P region, and W3 represents the width of the second trench.

9. The diode according to claim 7, characterized in that, The size of the composite structure satisfies the formula: (H0 + Hz):(W1 + L3 + L4) > 2.5; H5 > 2W2; Wherein, H0 represents the thickness of the fourth P-type sub-region, Hz represents the thickness of the third P-type sub-region, W1 represents the width of the third P-type sub-region, L3 represents the width of the seventh P-type sub-region, L4 represents the width of the eighth P-type sub-region, H5 represents the depth of the second trench, and W2 represents the distance between the side wall of the second trench and the eighth P-type sub-region.

10. A method for manufacturing a diode, characterized in that, For manufacturing the diode according to any one of claims 1 to 9, the method includes: Providing an N-type epitaxial wafer; Defining a terminal region and an active region based on the surface of the N-type epitaxial wafer; wherein, the active region includes a composite structure and a plurality of P pillars, the plurality of P pillars are arranged at intervals, and the composite structure is also arranged at intervals with the P pillars on both sides; The composite structure includes a first P region and second P regions and third P regions on both sides of the first P region. The first P region, the second P regions, and the third P regions are arranged at intervals. The width of the first P region is greater than the widths of the second P regions, the third P regions, and the P pillars. The bottoms of the second P regions and the third P regions are arranged in a stepped shape, and the depths of the second P regions and the third P regions are greater than the depth of the first P region; wherein, when the diode is in a surge current working condition, the first P region is used to provide a main surge current channel, and the second P regions and the third P regions are used to share part of the surge current; Manufacturing an ohmic contact layer based on the surfaces of the first P region, the second P regions, and the third P regions; Manufacturing a first metal layer based on the surface of the active region; Manufacturing a passivation protection layer based on the surface of the terminal region; Manufacturing a second metal layer based on the back surface of the epitaxial wafer.

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