Power semiconductor device and method of manufacturing power semiconductor device

Abstract

A power semiconductor device includes: a semiconductor body having a drift region of a first conductivity type; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal; a trench grid structure extending from the first side into the semiconductor body, where the trench grid structure includes a plurality of macro cells, each macro cell including at least one first type micro cell configured for forward load current conduction and a number of second type micro cells not configured for forward load current conduction. Each of the first type of microcells and the second type of microcells is laterally confined by a respective portion of the trench grid structure. In each macro-cell, the number of the second type micro-cells is equal to or greater than the number of the first type micro-cells.

Description

Technical Field

[0001] This specification relates to embodiments of power semiconductor devices and methods of manufacturing power semiconductor devices. Background Art

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving electric motors or machines, rely on power semiconductor devices. For example, to name just a few, insulated gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in various applications, including but not limited to switching in power supplies and power converters.

[0003] Power semiconductor devices typically include a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted through the active region of the power semiconductor device. The active region is typically surrounded by an edge termination region, which is terminated by the edge of the chip.

[0004] In the case of a controllable power semiconductor device (e.g., a transistor), the load current path can be controlled by means of an insulating electrode (commonly referred to as a gate electrode). For example, when a corresponding control signal is received from a driver unit via a control terminal of the device, the control electrode can set the power semiconductor device to one of a forward conducting state and a blocking state.

[0005] In addition, some devices provide reverse load current capability; that is, the active region of the semiconductor body is also configured to conduct a reverse load current along a reverse load current path between two load terminals of the device. For example, an RC (reverse current) IGBT is a representative of such devices. In an RC IGBT, a single chip combines an IGBT structure and a diode structure.

[0006] Regarding IGBTs, a trend can be observed towards further reducing the pitch and subsequent mesa width in a typical strip cell design, called a micro-pattern trench (MPT) IGBT, which results in a lower V ce,sat and increased hole confinement. In doing so, several methods are implemented to restore dV / dt and / or dI / dt control (e.g., n-doped regions in the mesa, or p-doped regions at the bottom of the trench). This is supported by a carefully designed contact scheme, for example, by placing the trench at the gate or source potential and placing or omitting contact slots in different mesas. Summary of the Invention

[0007] The subject matter of the independent claims is proposed. The features of the exemplary embodiments are defined in the dependent claims.

[0008] According to an embodiment, a power semiconductor device includes: a semiconductor body having a drift region of a first conductivity type; a first load terminal located on a first side of the semiconductor body; a second load terminal located on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal; a trench grid structure extending from the first side into the semiconductor body, wherein the trench grid structure includes a plurality of macro cells, each macro cell including at least one first type of micro cell configured for forward load current conduction and a certain number of second type of micro cells not configured for forward load current conduction. Each of the first type of micro cell and the second type of micro cell is laterally confined by a corresponding portion of the trench grid structure. In each macro cell, the number of second type of micro cells is equal to or greater than the number of first type of micro cells.

[0009] According to another embodiment, a method of manufacturing a power semiconductor device includes forming the following components: a semiconductor body having a drift region of a first conductivity type; a first load terminal located on a first side of the semiconductor body; a second load terminal located on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal; a trench grid structure extending from the first side into the semiconductor body, wherein the trench grid structure includes a plurality of macro cells, each macro cell including at least one first type of micro cell configured for forward load current conduction and a certain number of second type of micro cells not configured for forward load current conduction. Each of the first type of micro cell and the second type of micro cell is laterally confined by a corresponding portion of the trench grid structure. In each macro cell, the number of second type of micro cells is equal to or greater than the number of first type of micro cells.

[0010] According to some embodiments described herein, herein, a simple and cost-effective cell design is proposed based on a simple square cell, which retains the important features of the MPT technology. For example, the new cell design outperforms previous solutions in maintaining good dV / dt and dI / dt control.

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the drawings. Description of the Drawings

[0012] The components in the various figures are not necessarily to scale; instead, emphasis is placed on illustrating the principles of the invention. Further, in the various figures, the same reference numerals designate corresponding components. In the drawings:

[0013] Figure 1 Schematically and exemplarily illustrates a horizontal projection of a power semiconductor device according to one or more embodiments;

[0014] Figure 2 Schematically and exemplarily illustrate a horizontal projection of a power semiconductor device according to one or more embodiments;

[0015] Figure 3 (A) Schematically and exemplarily illustrate a perspective projection of a power semiconductor device according to one or more embodiments;

[0016] Figure 3 (B) Schematically and exemplarily illustrate a horizontal projection of a power semiconductor device according to one or more embodiments;

[0017] Figure 4 Schematically and exemplarily illustrate a perspective projection of a power semiconductor device according to one or more embodiments;

[0018] Figure 5 Schematically and exemplarily illustrate a perspective projection of a power semiconductor device according to one or more embodiments;

[0019] Figure 6 Schematically and exemplarily illustrate a horizontal cross-section of a power semiconductor device according to one or more embodiments;

[0020] Figure 7 Schematically and exemplarily illustrate a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0021] Figure 8 (A) Schematically and exemplarily illustrate a horizontal cross-section of a power semiconductor device according to one or more embodiments;

[0022] Figure 8 (B) Schematically and exemplarily illustrate a perspective projection of a power semiconductor device according to one or more embodiments; and

[0023] Figure 9 Schematically and exemplarily illustrate a horizontal cross-section of a power semiconductor device according to one or more embodiments. Detailed Description

[0024] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced.

[0025] In this regard, directional terms such as "top", "bottom", "below", "front", "rear", "back", "leading", "trailing", "above", etc. may be used with reference to the orientation of the figure being described. Since the components of the embodiments may be positioned in many different orientations, the directional terms are for illustrative purposes and are in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0026] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and is not meant to be limiting of the invention. For example, features illustrated or described as part of one embodiment may be used on or in combination with other embodiments to yield yet additional embodiments. It is intended that the present invention include such modifications and variations. By using specific language to describe the examples, such specific language should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or fabrication steps have been designated by the same reference numerals in different figures where not otherwise stated.

[0027] As used in this specification, the term "horizontal" is intended to describe an orientation that is generally parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer or die or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, where the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0028] As used in this specification, the term "vertical" is intended to describe an orientation that is generally arranged perpendicular to a horizontal surface, i.e., parallel to the normal direction of the surface of a semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as the "vertical direction Z".

[0029] In this specification, n-doping is referred to as the "first conductivity type", while p-doping is referred to as the "second conductivity type". Alternatively, the opposite doping relationship may be employed such that the first conductivity type may be p-doping and the second conductivity type may be n-doping.

[0030] In the context of the present specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection", and "electrically connected" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, zones, parts, or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode of a semiconductor device and a part or component, where "low-ohmic" may mean that the characteristics of the corresponding contact are substantially not affected by ohmic resistance. Further, in the context of the present specification, the term "in contact" is intended to describe the presence of a direct physical connection between two elements of the corresponding semiconductor device; for example, the transition between two elements in contact with each other may not include additional intermediate elements and the like.

[0031] Additionally, in the context of the present specification, if not otherwise stated, the term "electrically insulated" is used in its generally reasonable understanding context and is thus intended to describe two or more components being positioned separately from each other and there being no ohmic connection connecting those components. However, components that are electrically insulated from each other may nevertheless be coupled to each other, for example, mechanically and / or capacitively and / or inductively and / or electrostatically (e.g., in the case of a "junction"). By way of example, the two electrodes of a capacitor may be electrically insulated from each other and at the same time mechanically and capacitively coupled to each other, for example, by means of an insulating part, such as a dielectric.

[0032] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that may be used in a power converter or a power supply. Thus, in one embodiment, such a power semiconductor device may be configured to carry a load current to be fed to a load and / or provided by a power supply, respectively. For example, the power semiconductor device may include one or more active power semiconductor unit cells, such as a monolithic integrated diode unit, a derivative of a monolithic integrated diode unit, a monolithic integrated transistor unit, such as a monolithic integrated IGBT or MOSFET unit and / or its derivatives. Such diode / transistor units may be integrated within a single chip. A plurality of such units may form a unit field arranged in the active region of the power semiconductor device.

[0033] The term "blocking state" of a power semiconductor device may refer to the situation when the power semiconductor is configured to block the flow of load current when an external voltage is applied. More specifically, the power semiconductor device may be configured to block the forward load current from passing through the power semiconductor device when a forward bias voltage is applied. In contrast, the power semiconductor device may be configured to conduct the forward load current in the "on state" of the power semiconductor device when a forward bias voltage is applied. The transition between the blocking state and the on state may be controlled by a control electrode, or more specifically, by the potential of the control electrode. Of course, the electrical characteristics may only apply within a predetermined operating range of the external voltage and current density within the power semiconductor device. Thus, the term "forward bias blocking state" may refer to the situation when the power semiconductor device is in the blocking state when a forward bias voltage is applied.

[0034] The term "power semiconductor device" as used in this specification is intended to describe a power semiconductor device on a single chip having high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor device is intended for high currents, typically in the ampere range, e.g., up to several tens or hundreds of amperes, and / or high voltages, typically above 15V, more typically 100V and above, e.g., up to at least 400V or even higher, e.g., up to at least 3kV, or even up to 10kV or higher, depending on the respective application.

[0035] For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices used for, e.g., storing data, computing data, and / or other types of semiconductor-based data processing.

[0036] For example, the power semiconductor device described below may be a single semiconductor chip, which, for example, exhibits a rectangular cell configuration, a square cell configuration, or a hexagonal cell configuration, and may be configured to be used as a power component in low, medium, and / or high voltage applications.

[0037] First, referring to Figure 6 and 7 , a possible general configuration of the power semiconductor device 1 will be explained:

[0038] The power semiconductor device 1 (also referred to herein as the "device") includes, for example, a semiconductor body 10 in a single chip, and the semiconductor body 10 is configured to conduct a load current between a first load terminal 11 at a first side 110 of the semiconductor body 10 and a second load terminal 12 at a second side 120 of the semiconductor body 10.

[0039] The first side 110 and the second side 120 can be arranged opposite to each other. For example, the first side 110 is the front side of the device 1 and the second side 20 is the back side of the device 1. Thus, the device 1 can exhibit a vertical configuration, according to which the load current within the device 1 follows a path parallel to the vertical direction Z. The semiconductor body 10 can be sandwiched between the first load terminal 11 and the second load terminal 12, and exhibits a vertical extension d, for example in the range of 50 μm to 700 μm, which depends on the specified maximum blocking voltage.

[0040] The device 1 further includes a drift region 100 of a first conductivity type within the semiconductor body 10. Herein, the meaning of the term "drift region" is what a person skilled in the art would typically associate with it in the field of power semiconductor devices. For example, the vertical extension of the drift region 100 affects the voltage blocking ability of the device 1 (e.g., the maximum blocking voltage).

[0041] The device 1 further includes a trench grid structure 13 that extends from the first side 110 towards the second side 120, for example along the vertical direction Z into the semiconductor body 10. The trench grid structure 13 will be described in more detail below. The trench grid structure 13 can include at least one trench control electrode 141 (see Figure 3 ), which is electrically insulated from the first load terminal 11 and is configured to receive a control signal. For this purpose, according to one embodiment, the trench control electrode 141 can be electrically connected to a control terminal (not shown) of the device 1.

[0042] On the first side 110, the semiconductor body 10 further includes a semiconductor body region 102 of a second conductivity type electrically connected to the first load terminal 11 and a semiconductor source region 101 of a first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is isolated from the drift region 100 by at least the semiconductor body region 102. The trench control electrode 141 of the trench grid structure 13 can be configured to induce an inversion channel in the semiconductor body region 102 when a corresponding conduction control signal is received. This process can set the device 1 to the forward conduction state. The trench control electrode 141 can also be configured to cut off the inversion channel in the semiconductor body region 102 when a corresponding turn-off control signal is received, which can set the device 1 to the forward blocking state.

[0043] The doped region 108 of the semiconductor body 10, which is adjacent to the second load terminal 12 at the second side 120 and is below the drift region 100, can be configured according to the specified characteristics of the device 1. For example, if the device 1 is to exhibit an IGBT configuration, the doped region 108 can be an emitter region of a second conductivity type. The emitter region is arranged to contact the second load terminal 12.

[0044] Furthermore, a field stop region of a first conductivity type (not shown) may be provided between the drift region 100 and the second load terminal 12, where the field stop region exhibits a greater dopant concentration than the drift region 100.

[0045] If the device 1 is to exhibit a MOSFET configuration, the emitter region is omitted such that the field stop region (or another highly doped region of the first conductivity type) will be adjacent to the second load terminal 12. As is known to those skilled in the art, if the device 1 is to exhibit an RC IGBT configuration, the emitter region may exhibit a sub-segment of the first conductivity type.

[0046] The above components of the power semiconductor device 1 are arranged in the active region 1-2 of the device 1 (see Figure 6 ), which active region is surrounded by an edge termination region 1-3. In the active region 1-2, a trench grid structure (13) may form cell fields, which will be further explained below. As is known to those skilled in the art, the edge termination region 1-3 is generally not used for load current conduction. The edge termination region 1-3 is terminated by the chip edge 1-4.

[0047] Figure 1 and Figure 2 both schematically and exemplarily illustrate a horizontal projection of a power semiconductor device according to one or more embodiments. Illustrated is an example of a trench grid structure 13 extending from a first side 110 into the semiconductor body 10. The trench grid structure 13 includes a plurality of macro cells 130, Figure 1 and Figure 2 illustrate one of the macro cells therein, respectively.

[0048] Each macro cell 130 includes at least one first type micro cell 131 configured for forward load current conduction and a certain number of second type micro cells 132 not configured for forward load current conduction. The number of second type micro cells 132 may total zero, one, or more than one. In these second type micro cells, there is no forward load current conduction. For example, for this purpose, according to one embodiment, the semiconductor source region 101 is implemented only in the first type micro cells 131 and not in the second type micro cells. Furthermore, according to one embodiment, each first type micro cell 131 is electrically connected to the first load terminal 11, for example based on an ohmic contact. The second type micro cells 132 do not have to be electrically connected to the first load terminal 11.

[0049] In one embodiment, none of the second type micro cells 132 are electrically connected to the first load terminal 11. For example, this variant may be suitable in the case where the device 1 exhibits an IGBT configuration.

[0050] In one embodiment, some or all of the second type of microcells 132 are also electrically connected to the first load terminal 11. For example, this variant may be appropriate in the case where the device 1 exhibits an RC-IGBT configuration. Still, in this embodiment, none of the second type of microcells 132 includes a semiconductor source region 101.

[0051] As Figure 1 and Figure 2 illustrated both therein, each of the first type of microcells 131 and the second type of microcells 132 is laterally confined by a respective portion of the trench grid structure 13. Additionally, in each macrocell 130, the number of second type of microcells 132 (if implemented) is equal to or greater than the number of first type of microcells 131.

[0052] In one embodiment, each first type of microcell 131 exhibits a rectangular horizontal cross-sectional area with an aspect ratio between its sides of at most 2:1. For example, each first type of microcell 131 exhibits a square horizontal cross-sectional area. For example, each first type of microcell 131 exhibits a rectangular horizontal cross-sectional area with an aspect ratio between its sides greater than 1:1 (such that the first type of microcell 131 is not square) and at most 2:1. Similarly, each second type of microcell 132 may exhibit a rectangular horizontal cross-sectional area with an aspect ratio between its sides of at most 2:1. For example, each second type of microcell 132 exhibits a square horizontal cross-sectional area. For example, each second type of microcell 132 exhibits a rectangular horizontal cross-sectional area with an aspect ratio between its sides greater than 1:1 (such that the second type of microcell 131 is not square) and at most 2:1.

[0053] Referring Figure 9 , in one embodiment, each of the first type of macrocells 131 and the second type of macrocells 132 exhibits the same size and shape, namely a hexagonal shape. The first type of macrocells 131 and the second type of macrocells 132 may be arranged in a hexagonal packing within the active region 1-2. For example, the length a of each side of each hexagon hex may be in the range of 2 μm to 4 μm, such as 3 μm.

[0054] Still referring Figure 9 , according to one embodiment, it can be ensured that the source region 101 extends only along the sections of the trench structure 13 that exhibit the same orientation, such as along the first transverse direction X, as Figure 9 illustrated therein. Thus, variations in the threshold voltage V of the device 1 due to eventual variations in the thickness of the trench insulator 142 can be reduced or even avoided. This variant can also be provided to the embodiments illustrated in, for example, th and Figure 1 and Figure 2 contrary to the exemplary illustration therein.

[0055] In addition, return reference Figure 1 and Figure 2 both, according to one embodiment, each macro cell 130, each first type of micro cell 131, and each second type of micro cell 132 exhibit at least substantially rectangular horizontal cross-sectional areas. For example, Figure 1 the second type of micro cell 132 in Figure 2 has a rectangular horizontal cross-sectional area, while the second type of micro cell 132 in

[0056] has a substantially rectangular horizontal cross-sectional area, where small sub-sections are "carved out" by the first type of micro cell 131. For example, each first type of micro cell 131 (e.g., having, for example, a rectangular or square horizontal cross-section) exhibits a horizontal cross-sectional area less than 5μm * 5μm, less than 4μm * 4μm, less than 3μm * 3μm, or even less than 2μm * 2μm. Similarly, each second type of micro cell 132 (e.g., having, for example, a rectangular or square horizontal cross-section) exhibits a horizontal cross-sectional area less than 5μm * 5μm, less than 4μm * 4μm, less than 3μm * 3μm, or even less than 2μm * 2μm.

[0057] In addition, according to one embodiment, each part of the grid structure 13 is shorter than 10μm, and each part laterally confines one of the first type of micro cells 131 and / or one of the second type of micro cells 132 and continuously extends along the first lateral direction X or the second lateral direction Y until it abuts another part of the grid structure 13 that extends perpendicularly thereto.

[0058] In one embodiment, in each macro cell 130, at least one first type of micro cell 131 is surrounded by the second type of micro cells 132. For example, as best illustrated in Figure 1 , 2 and 8, it can be stipulated that in each macro cell 130, at least one first type of micro cell 131 is only surrounded by the second type of micro cells 132.

[0059] In another embodiment, in each macro cell 130, at least one first type of micro cell 131 exhibits a horizontal cross-sectional area smaller than each of the horizontal cross-sectional areas of the second type of micro cells 132. In another embodiment, in each macro cell 130, at least one first type of micro cell 131 exhibits a horizontal cross-sectional area equal to the horizontal cross-sectional area of at least one of the second type of micro cells 132; for example, each of the first type of micro cells 131 and the second type of micro cells 132 exhibits the same size. In yet another embodiment, at least one first type of micro cell 131 exhibits a horizontal cross-sectional area larger than each of the horizontal cross-sectional areas of the second type of micro cells 132.

[0060] In another embodiment, in each macro cell 130, the ratio of the number of second type micro cells 132 to the number of first type micro cells 131 is at least 3 / 1. For example, each macro cell 130 includes a first number of first type micro cells 131 and a second number of second type micro cells 132, where the second number is at least three times the first number.

[0061] Regarding Figure 3 (A) and (B), further optional aspects of the trench grid structure 13 will be explained. Figure 3 (B) corresponds to what was explained above Figure 2 and Figure 3 (A) illustrates the Figure 3 associated perspective view of the part of Figure 3 (B) indicated by the dashed line in

[0062] Thus, the trench grid structure 13 can accommodate the trench control electrode 141 and the trench insulator 142 that electrically insulates the trench control electrode 141 from the semiconductor body 10. In one embodiment, at least each first type micro cell 131 is surrounded by a corresponding part of the grid structure 13. For example, at least each first type micro cell 131 is surrounded by a part of the trench control electrode 141. As explained above regarding Figure 1 and Figure 2 the trench control electrode 141 is configured to induce an inversion channel in each first type micro cell 131 when a control signal is applied.

[0063] In one embodiment, it can even be stipulated that the trench grid structure 13 exclusively accommodates the trench control electrode 141, where, for example, the trench control electrode 141 forms an uninterrupted conductive structure within the trench grid structure 13. For example, the design proposed herein allows for avoiding the implementation of source trenches or other trench types, which in turn facilitates the contact scheme.

[0064] Furthermore, each first type micro cell 131 can be electrically connected to the first load terminal 11, for example based on an ohmic contact such as a contact plug 111, which can present a closed route substantially along the outer periphery of the corresponding first type micro cell 131, as Figure 3 schematically illustrated in

[0065] Each first-type microcell 131 may further include the semiconductor source region 101 of a first conductivity type and the semiconductor body region 102 of a second conductivity type. The semiconductor body region 102 isolates the semiconductor source region 101 from the drift region 100, and both the semiconductor source region 101 and the semiconductor body region 102 are electrically connected to the first load terminal 11, for example, based on the contact plug 111.

[0066] The doping and size of the source region 101 can be adjusted according to the specified characteristics of the device. For example, for the contact plug 111, it can also be specified that the source region 101 also presents a closed route substantially along the outer circumference of the corresponding first-type microcell 131, rather than only about 50% of it, as Figure 3 schematically illustrated. Then, the first-type microcell 131 will be "surrounded" by the semiconductor source region 101.

[0067] The body region 102 may extend into both the first- and second-type microcells 131, 132.

[0068] Both the semiconductor source region 101 and the semiconductor body region 102 are electrically connected to the first load terminal 11.

[0069] For example, on the first side 110, the body region 102 presents a highly doped sub-part 1021 to improve the electrical contact with the first load terminal 11. In one embodiment, it is further ensured that the depth presented by the body region 102 within the macrocell 130 is less than 50% of the depth of the trench grid structure 13. For example, ensuring that the bottom of the trench grid structure 13 terminates in the drift region 100 or in a differently doped sub-segment thereof, such as a barrier region, etc.

[0070] Furthermore, as illustrated, according to one embodiment, the trench grid structure 13 presents a constant depth along the vertical direction Z, and the local variation of the constant depth is less than 1 μm. The variation can also be significantly less than 1 μm.

[0071] Part of the trench grid structure 13 is filled with an isolation material instead of the electrode material for forming the trench control electrode 141, for example, in order to adjust the total gate charge.

[0072] Figure 4 A slightly modified version of the first-type microcell 131 is shown. The first-type microcell 131 also presents a square horizontal cross-sectional area, where the semiconductor source region 101 extends only between two of the four corners ( Figure 4(Only one of the corners is illustrated). In this embodiment, the macro cell 130 does not include any micro cells 132 of the second type; thus, due to the relatively high density of the micro cells 131 of the first type, the size of the source region 101 in each micro cell 131 of the first type remains relatively small. According to other embodiments, there are regions on the semiconductor device 10 that are entirely formed by the micro cells 131 of the first type and are separated from each other by regions composed of the micro cells 132 of the second type.

[0073] In one embodiment, in each micro cell 131 of the first type, the ratio between the lateral length of the source region 101 and the horizontal cross-sectional area of the micro cell 131 of the first type is less than 1 / 5 μm.

[0074] Figure 5 A variant of the macro cell 130 is shown, including three micro cells 132 of the second type and one micro cell 131 of the first type, each of which presents a square horizontal cross-sectional region and is separated from each other based on the trench grid structure 13. For example, in this variant, compared with Figure 4 the variant of, the size of the source region 101 in each micro cell 131 of the first type increases.

[0075] Figure 8 (A) and Figure 8 (B) show yet another variant of the macro cell 130, including eight micro cells 132 of the second type and one micro cell 131 of the first type, each micro cell presenting a rectangular / square horizontal cross-sectional region and being separated from each other based on the trench grid structure 13. For example, in this variant, compared with Figure 4 the variant of, the size of the source region 101 in each micro cell 131 of the first type increases. In addition, Figure 8 One feature of the above embodiment is illustrated, according to which a part of the trench grid structure is filled with the isolation material 143 instead of the electrode material.

[0076] Of course, Figure 8 (A) and (B) are merely schematic and exemplary; depending on the specified characteristics of the device 1, the part and position of the trench grid structure including the isolation material 143 can vary. For example, the isolation material 143 can also be deposited in the bottom region of the trench grid structure 13, for example, before filling the trench grid structure with the electrode material for forming the trench control electrode 141.

[0077] The present invention also provides a method for manufacturing a power semiconductor device. For example, the method for manufacturing a power semiconductor device includes forming the following components: a semiconductor body having a drift region of a first conductivity type; a first load terminal located on a first side of the semiconductor body; a second load terminal located on a second side of the semiconductor body opposite to the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal; a trench grid structure extending from the first side into the semiconductor body, wherein the trench grid structure includes a plurality of macro cells, each macro cell including at least one first type of micro cell configured for forward load current conduction and a certain number of second type of micro cells not configured for forward load current conduction. Each of the first type of micro cells and the second type of micro cells is laterally confined by a corresponding portion of the trench grid structure. In each macro cell, the number of the second type of micro cells is equal to or greater than the number of the first type of micro cells.

[0078] Embodiments of the method described above correspond to embodiments of the power semiconductor device 1 described above. Therefore, these embodiments of the method will not be described verbatim herein, but reference is made to the above.

[0079] For example, as indicated above, according to one embodiment, the proposed trench grid structure allows for a relatively low complexity manufacturing process, for example because there is no need for contact source trenches or other trenches. Further, in one embodiment, only the gate runners in the edge termination regions 1-3 are required to electrically contact the control electrodes 141 in the trench structure 13. For example, the control electrodes 141 are connected to each other uninterruptedly across the macro cells 130. Thereby, it is possible to avoid gate fingers (or other structures) extending into the active region 1-2 to contact the control electrodes 141 there, and the processing complexity for manufacturing the power semiconductor device 1 is correspondingly lower.

[0080] In the foregoing, embodiments of the power semiconductor device and the corresponding manufacturing method have been explained.

[0081] For example, these power semiconductor devices are based on silicon (Si). Correspondingly, the single crystal semiconductor region or layer, such as the semiconductor body and its regions / zones, such as zones, etc., may be single crystal Si regions or Si layers. In other embodiments, polycrystalline or amorphous silicon may be employed.

[0082] However, it should be understood that the semiconductor body and its regions / zones can be made of any semiconductor material suitable for fabricating semiconductor devices. Examples of such materials include, but are not limited to, the following: elemental semiconductor materials such as silicon (Si) or germanium (Ge); group-IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The previously mentioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, the following: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs, and GaN materials are currently mainly used.

[0083] Spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., are used for ease of description to explain the orientation of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding device in addition to those depicted in the figures. Further, terms such as "first", "second", etc. are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout this description, the same terms may refer to the same elements.

Claims

1. A power semiconductor device (1), comprising: - a semiconductor body (10) having a drift region (100) of a first conductivity type; - a first load terminal (11) located on a first side (110) of the semiconductor body (10); a second load terminal (12) located at a second side (120) of the semiconductor body (10) opposite to the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12); - a trench grid structure (13) extending from the first side (110) into the semiconductor body (10), wherein the trench grid structure comprises a plurality of macro cells (130), each macro cell (130) comprising at least one first type micro cell (131) configured for forward load current conduction and a number of second type micro cells (132) not configured for forward load current conduction, wherein: o each of the first type microcell (131) and the second type microcell (132) is laterally confined by a respective portion of the trench grid structure (13); and o In each macrocell (130), the number of the second type microcells (132) is equal to or greater than the number of the first type microcells (131).

2. The power semiconductor device (1) according to claim 1, wherein the trench grid structure (13) accommodates a trench control electrode (141) and a trench insulator (142) which electrically insulates the trench control electrode (141) from the semiconductor body (10).

3. The power semiconductor device (1) according to claim 2, wherein: At least each first type microcell (131) is surrounded by a portion of the trench control electrode (141).

4. The power semiconductor device (1) according to claim 2 or 3, wherein: The channel control electrode (141) is configured to induce an inversion channel in each of the first-type microcells (131) when receiving a control signal.

5. The power semiconductor device (1) according to any one of the preceding claims 2 to 4, wherein: The trench grid structure (13) exclusively accommodates the trench control electrode (141), and wherein the trench control electrode (141) forms an uninterrupted conductive structure within the trench grid structure (13).

6. The power semiconductor device (1) according to any one of the preceding claims, wherein: Each first type microcell (131) is electrically connected to a first load terminal (11), for example based on an ohmic contact.

7. The power semiconductor device (1) according to any one of the preceding claims, wherein: Each first type microcell (131) comprises a semiconductor source region (101) of a first conductivity type and a semiconductor body region (102) of a second conductivity type, wherein the semiconductor body region (102) isolates the semiconductor source region (101) from the drift region (100), and wherein both the semiconductor source region (101) and the semiconductor body region (102) are electrically connected to a first load terminal (11).

8. The power semiconductor device (1) according to any one of the preceding claims, wherein: None of the second type microcells (132) include a region of the first conductivity type electrically connected to the first load terminal (11).

9. The power semiconductor device (1) according to any one of the preceding claims, wherein: Each first type micro unit (131) presents a rectangular horizontal cross-sectional area, and the aspect ratio between its sides is at most 2:

1.

10. The power semiconductor device (1) according to any one of the preceding claims, wherein: Each macro unit (130), each first type micro unit (131) and each second type micro unit (132) presents a rectangular horizontal cross-sectional area.

11. The power semiconductor device (1) according to any one of the preceding claims, wherein: Each first type micro-unit (131) presents a horizontal cross-sectional area smaller than 5 μm*5 μm.

12. The power semiconductor device (1) according to any one of the preceding claims, wherein: In each macro-unit (130), the at least one first-type micro-unit (131) presents a horizontal cross-sectional area that is smaller than each of the horizontal cross-sectional areas of the second-type micro-unit (132).

13. The power semiconductor device (1) according to any one of the preceding claims, wherein: In each macrocell (130), at least one first-type microcell (131) is surrounded by a second-type microcell (132).

14. The power semiconductor device (1) according to any one of the preceding claims, wherein: In each macrocell (130), the ratio of the number of the second type microcells (132) to the number of the first type microcells (131) is at least 3 / 1.

15. The power semiconductor device (1) according to any one of the preceding claims, wherein: The groove grid structure (13) presents a constant depth along the vertical direction (Z), and the constant depth locally varies by less than 1 μm.

16. The power semiconductor device (1) according to any one of the preceding claims, wherein: Parts of the trench grid structure (13) are filled with an isolation material (143), for example, in order to adjust the total gate charge.

17. The power semiconductor device (1) according to any one of the preceding claims, wherein: Each first type micro unit (131) presents a square horizontal cross-sectional area.

18. The power semiconductor device (1) according to any one of the preceding claims, wherein: Each of the one or more first-type microcells (131) is surrounded by a semiconductor source region (101) within the corresponding first-type microcell (131).

19. The power semiconductor device (1) according to any one of the preceding claims, wherein: The semiconductor body region (102) has a depth within the macrocell (130) that is less than 50% of the depth of the trench grid structure (13).

20. A method of manufacturing a power semiconductor device (1), comprising forming the following components: - a semiconductor body (10) having a drift region (100) of a first conductivity type; - a first load terminal (11) located on a first side (110) of the semiconductor body (10); a second load terminal (12) located at a second side (120) of the semiconductor body (10) opposite to the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12); - a trench grid structure (13) extending from the first side (110) into the semiconductor body (10), wherein the trench grid structure comprises a plurality of macro cells (130), each macro cell (130) comprising at least one first type micro cell (131) configured for forward load current conduction and a number of second type micro cells (132) not configured for forward load current conduction, wherein: o each of the first type microcell (131) and the second type microcell (132) is laterally confined by a respective portion of the trench grid structure (13); and o In each macrocell (130), the number of the second type microcells (132) is equal to or greater than the number of the first type microcells (131).

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