Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a display area and a bending area located on one side of the display area, and a driving chip is arranged on the side, away from the display area, of the bending area; the display panel comprises a GOA circuit and a Fanout wire which are arranged on a substrate, the GOA circuit is located in a display area, and the signal input end of the GOA circuit is electrically connected with a driving chip through a GOA input wire; at least part of the Fanout wire is overlapped with the orthographic projection of the display area, the Fanout wire is electrically connected with the driving chip, and the GOA circuit located in the display area and the Fanout wire are arranged in a staggered mode; a pixel circuit is arranged on the side, away from the substrate, of the GOA circuit, the GOA circuit is electrically connected with the pixel circuit, and the Fanout wire is electrically connected with the pixel circuit. According to the display panel, the GOA circuit and part of Fanout wires are arranged below the pixel circuit, so that the frame width of the display panel can be remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related technology, the display panel layouts the GOA circuit on the left and right sides outside the display area AA, and layouts the Fanout wiring on the bottom side outside the display area. The GOA circuit and the Fanout wiring will occupy the space in the border area, which is not conducive to the narrow border design of the display panel and does not conform to the development trend of ultra-narrow border or even borderless display panels. Summary of the invention

[0003] In view of the above defects or shortcomings in the prior art, it is desirable to provide a display panel and a display device.

[0004] In a first aspect, a display panel is provided, comprising: a display area and a bending area located at one side of the display area, wherein a driving chip is arranged at a side of the bending area away from the display area; The display panel includes a GOA circuit and a Fanout wiring arranged on a base substrate, the GOA circuit is located in the display area, and a signal input end of the GOA circuit is electrically connected to the driving chip through the GOA input wiring passing through the bending area; At least a portion of the Fanout wiring is overlapped with the orthographic projection of the display area, the Fanout wiring is electrically connected to the driver chip, and the GOA circuit located in the display area and the Fanout wiring are staggered; A pixel circuit is arranged on a side of the GOA circuit away from the base substrate. The GOA circuit is electrically connected to a signal input terminal of the pixel circuit via a GOA output wiring, and the Fanout wiring is electrically connected to the pixel circuit.

[0005] In some embodiments, a first border area is provided between the display area and the bending area, and at least a portion of the Fanout wiring extends from an end surface of the display area away from the bending area to an end surface of the display area close to the bending area, and passes through the first border area and the bending area in sequence and is electrically connected to the driving chip.

[0006] In some embodiments, the display area includes a first fan-out area and a second fan-out area arranged in sequence away from the bending area, the Fanout wiring is arranged in both the first fan-out area and the second fan-out area, and the projection area of ​​the first fan-out area on the substrate is larger than the projection area of ​​the second fan-out area on the substrate.

[0007] In some embodiments, the width of the first fan-out region remains unchanged from the side of the display region away from the bending region to the side close to the bending region; the width of the second fan-out region gradually decreases from the side of the display region away from the bending region to the side close to the bending region, and the width of the first fan-out region does not exceed the width of the second fan-out region.

[0008] In some embodiments, a Cell detection circuit is provided between the first fan-out region and the second fan-out region.

[0009] In some embodiments, the GOA circuit includes a plurality of cascaded GOA units, the GOA units are distributed at both side edges adjacent to the bending region in the display region, and the GOA units are arranged on both sides of the first fan-out region, and the GOA units are arranged to avoid the Fanout traces in the first fan-out region and the second fan-out region.

[0010] In some embodiments, a plurality of GOA units arranged at the same-side edge position in the display region form at least two columns of GOA modules, and multiple columns of GOA modules arranged on the same side of the display region are arranged in sequence from the inside to the outside, and the plurality of GOA units included in each column of GOA modules are arranged from the side of the display region away from the bending region to the side close to the bending region.

[0011] In some embodiments, a plurality of GOA units arranged at the same-side edge position in the display region form two columns of GOA modules, namely a first column of GOA modules and a second column of GOA modules. The first column of GOA modules is located outside the second column of GOA modules, and both the first column of GOA modules and the second column of GOA modules are spaced from the end face of the display region away from the bending region to form a routing layout space, and the second fan-out region is located within the routing layout space.

[0012] In some embodiments, a flexible circuit board is further provided on the side of the driving chip away from the bending region; The display panel further includes a second border region, a third border region, and a fourth border region sequentially arranged around the display region. The first border region and the third border region are oppositely arranged in a first direction, the second border region and the fourth border region are oppositely arranged in a second direction, and the first direction intersects with the second direction; A first VSS trace is formed by surrounding within the first border region, the second border region, the third border region, and the fourth border region, and both ends of the first VSS trace in the first border region are electrically connected to the flexible circuit board; The first VSS trace in the first border area and the first VSS trace in the third border area are electrically connected through a second VSS trace covering the display area.

[0013] In some embodiments, the first VSS trace and the second VSS trace are disposed on the same layer, and the first VSS trace and the Fanout trace are not disposed on the same layer.

[0014] In some embodiments, the GOA unit includes a first thin film transistor, and the pixel circuit includes a second thin film transistor, and the second thin film transistor is stacked on a side of the first thin film transistor away from the substrate; The output signal trace of the first thin film transistor extends to the second border area or the fourth border area, and is electrically connected to the signal input end of the second thin film transistor through an inorganic via in the corresponding border area.

[0015] In some embodiments, a spacer layer is disposed between the first thin film transistor and the second thin film transistor, and the spacer layer is an inorganic spacer layer or / and an organic spacer layer.

[0016] In some embodiments, the spacer layer includes a first source electrode and a first drain electrode for forming the first thin film transistor in the display area, and a first source-drain electrode in the second border area and the fourth border area; A planarization layer is disposed on a side of the spacer layer away from the substrate, and the planarization layer includes a second source electrode and a second drain electrode for forming the second thin film transistor in the display area, and a second source-drain electrode in the second border area and the fourth border area; The first source-drain electrode and the second source-drain electrode in the same border area are electrically connected through an inorganic via provided in the corresponding border area, and the second source-drain electrode is electrically connected to the gate of the second thin film transistor through the inorganic via.

[0017] In some embodiments, the first thin film transistor also includes a first active layer arranged on the base substrate, a first gate insulating layer covering the first active layer is arranged on a side of the first active layer away from the base substrate, a first gate is arranged on a side of the first gate insulating layer away from the first active layer, a first interlayer dielectric layer covering the first gate and the first gate insulating layer is arranged on a side of the first gate away from the first active layer, a second interlayer dielectric layer is arranged on a side of the first interlayer dielectric layer away from the first gate insulating layer, the first source, the first drain and the first source and drain are arranged on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer, the first source and the first drain are connected to the two sides of the first active layer through a first via and a second via penetrating the second interlayer dielectric layer, the first interlayer dielectric layer and the first gate insulating layer; the spacer layer covers the first source, the first drain, the first source and drain and the second interlayer dielectric layer.

[0018] In some embodiments, a first electrode plate is disposed in the first interlayer dielectric layer, a second electrode plate is disposed in the second interlayer dielectric layer, and the first electrode plate and the second electrode plate are disposed opposite to each other to form a first capacitor; The Fanout wiring is located in the first interlayer dielectric layer and the second interlayer dielectric layer, and the Fanout wiring is staggered with a gate scanning line corresponding to the first gate and a capacitor line corresponding to the first capacitor.

[0019] In some implementations, the first VSS trace and the second VSS trace are located within the spacer layer.

[0020] In some embodiments, at least one of the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer and the spacer layer is provided with a dummy pattern, the dummy pattern is located in the display area, and the dummy pattern and the projection of the GOA circuit on the substrate are staggered.

[0021] In a second aspect, a display device is provided, wherein the display device comprises the display panel described in any embodiment of the present application.

[0022] The display panel and display device provided by the present disclosure place the GOA circuit and part of the Fanout wiring under the pixel circuit, which can significantly reduce the border width of the display panel and help achieve the goal of an extremely narrow border of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, the actual timings of the signals, etc.

[0024] Figure 1 is the backplane circuit layout diagram of the existing display panel; Figure 2 is the cross-sectional schematic diagram of the existing display panel; Figure 3 is the first backplane circuit layout diagram of the display panel provided by the present application; Figure 4 is the first structural cross-sectional schematic diagram of the display panel provided by the present application (showing the inorganic spacer layer, the pixel circuit uses NMOS, and the GOA circuit uses PMOS); Figure 5 is the GOA output trace layout diagram of the first structure of the display panel provided by the present application; Figure 6 is the second backplane circuit layout diagram of the display panel provided by the present application; Figure 7 is the second structural cross-sectional schematic diagram of the display panel provided by the present application (showing the inorganic spacer layer and the organic spacer layer, the pixel circuit uses NMOS, and the GOA circuit uses PMOS); Figure 8 is the third backplane circuit layout diagram of the display panel provided by the present application; Figure 9 is the third structural cross-sectional schematic diagram of the display panel provided by the present application (showing the virtual pattern); Figure 10 is the fourth structural cross-sectional schematic diagram of the display panel provided by the present application (showing the virtual pattern and the first VSS trace); Figure 11 is the fifth structural cross-sectional schematic diagram of the display panel provided by the present application, the pixel circuit uses PMOS, and the GOA circuit uses PMOS; Figure 12 is the sixth structural cross-sectional schematic diagram of the display panel provided by the present application, the pixel circuit uses PMOS+NMOS, and the GOA circuit uses PMOS; Figure 13 is a partial flowchart of the manufacturing method of the display panel provided by the present application; Figure 14 is a partial flowchart of the manufacturing method of the display panel provided by the present application; Figure 15 A partial flow chart of the method for preparing a display panel provided in the present application; Figure 16 A partial flow chart of the method for preparing a display panel provided in the present application; Figure 17 This is a structural diagram of a display device provided in an embodiment of the present application.

[0025] In the above picture: 10 display panel; 101 display area; 102 bending area; 11 substrate substrate; 12 GOA circuit; 121 first active layer; 122 first gate insulating layer; 123 first gate; 124 first electrode plate; 125 first interlayer dielectric layer; 126 second electrode plate; 127 second interlayer dielectric layer; 128 first source; 129 first drain; 130 first source and drain; 131 transfer electrode; 132 first via hole; 133 second via hole; 134 GOA input trace; 135 GOA output trace; 136 transfer hole; 13 Fanout routing; 14 pixel circuit; 141 third electrode plate; 142 first inorganic layer; 143 fourth electrode plate; 144 second gate; 145 second inorganic layer; 146 second active layer; 147 second gate insulating layer; 148 third gate; 149 third interlayer dielectric layer; 150 second source; 151 second drain; 152 second source and drain; 153 planar layer; 154 third via hole; 155 fourth via hole; 15 COP Pad; 16 FOP Pad; 17 ILB routing; 18 Cell detection circuit; 19 spacer layer; 191 inorganic spacer layer; 1910 inorganic via; 192 organic spacer layer; 1920 organic via; 20 First VSS routing; 21 Second VSS routing; 22 dummy pattern; 23 buffer layer; 100 display device. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0027] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc., are intended to indicate that a particular feature, structure, material, or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics described above may be included in any one or more embodiments or examples in any suitable manner.

[0028] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0029] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0030] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0031] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0032] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations caused by, for example, manufacturing.

[0033] Display devices 100 such as mobile phones are developing towards an extremely narrow frame. The narrowing of the frame is limited by the gate drive circuit (GOA, Gate on Array) and the fan-out (Fanout) wiring. Figure 1 and Figure 2 As shown, the backplane circuit layout diagram of the existing display panel 10, in the area above the bending area 102 (Bending) of the display panel 10, the GOA circuit 12 is located on the left and right sides outside the AA (pixel area or display area 101), the GOA circuit 12 inputs the signal through the GOA input line 134 (GOA_line), and the GOA circuit 12 is electrically connected to the pixel circuit 14 in the AA area through the GOA output line 135; the Fanout line 13 is provided on the lower side outside the AA area for transmitting the data (Data) signal provided by the driver chip. In the area below the Bending, the GOA input line 134 and the Fanout line 13 are finally connected to the COP Pad 15 to receive the IC output signal. Both the GOA circuit 12 and the Fanout line 13 will occupy the space in the frame area, which is not conducive to the narrow frame design of the display panel 10, and does not conform to the development trend of the display panel 10 with an ultra-narrow frame or even a frameless frame.

[0034] To solve the above technical problems, Figures 3 to 7 As shown, in a first aspect, a display panel 10 is provided, comprising: a display area 101 and a bending area 102 located at one side of the display area 101, wherein a driving chip is arranged at a side of the bending area 102 away from the display area 101; The display panel 10 includes a GOA circuit 12 and a Fanout line 13 disposed on a base substrate 11, wherein the GOA circuit 12 is located in the display area 101, and a signal input end of the GOA circuit 12 is electrically connected to the driving chip via a GOA input line 134 passing through the bending area 102; At least a portion of the Fanout wiring 13 overlaps with the orthographic projection of the display area 101, the Fanout wiring 13 is electrically connected to the driver chip, and the GOA circuit 12 located in the display area 101 and the Fanout wiring 13 are staggered; A pixel circuit 14 is disposed on a side of the GOA circuit 12 away from the base substrate 11 . The GOA circuit 12 is electrically connected to a signal input terminal of the pixel circuit 14 via a GOA output wiring 135 . The Fanout wiring 13 is electrically connected to the pixel circuit 14 .

[0035] Specifically, Figure 3 and Figure 6As shown, the display panel 10 has a display area 101 (AA area), the lower side of the display area 101 has a bending area 102 (Bending), and a COP Pad 15 is provided on the side of the bending area 102 away from the display area 101. COP (Chip On Panel) means that the driver chip (IC) is directly packaged in the non-display area of ​​the display panel 10, and the COP Pad 15 is a pad used to bind with the driver chip.

[0036] like Figure 4 , Figure 5 and Figure 7 As shown, the display panel 10 includes a GOA circuit 12 and a Fanout wiring 13 disposed on a base substrate 11, and a pixel circuit 14 is disposed on a side of the GOA circuit 12 away from the base substrate 11. The GOA circuit 12 is located in the display area 101, and the signal input end of the GOA circuit 12 is connected to a GOA input wiring 134 (GOA_line), and the GOA input wiring 134 is welded to the COP Pad 15 via the bending area 102 to achieve electrical connection with the driver chip, and the signal output end of the GOA circuit 12 is electrically connected to the signal input end of the pixel circuit 14 located in the display area 101 through the GOA output wiring 135 in the frame area, and the signal output of the IC is transmitted to the GOA circuit 12, and then the gate drive signal is provided to the pixel circuit 14 through the GOA circuit 12.

[0037] like Figure 6 As shown, the orthographic projection of a portion of the Fanout wiring 13 on the substrate 11 is located in the display area 101 and is staggered with the GOA circuit 12. This portion of the Fanout wiring 13 is electrically connected to the pixel circuit 14; a portion of the Fanout wiring 13 is welded to the COP Pad 15 via the bending area 102 to achieve electrical connection with the driver chip, and the Fanout wiring 13 is used to transmit the data signal provided by the driver chip to the pixel circuit 14. The pixel circuit 14 controls the light-emitting state of the pixel under the action of the gate drive signal, the data signal, etc., to achieve image display and dynamic update.

[0038] In this example, the GOA circuit 12 is placed below the pixel circuit 14 so that the GOA circuit 12 is located in the display area 101, which can significantly reduce the width of the left and right borders of the display panel 10; and a portion of the Fanout wiring 13 is placed below the pixel circuit 14 so that the portion of the Fanout wiring 13 is located in the display area 101, which can reduce the width of the lower border of the display panel 10, thereby reducing the overall border width of the display panel 10, which helps to achieve the goal of an extremely narrow border of the display panel 10.

[0039] In some embodiments, Figure 6As shown, between the display area 101 and the bending area 102 is the first border area. At least part of the Fanout trace 13 extends from the end face of the display area 101 far from the bending area 102 to the end face close to the bending area 102, and sequentially passes through the first border area and the bending area 102 and is electrically connected to the driving chip.

[0040] Specifically, the display area 101 has a first end face and a second end face oppositely arranged in the first direction. The first end face is arranged on the side close to the bending area 102, and the second end face is arranged on the side far from the bending area 102. Part of the Fanout trace 13 extends from the second end face to the first end face and covers the center line area of the display panel 10. This part of the Fanout trace 13 is welded to the COP Pad 15 through the first border area and the bending area 102. In this example, most of the Fanout traces 13 are located within the display area 101 in the orthographic projection on the substrate 11, which can greatly reduce the occupied space of the Fanout traces 13 on the lower border of the display panel 10 and achieve an extremely narrow border of the display panel 10.

[0041] In some embodiments, as Figure 6 shown, the display area 101 includes a first fan-out area and a second fan-out area sequentially arranged on the side far from the bending area 102. The Fanout traces 13 are arranged in both the first fan-out area and the second fan-out area. The projected area of the first fan-out area on the substrate 11 is larger than the projected area of the second fan-out area on the substrate 11.

[0042] Specifically, the first fan-out area is arranged near the first end face of the display area 101, and the second fan-out area is arranged near the second end face. The Fanout traces 13 are arranged in both the first fan-out area and the second fan-out area. The projected area of the first fan-out area on the substrate 11 is larger than the projected area of the second fan-out area on the substrate 11. In this example, by arranging the Fanout traces 13 in the first fan-out area and the second fan-out area, the internal space of the display area 101 of the display panel 10 can be fully utilized, the occupied space of the Fanout traces 13 on the lower border of the display panel 10 can be reduced, and an extremely narrow border of the display panel 10 can be achieved.

[0043] In some embodiments, as Figure 6 shown, the width of the first fan-out area remains unchanged from the side of the display area 101 far from the bending area 102 to the side close to the bending area 102; the width of the second fan-out area gradually decreases from the side of the display area 101 far from the bending area 102 to the side close to the bending area 102, and the width of the first fan-out area does not exceed the width of the second fan-out area.

[0044] Specifically, the projection of the first fan-out area on the base substrate 11 is a square, and the projection of the second fan-out area on the base substrate 11 is a trapezoid that is wide at the top and narrow at the bottom, so as to adapt to the external structure of the display panel 10 .

[0045] In some embodiments, Figure 6 As shown, a Cell detection circuit 18 is provided between the first fan-out area and the second fan-out area.

[0046] In related technologies, such as Figure 1 As shown, a cell detection circuit 18 is disposed inside the fanout wiring 13 between the bending area 102 and the COP Pad 15 . The cell detection circuit 18 occupies the lower frame space of the display panel 10 , which is not conducive to the narrow frame design of the display panel 10 .

[0047] In the embodiment of the present application, the Cell detection circuit 18 is disposed in the display area 101 of the display panel 10. The Cell detection circuit 18 is located between the first fan-out area and the second fan-out area, thereby reducing the space occupied by the Cell detection circuit 18 in the lower frame of the display panel 10, which is conducive to achieving an extremely narrow frame of the display panel 10.

[0048] The cell detection circuit 18 is used for lighting (ET) detection. The lighting test is a key link in the production process of the display panel 10. It is mainly used to test whether the brightness, color and other indicators of the display panel 10 meet the requirements. During the test, the system will simulate various usage scenarios, including different brightness, contrast, color settings, etc., to ensure that the display panel 10 can work normally under various conditions.

[0049] In some embodiments, Figure 6 As shown, the GOA circuit 12 includes a plurality of cascaded GOA units, the GOA units are distributed at the edge positions on both sides of the display area 101 adjacent to the bending area 102, and the GOA units are arranged on both sides of the first fan-out area, and the GOA units are arranged to avoid the Fanout routing 13 in the first fan-out area and the second fan-out area.

[0050] Specifically, the GOA circuit 12 includes a plurality of cascaded GOA units, and the plurality of GOA units are distributed on both sides of the first fan-out area along the second direction. The second direction is arranged to intersect with the first direction, preferably to be arranged vertically. The plurality of GOA units located on the same side of the first fan-out area are distributed at the edge of the display area 101 along the first direction. The GOA units are staggered with the Fanout wiring 13 to avoid interference with the Fanout wiring 13.

[0051] In some embodiments, Figure 6As shown in the figure, multiple GOA units arranged at the same-side edge position within the display area 101 form at least two columns of GOA modules. The multiple columns of GOA modules arranged on the same side of the display area 101 are arranged in sequence from the inside to the outside. The multiple GOA units included in each column of GOA modules are arranged from the side of the display area 101 far from the bending area 102 to the side close to the bending area 102.

[0052] Specifically, multiple GOA units on the same side of the first fan-out area are arranged in a first direction to form at least two columns of GOA modules. The number of GOA units included in each column of GOA modules may be equal or unequal. The end face of each column of GOA modules on the side far from the bending area 102 is spaced from the second end face of the display area 101 to reserve layout space for the Fanout trace 13 in the second fan-out area.

[0053] In some embodiments, as Figure 6 shown in the figure, multiple GOA units arranged at the same-side edge position within the display area 101 form two columns of GOA modules, namely the first column of GOA modules and the second column of GOA modules. The first column of GOA modules is located outside the second column of GOA modules. Both the first column of GOA modules and the second column of GOA modules are spaced from the end face of the display area 101 on the side far from the bending area 102 to form a trace layout space, and the second fan-out area is located within the trace layout space.

[0054] Specifically, the first column of GOA modules and the second column of GOA modules are on the same side of the first fan-out area, and the first column of GOA modules is arranged relatively farther from the center line of the display panel 10 than the second column of GOA modules. The end faces of the first column of GOA modules and the second column of GOA modules on the side far from the bending area 102 are flush with each other and are spaced from the second end face of the display area 101 to form a trace layout space. The second fan-out area is located within this trace layout space, so that the GOA units included in the first column of GOA modules and the second column of GOA modules are staggered from the Fanout trace 13. Among them, the first column of GOA modules extends along the first direction to the first end face of the display area 101 and is welded to the COP Pad 15 through the GOA input trace 134. The length of the second column of GOA modules along the first direction may be equal to the width of the trace layout space along the first direction.

[0055] In some embodiments, as Figure 8 shown in the figure, a flexible circuit board is further provided on the side of the driving chip far from the bending area 102; The display panel 10 further includes a second border area, a third border area, and a fourth border area that are sequentially arranged outside the display area 101. The first border area and the third border area are oppositely arranged in a first direction, the second border area and the fourth border area are oppositely arranged in a second direction, and the first direction intersects with the second direction; A first VSS trace 20 is formed by surrounding within the first border area, the second border area, the third border area, and the fourth border area, and both ends of the first VSS trace 20 in the first border area are electrically connected to the flexible circuit board respectively; The first VSS trace 20 in the first border area and the first VSS trace 20 in the third border area are electrically connected through a second VSS trace 21 covering the display area 101.

[0056] Specifically, on the side of the COP Pad 15 away from the bending area 102, there is a pad (FOP Pad 16) for connecting the flexible circuit board. FOP (Flexible Printed Circuit on Panel) means the connection between the flexible circuit board and the display panel 10.

[0057] In the related art, as Figure 1 shown, the second border area, the third border area, and the fourth border area surround to form the first VSS trace 20. The first VSS trace 20 is arranged outside the GOA circuit 12, and both ends of the first VSS trace 20 close to the bending area 102 are finally welded to the FOP Pad 16 to achieve electrical connection with the flexible circuit board.

[0058] In the embodiments of the present application, as Figure 8As shown, the periphery of the display area 101 has a border area, which includes a first border area (partial lower border), a second border area (left border), a third border area (upper border), and a fourth border area (right border) arranged in sequence. A first VSS trace 20 is formed by surrounding within the four border areas, and both ends of the first VSS trace 20 near the bending area 102 are finally welded to the FOP Pad 16 to achieve electrical connection with the flexible circuit board. The first VSS trace 20 in the first border area and the first VSS trace 20 in the third border area are electrically connected through a second VSS trace 21 extending in the first direction. The projection of the second VSS trace 21 on the substrate 11 and the projection of the Fanout trace 13 on the substrate 11 are at least partially overlapped, and the second VSS trace 21 and the Fanout trace 13 are formed by different inorganic metal layers. In this example, the first VSS trace 20 provided in the first border area and the second VSS trace 21 provided in the display area 101 can greatly reduce the voltage drop (IR Drop), and can also reduce the width of the first VSS trace 20 in the peripheral border area (the second border area and the fourth border area) of the display area 101 to achieve a narrower border.

[0059] It should be noted that, as Figure 3 , Figure 6 and Figure 8 shown, an ILB (Inner Lead Bonding) trace is provided between the FOP Pad 16 and the COP Pad 15. The IC input signal transmitted by the flexible circuit board first reaches the FOP Pad 16, and then is transmitted to the COP Pad 15 through the ILB trace 17, and then transmitted to the driving chip bonded to the COP Pad 15. To ensure the stability and reliability of signal transmission, the ILB trace 17 usually adopts a multi-layer metal wiring structure, and different layers of traces are separated by an insulating layer to reduce interference between signals.

[0060] In some embodiments, the first VSS trace 20 and the second VSS trace 21 are provided on the same layer, and the first VSS trace 20 and the Fanout trace 13 are not provided on the same layer.

[0061] Specifically, the first VSS trace 20 and the second VSS trace 21 are formed of the same material and provided on the same layer. The first VSS trace 20 and the second VSS trace 21 are located between the GOA circuit 12 and the pixel circuit 14. The first VSS trace 20 and the Fanout trace 13 are not provided on the same layer to avoid interference between them.

[0062] It should be noted that a pixel definition layer is provided on the side of the pixel circuit 14 away from the GOA circuit 12. The pixel definition layer is provided with a plurality of opening areas at intervals, and pixels are provided in each opening area. The pixels include organic light-emitting devices, and the organic light-emitting devices include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. Among them, the first VSS trace 20 is connected to the cathode of the pixel to provide a negative power supply signal, forming a current loop, enabling the pixel to work normally and emit light of different brightness and colors to achieve image display.

[0063] In some embodiments, such as Figure 4 , Figure 5 and Figure 7 , the GOA unit includes a first thin-film transistor, and the pixel circuit 14 includes a second thin-film transistor. The second thin-film transistor is stacked on the side of the first thin-film transistor away from the substrate 11; The output signal trace of the first thin-film transistor extends towards the second border area or the fourth border area, and is electrically connected to the signal input end of the second thin-film transistor through an inorganic via 1910 in the corresponding border area.

[0064] Specifically, each GOA unit corresponds to a row of pixel circuits 14 and is connected to the corresponding row of pixel circuits 14 through a scan control line. Among them, the GOA unit includes a first thin-film transistor, and the pixel circuit 14 includes a second thin-film transistor. The signal output trace of the first thin-film transistor on the left side of the display panel 10, that is, the GOA output trace 135, is electrically connected to the corresponding second thin-film transistor through the inorganic via 1910 penetrating the second border area to provide a gate driving signal to the second thin-film transistor, and the first thin-film transistor on the right side of the display panel 10 is electrically connected to the corresponding second thin-film transistor through the inorganic via 1910 penetrating the fourth border area.

[0065] The first thin-film transistor and the second thin-film transistor can be selected from any one of low-temperature poly-silicon (LTPS) TFTs, or oxide TFTs (Oixde TFTs), or low-temperature poly-oxide (LTPO) TFTs.

[0066] In some embodiments, a spacer layer 19 is provided between the first thin-film transistor and the second thin-film transistor, and the spacer layer 19 is an inorganic spacer layer 191 or / and an organic spacer layer 192.

[0067] Specifically, a spacer layer 19 is provided between the first thin-film transistor and the second thin-film transistor. Exemplarily, such as Figure 4As shown, the spacer layer 19 can be an inorganic spacer layer 191, and the inorganic vias 1910 penetrate through the inorganic spacer layer 191; for another example Figure 7 As shown, the spacer layer 19 includes an organic spacer layer 192 and an inorganic spacer layer 191. The organic spacer layer 192 is located between the inorganic spacer layer 191 and the first thin film transistor. The inorganic vias 1910 penetrate through the inorganic spacer layer 191. Organic vias 1920 are formed in the organic spacer layer 192. The inorganic vias 1910 and the organic vias 1920 are communicated with each other, so that the signal output end of the first thin film transistor is electrically connected to the signal input end of the second thin film transistor through the corresponding inorganic vias 1910 and organic vias 1920.

[0068] In some embodiments, such as Figure 4 and Figure 7 As shown, the spacer layer 19 includes a first source electrode 128 and a first drain electrode 129 for forming the first thin film transistor in the display area 101, and a first source-drain electrode 130 located in the second border area and the fourth border area; A planarization layer 153 is provided on a side of the spacer layer 19 away from the substrate 11. The planarization layer 153 includes a second source electrode 150 and a second drain electrode 151 for forming the second thin film transistor in the display area 101, and a second source-drain electrode 152 located in the second border area and the fourth border area; The first source-drain electrode 130 and the second source-drain electrode 152 in the same border area are electrically connected through the inorganic vias 1910 provided in the corresponding border area, and the second source-drain electrode 152 is electrically connected to the gate of the second thin film transistor through the inorganic vias 1910.

[0069] Specifically, as Figure 4 As shown, a spacer layer 19 is provided on the substrate 11. A first source electrode 128, a first drain electrode 129 and a first source-drain electrode 130 are provided in the spacer layer 19. The three are made of the same metal material and etched by the same process, reducing the setting of masks; among them, the first source electrode 128 and the first drain electrode 129 are located in the display area 101 and are used to form the first thin film transistor; the first source-drain electrode 130 is located in the second border area and the fourth border area.

[0070] A planarization layer 153 is provided on a side of the spacer layer 19 away from the substrate. The planarization layer 153 has a second source electrode 150, a second drain electrode 151 and a second source-drain electrode 152. The three are made of the same metal material and etched by the same process, reducing the setting of masks; among them, the second source electrode 150 and the second drain electrode 151 are located in the display area 101 and are used to form the second thin film transistor, and the second source-drain electrode 152 is located in the second border area and the fourth border area.

[0071] It should be noted that the signal output terminal of the first thin film transistor is electrically connected to the first source-drain electrode 130. The first source-drain electrode 130 is electrically connected to the second source-drain electrode 152 through an inorganic via 1910. The second source-drain electrode 152 is electrically connected to the gate electrode of the second thin film transistor through an inorganic via 1910. The gate electrode of the second thin film transistor can be the subsequent second gate electrode or third gate electrode.

[0072] In some embodiments, as Figure 4 and Figure 7 shown, the first thin film transistor further includes a first active layer 121 disposed on the substrate 11. A first gate insulating layer 122 covering the first active layer 121 is disposed on a side of the first active layer 121 away from the substrate 11. A first gate electrode 123 is disposed on a side of the first gate insulating layer 122 away from the first active layer 121. A first interlayer dielectric layer 125 covering the first gate electrode 123 and the first gate insulating layer 122 is disposed on a side of the first gate electrode 123 away from the first active layer 121. A second interlayer dielectric layer 127 is disposed on a side of the first interlayer dielectric layer 125 away from the first gate insulating layer 122. The first source electrode 128, the first drain electrode 129, and the first source-drain electrode 130 are disposed on a side of the second interlayer dielectric layer 127 away from the first interlayer dielectric layer 125. The first source electrode 128 and the first drain electrode 129 are connected to two sides of the first active layer 121 through a first via 132 and a second via 133 penetrating through the second interlayer dielectric layer 127, the first interlayer dielectric layer 125, and the first gate insulating layer 122. The spacer layer 19 covers the first source electrode 128, the first drain electrode 129, the first source-drain electrode 130, and the second interlayer dielectric layer 127.

[0073] Specifically, the first gate electrode 123 is located between the first source electrode 128 and the first drain electrode 129. The first source electrode 128 is connected to the first active layer 121 through a first via 132 penetrating through the second interlayer dielectric layer 127, the first interlayer dielectric layer 125, and the first gate insulating layer 122. The first drain electrode 129 is connected to the first active layer 121 through a second via 133 penetrating through the second interlayer dielectric layer 127, the first interlayer dielectric layer 125, and the first gate insulating layer 122. The first active layer 121, the first gate electrode 123, the first source electrode 128, and the first drain electrode 129 form the first thin film transistor. The signal output terminal of the first thin film transistor can be the signal output by the first gate electrode 123, the first source electrode 128, or the first drain electrode 129.

[0074] In some embodiments, as Figure 4 and Figure 7As shown, a first electrode plate 124 is disposed in the first interlayer dielectric layer 125, a second electrode plate 126 is disposed in the second interlayer dielectric layer 127, and the first electrode plate 124 and the second electrode plate 126 are disposed opposite to each other to form a first capacitor; The Fanout wiring 13 is located in the first interlayer dielectric layer 125 and the second interlayer dielectric layer 127, and the Fanout wiring 13 is staggered with the gate scanning line corresponding to the first gate 123 and the capacitor line corresponding to the first capacitor, wherein the first interlayer dielectric layer 125 and the second interlayer dielectric layer 127 can be inorganic layers.

[0075] Specifically, the GOA circuit 12 also includes a first capacitor, and the first electrode plate 124 and the second electrode plate 126 are arranged opposite to each other to form the first capacitor. The Fanout wiring 13 is formed by metal wiring arranged alternately in horizontal and vertical directions in the first interlayer dielectric layer 125 and the second interlayer dielectric layer 127, and the metal wiring is staggered with the gate scanning line corresponding to the first gate 123 and the capacitance line corresponding to the first capacitor.

[0076] It should be noted that a pixel circuit 14 is provided on one side of the spacer layer 19 away from the second interlayer dielectric layer 127, and the pixel circuit 14 includes a plurality of transistors, capacitors, and transistor driving components and other electronic components. For example, the pixel driving circuit may include three transistors and one capacitor, forming a 3T1C (i.e., one driving transistor, two switching transistors, and one capacitor). It may also include more than three transistors and at least one capacitor, such as a 4T1C (i.e., one driving transistor, three switching transistors, and one capacitor), a 5T1C (i.e., one driving transistor, four switching transistors, and one capacitor), or a 7T1C (i.e., one driving transistor, six switching transistors, and one capacitor).

[0077] For example, Figure 4 and Figure 7As shown, the pixel circuit 14 includes a second thin film transistor and a second capacitor. On the side of the spacer layer 19 away from the second interlayer dielectric layer 127, a third electrode plate 141 is provided. On the side of the spacer layer 19 away from the second interlayer dielectric layer 127, a first inorganic layer 142 covering the third electrode plate 141 is provided. On the side of the first inorganic layer 142 away from the spacer layer 19, a fourth electrode plate 143 and a second gate 144 are provided. The fourth electrode plate 143 and the third electrode plate 141 are oppositely arranged to form a second capacitor. On the side of the first inorganic layer 142 away from the spacer layer 19, a second inorganic layer 145 covering the fourth electrode plate 143 and the second gate 144 is provided. On the side of the second inorganic layer 145 away from the first inorganic layer 142, a second active layer 146 is provided. On the side of the second inorganic layer 145 away from the first inorganic layer 142, a second gate insulating layer 147 covering the second active layer 146 is provided. On the side of the second gate insulating layer 147 away from the second active layer 146, a third gate 148 is provided. On the side of the second gate insulating layer 147 away from the second active layer 146, a third interlayer dielectric layer 149 covering the third gate 148 is provided. On the side of the third interlayer dielectric layer 149 away from the third gate 148, a second source 150, a second drain 151, and a second source-drain 152 are provided. The second source-drain 152 is located in the second border area and the fourth border area, and the second source 150 and the second drain 151 are located in the display area 101. The second source 150 and the second drain 151 are respectively connected to both sides of the second active layer 146 through a third via 154 and a fourth via 155 penetrating through the third interlayer dielectric layer 149 and the second gate insulating layer 147. On the side of the third interlayer dielectric layer 149 away from the third gate 148, a planarization layer 153 covering the second source 150, the second drain 151, and the second source-drain 152 is provided. The second gate 144 and the third gate 148 are located between the second source 150 and the second drain 151. The second gate 144, the second active layer 146, the third gate 148, and the second source 150 and the second drain 151 constitute a second thin film transistor. Among them, the second gate insulating layer 147 and the third interlayer dielectric layer 149 can be inorganic layers.

[0078] As Figure 4 shown, when the spacer layer 19 is an inorganic spacer layer 191, an inorganic via 1910 penetrates through the third interlayer dielectric layer 149, the second gate insulating layer 147, the second inorganic layer 145, the first inorganic layer 142, and the inorganic spacer layer 191 along the stacking direction of the first thin film transistor and the second thin film transistor, so that the first source-drain 130 and the second source-drain 152 are electrically connected through the inorganic via 1910, and the second source-drain 152 is electrically connected to the second gate 144 and the third gate 148 through the inorganic via 1910.

[0079] As Figure 7As shown, when the spacer layer 19 includes an inorganic spacer layer 191 and an organic spacer layer 192, the second interlayer dielectric layer 127, the organic spacer layer 192, the inorganic spacer layer 191, and the first inorganic layer 142 are sequentially stacked. The inorganic via 1910 penetrates through the third interlayer dielectric layer 149, the second gate insulating layer 147, the second inorganic layer 145, the first inorganic layer 142, and the inorganic spacer layer 191 along the stacking direction of the first thin film transistor and the second thin film transistor. An organic via 1920 communicating with the inorganic via 1910 is formed in the organic spacer layer 192, so that the first source-drain electrode 130 and the second source-drain electrode 152 are electrically connected through the inorganic via 1910 and the organic via 1920.

[0080] It can be understood that the inorganic via 1910 and the organic via 1920 can be formed in two steps using the same mask, that is, first use the mask to form the inorganic via 1910, and then change the process parameters and use the same mask to form the organic via 1920; alternatively, use two masks, one mask is first used to form the organic via 1920, and the other mask forms the inorganic via 1910.

[0081] It should be noted that, as Figure 4 and Figure 7 shown, a transfer electrode 131 is further provided at a position of the second border area or / and the fourth border area opposite to the first source-drain electrode 130. The transfer electrode 131 is electrically connected to the first source-drain electrode 130, and the transfer electrode 131 is located on the first interlayer dielectric layer 125 or / and the second interlayer dielectric layer 127, so that the GOA output trace 135 is electrically connected to the first source-drain electrode 130 through the transfer electrode 131.

[0082] It can be understood that, as Figure 4 and Figure 7 shown, a buffer layer 23 and the like are further provided between the substrate 11 and the first active layer 121.

[0083] In some embodiments, as Figure 10 shown, the first VSS trace 20 and the second VSS trace 21 are located in the spacer layer 19.

[0084] Specifically, the first VSS trace 20 and the second VSS trace 21 are located in the spacer layer 19 between the pixel circuit 14 and the GOA circuit 12, such as in the inorganic spacer layer 191 or the organic spacer layer 192.

[0085] In some embodiments, as Figure 9 and Figure 10As shown, at least one of the first gate insulating layer 122, the first interlayer dielectric layer 125, the second interlayer dielectric layer 127, and the spacer layer 19 is provided with a dummy pattern 22. The dummy pattern 22 is located within the display area 101, and the dummy pattern 22 is disposed offset from the projection of the GOA circuit 12 on the substrate 11.

[0086] Specifically, a dummy pattern 22 (Dummy Pattern) is provided within the display area 101 to prevent the pixel circuits 14 above non-GOA circuits from being at the same horizontal plane as the pixel circuits 14 above the GOA circuit 12, so that the pixel circuits 14 arranged in an array within the display area 101 are all at the same horizontal plane. Exemplarily, the first gate insulating layer 122 is provided with a dummy pattern 22 that is the same as or similar to the image of the first active layer 121. Again, for example, the first interlayer dielectric layer 125 is provided with a dummy pattern 22 that is the same as or similar to the first gate 123 and the first electrode plate 124. Again, for example, the second interlayer dielectric layer 127 is provided with a dummy pattern 22 that is the same as or similar to the second electrode plate 126.

[0087] It should be noted that in the display panel 10 provided in the embodiment of the present application, the first thin film transistor employed by the GOA circuit 12 can be a PMOS or an NMOS, and the second thin film transistors included in the pixel circuit 14 can be a PMOS or an NMOS. Exemplarily, each of the second thin film transistors included in the pixel circuit 14 can all be PMOS (as shown in Figure 4 and Figure 7 ), can all be NMOS (as shown in Figure 11 ), or can be PMOS + NMOS (as shown in Figure 12 ). Exemplarily, the display panel 10 of the embodiment of the present application adopts the LTPO+ technology, that is, each of the first thin film transistors included in the GOA circuit 12 is a PMOS, and each of the second thin film transistors included in the pixel circuit 14 is an NMOS. Among them, the first active layer 121 of the first thin film transistor can adopt polycrystalline silicon (Poly) material, and the second active layer 146 of the second thin film transistor can adopt indium gallium zinc oxide (IGZO), etc.

[0088] Exemplarily, as shown in Figures 13 to 16 , a manufacturing method 200 of a display panel 10 includes: A buffer layer 23 formed on the substrate 11; Forming a first active layer 121 on a side of the buffer layer 23 away from the substrate 11; On the side of the buffer layer 23 away from the substrate 11, a first gate insulating layer 122 covering the first active layer 121 and the buffer layer 23 is formed; on the side of the first gate insulating layer 122 away from the first active layer 121, a first gate 123 and a first electrode plate 124 are formed through a patterning process; On the side of the first gate insulating layer 122 away from the first active layer 121, a first interlayer dielectric layer 125 covering the first gate 123 and the first electrode plate 124 is formed. On the side of the first interlayer dielectric layer 125 away from the first gate insulating layer 122, a second electrode plate 126 and a transfer electrode 131 are formed through a patterning process. The first electrode plate 124 and the second electrode plate 126 are arranged opposite to each other to form a capacitor; On the side of the first interlayer dielectric layer 125 away from the first gate insulating layer 122, a second interlayer dielectric layer 127 covering the second electrode plate 126 and the transfer electrode 131 is formed. Through a patterning process, a transfer hole 136 penetrating the second interlayer dielectric layer 127 is formed at a position opposite to the transfer electrode 131; and first vias 132 and second vias 133 penetrating the second interlayer dielectric layer 127, the first interlayer dielectric layer 125, and the first gate insulating layer 122 are formed at positions opposite to both sides of the first active layer 121, as Figure 13 shown; On the side of the second interlayer dielectric layer 127 away from the first interlayer dielectric layer 125, a first source electrode 128, a first drain electrode 129, and a first source-drain electrode 130 are formed through a patterning process. The first source electrode 128 and the first drain electrode 129 are connected to both sides of the first active layer 121 through corresponding first vias 132 and second vias 133. The first source-drain electrode 130 is connected to the transfer electrode 131 through the transfer hole 136; the first active layer 121, the first gate 123, and the first source electrode 128 and the first drain electrode 129 form a first thin-film transistor; On the side of the second interlayer dielectric layer 127 away from the first interlayer dielectric layer 125, an inorganic spacer layer 191 covering the first source electrode 128, the first drain electrode 129, and the first source-drain electrode 130 is formed. On the side of the inorganic spacer layer 191 away from the second interlayer dielectric layer 127, a third electrode plate 141 is formed through a patterning process; On the side of the inorganic spacer layer 191 away from the second interlayer dielectric layer 127, a first inorganic layer 142 covering the third electrode plate 141 is formed. On the side of the first inorganic layer 142 away from the inorganic spacer layer 191, a fourth electrode plate 143 and a second gate 144 are formed through a patterning process. The third electrode plate 141 and the fourth electrode plate 143 are arranged opposite to each other to form a second capacitor, as Figure 14 shown; A second inorganic layer 145 covering the fourth electrode plate 143 and the second gate 144 is formed on a side of the first inorganic layer 142 away from the inorganic spacer layer 191, and a second active layer 146 is formed on a side of the second inorganic layer 145 away from the first inorganic layer 142; A second gate insulating layer 147 covering the second active layer 146 is formed on a side of the second inorganic layer 145 away from the first inorganic layer 142, and a third gate 148 is formed on a side of the second gate insulating layer 147 away from the second inorganic layer 145 through a patterning process; A third interlayer dielectric layer 149 covering the third gate 148 is formed on a side of the second gate insulating layer 147 away from the second inorganic layer 145, and an inorganic via 1910 penetrating through the third interlayer dielectric layer 149, the second gate insulating layer 147, the second inorganic layer 145, the first inorganic layer 142, and the inorganic spacer layer 191 is formed through a patterning process, as Figure 15 shown; A third via 154 and a fourth via 155 penetrating through the third interlayer dielectric layer 149 and the second gate insulating layer 147 are formed through a patterning process; A second source electrode 150, a second drain electrode 151, and a second source-drain electrode 152 are formed on a side of the third interlayer dielectric layer 149 away from the second gate insulating layer 147 through a patterning process. The second source electrode 150 and the second drain electrode 151 are connected to both sides of the corresponding second active layer 146 through the third via 154 and the fourth via 155, and the second source-drain electrode 152 is connected to the first source-drain electrode 130 through the inorganic via 1910; the second gate 144, the second active layer 146, the third gate 148, and the second source electrode 150 and the second drain electrode 151 form a second thin film transistor; A planarization layer 153 covering the second source electrode 150, the second drain electrode 151, and the second source-drain electrode 152 is formed on a side of the third interlayer dielectric layer 149 away from the second gate insulating layer 147, as Figure 16 shown.

[0089] In the embodiments of the present application, the patterning process includes conventional technical means such as coating photoresist, mask exposure, development, etching, and stripping photoresist.

[0090] It can be understood that the manufacturing method of the display panel 10 provided in the embodiments of the present application is used to obtain the display panel 10 described in any embodiment of the present application. Its specific technical features and technical effects are the same as those of the display panel 10, and will not be elaborated in the embodiments of the present application.

[0091] In a second aspect, as Figure 17 shown, a display device 100 is provided, and the display device 100 includes the display panel 10 described in any embodiment of the present application.

[0092] The display device 100 can be a lighting device. In this case, the display device 100 serves as a light source to achieve the lighting function. For example, the display device 100 can be a backlight module in a liquid crystal display device 100, a lamp for internal or external lighting, or various signal lights, etc.

[0093] In some embodiments, the display device 100 can be a display substrate for achieving the function of displaying an image (i.e., a picture). The display device 100 can include a display or a product containing a display. Among them, the display can be a Flat Panel Display (FPD), a microdisplay, etc. If divided according to whether the user can see the scene on the back of the display, the display can be a transparent display or an opaque display. If divided according to whether the display can be bent or curled, the display can be a flexible display or a normal display (which can be called a rigid display).

[0094] Exemplarily, products containing a display can include: computer monitors, televisions, billboards, laser printers with a display function, telephones, mobile phones, Personal Digital Assistants (PDAs), laptop computers, digital cameras, portable video recorders, viewfinders, vehicles, large-area walls, theater screens, or stadium signs, etc.

[0095] The technical features and beneficial effects of the above display device 100 are the same as those of the display panel 10 provided in the above embodiments of the present disclosure, and will not be elaborated here.

[0096] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, technical solutions formed by mutually replacing the above features with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a bending area located at one side of the display area, and a driving chip is arranged on a side of the bending area away from the display area; The display panel includes a GOA circuit and a Fanout wiring arranged on a base substrate, the GOA circuit is located in the display area, and a signal input end of the GOA circuit is electrically connected to the driving chip through the GOA input wiring passing through the bending area; At least a portion of the Fanout wiring is overlapped with the orthographic projection of the display area, the Fanout wiring is electrically connected to the driver chip, and the GOA circuit located in the display area and the Fanout wiring are staggered; A pixel circuit is arranged on a side of the GOA circuit away from the base substrate. The GOA circuit is electrically connected to a signal input terminal of the pixel circuit via a GOA output wiring, and the Fanout wiring is electrically connected to the pixel circuit.

2. The display panel according to claim 1, characterized in that: A first border area is between the display area and the bending area, and at least a portion of the Fanout wiring extends from an end surface of the display area away from the bending area to an end surface of the display area close to the bending area, and passes through the first border area and the bending area in sequence and is electrically connected to the driver chip.

3. The display panel according to claim 2, characterized in that: The display area includes a first fan-out area and a second fan-out area which are sequentially arranged away from the bending area. The Fanout wiring is arranged in both the first fan-out area and the second fan-out area. The projection area of ​​the first fan-out area on the substrate is larger than the projection area of ​​the second fan-out area on the substrate.

4. The display panel according to claim 3, characterized in that: The width of the first fan-out area from the side of the display area away from the bending area to the side close to the bending area remains unchanged; The width of the second fan-out area decreases gradually from a side of the display area away from the bending area to a side close to the bending area, and the width of the first fan-out area does not exceed the width of the second fan-out area.

5. The display panel according to claim 3, characterized in that: A Cell detection circuit is arranged between the first fan-out area and the second fan-out area.

6. The display panel according to claim 3, characterized in that: The GOA circuit includes a plurality of cascaded GOA units, the GOA units are distributed at the edge positions on both sides of the display area adjacent to the bending area, and the GOA units are arranged on both sides of the first fan-out area, and the GOA units avoid the Fanout routing settings in the first fan-out area and the second fan-out area.

7. The display panel according to claim 6, characterized in that: A plurality of GOA units disposed at the same side edge position in the display area form at least two columns of GOA modules. The plurality of GOA modules disposed at the same side of the display area are disposed sequentially from the inside to the outside, and the plurality of GOA units included in each column of the GOA modules are arranged from a side of the display area away from the bending zone to a side close to the bending zone.

8. The display panel according to claim 7, characterized in that: Multiple GOA units arranged at the same side edge position in the display area form two columns of GOA modules, namely a first column of GOA modules and a second column of GOA modules. The first column of GOA modules are located outside the second column of GOA modules, and the first column of GOA modules and the second column of GOA modules are both spaced apart from the end surface of the display area away from the bending zone to form a wiring layout space, and the second fan-out area is located in the wiring layout space.

9. The display panel according to any one of claims 2 to 8, characterized in that: A flexible circuit board is also provided on one side of the driving chip away from the bending area; The display panel further comprises a second frame area, a third frame area and a fourth frame area which are sequentially arranged at the periphery of the display area, the first frame area and the third frame area are arranged opposite to each other along a first direction, the second frame area and the fourth frame area are arranged opposite to each other along a second direction, and the first direction intersects with the second direction; A first VSS trace is formed around the first frame area, the second frame area, the third frame area, and the fourth frame area, and the first VSS trace is electrically connected to the flexible circuit board at two ends of the first frame area; The first VSS routing line in the first frame area and the first VSS routing line in the third frame area are electrically connected via a second VSS routing line covering the display area.

10. The display panel according to claim 9, characterized in that: The first VSS routing and the second VSS routing are arranged on the same layer, and the first VSS routing and the Fanout routing are not arranged on the same layer.

11. The display panel according to claim 9, characterized in that: The GOA unit includes a first thin film transistor, the pixel circuit includes a second thin film transistor, and the second thin film transistor is stacked on a side of the first thin film transistor away from the substrate; The output signal wiring of the first thin film transistor extends to the second frame area or the fourth frame area, and is electrically connected to the signal input terminal of the second thin film transistor through an inorganic via in the corresponding frame area.

12. The display panel according to claim 11, characterized in that: A spacer layer is disposed between the first thin film transistor and the second thin film transistor, and the spacer layer is an inorganic spacer layer or / and an organic spacer layer.

13. The display panel according to claim 11, characterized in that: The spacer layer includes a first source electrode and a first drain electrode located in the display area for forming the first thin film transistor, and includes a first source and a drain electrode located in the second frame area and the fourth frame area; A flat layer is provided on one side of the spacer layer away from the base substrate, wherein the flat layer includes a second source and a second drain located in the display area for forming the second thin film transistor, and includes a second source and a drain located in the second frame area and the fourth frame area; The first source and drain and the second source and drain located in the same frame area are electrically connected through inorganic vias arranged in the corresponding frame area, and the second source and drain are electrically connected to the gate of the second thin film transistor through the inorganic vias.

14. The display panel according to claim 13, characterized in that: The first thin film transistor further comprises a first active layer disposed on the base substrate, a first gate insulating layer covering the first active layer is disposed on a side of the first active layer away from the base substrate, a first gate is disposed on a side of the first gate insulating layer away from the first active layer, a first interlayer dielectric layer covering the first gate and the first gate insulating layer is disposed on a side of the first gate away from the first active layer, a second interlayer dielectric layer is disposed on a side of the first interlayer dielectric layer away from the first gate insulating layer, the first source, the first drain and the first source-drain are disposed on a side of the second interlayer dielectric layer away from the first interlayer dielectric layer, and the first source and the first drain are connected to both sides of the first active layer through a first via hole and a second via hole penetrating the second interlayer dielectric layer, the first interlayer dielectric layer and the first gate insulating layer; The spacer layer covers the first source, the first drain, the first source and drain, and the second interlayer dielectric layer.

15. The display panel according to claim 14, characterized in that: A first electrode plate is disposed in the first interlayer dielectric layer, a second electrode plate is disposed in the second interlayer dielectric layer, and the first electrode plate and the second electrode plate are disposed opposite to each other to form a first capacitor; The Fanout wiring is located in the first interlayer dielectric layer and the second interlayer dielectric layer, and the Fanout wiring is staggered with a gate scanning line corresponding to the first gate and a capacitor line corresponding to the first capacitor.

16. The display panel according to claim 14, characterized in that: The first VSS routing line and the second VSS routing line are located in the spacer layer.

17. The display panel according to claim 14, characterized in that: At least one of the first gate insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer and the spacer layer is provided with a dummy pattern, the dummy pattern is located in the display area, and the dummy pattern and the projection of the GOA circuit on the base substrate are staggered.

18. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1-17.

Images