Intelligent cabin suitable for high-efficiency serial deserialization

Abstract

The invention provides an intelligent cabin suitable for high-efficiency serial deserialization and a vehicle, the intelligent cabin comprises a central control display screen and a main controller, the main controller is used for obtaining screen display data, analyzing the screen display data and forwarding the analyzed screen display data to the central control display screen and a system on chip, and the central control display screen and the system on chip are used for displaying the analyzed screen display data. The system on chip is a high-speed serial transmission system based on an FPGA (Field Programmable Gate Array); the high-speed serial transmission system based on the FPGA comprises data sending processing and data receiving processing. The data transmission processing flow comprises the following steps of: inputting parallel data, converting the data through a 64B / 66B coding module, scrambling the data through a scrambling module, and transmitting the data through parallel / serial conversion; and the data receiving and processing flow comprises the following steps of: performing serial / parallel conversion on the self-loop data, sending the data to a descrambling module for descrambling, and decoding the descrambled data through a 64B / 66B decoding module. According to the invention, the serial deserialization process is optimized, so that the data transmission speed is increased and the delay is reduced.

Description

Technical Field

[0001] This application relates to the field of information technology, and particularly to an intelligent cockpit suitable for high-efficiency serial deserialization. Background Art

[0002] The intelligent cockpit is an in-vehicle application scenario under the background of intelligence and Internet of Everything. By integrating driving information and in-vehicle applications and utilizing the powerful information data processing ability of the in-vehicle system, it provides a highly efficient and technological driving experience for the driver. The intelligent cockpit consists of three major parts: hardware (cockpit chips, HUD, electronic rearview mirrors, etc.), software, and interaction (voice recognition, face recognition, touch recognition, biometric recognition).

[0003] The human-machine interaction system (HMI) includes cockpit interior and cockpit electronics. Cockpit interior: It is developing towards intelligence, and users can control all its functions, including seats, lights, air conditioners, passive vehicle safety, etc.; Cockpit electronics: The electronic systems used by users in the vehicle, including music, screens, ecological software, etc.; The technical architecture of the intelligent cockpit mainly has five layers: hardware layer, system software layer, functional software layer, service layer, and support layer.

[0004] Currently, the interface between the autonomous driving domain controller and the intelligent cockpit domain controller widely uses a serializer / deserializer (abbreviated as SERDES) interface. The serial deserialization efficiency of the existing SERDES interface is relatively low, and how to solve this problem is a difficulty to be overcome in this field.

[0005] A serial deserializer is a hardware device that can convert the bytes in a continuous data stream into single bytes and then parse out the information in a specific order. It has a wide range of applications and plays an important role in consumer electronics products, communication systems, industrial control systems, etc.

[0006] The basic principle of the serial deserializer is to use a set of circuits to store the continuously transmitted byte data in the form of discrete bytes inside the serial deserializer. It processes the input byte data to complete the deserialization or byte splitting operation, and can change the speed of the input byte stream to change the signal, and then parse it in a specific order.

[0007] The circuit of the serial deserializer includes a transceiver, a filter, and the circuit of the deserializer. The transceiver is used to receive the byte data transmitted externally, the filter is used to remove the interference during the external data transmission process, and the deserializer is the core circuit, which is used to store the continuously transmitted byte data into the internal buffer.

[0008] The internal buffer of the deserialiser stores 8-bit bytes. By comparing two consecutive bytes, the deserialiser calculates the difference between them to determine the input byte order and byte content. When the deserialiser detects that the number of input bytes is greater than 8 bits, it parses and rearranges the bytes exceeding 8 bits and converts the parsed bytes into a format that is easy for users to understand.

[0009] The serial deserialiser is characterised by high efficiency, reliability and large capacity. It can parse the byte stream according to custom rules and reverse the order of the bytes in the data stream to achieve reliable transmission. In addition, the serial deserialiser can also be used for verification, checking and data synchronisation operations to ensure correct data transmission.

[0010] The advantage of the serial deserialiser is that it can quickly and accurately analyse the input electrical signals and ensure the correctness of the input data. Therefore, in today's communication systems, serial deserialisers are increasingly widely used and will provide stable and reliable data transmission solutions for various systems.

[0011] With the increasing demand for the throughput of electronic systems, the parallel data transmission mode can no longer meet the transmission requirements of high-bandwidth applications. High-speed serial transmission technology has the advantages of high bandwidth, low latency, good signal integrity and strong scalability, and has become the mainstream technology for data transmission, being widely used in many fields such as communication networks, data storage, personal computers, servers and embedded control.

[0012] The existing serial deserialiser has a low serial transmission speed and working efficiency. Summary of the Invention

[0013] The present invention provides an intelligent cockpit suitable for high-efficiency serial deserialisation to achieve high efficiency in vehicle cockpit function control, media transmission and output.

[0014] The present invention provides an intelligent cockpit suitable for high-efficiency serial deserialization, including: a cockpit domain controller, a central control display screen, and a main controller. The central control display screen is connected to the main controller, and the main controller is connected to a system on a chip. The main controller is used to obtain screen display data, parse the screen display data, and forward the parsed screen display data to the central control display screen and the system on a chip. The central control display screen is used to display target information according to the parsed screen display data, and the target information is used to indicate the current state of the vehicle. The system on a chip is a high-speed serial transmission system based on FPGA. The high-speed serial transmission system based on FPGA includes: data sending processing and data receiving processing. Data sending processing flow: parallel data is input, converted by a 64B / 66B encoding module, then scrambled by a scrambling module, and then sent out after serial / parallel conversion. Data receiving processing flow: loopback data is sent to a descrambling module for descrambling after serial / parallel conversion, and the descrambled data is then decoded by a 64B / 66B decoding module.

[0015] The working method of the high-speed serial transmission system based on FPGA includes: 1) The input signal is buffered into the fifo through a receiving module. In the 64B / 66B encoding module, according to different 64b code formats, if the 8-byte group is a data character, the "01" identifier is added; if one or more bytes are control characters, the "10" identifier is added. 2) The 64-bit signal is added with a synchronization header and converted into a 66b signal. Then, only the 64b data is scrambled in the scrambling module, and after scrambling, it is converted into a single-bit serial signal and output in the serial / parallel conversion module. The data receiving processing is a complete reverse process compared to the data sending. The signal goes through serial / parallel conversion, first the data is descrambled, and then the data type is judged according to the synchronization header of the 66b code. If it is a data block, it is directly output; if it is a control block, the data needs to be decoded by referring to a look-up table and then output.

[0016] The main controller is connected to a conversion component, which includes: a memory and a serializer. The input ends of the memory and the serializer are respectively connected to the central control display screen. The output end of the serializer is connected to the cockpit domain controller. The memory is used to store the display attribute information of the central control display screen. The serializer is used to convert the image signal input by the central control display screen into a serial signal. The cockpit domain chip is used to parse the parallel image signal and transmit the parsed image signal to the central control display screen; obtain the display attribute information from the conversion component and send the image signal to the test conversion component according to the display attribute information; the display attribute information includes the data format supported by the test conversion component; convert the image signal sent by the input device into a serial SERDES signal supported by the cockpit domain controller; convert the serial SERDES signal into a parallel image signal and display the image signal.

[0017] The technical effects obtained by the present invention are as follows: The intelligent cockpit provided adopts a high-speed serial system. The FPGA device used combines the advantages of programmability and high-speed I / O, realizing high-speed and stable digital communication. Based on the FPGA development environment, an IP core for 64B / 66B encoding and decoding is designed and programmed using the VHDL language on the vivado development platform, and the functional simulation verification of the key module is completed, providing an effective design method for the high-speed serial transmission system. The Field Programmable Gate Array (FPGA) has a faster processing speed than the digital signal processor. The FPGA can handle complex high-speed logic. Compared with the dedicated chip, it has a shorter development cycle and higher flexibility. The system design verification based on FPGA has the advantages of high stability, low cost, and fast processing speed. The FPGA device has become an ideal connection platform for realizing serial interface applications. In the FPGA-based development environment, the VHDL language is used to design and implement the IP core for 64B / 66B encoding and decoding functions, and the high-speed serial transmission system is designed through the scrambling, descrambling module and the parallel-serial / serial-parallel conversion module. After experimental simulation verification, the encoding result is consistent with the encoding and decoding truth table. The entire high-speed communication system operates stably. The present invention optimizes the serial deserialization process to improve the data transmission speed and reduce the delay. Description of the Drawings

[0018] Figure 1 It is the system schematic diagram of the high-speed serial transmission system based on FPGA; Figure 2 It is the schematic diagram of the working principle of the high-speed serial transmission system based on FPGA. Embodiment

[0019] An intelligent cockpit refers to a vehicle-mounted product equipped with intelligence and networking capabilities, such as display screens, controllers, etc., which can perform intelligent interactions with people, roads, and the vehicle itself.

[0020] Various status information of the vehicle can be displayed on the interface of the instrument display screen. These status information are directly related to driving, including vehicle speed, engine speed, warning lights, etc. In addition, an entertainment display screen is also provided on the vehicle, which can be used for user interaction, such as providing map navigation for users, realizing functions such as audio and video playback.

[0021] Among them, whether it is the instrument display screen or the entertainment display screen, a processor is required to obtain information from the central network gateway of the entire vehicle and process this information before it can be transmitted to the corresponding display screen for display. In actual life applications, since the information displayed on the instrument display interface is closely related to driving, it is generally regarded as a functional safety part and isolated from the non-functional safety part.

[0022] In the prior art, a dual-SOC system is mainly adopted. One SOC system realizes the display of instrument information, and the other SOC system realizes the functions of the in-vehicle infotainment (IVI) system, thereby realizing the isolation of the functional safety part and the non-functional safety part and improving the safety of the intelligent cockpit. However, this method of using a dual-SOC system requires the use of two SOC chips, resulting in a relatively high hardware cost. Further, in order to reduce the hardware cost, another method using a single-SOC system and a hypervisor to implement functional safety and non-functional safety at the operating system level has emerged. This method can save hardware costs because the two operating systems share one SOC chip. However, due to the involvement of two operating systems, the software cost will increase, and when the SOC chip has an output failure, the instrument display screen will be unable to output information, resulting in a decrease in the safety of the intelligent cockpit.

[0023] In view of the above problems, the embodiments of the present application provide an intelligent cockpit and a vehicle. The main controller transmits the screen display data to the central control display screen, and the central control display screen completes the display of the current status information of the vehicle. There is no need to use an additional system-on-chip and use a virtual machine to divide an additional operating system, reducing the hardware cost and software cost. When the system-on-chip has an image output failure, the central control display screen can still display normally, reducing the hardware failure rate and improving the safety of the intelligent cockpit.

[0024] The intelligent cockpit can be applied to various vehicles. As shown in the figure, the intelligent cockpit includes a host and a central control display screen, and a main controller is set in the host. Among them, the central control display screen is connected to the main controller, and the main controller is connected to a system-on-chip; the main controller is used to obtain the screen display data, parse the screen display data, and forward the parsed screen display data to the central control display screen and the system-on-chip; the central control display screen is used to display the target information according to the parsed screen display data. Among them, the target information is used to indicate the current state of the vehicle. Exemplarily, the current state of the vehicle includes the driving speed, rotation speed of the vehicle, and the state indicated by the warning indicator light. For example, the warning indicator light indicates that the current fuel is insufficient.

[0025] In this embodiment, a single SOC chip is used for the system-on-chip to reduce the hardware cost of the intelligent cockpit. The main controller can communicate with the central control display screen through the CAN bus and transmit the screen display data to the central control display screen. Among them, the main controller can be a microcontroller unit (MCU).

[0026] Exemplarily, the screen display data can be the vehicle speed, engine speed, warning light information of the vehicle, etc. Among them, the warning lights can include the engine fault light, the brake system warning light, the fuel warning light, etc.

[0027] Optionally, the screen display data can be collected through sensors on the vehicle. For example, the driving speed of the vehicle can be collected through a speed sensor. The main controller obtains the data collected by the sensors through the vehicle central network gateway and sends these data to the central control display screen and the system-on-chip.

[0028] Optionally, the central control display screen includes an instrument display screen, and the instrument display screen can be a liquid crystal display (LCD).

[0029] In the embodiment of the present application, by creating an independent communication link between the main controller and the central control display screen, there is no need to pass through the SOC, and the part of the SOC with complex hardware circuit functions is excluded. When an output failure occurs in the SOC, the central control display screen can still display normally, reducing the hardware failure rate.

[0030] On the basis of the above embodiment, the intelligent cockpit further includes a first transceiver and a second transceiver. Among them, the first transceiver is connected to the main controller, the main controller is connected to the second transceiver, and the second transceiver is connected to the central control display screen. The first transceiver, the second transceiver, and the first control can be integrated on the host.

[0031] The first transceiver is used to interact with the central gateway of the vehicle to obtain the display data. The main controller is used to parse the display data to obtain the parsed display data and transmit it to the second transceiver and the system-on-chip. The second transceiver is used to transmit the parsed display data to the central control display screen.

[0032] In this embodiment, the first transceiver interacts with the central gateway of the vehicle through the CAN bus to obtain the display data. Exemplarily, the first transceiver can also obtain entertainment information from the central gateway and transmit the entertainment information to the system-on-chip through the main controller. The system-on-chip can display the entertainment information on the IVI display screen to realize the information interaction between the user and the vehicle.

[0033] Exemplarily, the entertainment information can include information such as weather forecast, video, map, and reverse image.

[0034] Optionally, the first transceiver and the second transceiver can be CAN transceivers. Exemplarily, the second transceiver is connected to the central control display screen through the CAN bus to achieve data communication.

[0035] In the embodiment of the present application, through the first transceiver and the second transceiver, the first transceiver is used to obtain the display data, and the second transceiver is used to transmit the display data parsed by the main controller to the central control display screen to form an independent communication link, so that even when the SOC fails, the central control display screen can still display normally, improving the safety of the intelligent cockpit.

[0036] In some embodiments, the first transceiver, the second transceiver, the main controller, and the system-on-chip can be integrated into the host. The intelligent cockpit can be provided with a first power supply component, wherein the first power supply component is connected to the main controller.

[0037] The first power supply component is used to supply power to the main controller, the system-on-chip, the first transceiver, and the second transceiver.

[0038] In this embodiment, when the main controller is connected to the first power supply component, the main controller can also be used for the power management of the host. Exemplarily, the first power supply component can include a power supply and a power diagnosis and detection circuit. Through the power diagnosis and detection circuit, power diagnosis and detection can be performed when a circuit failure occurs in the main controller, the system-on-chip, the first transceiver, or the second transceiver, which is convenient for maintenance and management.

[0039] Based on the above embodiments, the figure is a schematic structural diagram of the third embodiment of the intelligent cockpit provided by this application. As shown in the figure, the above intelligent cockpit includes a host computer. Among them, a first transceiver, a second transceiver, and a main controller are provided in the host computer. The first transceiver, the second transceiver, and the main controller can refer to the explanations in the above embodiments and will not be elaborated here. The central control display screen in the intelligent cockpit includes: a third transceiver, a second controller, and a display device. Among them, the third transceiver is connected to the second transceiver, the second controller is connected to the third transceiver, and the display device is connected to the second controller.

[0040] The third transceiver is used to obtain the parsed screen display data transmitted by the second transceiver and transmit the parsed screen display data to the second controller. The second controller is used to control the display device to display the target information according to the parsed screen display data.

[0041] The above intelligent cockpit further includes: a first serializer. Among them, the system on a chip is connected to the central control display screen through the first serializer. The system on a chip is used to obtain the parsed screen display data and transmit it to the central control display screen through the first serializer. Among them, the first serializer is an interface circuit in high-speed data communication. In this application embodiment, by setting the first serializer, the SOC can transmit the screen display data to the central control display screen through the first serializer, so that the central control display screen can complete the display of the target information based on the screen display data transmitted by the SOC when the SOC is not faulty.

[0042] The above central control display screen further includes a first deserialzier. Among them, the first serializer is connected to the first deserialzier, and the first deserialzier is connected to the display device.

[0043] In this application embodiment, by setting the first deserialzier paired with the first serializer, after the parsed screen display data transmitted by the SOC is deserialized by the first deserialzier, it is transmitted to the display device of the central control display screen, so that the central control display screen can complete the display of the target information based on the screen display data transmitted by the SOC when the SOC is not faulty.

[0044] The intelligent cockpit further includes: an in-vehicle infotainment system display module and a second serializer. Among them, the in-vehicle infotainment system display module is connected to the system on a chip through the second serializer. The system on a chip is used to obtain entertainment information and send it to the in-vehicle infotainment system display module through the second serializer. Among them, the in-vehicle infotainment system display module is used to display entertainment information. In this application embodiment, the in-vehicle infotainment display module obtains the entertainment information of the system on a chip, so that the system on a chip can use a single SOC chip to complete the display of entertainment information and instrument information, without separately configuring a SOC chip for the display of entertainment information and instrument information, reducing the hardware cost.

[0045] The system-on-chip is a high-speed serial transmission system based on FPGA; the high-speed serial transmission system based on FPGA includes: data transmission processing and data reception processing; data transmission processing flow: parallel data is input, converted by a 64B / 66B encoding module, then scrambled by a scrambling module, and then sent out after parallel-to-serial conversion; data reception processing flow: loopback data is sent to a descrambling module for descrambling after serial-to-parallel conversion, and the descrambled data is then decoded by a 64B / 66B decoding module.

[0046] The working method of the high-speed serial transmission system based on FPGA includes: 1) The input signal is buffered into the fifo through a receiving module. In the 64B / 66B encoding module, according to different 64b code formats, if the 8-byte group is a data character, the "01" identifier is added; if one or more bytes are control characters, the "10" identifier is added. 2) The 64-bit signal is added with a synchronization header and converted into a 66b signal. Then, only the 64b data is scrambled in the scrambling module, and after scrambling, it is converted into a single-bit serial signal and output in the parallel-to-serial conversion module; the data reception processing is a complete reverse process compared to the data transmission. The signal goes through serial-to-parallel conversion, first descrambles the data, and then determines the data type according to the synchronization header of the 66b code. If it is a data block, it is directly output; if it is a control block, the data needs to be decoded by referring to the look-up table and then output.

[0047] The main controller is connected to a conversion component, which includes: a memory and a serializer. The inputs of the memory and the serializer are respectively connected to the central control display screen. The output of the serializer is connected to the cockpit domain controller; the memory is used to store the display attribute information of the central control display screen; the serializer is used to convert the image signal input by the central control display screen into a serial signal. The cockpit domain chip is used to parse the parallel image signal and transmit the parsed image signal to the central control display screen; obtain the display attribute information from the conversion component and send the image signal to the test conversion component according to the display attribute information; the display attribute information includes the data format supported by the test conversion component; convert the image signal sent by the input device into a serial SERDES signal supported by the cockpit domain controller; convert the serial SERDES signal into a parallel image signal and display the image signal.

[0048] 64B / 66B encoding is a high-performance serial data encoding standard. It is not a true encoding but a codec method based on a scrambling mechanism and is the encoding method recommended by IEEE for 10G communication standards. Compared with 8B / 10B encoding, 64B / 66B encoding has lower encoding overhead, is more adaptable to complex hardware, and supports the latest data and programs. Currently, 64B / 66B encoding is mainly applied to Fiber Channel 10G FC and 16G FC, 10G Ethernet, 100G Ethernet, 10G EPON, InfiniBand, Thunderbolt, and Xilinx's Aurora protocol.

[0049] The 64B / 66B encoding format is as follows in the table

[0050] The basic idea of 64B / 66B encoding is to encode 64-bit data or control information into 66-bit blocks for transmission. This is mainly for data alignment at the receiver and synchronization of the received data bit stream. "10" and "01" represent two types of synchronization headers. "10" indicates that the data is a mixture of control information and data. Among them, the 8-bit data adjacent to the synchronization header is the type field, and the remaining 56 bits are control information or data or a mixture of both. As shown in the above table, D represents the data encoding of 64B / 66B, and each data code is 8 bits; Z represents the control code, and each control code is 7 bits; S represents the start of the packet, and T represents the end of the packet. T can exist in any byte, but S can only appear in the 0th and 4th bytes of 8 bytes. Except for the synchronization code, the 64-bit data must be scrambled before transmission. The characteristic polynomial of the scrambler used for 64B / 66B encoding is X58 + X39 + 1.

[0051] To improve the stability of high-speed data transmission and increase transmission efficiency, the high-speed serial data transmission system has changed from the initially stability-seeking 8B / 10B to the now widely used 64B / 66B encoding. The scrambling technology in 64B / 66B encoding rearranges or encodes the data to optimize it, making the "0" and "1" of the data bits reach a random distribution to the greatest extent, further reducing the inter-symbol interference of jitter and improving the reliability of data transmission. The greatest advantage of 64B / 66B encoding is its high efficiency. There are only 2 redundant bits in transmission, and the encoding overhead is about 3%. The efficiency of data transmission using 64B / 66B encoding is guaranteed, and it has more advantages in a higher-speed transmission environment.

[0052] The high-speed serial transmission system based on FPGA is mainly divided into two parts: data sending processing and data receiving processing. The data sending processing flow is mainly as follows: parallel data is input, converted by a 64B / 66B encoding module, then scrambled by a scrambling module, and finally sent out after parallel-to-serial conversion. The test system loops the serial sending and receiving ends. The data receiving processing flow is: the looped data is sent to the descrambling module for descrambling after serial-to-parallel conversion, and the descrambled data is then decoded by a 64B / 66B decoding module, which not only ensures the stable transmission of data but also ensures the transmission efficiency of data. The overall system schematic diagram is as Figure 1 shown.

[0053] First, the input signal is buffered into the fifo by the receiving module. In the 64B / 66B encoding module, according to different 64b code formats, if the 8-byte group is a data character, the "01" identifier is added; if one or more bytes are control characters, the "10" identifier is added. The 64-bit signal is added with a synchronization header and converted into a 66b signal. Then, only the 64b data is scrambled in the scrambling module, and after scrambling, it is converted into a single-bit serial signal output in the parallel-to-serial conversion module. The data receiving processing is a complete reverse process compared to data sending. The signal undergoes serial-to-parallel conversion, first the data is descrambled, and then the data type is judged according to the synchronization header of the 66b code. If it is a data block, it is directly output; if it is a control block, the data needs to be decoded by referring to the look-up table and then output.

[0054] In the present invention, a 64 B / 66 B encoding and decoding module is written in a VHDL hardware description language in an FPGA-based environment, and the entire high-speed communication system is implemented through a scrambling and descrambling module and a parallel-to-serial / serial-to-parallel conversion module. In the overall system design, each module can complete independent function implementation. The 64 B / 66 B encoding maximizes the balance of the number of "0" and "1" of data bits and has extremely high transmission efficiency, which is very suitable for ultra-high-speed information transmission. The synchronous clock can ensure the synchronization between sending and receiving, and at the same time can provide a reliable clock reference for the decoding module.

Claims

1. An intelligent cockpit suitable for high-efficiency serial deserialization, characterized in that, it includes: a cockpit domain controller, a central control display screen, and a main controller. The central control display screen is connected to the main controller, and the main controller is connected to a system-on-chip; The main controller is used to obtain screen display data, parse the screen display data, and forward the parsed screen display data to the central control display screen and the system-on-chip; The central control display screen is used to display target information according to the parsed screen display data, and the target information is used to indicate the current state of the vehicle; The system-on-chip is a high-speed serial transmission system based on FPGA; The high-speed serial transmission system based on FPGA includes: data sending processing and data receiving processing; Data sending processing flow: Parallel data is input, converted by a 64B / 66B encoding module, then scrambled by a scrambling module, and then sent out after serial / parallel conversion; Data receiving processing flow: The loopback data is sent to a descrambling module for descrambling after serial / parallel conversion, and the descrambled data is then decoded by a 64B / 66B decoding module.

2. The intelligent cockpit according to claim 1, characterized in that, The working method of the high-speed serial transmission system based on FPGA includes: 1) The input signal is cached into a fifo through a receiving module. In the 64B / 66B encoding module, according to different 64b code formats, if the 8-byte group is a data character, add a "01" identifier; if one or more bytes are control characters, add a "10" identifier; 2) Add a synchronization header to the 64-bit signal to convert it into a 66b signal. Then, only the 64b data is scrambled in the scrambling module, and after scrambling, it is converted into a one-bit serial signal and output in the serial / parallel conversion module; The data receiving processing is a complete inverse process relative to the data sending. The signal goes through serial / parallel conversion, first descrambles the data, and then judges the data type according to the synchronization header of the 66b code. If it is a data block, it is directly output; if it is a control block, the data needs to be decoded according to the lookup table and then output.

3. The intelligent cockpit according to claim 2, characterized in that, The main controller is connected to a conversion component, which includes: a memory and a serializer. The inputs of the memory and the serializer are respectively connected to the central control display screen, and the output of the serializer is connected to the cockpit domain controller; The memory is used to store the display attribute information of the central control display screen; The serializer is used to convert the image signal input by the central control display screen into a serial signal; The cockpit domain chip is used to parse the parallel image signal and transmit the parsed image signal to the central control display screen; Obtain display attribute information from the conversion component and send an image signal to the test conversion component according to the display attribute information; The display attribute information includes the data format supported by the test conversion component; Convert the image signal sent by the input device into a serial SERDES signal supported by the cockpit domain controller; Convert the serial SERDES signal into a parallel image signal and display the image signal.

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