Capacitive chip structure

Abstract

The invention belongs to the technical field of micro electro mechanical systems (MEMS), and particularly relates to a capacitive chip structure. The invention provides a novel capacitive chip structure with low manufacturing cost. The pressure-sensitive variable capacitor comprises an upper polar plate (02), a lower polar plate (01) and a substrate (11), the lower polar plate (01) is arranged on the substrate (11), a cavity (05) is formed between the upper polar plate (02) and the lower polar plate (01), the peripheries of the upper polar plate (02) and the lower polar plate (01) are connected through a first dielectric layer (03), the first dielectric layer (03) is the side wall of the cavity (05), the pressure-sensitive variable capacitor is characterized in that the upper polar plate (02) is a pressure-sensitive polar plate, and the upper polar plate (02) and the lower polar plate (01) form a pressure-sensitive variable capacitor.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectromechanical systems (MEMS), and particularly relates to a capacitive chip structure. Background Art

[0002] With the development of MEMS technology, pressure sensors have become indispensable key devices in various industries and have been widely used in automotive electronics, petrochemical, biomedical, and national defense industries. Compared with piezoresistive pressure sensors, capacitive pressure sensors have advantages such as high sensitivity, low power consumption, and good temperature characteristics, and are more suitable for developing high-precision pressure sensors. Especially in the context of the increasing requirements for pressure measurement accuracy and reliability in modern aerospace technology and modern defense equipment, the research on MEMS capacitive pressure sensors has received great attention at home and abroad.

[0003] For ordinary capacitive pressure sensors, a parallel plate capacitor structure is generally adopted, which mainly consists of a movable plate and a fixed plate. When pressure acts on the movable plate, the distance between the two plates changes, resulting in a change in capacitance value, and the pressure is measured by detecting the capacitance value. However, there are deficiencies such as severe nonlinearity between input and output, low overload capacity, easy short circuit or breakdown, and low integration in the manufacturing of capacitive sensitive chips. Currently, it is mainly realized through sacrificial layer process or bonding process. The sacrificial layer process is complex, with many process steps and difficult precision control, while the bonding process uses SOI materials in the manufacturing process, and the bonding technology difficulties between single crystal silicon and polycrystalline silicon have not been solved yet, resulting in high manufacturing costs. Summary of the Invention

[0004] The present invention aims at the above problems and provides a new type of capacitive chip structure with low manufacturing cost.

[0005] To achieve the above object, the present invention adopts the following technical solutions. The present invention includes an upper plate (02), a lower plate (01), and a substrate (11). The lower plate (01) is disposed on the substrate (11). A cavity (05) is formed between the upper plate (02) and the lower plate (01). The periphery between the upper plate (02) and the lower plate (01) is connected by a first dielectric layer (03). The first dielectric layer (03) is the side wall of the cavity (05). It is characterized in that the upper plate (02) is a pressure-sensitive plate, and a pressure-sensitive variable capacitor is formed between the upper plate (02) and the lower plate (01), as Figure 1 shown.

[0006] As a preferred solution, the substrate (11) of the present invention is an insulating material or a semiconductor material with a conductivity type opposite to that of the lower plate (01). If a dielectric layer is provided on the substrate (11), the substrate (11) does not need to adopt a semiconductor material with a conductivity type opposite to that of the lower plate (01).

[0007] As a preferred embodiment, the cavity (05) of the present invention is a sealed cavity.

[0008] As another preferred embodiment, a second dielectric layer (04) is provided at the upper end of the lower electrode plate (01) of the present invention, and the thickness of the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) may be of the same material or different materials, such as Figure 2 shown.

[0009] As another preferred embodiment, a third dielectric layer (06) is provided at the upper end of the second dielectric layer (04) of the present invention, and the sum of the thicknesses of the third dielectric layer (06) and the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) may be of the same material or different materials, and the third dielectric layer (06) and the first dielectric layer (03) may be of the same material or different materials. Such as Figure 3 shown.

[0010] As another preferred embodiment, a second dielectric layer (04) is provided at the lower end of the upper electrode plate (02) of the present invention, and the thickness of the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) may be of the same material or different materials. Such as Figure 4 shown.

[0011] As another preferred embodiment, a second dielectric layer (04) is provided at the upper end of the lower electrode plate (01) of the present invention, and a third dielectric layer (06) is provided at the lower end of the upper electrode plate (02). The sum of the thicknesses of the third dielectric layer (06) and the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) may be of the same material or different materials, and the third dielectric layer (06) and the first dielectric layer (03) may be of the same material or different materials. Such as Figure 5 shown.

[0012] As another preferred embodiment, on the basis of Figure 1 a fourth dielectric layer (12) is provided between the lower electrode plate (01) and the substrate (11) of the present invention. The fourth dielectric layer (12) and the first dielectric layer (03) may be of the same material or different materials, and the substrate (11) may be an insulating material or a semiconductor material, such as Figure 6 shown.

[0013] As another preferred embodiment, on the basis of Figure 6Based on this, on the upper end of the lower plate (01) of the present invention, a second dielectric layer (04) is provided, and the thickness of the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) can be of the same material or different materials. The fourth dielectric layer (12) and the first dielectric layer (03) can be of the same material or different materials, such as Figure 7 as shown

[0014] As another preferred solution, on the basis of Figure 6 this, on the lower end of the upper plate (02) of the present invention, a second dielectric layer (04) is provided, and the thickness of the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) can be of the same material or different materials. The fourth dielectric layer (12) and the first dielectric layer (03) can be of the same material or different materials. The substrate (11) can be an insulating material or a semiconductor material, such as Figure 8 as shown

[0015] As another preferred solution, on the basis of Figure 6 this, on the upper end of the lower plate (01) of the present invention, a second dielectric layer (04) is provided, and on the lower end of the upper plate (02), a third dielectric layer (06) is provided. The thickness of the third dielectric layer (06) plus the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) can be of the same material or different materials. The third dielectric layer (06) and the first dielectric layer (03) can be of the same material or different materials. The fourth dielectric layer (12) and the first dielectric layer (03) can be of the same material or different materials. Such as Figure 9 as shown

[0016] As another preferred solution, on the basis of Figure 6 this, on the upper end of the lower plate (01) of the present invention, a second dielectric layer (04) is provided, and on the upper end of the second dielectric layer (04), a third dielectric layer (06) is provided. The thickness of the third dielectric layer (06) plus the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) can be of the same material or different materials. The third dielectric layer (06) and the first dielectric layer (03) can be of the same material or different materials. The fourth dielectric layer (12) and the first dielectric layer (03) can be of the same material or different materials. Such as Figure 10 as shown

[0017] As another preferred solution, on the basis of Figure 1Based on this, a fifth dielectric layer (07) is provided at the upper end of the upper electrode plate (02) of the present invention. The fifth dielectric layer (07) and the first dielectric layer (03) can be of the same material or different materials, such as Figure 11 as shown.

[0018] As another preferred solution, on the basis of Figure 11 this, the fifth dielectric layer (07) of the present invention is provided on the upper surface and the side surface of the upper electrode plate (02); the fifth dielectric layer (07) is also provided on the side surface of the first dielectric layer (03) and the lower electrode plate (01) or the fifth dielectric layer (07) is also provided on the side surface of the lower electrode plate (01). Such as Figure 23 and 24 as shown.

[0019] As another preferred solution, on the basis of Figure 11 this, a second dielectric layer (04) is provided at the upper end of the lower electrode plate (01) of the present invention, and the thickness of the second dielectric layer (04) is less than that of the first dielectric layer (03). The second dielectric layer (04) and the first dielectric layer (03) can be of the same material or different materials. The fifth dielectric layer (07) and the first dielectric layer (03) can be of the same material or different materials, such as Figure 12 as shown.

[0020] As another preferred solution, on the basis of Figure 11 this, a third dielectric layer (06) is provided between the upper electrode plate (02) and the fifth dielectric layer (07) of the present invention. The fifth dielectric layer (07) and the first dielectric layer (03) can be of the same material or different materials. The third dielectric layer (06) and the first dielectric layer (03) can be of the same material or different materials, such as Figure 13 as shown.

[0021] As another preferred solution, on the basis of Figure 11 this, a notch (08) is provided in the middle of the fifth dielectric layer (07) of the present invention. The notch (08) can be one or more, and the shape of the notch (08) includes but is not limited to circular, square, diamond, polygon (the shape is adjusted according to the thickness of the upper electrode plate substrate and the thickness of the dielectric layer 07). The fifth dielectric layer (07) and the first dielectric layer (03) can be of the same material or different materials, such as Figure 14 as shown.

[0022] As another preferred solution, on the basis of Figure 13On the basis of this, a notch (08) is provided in the middle of the fifth dielectric layer (07) of the present invention. The notch (08) can be one or multiple. The shape of the notch (08) includes but is not limited to circular, square, diamond, polygon (the shape is adjusted according to the thickness of the upper plate substrate and the thickness of the dielectric layer 07). The fifth dielectric layer (07) and the first dielectric layer (03) can be the same material or different materials. The third dielectric layer (06) and the first dielectric layer (03) can be the same material or different materials, such as Figure 15 shown.

[0023] As another preferred solution, on the basis of Figure 13 this, a notch (08) is provided in the middle of the fifth dielectric layer (07) and the third dielectric layer (06) of the present invention. The notch (08) can be one or multiple. The shape of the notch (08) includes but is not limited to circular, square, diamond, polygon (the shape is adjusted according to the thickness of the upper plate substrate and the thickness of the dielectric layer 07). The fifth dielectric layer (07) and the first dielectric layer (03) can be the same material or different materials. The third dielectric layer (06) and the first dielectric layer (03) can be the same material or different materials, such as Figure 16 shown.

[0024] As another preferred solution, on the basis of Figure 1 this, a through hole (10) for communicating the cavity (05) with the outside is provided on the first dielectric layer (03) or the lower plate (01) and the substrate (11) of the present invention. Such as Figure 17 shown.

[0025] As another preferred solution, capacitors C1 and C2 are provided on the substrate (11) in the present invention. Capacitor C1 is of the structure of Figure 1 and capacitor C2 is of the structure that on the basis of Figure 17 a through hole (10) can also be provided on the upper plate (02). The lower plates (01) of capacitor C1 and capacitor C2 are provided on the substrate (11), and the lower plates (01) of capacitor C1 and capacitor C2 are connected and / or the upper plates (02) of capacitor C1 and capacitor C2 are connected; Capacitor C1 and capacitor C2 include an upper plate (02) and a lower plate (01), and there is a cavity (05) between the upper plate (02) and the lower plate (01). The periphery between the upper plate (02) and the lower plate (01) is connected by the first dielectric layer (03); A through hole (10) for communicating the cavity (05) with the outside is provided on the first dielectric layer (03) or the lower plate (01) and the substrate (11) or the upper plate (02) of capacitor C2. Such as Figure 18 , Figure 19 shown.

[0026] As another preferred embodiment, the present invention provides four capacitive structures, namely capacitor C1, capacitor C2, capacitor C3, and capacitor C4, on a substrate (11). The lower plates (01) of capacitors C1, C2, C3, and C4 are disposed on the substrate (11). A dielectric layer (03) is provided above the lower plates (01), and upper plates (02) are provided on the dielectric layer (03). The upper plates (02), lower plates (01), and dielectric layer (03) form cavities (05) and a cavity (09) connected to a through hole (10). The through hole (10) is disposed on the dielectric layer (03), or on the lower plate (01) and the substrate (11), or on the upper plate (02), and through holes (10) are provided in two of the capacitors; the four capacitors are divided into two groups, one group consisting of a capacitor with a through hole (10) and a capacitor without a through hole (10), and the upper plates (02) of the two capacitors in each group are connected respectively; then the four capacitors are re-divided into two groups, one group consisting of a capacitor with a through hole (10) and a capacitor without a through hole (10) whose upper plate (02) is not connected, and the lower plates (01) of the two capacitors in each group are connected respectively. As Figure 20 , Figure 21 , Figure 22 shown is one of the connection methods.

[0027] Secondly, the present invention provides a first lower support (13) between the lower plate (01) of capacitor C1 and the lower plate (01) of C2, and a second lower support (14) between the lower plate (01) of capacitor C3 and the lower plate (01) of C4;

[0028] A first part (15) of the upper plate (02) is provided between the upper plate (02) of C1 and the upper plate (02) of C2 corresponding to the first lower support (13), and a second part (16) of the upper plate (02) is provided between the upper plate (02) of C3 and the upper plate (02) of C4 corresponding to the second lower support (14).

[0029] In addition, the upper plate (1), lower plate (2), and substrate (11) of the present invention are connected to an external circuit through bonding pads and metal leads or bonding pads.

[0030] Advantages of the present invention.

[0031] When the structure of the present invention is in use, the upper plate (02) serves as a pressure-sensitive plate, and the upper plate (02) and the lower plate (01) form a pressure-sensitive variable capacitor, thereby measuring the pressure value to be measured. When the lower plate (01) is directly disposed on the substrate (11), the substrate (11) can select an insulating material such as glass, or a semiconductor material with a conductivity type opposite to that of the lower plate (01). During the production process, the SOI material can be no longer used based on the bonding process, and the process steps can be reduced, which can significantly reduce the manufacturing cost. Description of the Drawings

[0032] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The protection scope of the present invention is not limited to the description of the following content.

[0033] Figure 1 It is a schematic structural diagram of the first embodiment of the present invention.

[0034] Figure 2 It is a schematic structural diagram of the second embodiment of the present invention.

[0035] Figure 3 It is a schematic structural diagram of the third embodiment of the present invention.

[0036] Figure 4 It is a schematic structural diagram of the fourth embodiment of the present invention.

[0037] Figure 5 It is a schematic structural diagram of the fifth embodiment of the present invention.

[0038] Figure 6 It is a schematic structural diagram of the sixth embodiment of the present invention.

[0039] Figure 7 It is a schematic structural diagram of the seventh embodiment of the present invention.

[0040] Figure 8 It is a schematic structural diagram of the eighth embodiment of the present invention.

[0041] Figure 9 It is a schematic structural diagram of the ninth embodiment of the present invention.

[0042] Figure 10 It is a schematic structural diagram of the tenth embodiment of the present invention.

[0043] Figure 11 It is a schematic structural diagram of the eleventh embodiment of the present invention.

[0044] Figure 12 It is a schematic structural diagram of the twelfth embodiment of the present invention.

[0045] Figure 13 It is a schematic structural diagram of the thirteenth embodiment of the present invention.

[0046] Figure 14 It is a schematic structural diagram of the fourteenth embodiment of the present invention.

[0047] Figure 15 It is a schematic structural diagram of the fifteenth embodiment of the present invention.

[0048] Figure 16 It is a schematic structural diagram of the sixteenth embodiment of the present invention.

[0049] Figure 17 It is a schematic structural diagram of the seventeenth embodiment of the present invention.

[0050] Figure 18 It is a schematic structural diagram of the eighteenth embodiment of the present invention.

[0051] Figure 19 It is a schematic structural diagram of the eighteenth embodiment of the present invention.

[0052] Figure 20 It is a schematic structural diagram of the nineteenth embodiment of the present invention.

[0053] Figure 21 It is a top view of the lower plate of the nineteenth embodiment of the present invention.

[0054] Figure 22 It is a schematic top view of the upper plate of the nineteenth embodiment of the present invention.

[0055] Figure 23 It is a schematic structural diagram of the twentieth embodiment of the present invention.

[0056] Figure 24 It is a schematic structural diagram of the twenty-first embodiment of the present invention.

[0057] Figure 25 It is a schematic structural diagram of the twenty-second embodiment of the present invention.

[0058] Figure 26 It is a schematic structural diagram of the twenty-third embodiment of the present invention.

[0059] Figure 27 、 28 It is a curve diagram of the output characteristics of the present invention.

[0060] Description of reference numerals:

[0061] 01. Lower plate, 02. Upper plate, 03. First dielectric layer, 04. Second dielectric layer, 05. Cavity, 06. Dielectric layer, 07. Fifth dielectric layer, 08. Notch, 10. Through hole, 11. Substrate, 12. Fourth dielectric layer, 13. First lower support, 14. Second lower support, 15. First part of the upper plate, 16. Second part of the upper plate. Detailed implementation manners

[0062] As Figure 1 shown, the present invention includes a lower plate (01), an upper plate (02), a first dielectric layer (03), a cavity (05) and a substrate (11). There is a sealed cavity (05) between the upper plate (02) and the lower plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolation between the upper plate (02) and the lower plate (01). As the upper plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. When the substrate (11) is selected as an insulating material, such as glass, the process steps are simplified at this time, and SOI materials are not required, greatly reducing the cost.

[0063] When the substrate (11) is made of a semiconductor material with a conductivity type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a reverse-biased cut-off state, and the lower electrode plate (2) only serves as one electrode plate of the capacitor. When the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a forward-biased state. When the capacitance value is small, the forward voltage of the PN junction has not reached the conduction voltage, the PN junction is in a cut-off state, no current passes through, and the lower electrode plate (01) only serves as one electrode plate of the capacitor. As the upper electrode plate (02) deforms downward under pressure, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts, and the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction at this time. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the change of the capacitance. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystal silicon oxide layers in the bonding process, and no longer requires SOI materials, saving process steps and greatly reducing costs.

[0064] When the lower electrode plate (01) is made of a metal material and the substrate (11) is made of an insulating material, this structure can be manufactured by a deposition process, which simplifies the process steps, does not require SOI materials, and greatly reduces costs.

[0065] When the structure of the present invention is used, the upper electrode plate (02) can be used as a pressure-sensing electrode plate. The upper electrode plate (02) and the lower electrode plate (01) form a pressure-sensing variable capacitor C1. By applying a voltage to the PN junction and regarding the capacitance of the PN junction as capacitor C2 (the capacitance of the PN junction is a barrier capacitance or a diffusion capacitance), C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, saving chip area and improving the integration degree.

[0066] Such as Figure 2As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11) and a second dielectric layer (04). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolation for the upper electrode plate (02) and the lower electrode plate (01). The second dielectric layer (04) is fabricated on the lower electrode plate (01). As the upper electrode plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. The second dielectric layer (04) is selected from materials with high dielectric constant, which increases the initial capacitance value of the capacitor, increases the capacitance change amount, improves the accuracy and sensitivity, and improves the linearity of the capacitance change. When the second dielectric layer (04) is selected as an insulating material, it can prevent short circuit when the upper electrode plate (02) contacts the lower electrode plate (01) due to excessive overload, and at the same time increases the breakdown voltage of the capacitor.

[0067] When the substrate (11) is selected as an insulating material, such as glass, the process steps are simplified at this time, SOI material is not required, and the cost is greatly reduced. When the substrate (11) is selected as a semiconductor material with a conductivity type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in the reverse bias cut-off state, and the lower electrode plate (2) only serves as one electrode plate of the capacitor. When the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in the forward bias state. When the capacitance value is small, the forward voltage of the PN junction has not reached the conduction voltage, and the PN junction is in the cut-off state, and no current passes through. The lower electrode plate (01) only serves as one electrode plate of the capacitor. As the upper electrode plate (02) deforms downward under pressure, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts. At this time, the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single crystal silicon oxide layer in the bonding process, and no longer requires SOI material, saves the process steps, and greatly reduces the cost.

[0068] When the structure of the present invention is used, the upper electrode plate (02) can be used as a pressure-sensing electrode plate. The upper electrode plate (02) and the lower electrode plate (01) form a pressure-sensing variable capacitor C1. Apply voltage to the PN junction, and regard the PN junction capacitance as capacitor C2 (the capacitance of the PN junction is the barrier capacitance or diffusion capacitance). C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, save the chip area, and improve the integration degree.

[0069] As shown Figure 3 in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a second dielectric layer (04) and a third dielectric layer (06). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The second dielectric layer (04) is fabricated on the lower electrode plate (01), and the third dielectric layer (06) is fabricated on the second dielectric layer (04). As the upper electrode plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. The second dielectric layer (04) and the third dielectric layer (06) are made of materials with high dielectric constants, which increases the initial capacitance value of the capacitor, increases the change amount of the capacitance, and improves the accuracy and sensitivity. Different materials are used for the second dielectric layer (04) and the third dielectric layer (06). By adjusting the shape, size and thickness, the linearity of the capacitance change can be well improved, and at the same time, the breakdown voltage of the capacitor is increased. When the third dielectric layer (06) is selected as an insulating material, it can prevent short circuit when the upper electrode plate (02) contacts the lower electrode plate (01) due to excessive overload, and at the same time, the breakdown voltage of the capacitor is increased.

[0070] When the substrate (11) is selected as an insulating material, such as glass, the process steps are simplified at this time, SOI material is not required, and the cost is greatly reduced. When the substrate (11) is selected as a semiconductor material with a conductive type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a reverse-biased cut-off state, and the lower electrode plate (2) only serves as one electrode plate of the capacitor; when the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a forward-biased state. When the capacitance value is small, the forward voltage of the PN junction has not reached the conduction voltage, the PN junction is in a cut-off state, and no current passes through. The lower electrode plate (01) only serves as one electrode plate of the capacitor. As the upper electrode plate (02) deforms downward under pressure, the capacitance increases and the voltage increases. When the voltage increases to the conduction voltage of the PN junction as the capacitance increases, the PN junction conducts. At this time, the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystalline silicon oxide layers in the bonding process, and no longer requires SOI material, saving process steps and greatly reducing the cost.

[0071] When the structure of the present invention is in use, the upper plate (02) can be used as a pressure-sensitive plate. The upper plate (02) and the lower plate (01) form a pressure-sensitive variable capacitor C1. A voltage is applied to the PN junction, and the PN junction capacitance is regarded as capacitor C2 (the capacitance of the PN junction is the barrier capacitance or the diffusion capacitance). C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, saving the chip area and improving the integration degree.

[0072] As Figure 4 shown, the present invention includes a lower plate (01), an upper plate (02), a first dielectric layer (03), a cavity (05), a substrate (11) and a second dielectric layer (04). A sealed cavity (05) is formed between the upper plate (02) and the lower plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolation between the upper plate (02) and the lower plate (01). A second dielectric layer (04) is made on the lower surface of the upper plate (02). As the upper plate (02) deforms under pressure, the capacitance value also changes, so as to measure the pressure value. The second dielectric layer (04) is made of a material with a high dielectric constant, increasing the initial capacitance value of the capacitor, increasing the change amount of the capacitance, and improving the accuracy and sensitivity. When the upper plate (02) deforms under pressure, the second dielectric layer (04) also deforms accordingly, thus better improving the linearity of the capacitance change; when the second dielectric layer (04) is selected as an insulating material, it can prevent short circuit when the upper plate (02) contacts the lower plate (01) due to excessive overload, and at the same time improve the breakdown voltage of the capacitor.

[0073] When the substrate (11) is made of an insulating material such as glass, the process steps are simplified, SOI material is not required, and the cost is significantly reduced. When the substrate (11) is made of a semiconductor material with a conductivity type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in the reverse bias cut-off state, and the lower electrode plate (2) serves only as one electrode plate of the capacitor; when the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in the forward bias state. When the capacitance value is small and the forward voltage of the PN junction has not reached the conduction voltage, the PN junction is in the cut-off state and no current passes through. The lower electrode plate (01) serves only as one electrode plate of the capacitor. As the upper electrode plate (02) senses pressure and deforms towards the lower electrode plate, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts. At this time, the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single crystal silicon oxide layers in the bonding process, no longer requires SOI material, saves process steps, and significantly reduces the cost.

[0074] When the structure of the present invention is in use, the upper electrode plate (02) can be used as a pressure-sensing electrode plate. The upper electrode plate (02) and the lower electrode plate (01) form a pressure-sensing variable capacitor C1. By applying a voltage to the PN junction and regarding the capacitance of the PN junction as capacitor C2 (the capacitance of the PN junction is a barrier capacitance or a diffusion capacitance), C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, save chip area, and improve the integration level.

[0075] Such as Figure 5As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11) and a second dielectric layer (04). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolation for the upper electrode plate (02) and the lower electrode plate (01). A second dielectric layer (04) is fabricated on the lower electrode plate (01), and a third dielectric layer (06) is fabricated on the lower surface of the upper electrode plate (02). As the upper electrode plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. The second dielectric layer (04) is made of a material with a high dielectric constant, which increases the initial capacitance value of the capacitor, increases the change amount of the capacitance, and improves the accuracy and sensitivity. When the upper electrode plate (02) deforms under pressure, the third dielectric layer (06) also deforms accordingly. The second dielectric layer (04) and the third dielectric layer (06) are made of different materials. By adjusting the shape, size and thickness, the linearity of the capacitance change is better improved. When the second dielectric layer (04) or the third dielectric layer (06) is selected as an insulating material, it can prevent short circuit when the upper electrode plate (02) contacts the lower electrode plate (01) due to excessive overload, and at the same time increases the breakdown voltage of the capacitor.

[0076] When the substrate (11) is selected as an insulating material, such as glass, the process steps are simplified at this time, and SOI materials are not required, which greatly reduces the cost. When the substrate (11) is selected as a semiconductor material with a conductive type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in the reverse bias cut-off state, and the lower electrode plate (2) only serves as one electrode plate of the capacitor; when the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in the forward bias state. When the capacitance value is small, the forward voltage of the PN junction has not reached the conduction voltage, and the PN junction is in the cut-off state, and no current passes through. The lower electrode plate (01) only serves as one electrode plate of the capacitor. As the upper electrode plate (02) deforms under pressure towards the lower electrode plate, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts, and the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction at this time. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single crystal silicon oxide layers in the bonding process, and no longer requires SOI materials, saving process steps and greatly reducing the cost.

[0077] When the structure of the present invention is in use, the upper plate (02) can be used as a pressure-sensitive plate. The upper plate (02) and the lower plate (01) form a pressure-sensitive variable capacitor C1. A voltage is applied to the PN junction, and the PN junction capacitance is regarded as capacitor C2 (the capacitance of the PN junction is the barrier capacitance or the diffusion capacitance). C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, save the chip area, and improve the integration degree.

[0078] As Figure 6 shown, the present invention includes a lower plate (01), an upper plate (02), a first dielectric layer (03), a cavity (05), a substrate (11) and a fourth dielectric layer (12). A sealed cavity (05) is formed between the upper plate (02) and the lower plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolates the upper plate (02) and the lower plate (01). The fourth dielectric layer (12) is arranged between the substrate (11) and the lower plate (01). As the upper plate (02) deforms under pressure, the capacitance value also changes, so as to measure the pressure value. When the fourth dielectric layer (12) is made of a porous material or an elastic material, it can protect the capacitance structure, improve the seismic resistance and reduce the external stress interference; when the substrate (11) is made of a semiconductor material, the lower plate (01) and the substrate (11) form a capacitor C2, and the capacitor C1 between the upper plate (02) and the lower plate (01) forms a differential capacitance to shield the common-mode interference and improve the anti-interference ability. When the lower plate (01) is made of a metal material and the dielectric layer is made of an insulating material, the material cost can be greatly reduced. When the lower plate (01), the fourth dielectric layer (12) and the substrate (11) are made of customized materials, the manufacturing process of the lower plate is reduced and the process steps are optimized.

[0079] When the lower plate (01) is arranged on the fourth dielectric layer (12) and the fourth dielectric layer (12) is arranged on the substrate (11), the substrate (11) can be made of an insulating material or a semiconductor material. In the production process, based on the bonding process, the process steps can be reduced and the manufacturing cost can be greatly reduced; when the structure of the present invention is in use, by selecting the dielectric layer material and adjusting the parameters, the linearity of the capacitance can be significantly improved, the change amount of the capacitance can be increased, the precision can be improved, and the sensitivity can be improved.

[0080] As Figure 7As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fourth dielectric layer (12) and a second dielectric layer (04). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolates the upper electrode plate (02) and the lower electrode plate (01). The fourth dielectric layer (12) is disposed between the substrate (11) and the lower electrode plate (01). The second dielectric layer (04) is fabricated on the lower electrode plate (01). As the upper electrode plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. The second dielectric layer (04) is selected as a material with a high dielectric constant, which increases the initial capacitance value of the capacitor, increases the change amount of the capacitance, improves the accuracy and sensitivity, and improves the linearity of the capacitance change. When the second dielectric layer (04) is selected as an insulating material, it can prevent short circuit when the upper electrode plate (02) contacts the lower electrode plate (01) due to excessive overload, and at the same time increases the breakdown voltage of the capacitor. When the fourth dielectric layer (12) is selected as a porous material or an elastic material, it can protect the capacitor structure, improve the seismic resistance, and reduce the interference of external stress. When the substrate (11) is selected as a semiconductor material, a capacitor C2 is formed between the lower electrode plate (01) and the substrate (11), and a differential capacitance is formed with the capacitance C1 between the upper and lower electrode plates (02) and the lower electrode plate (01), shielding the common-mode interference and improving the anti-interference ability. When the lower electrode plate (01) is made of a metal material and the dielectric layer is an insulating material, the material cost can be significantly reduced. When the lower electrode plate (01), the fourth dielectric layer (12) and the substrate (11) are made of customized materials, the manufacturing process of the lower electrode plate is reduced, and the process steps are optimized.

[0081] As Figure 8As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fourth dielectric layer (12), and a second dielectric layer (04). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03), and the first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The fourth dielectric layer (12) is disposed between the substrate (11) and the lower electrode plate (01). The second dielectric layer (04) is fabricated on the upper electrode plate (02). As the upper electrode plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. The second dielectric layer (04) is made of a material with a high dielectric constant, which increases the initial capacitance value of the capacitor, increases the change amount of the capacitance, and improves the accuracy and sensitivity. When the upper electrode plate (02) deforms under pressure, the second dielectric layer (04) also deforms accordingly, thus better improving the linearity of the capacitance change. When the second dielectric layer (04) is made of an insulating material, it can prevent short - circuit when the upper electrode plate (02) contacts the lower electrode plate (01) due to excessive overload, and at the same time increases the breakdown voltage of the capacitor. When the fourth dielectric layer (12) is made of a porous material or an elastic material, it can protect the capacitor structure, improve the seismic resistance, and reduce the interference of external stress. When the substrate (11) is made of a semiconductor material, a capacitor C2 is formed between the lower electrode plate (01) and the substrate (11), and a differential capacitor is formed with the capacitor C1 between the upper and lower electrode plates (02) and the lower electrode plate (01), shielding the common - mode interference and improving the anti - interference ability. When the lower electrode plate (01) is made of a metal material and the dielectric layer is an insulating material, the material cost can be significantly reduced. When the lower electrode plate (01), the fourth dielectric layer (12), and the substrate (11) are made of customized materials, the manufacturing process of the lower electrode plate is reduced, and the process steps are optimized.

[0082] As Figure 9As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fourth dielectric layer (12), a second dielectric layer (04) and a third dielectric layer (06). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolates the upper electrode plate (02) and the lower electrode plate (01). The fourth dielectric layer (12) is disposed between the substrate (11) and the lower electrode plate (01). The second dielectric layer (04) is fabricated on the lower electrode plate (01), and the third dielectric layer (06) is fabricated on the lower surface of the upper electrode plate (02). As the upper electrode plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. The second dielectric layer (04) is made of a material with a high dielectric constant, which increases the initial capacitance value of the capacitor, increases the change amount of the capacitance, and improves the accuracy and sensitivity. When the upper electrode plate (02) deforms under pressure, the third dielectric layer (06) also deforms accordingly. The second dielectric layer (04) and the third dielectric layer (06) are made of different materials. By adjusting the shape, size and thickness, the linearity of the capacitance change is better improved. When the second dielectric layer (04) or the third dielectric layer (06) is selected as an insulating material, it can prevent short circuit when the upper electrode plate (02) contacts the lower electrode plate (01) due to excessive overload, and at the same time increases the breakdown voltage of the capacitor. When the fourth dielectric layer (12) is made of a porous material or an elastic material, it can protect the capacitor structure, improve the seismic resistance and reduce the external stress interference. When the substrate (11) is made of a semiconductor material, a capacitor C2 is formed between the lower electrode plate (01) and the substrate (11), and a differential capacitor is formed with the capacitor C1 between the upper and lower electrode plates (02) and the lower electrode plate (01), shielding the common-mode interference and improving the anti-interference ability. When the lower electrode plate (01) is made of a metal material and the dielectric layer is made of an insulating material, the material cost can be significantly reduced. When the lower electrode plate (01), the fourth dielectric layer (12) and the substrate (11) are made of customized materials, the manufacturing process of the lower electrode plate is reduced and the process steps are optimized.

[0083] As Figure 10As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fourth dielectric layer (12), a second dielectric layer (04), and a third dielectric layer (06). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The fourth dielectric layer (12) is disposed between the substrate (11) and the lower electrode plate (01). The second dielectric layer (04) is fabricated on the lower electrode plate (01), and the third dielectric layer (06) is fabricated on the second dielectric layer (04). As the upper electrode plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. The second dielectric layer (04) is made of a material with a high dielectric constant, which increases the initial capacitance value of the capacitor, increases the change amount of the capacitance, and improves the accuracy and sensitivity. The second dielectric layer (04) and the third dielectric layer (06) are made of different materials. By adjusting the shape, size, and thickness, the linearity of the capacitance change is better improved. When the third dielectric layer (06) is selected as an insulating material, it can prevent short circuit when the upper electrode plate (02) contacts the lower electrode plate (01) due to excessive overload, and at the same time increases the breakdown voltage of the capacitor. When the fourth dielectric layer (12) is selected as a porous material or a material with elasticity, it can protect the capacitor structure, improve the seismic resistance, and reduce the interference of external stress. When the substrate (11) is selected as a semiconductor material, a capacitor C2 is formed between the lower electrode plate (01) and the substrate (11), and a differential capacitance is formed with the capacitance C1 between the upper and lower electrode plates (02) and the lower electrode plate (01), shielding the common-mode interference and improving the anti-interference ability. When the lower electrode plate (01) is made of a metal material and the dielectric layer is an insulating material, the material cost can be significantly reduced. When the lower electrode plate (01), the fourth dielectric layer (12), and the substrate (11) are made of customized materials, the manufacturing process of the lower electrode plate is reduced, and the process steps are optimized.

[0084] As Figure 11 shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), and a fifth dielectric layer (07). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The fifth dielectric layer (07) is fabricated on the upper electrode plate (02). When the upper electrode plate (02) deforms under pressure, the fifth dielectric layer (07) also deforms accordingly, adjusting the deformation coefficient of the upper electrode plate (02) and the amount of deformation of the upper electrode plate (02), thereby better improving the linearity of the capacitance change and increasing the measurement range of the capacitance change with pressure under the same conditions.

[0085] The fifth dielectric layer (07) is fabricated on the top and side surfaces of the upper electrode plate (02), and at the same time, the fifth dielectric layer (07) is fabricated on the side surfaces of the first dielectric layer (03) and the lower electrode plate (01), making the cavity (05) have better sealing performance, improving the airtightness, enhancing the durability of the structure, increasing the reliability, and improving the overload capacity. The fifth dielectric layer (07) provides insulating protection for the upper electrode plate (02) and the lower electrode plate (01), shielding external interference and improving the anti-interference ability, as Figure 23 shown.

[0086] The fifth dielectric layer (07) is fabricated on the top and side surfaces of the upper electrode plate (02), and at the same time, the fifth dielectric layer (07) is fabricated on the side surface of the lower electrode plate (01). The fifth dielectric layer (07) provides insulating protection for the upper electrode plate (02) and the lower electrode plate (01), shielding external interference, improving the anti-interference ability, and increasing the overload capacity, as Figure 24 shown. When the substrate (11) is made of an insulating material such as glass, the process steps are simplified, the SOI material is not required, and the cost is greatly reduced.

[0087] When the substrate (11) is made of a semiconductor material with a conductivity type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, making the PN junction between the lower electrode plate (01) and the substrate (11) in the reverse-biased cut-off state, and the lower electrode plate (2) only serves as one electrode plate of the capacitor; when the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, making the PN junction between the lower electrode plate (01) and the substrate (11) in the forward-biased state. When the capacitance value is small and the forward voltage of the PN junction has not reached the conduction voltage, the PN junction is in the cut-off state and no current passes through. The lower electrode plate (01) only serves as one electrode plate of the capacitor. As the upper electrode plate (02) deforms downward under pressure towards the lower electrode plate, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts, and at this time, the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the change of capacitance. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystalline silicon oxide layers during the bonding process, and no longer requires the SOI material, saving process steps and greatly reducing the cost.

[0088] When the lower electrode plate (01) is made of a metal material and the substrate (11) is made of an insulating material, this structure can be fabricated by a deposition process, and the process steps are simplified, the SOI material is not required, and the cost is greatly reduced.

[0089] When the structure of the present invention is in use, the upper plate (02) can be used as a pressure-sensitive plate. The upper plate (02) and the lower plate (01) form a pressure-sensitive variable capacitor C1. A voltage is applied to the PN junction, and the PN junction capacitance is regarded as capacitor C2 (the capacitance of the PN junction is the barrier capacitance or the diffusion capacitance). C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, save the chip area, and improve the integration degree.

[0090] As Figure 12 shown, the present invention includes a lower plate (01), an upper plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fifth dielectric layer (07) and a second dielectric layer (04). There is a sealed cavity (05) between the upper plate (02) and the lower plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolates the upper plate (02) and the lower plate (01). The second dielectric layer (04) is made on the lower plate (01), and the fifth dielectric layer (07) is made on the upper plate (02). When the upper plate (02) deforms under pressure, the fifth dielectric layer (07) also deforms accordingly, adjusting the deformation coefficient of the upper plate (02) and the amount of deformation of the upper plate (02), thereby better improving the linearity of the capacitance change and increasing the range of capacitance change with pressure under the same conditions; The second dielectric layer (04) is selected from materials with a high dielectric constant, increasing the initial capacitance value of the capacitor, increasing the amount of capacitance change, improving the accuracy and sensitivity, and improving the linearity of the capacitance change; When the second dielectric layer (04) is selected as an insulating material, it can prevent short circuit when the upper plate (02) contacts the lower plate (01) due to excessive overload, and at the same time increase the breakdown voltage of the capacitor. The fifth dielectric layer (07) is made on the upper and side surfaces of the upper plate (02), and at the same time the fifth dielectric layer (07) is made on the side surfaces of the first dielectric layer (03) and the lower plate (01), making the cavity (05) have better sealing performance, improving the airtightness, improving the durability of the structure, improving the reliability, and improving the overload capacity. The fifth dielectric layer (07) provides insulation protection for the upper plate (02) and the lower plate (01), shields external interference, and improves the anti-interference ability, as Figure 23 shown.

[0091] The fifth dielectric layer (07) is made on the upper and side surfaces of the upper plate (02), and at the same time the fifth dielectric layer (07) is made on the side surface of the lower plate (01). The fifth dielectric layer (07) provides insulation protection for the upper plate (02) and the lower plate (01), shields external interference, improves the anti-interference ability, and improves the overload capacity, as Figure 24 shown.

[0092] When the substrate (11) selects an insulating material such as glass, the process steps are simplified, the SOI material is not required, and the cost is greatly reduced. When the substrate (11) selects a semiconductor material of a conductivity type opposite to that of the lower plate (01), for example, when the lower plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower plate (01) and the substrate (11) is in the reverse bias cut-off state, and the lower plate (2) only serves as one plate of the capacitor; when the lower plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower plate (01) and the substrate (11) is in the forward bias state. When the capacitance value is small, the forward voltage of the PN junction does not reach the conduction voltage, the PN junction is in the cut-off state, and no current passes between them. The lower plate (01) only serves as one plate of the capacitor. As the upper plate (02) deforms downward under pressure, the capacitance increases and the voltage increases. When the voltage increases to the conduction voltage of the PN junction as the capacitance increases, the PN junction conducts. At this time, the lower plate (01) is both one plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single crystal silicon oxide layers in the bonding process, and no longer requires the SOI material, saves the process steps, and greatly reduces the cost.

[0093] When the lower plate (01) selects a metal material and the substrate (11) selects an insulating material, this structure can be manufactured by a deposition process, and the process steps are simplified, the SOI material is not required, and the cost is greatly reduced.

[0094] When the structure of the present invention is used, the upper plate (02) can be used as a pressure-sensing plate. The upper plate (02) and the lower plate (01) form a pressure-sensing variable capacitor C1. The PN junction is connected to a voltage, and the capacitance of the PN junction is regarded as capacitor C2 (the capacitance of the PN junction is a barrier capacitance or a diffusion capacitance). C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, save the chip area, and improve the integration degree.

[0095] Such as Figure 13As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fifth dielectric layer (07), a second dielectric layer (04) and a third dielectric layer (06). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03), and the first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The second dielectric layer (04) is fabricated on the lower electrode plate (01), the third dielectric layer (06) is fabricated on the upper electrode plate (02), and the fifth dielectric layer (07) is fabricated on the third dielectric layer (06). When the upper electrode plate (02) deforms under pressure, the fifth dielectric layer (07) and the third dielectric layer (06) also deform accordingly, adjusting the deformation coefficient of the upper electrode plate (02) and the amount of deformation of the upper electrode plate (02), thereby better improving the linearity of capacitance change and increasing the range of capacitance variation with pressure under the same conditions.

[0096] The third dielectric layer (06) is fabricated on the upper surface and the side surface of the upper electrode plate (02), and at the same time, the third dielectric layer (06) is fabricated on the side surfaces of the first dielectric layer (03) and the lower electrode plate (01). The fifth dielectric layer (07) is fabricated on the third dielectric layer (06), making the seal of the cavity (05) better, improving the airtightness, enhancing the durability of the structure, improving the reliability, and increasing the overload capacity. The third dielectric layer (06) and the fifth dielectric layer (07) provide insulation protection for the upper electrode plate (02) and the lower electrode plate (01), shielding external interference and improving the anti-interference ability, as Figure 25 shown. The third dielectric layer (06) is fabricated on the upper surface and the exposed outer surface of the upper electrode plate (02), and at the same time, the third dielectric layer (06) is fabricated on the exposed outer surface of the lower electrode plate (01). The fifth dielectric layer (07) is fabricated on the third dielectric layer (06) and at the same time, the third dielectric layer (06) is fabricated on the side surface of the first dielectric layer (03), making the seal of the cavity (05) better, improving the airtightness, enhancing the durability of the structure, improving the reliability, and increasing the overload capacity. The fifth dielectric layer (07) provides insulation protection for the upper electrode plate (02) and the lower electrode plate (01), shielding external interference, improving the anti-interference ability, and increasing the overload capacity, as Figure 26 shown. When the substrate (11) is made of an insulating material such as glass, the process steps are simplified, the SOI material is not required, and the cost is significantly reduced.

[0097] When the substrate (11) is selected as a semiconductor material with a conductivity type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a reverse-biased cut-off state, and the lower electrode plate (2) only serves as one electrode plate of the capacitor; when the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a forward-biased state. When the capacitance value is small, the forward voltage of the PN junction has not reached the conduction voltage, the PN junction is in a cut-off state, and no current passes through. The lower electrode plate (01) only serves as one electrode plate of the capacitor. As the upper electrode plate (02) senses pressure and deforms towards the lower electrode plate, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts. At this time, the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the change of the capacitance. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystal silicon oxide layers in the bonding process, and no longer requires SOI materials, saving process steps and greatly reducing costs.

[0098] When the lower electrode plate (01) is selected as a metal material and the substrate (11) is selected as an insulating material, this structure can be manufactured by a deposition process, which simplifies the process steps, does not require SOI materials, and greatly reduces costs.

[0099] When the structure of the present invention is in use, the upper electrode plate (02) can be used as a pressure-sensing electrode plate. The upper electrode plate (02) and the lower electrode plate (01) form a pressure-sensing variable capacitor C1. For the conduction voltage of the PN junction, the capacitance of the PN junction is regarded as capacitor C2 (the capacitance of the PN junction is a barrier capacitance or a diffusion capacitance). C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, saving chip area and improving integration.

[0100] Such as Figure 14As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fifth dielectric layer (07), and a notch (08). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03). The first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The fifth dielectric layer (07) is fabricated on the upper electrode plate (02), and the fifth dielectric layer (07) is made with a notch (08). When the upper electrode plate (02) is deformed under pressure, the fifth dielectric layer (07) also deforms accordingly. The deformation of the upper electrode plate (02) at the notch (08) is larger, which adjusts the deformation coefficient of the upper electrode plate (02) and the amount of deformation of the upper electrode plate (02), thereby better improving the linearity of the capacitance change and increasing the range of capacitance variation with pressure under the same conditions.

[0101] The fifth dielectric layer (07) is fabricated on the upper and side surfaces of the upper electrode plate (02), and at the same time, the fifth dielectric layer (07) is fabricated on the side surfaces of the first dielectric layer (03) and the lower electrode plate (01), making the sealing performance of the cavity (05) better, improving the airtightness, enhancing the durability of the structure, improving the reliability, and increasing the overload capacity. The fifth dielectric layer (07) provides insulation protection for the upper electrode plate (02) and the lower electrode plate (01), shields external interference, and improves the anti-interference ability, as Figure 23 shown.

[0102] The fifth dielectric layer (07) is fabricated on the upper and side surfaces of the upper electrode plate (02), and at the same time, the fifth dielectric layer (07) is fabricated on the side surface of the lower electrode plate (01). The fifth dielectric layer (07) provides insulation protection for the upper electrode plate (02) and the lower electrode plate (01), shields external interference, improves the anti-interference ability, and increases the overload capacity, as Figure 24 shown.

[0103] When the substrate (11) is selected as a semiconductor material with a conductivity type opposite to that of the lower plate (01), for example, when the lower plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower plate (01) and the substrate (11) is in the reverse-biased cut-off state, and the lower plate (2) only serves as one plate of the capacitor; when the lower plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower plate (01) and the substrate (11) is in the forward-biased state. When the capacitance value is small and the forward voltage of the PN junction has not reached the conduction voltage, the PN junction is in the cut-off state and no current passes through. The lower plate (01) only serves as one plate of the capacitor. As the upper plate (02) deforms downward under pressure, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts. At this time, the lower plate (01) is both one plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystalline silicon oxide layers in the bonding process and no longer requires SOI materials, saving process steps and greatly reducing costs.

[0104] When the lower plate (01) is selected as a metal material and the substrate (11) is selected as an insulating material, this structure can be manufactured by a deposition process, which simplifies the process steps, does not require SOI materials, and greatly reduces costs.

[0105] When the structure of the present invention is used, the upper plate (02) can be used as a pressure-sensing plate. The upper plate (02) and the lower plate (01) form a pressure-sensing variable capacitor C1. By applying a voltage to the PN junction and regarding the capacitance of the PN junction as capacitor C2 (the capacitance of the PN junction is a barrier capacitance or a diffusion capacitance), C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, saving chip area and improving integration.

[0106] Such as Figure 15As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fifth dielectric layer (07), a third dielectric layer (06) and a notch (08). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03), and the first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The third dielectric layer (06) is fabricated on the upper electrode plate (02), and the fifth dielectric layer (07) is fabricated on the third dielectric layer (06). The fifth dielectric layer (07) is fabricated with a notch (08). When the upper electrode plate (02) senses pressure and deforms, the dielectric layer (06) and the fifth dielectric layer (07) also deform accordingly. The deformation amount of the upper electrode plate (02) at the notch (08) is large, which adjusts the deformation coefficient of the upper electrode plate (02) and the deformation amount of the upper electrode plate (02), thereby better improving the linearity of capacitance change and increasing the range of capacitance change with pressure under the same conditions. The third dielectric layer (06) is fabricated on the upper surface and the side surface of the upper electrode plate (02), and at the same time, the third dielectric layer (06) is fabricated on the side surface of the first dielectric layer (03) and the lower electrode plate (01). The fifth dielectric layer (07) is fabricated on the third dielectric layer (06), making the sealing performance of the cavity (05) better, improving the airtightness, enhancing the durability of the structure, improving the reliability, and increasing the overload capacity; the third dielectric layer (06) and the fifth dielectric layer (07) provide insulation protection for the upper electrode plate (02) and the lower electrode plate (01), shielding external interference and improving the anti-interference ability, such as Figure 25 shown. The third dielectric layer (06) is fabricated on the upper surface and the exposed outer surface of the upper electrode plate (02), and at the same time, the third dielectric layer (06) is fabricated on the exposed outer surface of the lower electrode plate (01). The fifth dielectric layer (07) is fabricated on the third dielectric layer (06) and at the same time, the third dielectric layer (06) is fabricated on the side surface of the first dielectric layer (03), making the sealing performance of the cavity (05) better, improving the airtightness, enhancing the durability of the structure, improving the reliability, and increasing the overload capacity. The fifth dielectric layer (07) provides insulation protection for the upper electrode plate (02) and the lower electrode plate (01), shielding external interference and improving the anti-interference ability and increasing the overload capacity, such as Figure 26 shown.

[0107] When the substrate (11) is made of a semiconductor material with a conductivity type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in the reverse-biased cut-off state, and the lower electrode plate (2) only serves as one plate of the capacitor; when the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in the forward-biased state. When the capacitance value is small and the forward voltage of the PN junction has not reached the conduction voltage, the PN junction is in the cut-off state and no current passes through. The lower electrode plate (01) only serves as one plate of the capacitor. As the upper electrode plate (02) deforms downward due to the sensed pressure towards the lower electrode plate, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts. At this time, the lower electrode plate (01) is both one plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure during the production process, this structure avoids the process problems of polysilicon and single-crystalline silicon oxide layers during the bonding process and no longer requires SOI materials, saving process steps and significantly reducing costs.

[0108] When the lower electrode plate (01) is made of a metal material and the substrate (11) is made of an insulating material, this structure can be manufactured by a deposition process, which simplifies the process steps, does not require SOI materials, and significantly reduces costs.

[0109] When the structure of the present invention is in use, the upper electrode plate (02) can be used as a pressure-sensing electrode plate. The upper electrode plate (02) and the lower electrode plate (01) form a pressure-sensing variable capacitor C1. By applying a voltage to the PN junction and regarding the capacitance of the PN junction as capacitor C2 (the capacitance of the PN junction is a barrier capacitance or a diffusion capacitance), C1 and C2 form a differential capacitance, thereby more accurately measuring the pressure value to be measured, saving chip area, and improving the integration degree.

[0110] Such as Figure 16As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a substrate (11), a fifth dielectric layer (07), a third dielectric layer (06), and a notch (08). A sealed cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The side wall of the cavity (05) is the first dielectric layer (03), and the first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The third dielectric layer (06) is fabricated on the upper electrode plate (02), and the fifth dielectric layer (07) is fabricated on the third dielectric layer (06). The fifth dielectric layer (07) and the third dielectric layer (06) are made with a notch (08). When the upper electrode plate (02) senses pressure and deforms, the dielectric layer (06) and the fifth dielectric layer (07) also deform accordingly. The deformation amount of the upper electrode plate (02) at the notch (08) is large, which adjusts the deformation coefficient of the upper electrode plate (02) and the deformation amount of the upper electrode plate (02), thereby better improving the linearity of the capacitance change and increasing the range of capacitance change with pressure under the same conditions. The third dielectric layer (06) is fabricated on the upper surface and the side surface of the upper electrode plate (02), and at the same time, the third dielectric layer (06) is fabricated on the side surfaces of the first dielectric layer (03) and the lower electrode plate (01). The fifth dielectric layer (07) is fabricated on the upper surface of the third dielectric layer (06), making the sealing performance of the cavity (05) better, improving the airtightness, enhancing the durability of the structure, improving the reliability, and increasing the overload capacity; the third dielectric layer (06) and the fifth dielectric layer (07) provide insulation protection for the upper electrode plate (02) and the lower electrode plate (01), shielding external interference and improving the anti-interference ability, such as Figure 25 shown in the figure. The third dielectric layer (06) is fabricated on the upper surface and the exposed outer surface of the upper electrode plate (02), and at the same time, the third dielectric layer (06) is fabricated on the exposed outer surface of the lower electrode plate (01). The fifth dielectric layer (07) is fabricated on the upper surface of the third dielectric layer (06) and at the same time, the third dielectric layer (06) is fabricated on the side surface of the first dielectric layer (03), making the sealing performance of the cavity (05) better, improving the airtightness, enhancing the durability of the structure, improving the reliability, and increasing the overload capacity. The fifth dielectric layer (07) provides insulation protection for the upper electrode plate (02) and the lower electrode plate (01), shielding external interference and improving the anti-interference ability and increasing the overload capacity, such as Figure 26 shown in the figure.

[0111] When the substrate (11) is selected as a semiconductor material with a conductivity type opposite to that of the lower plate (01), for example, when the lower plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower plate (01) and the substrate (11) is in the reverse-biased cut-off state, and the lower plate (2) only serves as one plate of the capacitor; when the lower plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower plate (01) and the substrate (11) is in the forward-biased state. When the capacitance value is small, the forward voltage of the PN junction has not reached the conduction voltage, the PN junction is in the cut-off state, and no current passes through. The lower plate (01) only serves as one plate of the capacitor. As the upper plate (02) deforms downward under pressure, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts. At this time, the lower plate (01) is both one plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the change of the capacitance. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystal silicon oxide layers in the bonding process, and no longer requires SOI materials, saving process steps and greatly reducing costs.

[0112] When the lower plate (01) is selected as a metal material and the substrate (11) is selected as an insulating material, this structure can be manufactured by a deposition process, which simplifies the process steps, does not require SOI materials, and greatly reduces costs.

[0113] When the structure of the present invention is used, the upper plate (02) can be used as a pressure-sensing plate. The upper plate (02) and the lower plate (01) form a pressure-sensing variable capacitor C1. By applying a voltage to the PN junction and regarding the capacitance of the PN junction as capacitor C2 (the capacitance of the PN junction is a barrier capacitance or a diffusion capacitance), C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, saving chip area and improving integration.

[0114] Such as Figure 17As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (09), a substrate (11) and a through hole (10). There is a cavity (09) between the upper electrode plate (02) and the lower electrode plate (01) (the unsealed cavity 05 in this figure is called cavity 09). The side wall of the cavity (09) is the first dielectric layer (03). The first dielectric layer (03) serves to support and isolate the upper electrode plate (02) and the lower electrode plate (01). The through hole (10) is fabricated on the first dielectric layer (03), or on the lower electrode plate (01) and the substrate (11). When the through hole (10) is connected to the external air, the pressure inside the cavity (09) is the same as the external air pressure. The upper electrode plate (02) is a pressure-sensitive electrode plate. At this time, the present invention is used as a gauge pressure measurement chip. As the upper electrode plate (02) deforms under pressure, the capacitance value also changes, thereby measuring the pressure value. When the through hole (10) is connected to a first pressure source, the pressure of the cavity (09) is the same as that of the first pressure source through the through hole (10). The upper electrode plate (02) senses the second pressure source. At this time, the chip of the present invention is a differential pressure measurement chip. As the second pressure source changes, the upper electrode plate (02) deforms under pressure, and the capacitance value also changes, thereby measuring the pressure value. When the substrate (11) is selected as an insulating material, such as glass, the process steps are simplified at this time. There is no need for SOI material, and the cost is greatly reduced.

[0115] When the substrate (11) is selected as a semiconductor material with a conductive type opposite to that of the lower electrode plate (01), for example, when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a reverse-biased cut-off state, and the lower electrode plate (2) only serves as one electrode plate of the capacitor; when the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a forward-biased state. When the capacitance value is small, the forward voltage of the PN junction has not reached the conduction voltage, and the PN junction is in a cut-off state, and no current passes through. The lower electrode plate (01) only serves as one electrode plate of the capacitor. As the upper electrode plate (02) deforms downward under pressure, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts. At this time, the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystalline silicon oxide layers in the bonding process, and no longer requires SOI material, saves the process steps, and greatly reduces the cost.

[0116] When the lower electrode plate (01) is made of a metal material and the substrate (11) is made of an insulating material, this structure can be fabricated by a deposition process, which simplifies the process steps, does not require SOI materials, and significantly reduces costs.

[0117] When the structure of the present invention is in use, the upper electrode plate (02) can be used as a pressure-sensitive electrode plate. The upper electrode plate (02) and the lower electrode plate (01) form a pressure-sensitive variable capacitor C1. A voltage is applied to the PN junction, and the PN junction capacitance is regarded as capacitor C2 (the capacitance of the PN junction is the barrier capacitance or the diffusion capacitance). C1 and C2 form a differential capacitance, so as to more accurately measure the pressure value to be measured, saving chip area and improving integration.

[0118] As Figure 18 、 Figure 19 shown, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a first dielectric layer (03), a cavity (05), a cavity (09), a substrate (11), and a through hole (10). Two capacitor structures, capacitor C1 and capacitor C2, are arranged on the substrate (11). The lower electrode plates (01) of capacitor C1 and C2 are arranged on the substrate (11). The lower electrode plates (01) of capacitor C1 and C2 are connected, or the upper electrode plates (02) of capacitor C1 and C2 are connected. A first dielectric layer (03) is arranged above the lower electrode plate (01), and an upper electrode plate (02) is arranged on the first dielectric layer (03). The upper electrode plate (02) of capacitor C1, the lower electrode plate (01), and the first dielectric layer (03) form a cavity (05). The upper electrode plate (02) of capacitor C2, the lower electrode plate (01), and the first dielectric layer (03) form a cavity (09). The through hole (10) of capacitor C2 is connected to the cavity (09). The through hole (10) is arranged on the first dielectric layer (03), or on the lower electrode plate (01) and the substrate (11), or on the upper electrode plate (02). The side walls of the cavity (05) and the cavity (09) are the first dielectric layer (03). The first dielectric layer (03) serves as a support and isolates the upper electrode plate (02) and the lower electrode plate (01). The upper electrode plate (02) of capacitor C1 is a pressure-sensitive electrode plate. When the pressure changes, the upper electrode plate (02) of capacitor C1 deforms with the pressure change, so that the capacitance value of capacitor C1 changes with the pressure change. The through hole (10) is connected to the external air, and the pressure inside the cavity (09) is the same as the external air pressure. The upper electrode plate (02) of capacitor C2 is a pressure-sensitive electrode plate and does not deform with the air pressure change, so that the capacitance value of capacitor C2 remains unchanged. Capacitor C1 and capacitor C2 form a differential capacitance, which can well shield the common-mode interference, so as to more accurately measure the pressure value to be measured, improve the accuracy, enhance the anti-interference ability, save chip area, and improve integration.

[0119] When the substrate (11) is made of an insulating material, such as glass, the process steps are simplified at this time, SOI materials are not required, and the material cost is significantly reduced.

[0120] When the substrate (11) is made of a semiconductor material with a conductivity type opposite to that of the lower electrode plate (01), when the lower electrode plate (01) is N-type doped, the substrate (11) is P-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a reverse-biased cut-off state, and the lower electrode plate (2) only serves as one electrode plate of the capacitor; when the lower electrode plate (01) is P-type doped, the substrate (11) is N-type doped, and the lower electrode plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower electrode plate (01) and the substrate (11) is in a forward-biased state. When the capacitance value of the capacitor C1 is small, the forward voltage of the PN junction does not reach the conduction voltage, the PN junction is in a cut-off state, and no current passes through. The lower electrode plate (01) only serves as one electrode plate of the capacitor. As the upper electrode plate (02) senses pressure and deforms towards the lower electrode plate, the capacitance increases and the voltage increases. When the voltage increases with the capacitance to the conduction voltage of the PN junction, the PN junction conducts. At this time, the lower electrode plate (01) is both one electrode plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystalline silicon oxide layers in the bonding process, and no longer requires SOI materials, saving process steps and greatly reducing costs.

[0121] When the lower electrode plate (01) is made of a metal material and the substrate (11) is made of an insulating material, this structure can be manufactured by a deposition process, and the process steps are simplified, no SOI material is required, and the material cost is greatly reduced.

[0122] As Figures 20 - 22 shown, as Figure 20 、 Figure 21 、 Figure 22As shown in the figure, the present invention includes a lower electrode plate (01), an upper electrode plate (02), a dielectric layer (03), a cavity (05), a cavity (09), a substrate (11), and a through hole (10). Four capacitor structures, namely capacitor C1, capacitor C2, capacitor C3, and capacitor C4, are arranged on the substrate (11). The lower electrode plates (01) of capacitors C1, C2, C3, and C4 are arranged on the substrate (11). A dielectric layer (03) is arranged above the lower electrode plate (01). An upper electrode plate (02) is arranged on the dielectric layer (03). The upper electrode plate (02), the lower electrode plate (01), and the dielectric layer (03) form a cavity (05) and a cavity (09) connected to the through hole (10). The through hole (10) is arranged on the dielectric layer (03), or on the lower electrode plate (01) and the substrate (11), or on the upper electrode plate (02). Among them, the through holes (10) of two capacitors are respectively capacitor C1 and C4, and the middle two capacitors without through holes are C2 and C3. The upper electrode plates (02) of capacitor C1 and C2 are connected, the upper electrode plates (02) of capacitor C3 and C4 are connected, the lower electrode plates (01) of capacitor C1 and C3 are connected by a metal lead, the lower electrode plates (01) of capacitor C2 and C4 are connected. The four capacitors form a capacitive bridge circuit, which can well shield the common-mode interference, increase the capacitance change amount, improve the sensitivity, thereby more accurately measure the pressure value to be measured, improve the accuracy, enhance the anti-interference ability, save the chip area, and improve the integration degree.

[0123] The lower electrode plate (01) of the structure of the present invention is as Figure 21 shown, and the upper electrode plate (02) is as Figure 22 shown. This connection method greatly simplifies the manufacturing process steps of the metal wiring, avoids the problems of short circuit and open circuit, and reduces the process cost.

[0124] As Figure 21 shown, a first lower support (13) is arranged between the lower electrode plate (01) of capacitor C1 and the lower electrode plate (01) of C2, and a second lower support (14) is arranged between the lower electrode plate (01) of capacitor C3 and the lower electrode plate (01) of C4;

[0125] As Figure 22 shown, a first part (15) of the upper electrode plate (02) is arranged between the upper electrode plate (02) of C1 and the upper electrode plate (02) of C2 corresponding to the first lower support (13), and a second part (16) of the upper electrode plate (02) is arranged between the upper electrode plate (02) of C3 and the upper electrode plate (02) of C4 corresponding to the second lower support (14).

[0126] Through the corresponding arrangement of the first lower support (13), the first part (15) of the upper electrode plate (02), the second lower support (14), and the second part (16) of the upper electrode plate (02), the open circuit or short circuit caused in the metal lead due to the height difference between the substrate, the lower electrode plate, and the upper electrode plate is avoided.

[0127] When the substrate (11) selects an insulating material such as glass, the process steps are simplified, the SOI material is not required, and the material cost is greatly reduced.

[0128] When the substrate (11) selects a semiconductor material of a conductivity type opposite to that of the lower plate (01), when the lower plate (01) is N-type doped, the substrate (11) is P-type doped. The lower plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower plate (01) and the substrate (11) is in a reverse-biased cut-off state, and the lower plate (2) only serves as one plate of the capacitor. When the lower plate (01) is P-type doped, the substrate (11) is N-type doped. The lower plate (01) and the substrate (11) are connected to electrical signals with opposite polarities, so that the PN junction between the lower plate (01) and the substrate (11) is in a forward-biased state. When the capacitance values of the first group of capacitors C2 and the second group of capacitors C1 are small, the forward voltage of the PN junction does not reach the conduction voltage, the PN junction is in a cut-off state, and no current passes between them. The lower plate (01) only serves as one plate of the capacitor. As the upper plate (02) deforms downward under pressure, the capacitance increases and the voltage increases. When the voltage increases to the conduction voltage of the PN junction as the capacitance increases, the PN junction conducts. At this time, the lower plate (01) is both one plate of the capacitor and the P region of the PN junction. This structure reduces the complexity of the circuit system, and the pressure source directly controls the working state of the PN junction through the capacitance change. Compared with the ordinary capacitor structure in the production process, this structure avoids the process problems of polysilicon and single-crystalline silicon oxide layers in the bonding process, no longer requires SOI materials, saves process steps, and greatly reduces costs.

[0129] When the lower plate (01) selects a metal material and the substrate (11) selects an insulating material, this structure can be manufactured by a deposition process, the process steps are simplified, the SOI material is not required, and the material cost is greatly reduced.

[0130] Such as Figure 27 shown, according to Figure 2 the structure shown, the sizes of the upper and lower plates are squares of 40um * 40um, the film thickness is 0.5um, and the capacitance-pressure output characteristic diagram shown in Figure 27 is obtained by using a finite element simulation software. The abscissa is the pressure value, and the ordinate is the output capacitance value. It can be seen from the figure that the linearity of the output characteristic curve diagram is very good.

[0131] Such as Figure 28 shown, according to Figure 2 the structure shown, the sizes of the upper and lower plates are squares of 40um * 40um, the film thickness is 0.5um, and the capacitance-pressure output characteristic diagram shown in Figure 28 is obtained by using a finite element simulation software. The abscissa is the pressure value, and the ordinate is the output capacitance value. It can be seen from the figure that the linearity of the output characteristic curve diagram is very good and the capacitance change amount increases.

[0132] The manufacturing method of the junction capacitance type chip of the present invention is as follows:

[0133] a. Bond the silicon wafer A to a glass substrate (or semiconductor material).

[0134] b. Thin the silicon wafer A to the required thickness, and form an oxide layer (i.e., the first dielectric layer (03), and the rest is etched away).

[0135] The oxide layer is formed by dry oxygen (or dry-wet-dry) method.

[0136] c. Photolithograph the pattern and etch the cavity (05).

[0137] When the wet etching process is selected for the etching process, a hydrofluoric acid HF ratio solution is selected and a catalyst is added to ensure the etching rate and reduce undercutting; when the dry etching process is selected, a suitable plasma is selected for etching, and at the same time, the bias voltage of the deep reactive ion etching machine needs to be adjusted, and the flow rate of the gas introduced is adjusted to achieve a better etching effect.

[0138] d. Select a new silicon wafer B and bond it to the oxide layer on the lower electrode plate.

[0139] e. Thin the bonded silicon wafer B to the required thickness. Bonding process: perform hydrophilic treatment, then perform room temperature pre-bonding, and then perform detection. Use infrared technology to detect bonding defects, and the minimum size of the detected defects can reach 3um, and then perform annealing, and the annealing temperature is 400 degrees Celsius or high temperature annealing at 1100 degrees Celsius.

[0140] f. Photolithograph the pattern and etch the shape of the upper electrode plate.

[0141] g. Photolithograph the pattern and etch the shape of the lower electrode plate.

[0142] h. Photolithograph the pattern and make lead holes.

[0143] i. Photolithograph the pattern and make aluminum leads.

[0144] j. Photolithograph the pattern and etch out the PAD.

[0145] k. Cut the wafer.

[0146] When the structure of the present invention is in use, a substance whose dielectric constant changes with temperature can be arranged in the cavity (05). This substance is connected to the outside and can be used as a detection component of a thermometer.

[0147] The present invention can be applied to pressure detection, automatic control switches, automatic control rectification, silicon microphones, hygrometers, accelerometers, flow meters, etc.

[0148] It is understandable that the above specific description of the present invention is only for the purpose of illustrating the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those of ordinary skill in the art should understand that the present invention can still be modified or equivalently replaced to achieve the same technical effects; as long as the usage requirements are met, they are all within the protection scope of the present invention.

Claims

1. A capacitive chip structure includes an upper electrode plate (02), a lower electrode plate (01) and a substrate (11). The lower electrode plate (01) is disposed on the substrate (11). A cavity (05) is formed between the upper electrode plate (02) and the lower electrode plate (01). The periphery between the upper electrode plate (02) and the lower electrode plate (01) is connected by a first dielectric layer (03), and the first dielectric layer (03) serves as the side wall of the cavity (05). It is characterized in that the upper electrode plate (02) is a pressure - sensitive electrode plate, and a pressure - sensitive variable capacitor is formed between the upper electrode plate (02) and the lower electrode plate (01).

2. The capacitive chip structure according to claim 1, It is characterized in that a second dielectric layer (04) is disposed at the upper end of the lower electrode plate (01), and the thickness of the second dielectric layer (04) is less than the thickness of the first dielectric layer (03); or a second dielectric layer (04) is disposed at the lower end of the upper electrode plate (02), and the thickness of the second dielectric layer (04) is less than the thickness of the first dielectric layer (03).

3. The capacitive chip structure according to claim 1, It is characterized in that a second dielectric layer (04) is disposed at the upper end of the lower electrode plate (01), and a third dielectric layer (06) is disposed at the upper end of the second dielectric layer (04). The sum of the thicknesses of the third dielectric layer (06) and the second dielectric layer (04) is less than the thickness of the first dielectric layer (03); or a second dielectric layer (04) is disposed at the upper end of the lower electrode plate (01), and a third dielectric layer (06) is disposed at the lower end of the upper electrode plate (02). The sum of the thicknesses of the third dielectric layer (06) and the second dielectric layer (04) is less than the thickness of the first dielectric layer (03).

4. The capacitive chip structure according to claim 1, It is characterized in that a fourth dielectric layer (12) is disposed between the lower electrode plate (01) and the substrate (11).

5. The capacitive chip structure according to claim 4, It is characterized in that a second dielectric layer (04) is disposed at the upper end of the lower electrode plate (01), and the thickness of the second dielectric layer (04) is less than the thickness of the first dielectric layer (03); or a second dielectric layer (04) is disposed at the lower end of the upper electrode plate (02), and the thickness of the second dielectric layer (04) is less than the thickness of the first dielectric layer (03).

6. The capacitive chip structure according to claim 4, It is characterized in that a second dielectric layer (04) is disposed at the upper end of the lower electrode plate (01), and a third dielectric layer (06) is disposed at the lower end of the upper electrode plate (02). The sum of the thicknesses of the third dielectric layer (06) and the second dielectric layer (04) is less than the thickness of the first dielectric layer (03); or a second dielectric layer (04) is disposed at the upper end of the lower electrode plate (01), and a third dielectric layer (06) is disposed at the upper end of the second dielectric layer (04). The sum of the thicknesses of the third dielectric layer (06) and the second dielectric layer (04) is less than the thickness of the first dielectric layer (03).

7. The capacitive chip structure according to claim 1, It is characterized in that a fifth dielectric layer (07) is disposed at the upper end of the upper electrode plate (02); or a fifth dielectric layer (07) is disposed at the upper end of the upper electrode plate (02), and a second dielectric layer (04) is disposed at the upper end of the lower electrode plate (01), and the thickness of the second dielectric layer (04) is less than that of the first dielectric layer (03); Or a fifth dielectric layer (07) is provided at the upper end of the upper electrode plate (02), and a third dielectric layer (06) is provided between the upper electrode plate (02) and the fifth dielectric layer (07).

8. The capacitive chip structure according to claim 7, wherein the fifth dielectric layer (07) is provided on the upper surface and the side surface of the upper electrode plate (02); the fifth dielectric layer (07) is further provided on the side surface of the first dielectric layer (03) and the lower electrode plate (01) or the fifth dielectric layer (07) is further provided on the side surface of the lower electrode plate (01).

9. The capacitive chip structure according to claim 7, wherein a notch (08) is provided in the middle of the fifth dielectric layer (07); or a notch (08) is provided in the middle of the fifth dielectric layer (07) and the third dielectric layer (06).

10. The capacitive chip structure according to claim 1, wherein a through hole (10) for communicating the cavity (05) with the outside is provided on the first dielectric layer (03) or on the lower electrode plate (01) and the substrate (11) or on the upper electrode plate (02).

11. A capacitive chip structure, wherein a capacitor C1 and a capacitor C2 are provided on a substrate (11), the lower electrode plates (01) of the capacitor C1 and the capacitor C2 are provided on the substrate (11), the lower electrode plates (01) of the capacitor C1 and the capacitor C2 are connected and / or the upper electrode plates (02) of the capacitor C1 and the capacitor C2 are connected; the capacitor C1 and the capacitor C2 include an upper electrode plate (02) and a lower electrode plate (01), a cavity (05) is between the upper electrode plate (02) and the lower electrode plate (01), and the periphery between the upper electrode plate (02) and the lower electrode plate (01) is connected by a first dielectric layer (03); a through hole (10) for communicating the cavity (05) with the outside is provided on the first dielectric layer (03) of the capacitor C2 or on the lower electrode plate (01) and the substrate (11) or on the upper electrode plate (02).

12. A capacitive chip structure, wherein four capacitor structures, namely a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4, are provided on a substrate (11), the lower electrode plates (01) of the capacitor C1, C2, C3 and C4 are provided on the substrate (11), a dielectric layer (03) is provided above the lower electrode plates (01), an upper electrode plate (02) is provided on the dielectric layer (03), the upper electrode plate (02), the lower electrode plate (01) and the dielectric layer (03) form a cavity (05) and a cavity (09) connected to a through hole (10), the through hole (10) is provided on the dielectric layer (03) or on the lower electrode plate (01) and the substrate (11) or on the upper electrode plate (02), and two of the capacitors are provided with through holes (10); the four capacitors are divided into two groups, one capacitor with a through hole (10) and one capacitor without a through hole (10) are in one group, and the upper electrode plates (02) of the two capacitors in each group are connected respectively; then the four capacitors are re-divided into two groups, one capacitor with a through hole (10) and one capacitor without a through hole (10) and whose upper electrode plate (02) is not connected are in one group, and the lower electrode plates (01) of the two capacitors in each group are connected respectively.

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