Method for testing semiconductor electrical characteristics and testing device for semiconductor electrical characteristics

Abstract

The application provides a semiconductor electrical property testing method and testing device. The method comprises: obtaining a semiconductor micro-Hall testing structure comprising at least one doping element; measuring the electrical parameter of the testing structure; removing a thin layer with a specific thickness from the testing structure by secondary ion mass spectrometry, and performing atomic composition analysis on the removed material; again measuring the electrical parameter of the testing structure; repeating the two steps until the distribution information of the doping concentration of the active doping element and the initial doping element in the testing structure is obtained, and calculating the distribution information of the doping efficiency of the testing structure according to the distribution information of the doping concentration. The application can combine the electrical property with the doping concentration, obtain the distribution information of the semiconductor electrical property and the doping concentration, deduce the distribution of the doping efficiency, and remove the thin layer controllably by the secondary ion mass spectrometry technology, so that the semiconductor doping profile information with higher precision is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a semiconductor electrical property testing method and a semiconductor electrical property testing device. BACKGROUND

[0002] The selectively grown semiconductor has electrical properties related to depth and varies with depth, and these depth-dependent electrical properties have a great impact on the performance of electronic devices. In the prior art, Hall effect is usually used to measure the derived semiconductor type, total free carrier density and total mobility, and the doping profile of the semiconductor is obtained by etching a cross-section (such as cross-sectional SEM / TEM). However, the depth-based electrical properties cannot be correlated with the doping profile, and thus the influence of the doping profile at different depths on the electrical properties of the semiconductor cannot be further analyzed. SUMMARY

[0003] Therefore, the embodiments of the present application aim to provide a semiconductor electrical property testing method and a semiconductor electrical property testing device to solve the problem that the electrical properties of the semiconductor cannot be analyzed based on the doping profile at different depths in the prior art.

[0004] In one aspect, the present application provides a semiconductor electrical property testing method, comprising: S100, obtaining a semiconductor micro-Hall testing structure, the semiconductor micro-Hall testing structure comprising at least one doping element; S200, measuring the electrical parameters of the semiconductor micro-Hall testing structure and obtaining the doping concentration of the active doping element in the semiconductor micro-Hall testing structure; S300, removing a thin layer of a specific thickness from the semiconductor micro-Hall testing structure by secondary ion mass spectrometry, analyzing the atomic composition of the removed material, and obtaining the doping concentration of the initial doping element in the thin layer of the semiconductor micro-Hall testing structure; S400, after removing the thin layer of the specific thickness, measuring the electrical parameters of the semiconductor micro-Hall testing structure again, and obtaining the doping concentration of the active doping element in the semiconductor micro-Hall testing structure, wherein the change in the doping concentration of the active doping element in the semiconductor micro-Hall testing structure obtained before and after removing the thin layer can obtain the doping concentration of the active doping element in the thin layer of the semiconductor micro-Hall testing structure; repeating steps S300 and S400 until the distribution information of the electrical parameters, the doping concentration of the initial doping element, and the doping concentration of the active doping element in the semiconductor micro-Hall testing structure in the thickness direction is obtained, and calculating the distribution information of the doping efficiency of the semiconductor micro-Hall testing structure according to the distribution information of the doping concentration of the active doping element and the doping concentration of the initial doping element.

[0005] In some implementations of the first aspect, the semiconductor micro-Hall test structure includes: a center region located at the intersection of a first axis and a second axis of the semiconductor micro-Hall test structure, the first axis and the second axis being perpendicular to each other; two pairs of arms extending from the center region, one pair of arms being symmetric with respect to the first axis and the other pair of arms being symmetric with respect to the second axis; and pads located at the end points of the arms away from the center region.

[0006] In some implementations of the first aspect, the width of the arms is less than or equal to 2.8 mm.

[0007] In some implementations of the first aspect, determining the electrical parameters of the semiconductor micro-Hall test structure includes: applying a current to two adjacent arms of the semiconductor micro-Hall test structure through the pads, measuring the voltage between the other two adjacent arms of the semiconductor micro-Hall test structure to calculate the resistivity of the semiconductor micro-Hall test structure; and applying a current to two non-adjacent arms of the semiconductor micro-Hall test structure through the pads when a magnetic field perpendicular to the plane of the semiconductor micro-Hall test structure is applied, measuring the change in voltage between the other two non-adjacent arms of the semiconductor micro-Hall test structure to measure the carrier concentration and the carrier mobility of the semiconductor micro-Hall test structure.

[0008] In some implementations of the first aspect, the semiconductor micro-Hall test structure includes: a center region located at the intersection of a first axis and a second axis of the semiconductor micro-Hall test structure, the first axis and the second axis being perpendicular to each other; two pairs of arms extending from the center region, one pair of arms being symmetric with respect to the first axis and the other pair of arms being symmetric with respect to the second axis; and pads located at the end points of the arms away from the center region.

[0009] In some implementations of the first aspect, the width of the arms is less than or equal to 0.5 mm.

[0010] In some implementations of the first aspect, determining the electrical parameters of the semiconductor micro-Hall test structure includes: applying a current to two arms symmetric with respect to the first axis through the pads, measuring the voltage between two arms on the same side of the second axis among the other four arms to calculate the resistivity of the semiconductor micro-Hall test structure; and applying a current to two arms symmetric with respect to the first axis through the pads when a magnetic field perpendicular to the plane of the semiconductor micro-Hall test structure is applied, measuring the change in voltage between any two arms symmetric with respect to the second axis among the other four arms to measure the carrier type, the carrier concentration, and the carrier mobility.

[0011] In some implementations of the first aspect, the semiconductor micro-Hall test structure includes a selectively grown semiconductor structure.

[0012] With reference to the first aspect, in some implementations of the first aspect, the material of the semiconductor micro-Hall test structure includes a GaN-based material.

[0013] With reference to the first aspect, in some implementations of the first aspect, the material of the semiconductor micro-Hall test structure includes a P-type GaN, and the doping element includes at least one of Mg element, Zn element, Ca element, Sr element, Ba element, Li element, Na element or K element.

[0014] With reference to the first aspect, in some implementations of the first aspect, the material of the semiconductor micro-Hall test structure includes a PN junction material.

[0015] With reference to the first aspect, in some implementations of the first aspect, the P-type doping element in the PN junction material includes at least one of Mg element, Zn element, Ca element, Sr element, Ba element, Li element, Na element or K element, and the N-type doping element includes at least one of Si element, Ge element, Sn element, Se element or Te element.

[0016] With reference to the first aspect, in some implementations of the first aspect, the determining the electrical parameter of the semiconductor micro-Hall test structure further includes: applying an alternating magnetic field perpendicular to the plane where the semiconductor micro-Hall test structure is located to measure the electron mobility and the hole mobility of the semiconductor micro-Hall test structure.

[0017] With reference to the first aspect, in some implementations of the first aspect, in the removing the thin layer with a specific thickness from the semiconductor micro-Hall test structure layer by layer by using the secondary ion mass spectrometry, the etching range is a circular area with the center area as the center and a maximum diameter less than or equal to 4 mm.

[0018] With reference to the first aspect, in some implementations of the first aspect, the secondary ion mass spectrometry includes Glow Dischange Spectrometry-Secondary Ion Mass Spectroscopy (GDS-SIMS) or Time of Flight Secondary Ion Mass Spectrometry (TOF-SIMS).

[0019] With reference to the first aspect, in some implementations of the first aspect, in the removing the thin layer with a specific thickness from the semiconductor micro-Hall test structure layer by layer by using the secondary ion mass spectrometry, the specific thickness is a fixed thickness, and the fixed thickness is less than or equal to 100 nm.

[0020] In a second aspect, the application provides a device for testing semiconductor electrical characteristics, comprising: an acquisition module configured to acquire a selectively grown semiconductor micro-Hall test structure, the semiconductor micro-Hall test structure comprising at least one doping element; an electrical testing module configured to determine electrical parameters of the semiconductor micro-Hall test structure and obtain a doping concentration of active doping elements in the semiconductor micro-Hall test structure; an element analysis module configured to remove a thin layer of a specific thickness from the semiconductor micro-Hall test structure using secondary ion mass spectrometry, perform atomic composition analysis on the removed material, and obtain a doping concentration of initial doping elements in the thin layer of the semiconductor micro-Hall test structure; and a calculation module configured to calculate distribution information of doping efficiency of the semiconductor micro-Hall test structure based on the doping concentration of the active doping elements and the distribution information of the doping concentration of the initial doping elements; wherein the electrical testing module and the element analysis module are configured to be repeatedly executed until the distribution information of the electrical parameters of the semiconductor micro-Hall test structure, the doping concentration of the initial doping elements, and the doping concentration of the active doping elements are obtained.

[0021] The device for testing semiconductor electrical characteristics provided by the embodiments of the application can combine electrical characteristics and doping concentration, obtain distribution information of semiconductor electrical characteristics and doping concentration, deduce distribution of doping efficiency, and controllably remove a thin layer using secondary ion mass spectrometry, thereby obtaining more accurate semiconductor doping profile information. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and other objects, features and advantages of the application will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. The drawings provided herein are for illustrative purposes only and, therefore, do not limit the present application. In the drawings:

[0023] Figure 1 Fig. 1 shows a flowchart of a method for testing semiconductor electrical characteristics according to an embodiment of the application.

[0024] Figure 2 Fig. 2 shows a structure diagram of a semiconductor micro-Hall test structure according to an embodiment of the application.

[0025] Figure 3 Fig. 3 shows a structure diagram of a semiconductor micro-Hall test structure according to another embodiment of the application.

[0026] Figure 4 Fig. 4 shows a flowchart of a method for testing semiconductor electrical characteristics according to another embodiment of the application.

[0027] Figure 5Fig. 1 shows a flowchart of a method for testing semiconductor electrical characteristics according to an embodiment of the present application.

[0028] Figure 6 Fig. 2 shows a flowchart of a method for testing semiconductor electrical characteristics according to another embodiment of the present application.

[0029] Figure 7 Fig. 3 shows a structural diagram of a testing device for testing semiconductor electrical characteristics according to an embodiment of the present application.

[0030] Figure 8 Fig. 4 shows a structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0032] Summary of the application

[0033] The basic idea of the present application is to provide a semiconductor electrical characteristic testing method and a testing device to solve the problem that the electrical characteristics of a semiconductor cannot be analyzed based on different doping profiles in the prior art.

[0034] The electrical characteristics of a semiconductor are related to the doping depth and the doping concentration distribution of the semiconductor. The prior art cannot specifically test the relationship between the doping concentration distribution of the semiconductor thin layer and the electrical characteristic distribution. In the prior art, the doping concentration distribution of the semiconductor thin layer is usually analyzed by a destructive method, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), etc., but the electrical activation is not required. Therefore, the electrical parameters and the electrical characteristics of the semiconductor related to the doping concentration cannot be accurately obtained.

[0035] Secondary Ion Mass Spectroscopy (SIMS) can detect very low concentration of doping and impurities, and can also provide element depth distribution in the range from several nanometers to tens of microns. Ions with certain energy hitting the surface of solid will cause secondary emission of surface atoms, molecules or atomic groups, i.e. ion sputtering. The sputtered particles are generally neutral, some of which have positive or negative charges, which are secondary ions. The secondary ions are analyzed by using a mass analyzer to obtain secondary ion mass spectrum. SIMS has very high sensitivity.

[0036] The semiconductor electrical property testing method provided by the application comprises the following steps: obtaining a semiconductor micro-Hall testing structure comprising at least one doping element; measuring electrical parameters of the semiconductor micro-Hall testing structure; removing a thin layer with a certain thickness from the semiconductor micro-Hall testing structure layer by layer by using SIMS, and performing atomic composition analysis on the removed material; measuring the electrical parameters of the semiconductor micro-Hall testing structure again; repeating the above two steps until the distribution information of the doping concentration of the active doping element and the initial doping element in the semiconductor micro-Hall testing structure is obtained, and calculating the distribution information of the doping efficiency of the semiconductor micro-Hall testing structure according to the distribution information of the doping concentration.

[0037] The various non-limiting embodiments of the application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the application, and are not all the embodiments of the application. It should be understood that the application is not limited by the example embodiments described herein.

[0038] Exemplary methods

[0039] Figure 1 The semiconductor micro-Hall testing method provided by the embodiment of the application is shown in the flowchart. As shown in the figure, Figure 1 The semiconductor micro-Hall testing method provided by the embodiment of the application comprises the following steps.

[0040] Step S100: obtaining a semiconductor micro-Hall testing structure, the semiconductor micro-Hall testing structure comprising at least one doping element.

[0041] Specifically, the semiconductor micro-Hall test structure is disposed on a substrate. The substrate material can be an insulating material or a high-impedance material with a resistivity higher than a preset threshold value, which can be set according to a specific experimental material, and the application does not limit this. Alternatively, the substrate material can also be a material opposite in electrical properties to the semiconductor micro-Hall test structure being tested. The material of the semiconductor micro-Hall test structure is a material with a doping profile, including a GaN-based material. When the material of the semiconductor micro-Hall test structure is P-type GaN, the doping elements include at least one of Mg, Zn, Ca, Sr, Ba, Li, Na or K. Optionally, the material of the semiconductor micro-Hall test structure includes PN junction material, and the P-type doping elements in the PN junction material include at least one of Mg, Zn, Ca, Sr, Ba, Li, Na or K, and the N-type doping elements include at least one of Si, Ge, Sn, Se or Te. The above doping elements are all gallium substitutes in the GaN material, avoiding excessive doping to cause nitrogen substitution in the GaN material, resulting in a decrease in the concentration of electrons in N-type doping or holes in P-type doping. The material of the semiconductor micro-Hall test structure can also be a compensating doped material (a material including both P-type doping and N-type doping). The semiconductor micro-Hall test structure can also be an island-shaped isolated or trench-isolated semiconductor structure after etching, a super-junction device or a selectively grown semiconductor structure. The semiconductor micro-Hall test structure provided by the embodiments of the application can be prepared from a scribe line between a wafer grain array or from a grain in the grain array. Therefore, the semiconductor micro-Hall test structure provided by the embodiments of the application has the same electrical parameter distribution information as the grains on the wafer in depth. The parameter distribution of the semiconductor micro-Hall test structure is tested, and the parameter distribution of the grains on the wafer can be obtained.

[0042] The semiconductor micro-Hall test structure includes: a central region located at the intersection of a first axis and a second axis of the semiconductor micro-Hall test structure, the first axis and the second axis being perpendicular to each other; two arms symmetrical to the first axis and two arms symmetrical to the second axis extending from the central region; and pads located at the end points of the arms away from the central region; wherein the width of the arm is less than or equal to 2.8 mm.

[0043] Exemplarily, Figure 2 The semiconductor micro-Hall test structure provided by an embodiment of the application is like Figure 2As shown, the semiconductor micro-Hall test structure includes: a center region 10 located at the intersection of a first axis and a second axis of the semiconductor micro-Hall test structure, the first axis and the second axis being perpendicular to each other; two arms 31 and 33 symmetric to the first axis and two arms 32 and 34 symmetric to the second axis extending from the center region 10; and pads 21, 22, 23 and 24 located at the end points of the arms away from the center region 10. The width of each arm is less than or equal to 2.8 mm.

[0044] According to another embodiment provided by the present application, the semiconductor micro-Hall test structure includes: a center region located at the intersection of a first axis and a second axis of the semiconductor micro-Hall test structure, the first axis and the second axis being perpendicular to each other; two arms symmetric to the first axis and four arms symmetric to each other extending from the center region; and pads located at the end points of the arms away from the center region; wherein the width of each arm is less than or equal to 0.5 mm.

[0045] Exemplarily, Figure 3 The semiconductor micro-Hall test structure provided by another embodiment of the present application includes: Figure 3 As shown, the semiconductor micro-Hall test structure provided by another embodiment of the present application includes: a center region 12 located at the intersection of a first axis and a second axis of the semiconductor micro-Hall test structure, the first axis and the second axis being perpendicular to each other; two arms 51 and 52 symmetric to the first axis and four arms 53, 54, 55 and 56 symmetric to each other extending from the center region 12; and pads 41, 42, 43, 44, 45 and 46 located at the end points of the arms away from the center region 12; wherein the width of each arm is less than or equal to 0.5 mm.

[0046] Step S200: measuring the electrical parameters of the semiconductor micro-Hall test structure and obtaining the doping concentration of the active doping element in the semiconductor micro-Hall test structure.

[0047] Specifically, the semiconductor micro-Hall test structure is applied with current and magnetic field to measure the resistivity, Hall coefficient and carrier mobility of the measured semiconductor micro-Hall test structure; and the carrier concentration, i.e. the doping concentration, is calculated from the carrier mobility. For example, the doping concentration of Mg ions doped in P-type GaN material.

[0048] The resistivity of the semiconductor material can be measured by Van der Pauw method. The Hall coefficient can be obtained by the formula RH=(V H ×d) / (I×B), wherein V H represents the Hall coefficient, d represents the thickness of the measured semiconductor micro-Hall test structure, V HWhere RH represents the Hall voltage, I represents the current intensity, and B represents the magnetic field intensity. Through the formula, the Hall coefficient can be calculated.

[0049] In addition, the conductivity σ can be measured by Van Der Pauw, Eddy current Testing or microwave reflection method, and the carrier mobility μ is further obtained, i.e. the carrier mobility μ is obtained by the formula σ = μ / |RH|. According to the related formula of the carrier concentration: n = σ / (e x μ), the carrier concentration n can be obtained in combination with the carrier mobility μ and the conductivity σ obtained by the foregoing method.

[0050] Step S300: removing a thin layer with a specific thickness from the semiconductor micro-Hall test structure by secondary ion mass spectrometry, analyzing the atomic composition of the removed material, and obtaining the doping concentration of the initial doping element in the thin layer of the semiconductor micro-Hall test structure.

[0051] Specifically, the secondary ion mass spectrometry can be used to remove the semiconductor thin layer with controllable thickness. The atomic composition of the removed thin layer is analyzed each time the thin layer is removed, and the doping concentration of the initial doping element in the thin layer of the semiconductor micro-Hall test structure is obtained.

[0052] Step S400: After removing the thin layer with a specific thickness, the electrical parameters of the semiconductor micro-Hall test structure are measured again, and the doping concentration of the active doping element in the semiconductor micro-Hall test structure is obtained. The change of the doping concentration of the active doping element in the semiconductor micro-Hall test structure obtained before and after removing the thin layer can obtain the doping concentration of the active doping element in the thin layer of the semiconductor micro-Hall test structure.

[0053] After each layer of thin layer with a fixed thickness is removed, the electrical parameters of the semiconductor micro-Hall test structure are measured again to obtain the doping concentration of the active doping element in the semiconductor micro-Hall test structure at the current thickness.

[0054] Steps S300 and S400 are repeatedly executed until the distribution information of the electrical parameters, the doping concentration of the initial doping element, and the doping concentration of the active doping element of the semiconductor micro-Hall test structure in the thickness direction are obtained, and the distribution information of the doping efficiency of the semiconductor micro-Hall test structure is calculated according to the distribution information of the doping concentration of the active doping element and the doping concentration of the initial doping element.

[0055] Specifically, according to the above steps, with respect to the electrical parameter measurement result before the thin layer is removed each time, the carrier concentration change of the current and previous semiconductor can be obtained by comparing the change of the current electrical parameter measurement result and the previous electrical parameter measurement result, so as to obtain the carrier concentration of the removed thin layer, and the concentration of the active dopant of the thin layer is calculated. Further, the concentration of the initial input dopant can be calculated in combination with the atomic composition information. Therefore, the doping efficiency (percentage of active doping) of the measured semiconductor can be inferred by calculating the ratio of the concentration of the active dopant and the concentration of the initial input dopant. After the above steps are repeated for measurement, the dopant / carrier concentration / mobility distribution in the entire measured semiconductor micro-Hall test structure can be obtained.

[0056] Optionally, when the semiconductor micro-Hall test structure is removed by a specific thickness of the thin layer by the secondary ion mass spectrometry, the specific thickness is a fixed thickness, and the fixed thickness is less than or equal to 100 nm.

[0057] Preferably, the secondary ion mass spectrometry includes glow discharge optical emission spectrometry-secondary ion mass spectrometry or time-of-flight secondary ion mass spectrometry.

[0058] The semiconductor electrical property testing method provided by the embodiments of the present application can locally remove the thin layer in a controllable manner by the secondary ion mass spectrometry, analyze the atomic composition of the removed thin layer, infer the doping efficiency by obtaining the information of the semiconductor electrical property and the doping concentration distribution, and obtain more accurate semiconductor doping profile information because the thickness of the removed thin layer is controllable.

[0059] In another embodiment of the present application, according to the measured electrical parameter of the semiconductor micro-Hall test structure and the distribution information of the doping concentration of the semiconductor micro-Hall test structure, the relationship between the doping concentration distribution of the semiconductor and the electrical parameter can be obtained.

[0060] Specifically, the atomic distribution information of each layer obtained after the thin layer is removed layer by layer and the corresponding electrical parameter can be used to obtain the corresponding relationship curve, and the relationship between the carrier mobility at different depths and the doping concentration distribution can be obtained by analyzing the relationship curve. Therefore, the relationship between the doping efficiency and the electrical property can be more accurately supported by analyzing the relationship between the doping concentration at different depths and the electrical parameter of the measured semiconductor.

[0061] In another embodiment of this application, when removing a thin layer of a specific thickness from the semiconductor micro Hall effect test structure using secondary ion mass spectrometry in step S300, the etching range is a circular area with a maximum diameter less than or equal to 4 mm, centered on the central region. The actual etched area of ​​the semiconductor micro Hall effect test structure is cross-shaped. Optionally, the two arms of the cross shape have the same width, equal to the width of any one arm in the semiconductor micro Hall effect test structure.

[0062] The semiconductor electrical property testing method provided in this application can effectively reduce the impact of depth variations of the structure other than the central region on the electrical property testing of the semiconductor by etching only the central region of the semiconductor micro Hall test structure under test.

[0063] Figure 4 The diagram shown is a flowchart illustrating a method for testing the electrical properties of semiconductors according to another embodiment of this application. Figure 1 Extending from the illustrated embodiment Figure 4 The illustrated embodiment will be described in detail below. Figure 4 The illustrated embodiments and Figure 1 The differences between the embodiments shown are not repeated here, and the similarities are not repeated here.

[0064] When the semiconductor micro Hall effect test structure under test is like Figure 2 As shown, in step S200, determining the electrical parameters of the semiconductor micro Hall effect test structure includes the following steps:

[0065] Step S210: Apply current to two adjacent arms of the semiconductor micro Hall test structure through the pads, measure the voltage between the other two adjacent arms of the semiconductor micro Hall test structure, and calculate the resistivity of the semiconductor micro Hall test structure.

[0066] Specifically, in this embodiment, any one of the two arms symmetrical about the first axis is adjacent to any one of the two arms symmetrical about the second axis. For example... Figure 2 As shown, current I is applied to support arms 31 and 32 through pads 21 and 22. 12 Then, the voltage V between support arm 33 and support arm 34 is measured through pads 23 and 24. 34 Current I is applied to support arms 32 and 33 through pads 22 and 23. 23 Then, the voltage V between support arm 34 and support arm 31 is measured through pads 24 and 21. 41 Current I is applied to support arms 33 and 34 through pads 23 and 24. 34 Then, the voltage V between support arm 31 and support arm 32 is measured through pads 21 and 22. 12 Current I is applied to support arms 34 and 31 through pads 24 and 21.41 Then, the voltage V between the branch 32 and the branch 33 is measured through the pad 22 and the pad 23 23 ; wherein I 12 = I 23 = I 34 = I 41 = I. The reverse direction is measured in the same way, V 21 , V 32 , V 43 , V 14 , and the corresponding current values are: I 21 = I 32 = I 43 = I 14 = I.

[0067] Therefore, the resistivity p of the measured semiconductor micro-Hall test structure can be obtained by the Van der Pauw method, i.e. by the following formula:

[0068] p A = (π / ln2)(f A ×t s )(V 34 -V 41 +V 12 -V 23 ) / 4I;

[0069] p B = (π / ln2)(f B ×t s )(V 43 -V 14 +V 21 -V 32 ) / 4I;

[0070] p = (p A + p B ) / 2.

[0071] wherein f A = f B = 1, and t s is the thickness of the measured semiconductor micro-Hall test structure.

[0072] Step S220: When a magnetic field perpendicular to the plane where the semiconductor micro-Hall test structure is located is applied, the current is applied to two non-adjacent branches of the semiconductor micro-Hall test structure through the pad, and the change of the voltage between the other two non-adjacent branches of the semiconductor micro-Hall test structure is measured, so as to measure the carrier concentration and the Hall mobility of the semiconductor micro-Hall test structure.

[0073] Specifically, the two arms symmetrical to the first axis or the two arms symmetrical to the second axis in the embodiment are two non-adjacent arms. When a magnetic field perpendicular to the plane where the semiconductor micro-Hall test structure is located is applied, the current is applied to the two non-adjacent arms of the semiconductor micro-Hall test structure through the pads, for example, the current is applied to the arms 31 and 33 through the pads 21 and 23, and the voltage change between the other two non-adjacent arms of the semiconductor micro-Hall test structure is measured, for example, the voltage change between the arms 32 and 34 is measured through the pads 22 and 24, so as to measure the carrier concentration and the Hall mobility of the semiconductor micro-Hall test structure.

[0074] As described above, after the Hall coefficient RH is measured, the conductivity σ can be measured by the Van Der Pauw method, the Eddy current Testing method or the microwave reflection method, and the carrier mobility μ is further obtained, that is, the carrier mobility μ is obtained by the formula σ = μ / |RH| of the conductivity. In addition, the related formula for obtaining the carrier concentration is: n = σ / (e x μ); therefore, the carrier concentration n can be obtained.

[0075] Alternatively, the width of the arm is one or more of 1 μm, 5 μm, 10 μm, 100 μm and 200 μm, that is, the arms of different widths can be designed, such as 1 μm, 5 μm, 10 μm, to wider arms, such as 100 μm, 200 μm. The semiconductor electrical property test method provided in the embodiment can obtain semiconductor micro-Hall test structures of different arm widths by changing the arm width. According to the test method provided in the application, by comparing the measured electrical properties of these different structures, the lateral profile information related to the arm width, the filling factor / transmittance / load effect can be inferred. Specifically, the arm width is related to the lateral profile, and the lateral profile depends on the process conditions of selective area epitaxy and the filling factor / transmittance / load effect. Therefore, some dummy structures of selective area epitaxy can be added to optimize the lateral profile of selective area epitaxy. Alternatively, different crystal orientations also affect the lateral profile of selective area epitaxy.

[0076] Figure 5 Fig. 4 shows a flowchart of the semiconductor electrical property test method provided in another embodiment of the application, which is based on the embodiment shown in Fig. 3. Figure 1 The embodiment shown in Fig. 4 is extended on the basis of the embodiment shown in Fig. 3. Figure 5 The embodiment shown in Fig. 4 is extended on the basis of the embodiment shown in Fig. 3. Figure 5 The embodiment shown in Fig. 4 is extended on the basis of the embodiment shown in Fig. 3. Figure 1 The embodiment shown in Fig. 4 is extended on the basis of the embodiment shown in Fig. 3.

[0077] When the semiconductor micro-Hall test structure to be measured is, for example, the semiconductor micro-Hall test structure shown in Fig. 1, the semiconductor electrical property test method provided in the embodiment is as follows. Figure 3At the time, in step S200, the measuring of the electrical parameters of the semiconductor micro-Hall test structure includes the following steps:

[0078] Step S230: applying current to two arms symmetrical to the first axis through the pads, measuring the voltage between two arms on the same side of the second axis among the other four arms to calculate the resistivity of the semiconductor micro-Hall test structure.

[0079] Specifically, current is applied to two arms symmetrical to the first axis through the pads, for example, current is applied to arms 51 and 52 symmetrical to the first axis through pads 41 and 42. The voltage between two arms on the same side of the second axis among the other four arms is measured, for example, the voltage between arms 53 and 55 is measured through pads 43 and 45, to calculate the resistivity of the semiconductor micro-Hall test structure.

[0080] Step S240: When a magnetic field perpendicular to the plane where the semiconductor micro-Hall test structure is located is applied, current is applied to two arms symmetrical to the first axis through the pads, and the change in voltage between any two arms symmetrical to the second axis among the other four arms is measured to measure the carrier type, carrier concentration and carrier mobility.

[0081] Specifically, when a magnetic field perpendicular to the plane where the semiconductor micro-Hall test structure is located is applied, current is applied to two arms symmetrical to the first axis through the pads, for example, current is applied to arms 51 and 52 through pads 41 and 42, and the change in voltage between any two arms symmetrical to the second axis among the other four arms, for example, the voltage between arms 53 and 54 is measured through pads 43 and 44, to measure the carrier type, carrier concentration and carrier mobility.

[0082] As can be seen from the foregoing embodiments, the Hall coefficient RH can be measured by the foregoing formula. According to the semiconductor micro-Hall test structure provided by the present application, the conductivity type of the measured semiconductor can be determined according to the sign of RH, and the carrier type, carrier concentration and carrier mobility of the measured semiconductor can be further calculated.

[0083] Figure 6 The flowchart of the semiconductor electrical property test method provided by another embodiment of the present application is shown. In the embodiment shown in Figure 5 The embodiment shown in the embodiment shown in Figure 6 The embodiment shown in the embodiment shown in Figure 6 The embodiment shown in the embodiment shown in Figure 5 The differences between the embodiment shown in the embodiment shown in

[0084] When the measured semiconductor micro-Hall test structure is as shown in Figure 3 as shown inFigure 6 As shown, the method for testing semiconductor electrical characteristics provided by an embodiment of the present application further includes the following steps:

[0085] Step S250: When the material of the semiconductor micro-Hall test structure is PN junction material, an alternating magnetic field perpendicular to the plane where the semiconductor micro-Hall test structure is located is applied, and the electron mobility and the hole mobility of the semiconductor micro-Hall test structure are measured respectively.

[0086] Specifically, as known from the foregoing, the Hall coefficient can be obtained by the formula RH=(V H ×d) / (I×B), where V H represents the Hall coefficient, d represents the thickness of the measured semiconductor micro-Hall test structure, V H represents the Hall voltage, I represents the current intensity, and B represents the magnetic field intensity. The Hall coefficient is calculated by this formula, which represents the strength of the Hall effect. In addition, RH=μ×ρ, that is, the Hall constant RH is equal to the product of the resistivity p and the carrier mobility μ of the material. The alternating magnetic field makes the direction of the magnetic field change periodically, and thus the mobility of the holes and the electrons in the carriers corresponding to the positive and negative magnetic fields can be measured.

[0087] The method for testing semiconductor electrical characteristics provided by the embodiment of the present application can more directly measure the hole mobility and the electron mobility of the measured semiconductor.

[0088] Figure 7 As shown is a structure schematic diagram of a testing device for semiconductor electrical characteristics provided by another embodiment of the present application. As shown in the figure, the testing device for semiconductor electrical characteristics 700 includes an acquisition module 710, an electrical test module 720, an element analysis module 730, and a calculation module 740. Figure 7 As shown, the testing device for semiconductor electrical characteristics 700 provided by an embodiment of the present application includes an acquisition module 710, an electrical test module 720, an element analysis module 730, and a calculation module 740.

[0089] Specifically, the acquisition module 710 is configured to acquire a semiconductor micro-Hall test structure, the semiconductor micro-Hall test structure comprising at least one doping element; the electrical test module 720 is configured to measure an electrical parameter of the semiconductor micro-Hall test structure, and obtain a doping concentration of an active doping element in the semiconductor micro-Hall test structure; the element analysis module 730 is configured to remove a thin layer with a specific thickness from the semiconductor micro-Hall test structure by using secondary ion mass spectrometry, perform atomic composition analysis on the removed material, and obtain a doping concentration of an initial doping element in the thin layer of the semiconductor micro-Hall test structure; and the calculation module 740 is configured to calculate distribution information of a doping efficiency of the semiconductor micro-Hall test structure according to the doping concentration of the active doping element and the doping concentration of the initial doping element; wherein the electrical test module 720 and the element analysis module 730 are configured to be repeatedly executed until the distribution information of the electrical parameter of the semiconductor micro-Hall test structure, the doping concentration of the initial doping element, and the doping concentration of the active doping element are obtained.

[0090] In an embodiment of the present application, the material of the semiconductor micro-Hall test structure is a material with a doping profile, including a GaN-based material or a PN junction material.

[0091] In an embodiment of the present application, the electrical test module 720 is further configured to apply a current to two adjacent arms of the semiconductor micro-Hall test structure through the pads, measure a voltage between the other two adjacent arms of the micro-Hall test structure, and calculate a resistivity of the semiconductor micro-Hall test structure; when a magnetic field perpendicular to a plane in which the semiconductor micro-Hall test structure is located is applied, the electrical test module 720 is further configured to apply a current to two non-adjacent arms of the semiconductor micro-Hall test structure through the pads, measure a change in a voltage between the other two non-adjacent arms of the semiconductor micro-Hall test structure, and measure a carrier concentration and a carrier mobility of the semiconductor micro-Hall test structure.

[0092] In an embodiment of the present application, the electrical test module 720 is further configured to apply a current to two arms symmetrical with respect to the first axis through the pads, measure a voltage between two arms on the same side of the second axis in the other four arms, and calculate a resistivity of the semiconductor micro-Hall test structure; when a magnetic field perpendicular to a plane in which the semiconductor micro-Hall test structure is located is applied, the electrical test module 720 is further configured to apply a current to two arms symmetrical with respect to the first axis through the pads, measure a change in a voltage between any two arms symmetrical with respect to the second axis in the other four arms, and measure a carrier type, a carrier concentration, and a carrier mobility.

[0093] In an embodiment of the present application, the electrical test module 720 is further configured to, when the material of the semiconductor micro-Hall test structure is a PN junction material, measure an electron mobility and a hole mobility of the semiconductor micro-Hall test structure when an alternating magnetic field perpendicular to a plane in which the semiconductor micro-Hall test structure is located is applied.

[0094] In an embodiment of the present application, the element analysis module 730 is configured to remove a thin layer of a certain thickness from the semiconductor micro-Hall test structure for secondary ion mass spectrometry, and the etching range is a circular region with a center region as a center and a maximum diameter less than or equal to 4 mm.

[0095] In an embodiment of the present application, the element analysis module 730 is configured to remove a thin layer of a certain thickness from the semiconductor micro-Hall test structure for secondary ion mass spectrometry, and the certain thickness is a fixed thickness, and the fixed thickness is less than or equal to 100 nm.

[0096] In an embodiment of the present application, the secondary ion mass spectrometry includes glow discharge optical emission spectrometry-secondary ion mass spectrometry or time-of-flight secondary ion mass spectrometry.

[0097] The testing device for semiconductor electrical characteristics provided by the embodiments of the present application can locally remove a thin layer in a controllable manner through secondary ion mass spectrometry, and simultaneously analyze the atomic composition of the removed thin layer, so as to obtain the information of semiconductor electrical characteristics and doping concentration distribution, and deduce the doping efficiency; and since the thickness of the removed thin layer is controllable, the semiconductor doping profile information with higher precision can be obtained.

[0098] An electronic device 800 for testing semiconductor electrical characteristics is also provided in an embodiment of the present application, which includes one or more processors 810 and a memory 820.

[0099] The processor 810 can be a central processing unit (CPU) or other forms of processing units with data processing capability and / or instruction execution capability, and can control other components in the electronic device 800 to perform desired functions.

[0100] The memory 820 can include one or more computer program products, which can include various forms of computer readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory can include, for example, random access memory (RAM), cache memory and the like. The non-volatile memory can include, for example, read-only memory (ROM), hard disk, flash memory and the like. One or more computer program instructions can be stored in the computer readable storage medium, and the processor 810 can run the program instructions to implement the semiconductor electrical characteristic testing method of various embodiments of the present application described above and / or other desired functions. Various contents such as doping concentration distribution information can also be stored in the computer readable storage medium.

[0101] In one example, the electronic device 800 can further include an input device 830 and an output device 840, which are interconnected to each other through a bus system and / or other forms of connection mechanisms (not shown).

[0102] The input device 830 can include, for example, a keyboard, a mouse, and the like.

[0103] The output device 840 can output various information including atomic composition information and the like to the outside. The output device 840 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0104] Of course, in order to simplify, Figure 8 Only some of the components of the electronic device 800 related to the present application are shown in FIG. 8, and components such as a bus, an input / output interface, and the like are omitted. In addition to this, the electronic device 800 can further include any other appropriate components according to a specific application.

[0105] In addition to the above-described method and device, an embodiment of the present application can be a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform steps of the image processing method according to various embodiments of the present application described above in the specification.

[0106] The computer program product can be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, C++, and the like, and conventional procedural programming languages, such as the "C" programming language, or the like. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server.

[0107] The above-described embodiments are merely possible implementations of the present application, and are not used to limit the present application. Any modification, equivalent replacement, and the like made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A method for testing the electrical properties of a semiconductor, characterized in that, The method comprises: S100, obtaining a semiconductor micro-Hall test structure, wherein the semiconductor micro-Hall test structure comprises at least one doping element; S200, measuring an electrical parameter of the semiconductor micro-Hall test structure, and obtaining a doping concentration of an active doping element in the semiconductor micro-Hall test structure; S300, removing a preset thickness of a thin layer from the semiconductor micro-Hall test structure by secondary ion mass spectrometry, performing atomic composition analysis on the removed material, and obtaining a doping concentration of an initial doping element in the thin layer of the semiconductor micro-Hall test structure; S400, after removing the preset thickness of the thin layer, measuring the electrical parameter of the semiconductor micro-Hall test structure again, and obtaining the doping concentration of the active doping element in the semiconductor micro-Hall test structure, wherein a change in the doping concentration of the active doping element in the semiconductor micro-Hall test structure obtained before and after removing the thin layer can obtain the doping concentration of the active doping element in the thin layer of the semiconductor micro-Hall test structure; The steps S300 and S400 are repeatedly executed until distribution information of the electrical parameter, the doping concentration of the initial doping element, and the doping concentration of the active doping element in the semiconductor micro-Hall test structure in the thickness direction is obtained, and distribution information of the doping efficiency of the semiconductor micro-Hall test structure is calculated according to the distribution information of the doping concentration of the active doping element and the doping concentration of the initial doping element.

2. The test method of claim 1, wherein, The semiconductor micro-Hall test structure comprises: a central region located at an intersection of a first axis and a second axis of the semiconductor micro-Hall test structure, wherein the first axis and the second axis are perpendicular to each other; two arms symmetric to the first axis and two arms symmetric to the second axis extending from the central region; and a pad located at an end point of each arm away from the central region.

3. The test method of claim 2, wherein, The width of the arm is less than or equal to 2.8 mm.

4. The test method of claim 2, wherein, The measuring of the electrical parameter of the semiconductor micro-Hall test structure comprises: applying a current to two adjacent arms of the semiconductor micro-Hall test structure through the pads, measuring a voltage between the other two adjacent arms of the micro-Hall test structure, and calculating a resistivity of the semiconductor micro-Hall test structure; when a magnetic field perpendicular to a plane in which the semiconductor micro-Hall test structure is located is applied, applying a current to two non-adjacent arms of the semiconductor micro-Hall test structure through the pads, measuring a change in a voltage between the other two non-adjacent arms of the semiconductor micro-Hall test structure, and measuring a carrier concentration and a carrier mobility of the semiconductor micro-Hall test structure.

5. The test method of claim 1, wherein, The semiconductor micro-Hall test structure comprises: a central region located at an intersection of a first axis and a second axis of the semiconductor micro-Hall test structure, wherein the first axis and the second axis are perpendicular to each other; two arms symmetric to the first axis and four arms symmetric to the second axis extending from the central region, wherein each two arms of the four arms symmetric to the second axis are a group, and are respectively located on two sides of the second axis and symmetric to the second axis; and a pad located at the end of each branch away from the center region.

6. The test method of claim 5, wherein, The width of the branch is less than or equal to 0.5 mm.

7. The test method of claim 5, wherein, The method further comprises: applying a current to the two branches symmetrical to the first axis through the pad, and measuring the voltage between the other two branches on the same side of the second axis to calculate the resistivity of the semiconductor micro-Hall test structure; applying a current to the two branches symmetrical to the first axis through the pad, and measuring the change of the voltage between any two branches symmetrical to the second axis to measure the carrier type, carrier concentration and carrier mobility when a magnetic field perpendicular to the plane of the semiconductor micro-Hall test structure is applied.

8. The test method of claim 1, wherein, The semiconductor micro-Hall test structure comprises a selectively grown semiconductor structure.

9. The test method of claim 1, wherein, The material of the semiconductor micro-Hall test structure comprises a GaN-based material.

10. The test method of claim 9, wherein, The material of the semiconductor micro-Hall test structure comprises P-type GaN, and the doping element comprises at least one of Mg, Zn, Ca, Sr, Ba, Li, Na or K.

11. The test method of claim 1, wherein, The material of the semiconductor micro-Hall test structure comprises PN junction material.

12. The test method of claim 11, wherein, The P-type doping element in the PN junction material comprises at least one of Mg, Zn, Ca, Sr, Ba, Li, Na or K, and the N-type doping element comprises at least one of Si, Ge, Sn, Se or Te.

13. The test method of claim 11, wherein, The method further comprises: applying an alternating magnetic field perpendicular to the plane of the semiconductor micro-Hall test structure to measure the electron mobility and hole mobility of the semiconductor micro-Hall test structure.

14. The test method of claim 2, wherein, In the step of removing a thin layer of a preset thickness from the semiconductor micro-Hall test structure by secondary ion mass spectrometry, the etching range is a circular region with the center region as the center and a maximum diameter less than or equal to 4 mm.

15. The test method of claim 1, wherein, In the step of removing a thin layer of a preset thickness from the semiconductor micro-Hall test structure by secondary ion mass spectrometry, the preset thickness is a fixed thickness, and the fixed thickness is less than or equal to 100 nm.

16. The test method of claim 1, wherein, The secondary ion mass spectrometry comprises glow discharge spectroscopy-secondary ion mass spectrometry or time-of-flight secondary ion mass spectrometry.

17. A device for testing electrical properties of a semiconductor, characterized by A device for performing the test method of any one of claims 1 to 16.

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