Chip design method, device, equipment, medium and product

Abstract

The invention relates to the technical field of FPGA, and discloses a chip design method, device and equipment, a medium and a product, a chip comprises a carry lookahead adder module, and the method comprises the following steps: obtaining a target bit number of the carry lookahead adder module; dividing the carry lookahead adder module into a plurality of adder sub-modules based on the target bit number; establishing a target relational expression, and cascading the plurality of adder sub-modules based on the target relational expression; the target relational expression represents the corresponding relation between the input signal and the signal receiving end of each adder sub-module. According to the invention, the carry lookahead adder is disassembled into a plurality of sub-modules, so that the implementation complexity can be reduced, the required logic resources and power consumption are reduced, the circuit area requirement of the carry lookahead adder is reduced, and the performance and expandability of a chip are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA, and specifically relates to a chip design method, device, equipment, medium and product. Background Art

[0002] In chip design, an adder is a key component for implementing basic arithmetic operations, especially when dealing with the addition of binary numbers. The design and performance of the adder have a direct impact on the efficiency of the entire digital system.

[0003] In related technologies, adders usually use ripple-carry adders and carry-lookahead adders. Among them, for ripple-carry adders, multiple full adders are connected in series, and the carry output of each bit must depend on the carry result of the previous bit, which makes the delay of the adder increase linearly with the increase of the input bit number, resulting in slow speed in high-bit addition. Although carry-lookahead adders can greatly improve the calculation efficiency of adders in high-bit addition operations, when the number of stages increases, the calculation delay of the adder will increase.

[0004] In view of this, a chip design method that can improve calculation efficiency and reduce calculation delay is needed. Summary of the Invention

[0005] In view of this, the present invention provides a chip design method to improve the calculation efficiency of adders in a chip.

[0006] In a first aspect, the present invention provides a chip design method. The chip includes a carry-lookahead adder module, and the method includes: obtaining the target bit number of the carry-lookahead adder module; dividing the carry-lookahead adder module into a plurality of adder sub-modules based on the target bit number; establishing a target relationship, and cascading the plurality of adder sub-modules based on the target relationship; the target relationship represents the corresponding relationship between the input signal and the signal receiving ends of each adder sub-module.

[0007] In this embodiment, first obtain the target bit number of the carry-lookahead adder module, then divide the carry-lookahead adder module into a plurality of adder sub-modules based on the target bit number, and finally cascade the adder sub-modules according to the target relationship. In the above solution, by disassembling the carry-lookahead adder into multiple sub-modules, the implementation complexity can be reduced, the requirements for the circuit area, logic resources, power consumption, etc. of the carry-lookahead adder can be reduced, and the performance and scalability of the chip can be improved.

[0008] In an optional embodiment, obtaining the target bit number of the carry-lookahead adder module includes: obtaining the application parameters of the chip, and determining the target algorithm based on the application parameters; determining the target bit number of the carry-lookahead adder module based on the target algorithm.

[0009] In this embodiment, by obtaining the application parameters of the chip, the target algorithm is determined, and then the target bit number of the carry-lookahead adder module is determined, which can improve the operation speed and stability of the chip.

[0010] In an alternative embodiment, based on the target bit number, the carry-lookahead adder module is divided into several adder sub-modules, including: determining a grouping strategy based on the target bit number; determining the inputs and outputs of each adder sub-module based on the grouping strategy, so as to divide the carry-lookahead adder module into several adder sub-modules.

[0011] In this embodiment, based on the target bit number, the grouping strategy and the inputs and outputs of the adder sub-modules are determined, and then it is divided into several adder sub-modules, which can improve the flexibility of the method and optimize the parallel processing ability of the adder.

[0012] In an alternative embodiment, several adder sub-modules are cascaded based on the target relational expression, including: determining the carry input of each adder sub-module based on the target relational expression; determining the cascade link based on the carry input to cascade the adder sub-modules.

[0013] In this embodiment, based on the target relational expression, the carry input of each adder sub-module can be determined to determine the cascade link and cascade the adder sub-modules, which can improve the flexibility of the method.

[0014] In an alternative embodiment, determining the carry input of each adder sub-module based on the target relational expression includes: obtaining the target number of stages, and obtaining the carry generation signal and carry propagation signal corresponding to the target number of stages based on the target relational expression; determining the carry input of the adder sub-module based on the carry generation signal and the carry propagation signal.

[0015] In this embodiment, based on the target relational expression and the target number of stages, the carry generation signal and carry propagation signal corresponding to the target number of stages are obtained, so as to determine the carry input of the adder sub-module, which can ensure the accuracy of the carry input.

[0016] In an alternative embodiment, the number of signal receiving ends of the adder sub-module is a power of the number of target adder sub-modules; the target adder sub-module represents the adder sub-module connected to the input signal.

[0017] In this embodiment, the number of signal receiving ends of the adder sub-module is a power of the number of input signals, which can reduce the carry delay of high-bit addition and improve the overall operation speed.

[0018] In a second aspect, the present invention provides a chip design device, including an acquisition module configured to acquire a target number of bits of a carry-lookahead adder module; a division module configured to divide the carry-lookahead adder into a plurality of adder sub-modules based on the target number of bits; and a cascading module configured to establish a target relational expression and cascade the plurality of adder sub-modules based on the target relational expression, where the target relational expression represents the corresponding relationship between an input signal and signal receiving ends of the respective adder sub-modules.

[0019] In a third aspect, the present invention provides a computer device, including: a memory and a processor, which are communicatively connected to each other, where computer instructions are stored in the memory, and the processor executes the computer instructions to execute the chip design method according to the first aspect or any corresponding embodiment thereof.

[0020] In a fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute the chip design method according to the first aspect or any corresponding embodiment thereof.

[0021] In a fifth aspect, the present invention provides a computer program product, including computer instructions, and the computer instructions are used to cause a computer to execute the chip design method according to the first aspect or any corresponding embodiment thereof. Description of the Drawings

[0022] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 is a connection schematic diagram of an eight-bit carry-lookahead adder;

[0024] Figure 2 is a logic chain schematic diagram of a nine-bit carry-lookahead adder;

[0025] Figure 3 is a logic chain schematic diagram of a nine-bit parallel adder;

[0026] Figure 4 is a flowchart of the chip design method according to an embodiment of the present invention;

[0027] Figure 5 is a flowchart of another chip design method according to an embodiment of the present invention;

[0028] Figure 6Schematic diagram of the connection of a carry-lookahead adder according to an embodiment of the present invention;

[0029] Figure 7 Schematic diagram of a logic chain according to an embodiment of the present invention;

[0030] Figure 8 Block diagram of the structure of a chip design device according to an embodiment of the present invention;

[0031] Figure 9 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed implementation manners

[0032] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] In digital logic design, an adder is a key component for implementing basic arithmetic operations, especially when dealing with the addition of binary numbers. The design and performance of the adder have a direct impact on the efficiency of the entire digital system.

[0034] The simplest multi-bit adder is the ripple carry adder (RCA), which is composed of multiple full adders connected in series. In an RCA, the carry output of each bit must depend on the carry result of the previous bit, which causes the delay of the adder to increase linearly with the increase in the number of input bits, resulting in a slow speed when adding high-order numbers.

[0035] The carry-lookahead adder (LCA) solves the carry propagation delay problem in traditional RCA adders by calculating the carry generate (G) and propagate (P) signals in parallel. The adopted strategy of pre-calculation enables the carry output of each stage to be predicted and generated in a short time, especially in high-order number addition operations, which can significantly improve the calculation efficiency of the adder.

[0036] Taking a 4-bit carry-lookahead adder as an example: among them, the carry generate signal G i = A i · B i , the carry propagate signal P i = A i ⊕ B i ; the carry calculation method is C i+1 = Gi +P i C i ; The four inputs C of the carry look-ahead adder 1 、C 2 、C 3 、C 4 are respectively:

[0037] C 1 = G 0 +P 0 C 0 ;

[0038] C 2 = G 1 +P 1 C 1 = G 1 +G 0 P 1 +P 0 P 1 C 0 ;

[0039] C 3 = G 2 +P 2 C 2 = G2 + G 1 P 2 +G 0 P 1 P 2 +P 0 P 1 P 2 C 0 ;

[0040] C 4 = G 3 +P 3 C 3 = G3 + G 2 P 3 +G 1 P 2 P 3 +G 0 P 1 P 2 P 3 +P 0 P 1 P 2 P 3 C 0 。

[0041] Among them, G i represents the carry generation signal of the i-th bit, and A i , B i respectively represent the two inputs of the i-th bit, and P iRepresents the carry propagation signal of the i-th bit, C i+1 Represents the carry of the (i + 1)-th bit, C i Represents the carry of the i-th bit.

[0042] Ideally, assuming no additional delays introduced by multi-bit or logic gates, the carry input needs to pass through two levels of logic gates to reach the carry output of each level. In practical applications, when the number of LCA levels increases, the fan-out of the carry input will also increase linearly. As the number of levels increases, to maintain the effective propagation of the carry, the required auxiliary logic resources will increase significantly, which will further exacerbate the system complexity and computational delay.

[0043] Therefore, in the actual internal design of FPGA (Field Programmable Gate Array), considering the fan-out effect and area constraints, usually four levels of LCA are cascaded as a module, and the carry output of the previous level is connected to the carry input of the next level. The calculation time of each group of LCA can be maintained within the range of two levels of logic gates.

[0044] However, for multi-bit addition operations, although the calculation delay of each group remains fixed, the overall calculation delay still shows a linear growth relationship with the number of bits. This is because as the number of bits of the adder increases, the amount of carry propagation and logical calculations to be processed also increases, resulting in a linear increase in the overall delay as the number of bits of the adder increases.

[0045] Figure 1 Provides a connection schematic diagram of an eight-bit carry-lookahead adder, as Figure 1 shown. The carry-lookahead adder includes eight carry logic processing modules, which can be connected in parallel to calculate the carry generation and carry propagation signals. Among them, c[0] represents the input terminal of the carry-lookahead adder and is connected to the eight carry logic processing modules, and c[1] to c[8] respectively represent the output terminals of each carry logic processing module. By calculating the carry generation and carry propagation signals in parallel, each level of carry input can be predicted and generated in a relatively short time. Especially in high-bit addition operations, it can significantly improve the calculation efficiency of the adder. It can solve the carry propagation delay problem in traditional RCA adders, but as the number of levels increases, the increase in fan-out will cause the circuit complexity and delay to rise again.

[0046] Figure 2 Provides a logic chain schematic diagram of a nine-bit carry-lookahead adder, as Figure 2 shown. Among them, the black square operator processes the input carry propagation signal P i and generation signal G i to obtain a new carry propagation signal P′ for calculating the current carry outputi and the newly generated signal G' i , the calculation method is as shown in the following formula:

[0047]

[0048] where P i represents the carry propagation signal of the i-th bit, G i represents the generation signal of the i-th bit, P' i-1 represents the new carry propagation signal of the (i - 1)-th bit, and G' i-1 represents the new generation signal of the (i - 1)-th bit.

[0049] The carry logic of the carry-lookahead adder grows exponentially as the number of bits increases, resulting in a sharp increase in resource consumption at high bit numbers.

[0050] Figure 3 A schematic diagram of the logic chain of a parallel adder is provided. The black square operator combines adjacent carry propagation signals P (left,mid) P (mid,right) and generation signals G (left,mid) G (mid,right) , pairwise into larger blocks of (G (left,right) , P (left,right) ), where G (left,right) represents the newly generated signal, and P (left,right) ) represents the new carry propagation signal; the carry propagation signal P (i+1,i) and the generation signal G (i+1,i) can be obtained respectively through the following formula:

[0051]

[0052] where P i represents the carry propagation signal of the i-th bit, G i represents the generation signal of the i-th bit, P (i+1,i) represents the carry propagation signal passed from the i-th bit to the (i + 1)-th bit, and G (i+1,i) represents the generation signal passed from the i-th bit to the (i + 1)-th bit.

[0053] The specific calculation method is as shown in the following formula:

[0054] (G (left,right) , P (left,right) ) = (G (left,mid) , P (left,mid) ) · (G (mid,right) , P (mid,right) )

[0055] = (G (left,mid) ∨ (P (left,mid) ∧ G (mid,right) ), P(left,mid) ∧G (mid,right) )

[0056] Among them, G (left,right) represents the newly generated signal, P (left,right) represents the new carry propagation signal, G (left,mid) represents the left-bit generation signal of G (left,right) P represents the left-bit carry propagation signal of P (left,mid) represents P (left,right) The left-bit carry propagation signal, G (mid,right) represents G (left,right) The right-bit generation signal, P (mid,right) represents P (left,right) The right-bit carry propagation signal.

[0057] Then, the global carry signal is distributed to the intermediate nodes level by level, and the final carry C i (carry of the i-th bit) of each bit is calculated. The right-bit signal of this method will finally become 0 after a series of calculations, so it is settled with C 0 (the initial carry input). Among them, the final carry C left = G (left,right) + P (left,rught) C right , that is, C left = G (left,0) + P (left,0) C 0 . Among them, C left represents the left-bit carry output, G (left,right) represents the newly generated signal, P (left,rught) represents the new carry propagation signal, C rught represents the right-bit carry input.

[0058] Then, the sum output of the current level is calculated through the formula S i = P i ⊕ C i . Among them, S i represents the sum output of the i-th bit, C i represents the carry of the i-th bit, P i represents the carry propagation of the i-th bit. Although this kind of parallel adder reduces the logic complexity, it increases the number of logic levels and resource consumption.

[0059] The embodiment of the present invention provides a chip design method. By obtaining the target number of bits of the carry-lookahead adder module, and then based on the target number of bits, dividing the carry-lookahead adder module into several adder sub-modules, and then cascading the adder sub-modules according to the target relational expression. In the above solution, by disassembling the carry-lookahead adder into multiple sub-modules, the implementation complexity can be reduced, the required logic resources and power consumption can be reduced, the circuit area requirement of the carry-lookahead adder can be reduced, and the performance and scalability of the chip can be improved.

[0060] According to an embodiment of the present invention, an embodiment of a chip design method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0061] In this embodiment, a chip design method is provided. The chip includes a carry-lookahead adder module. Figure 4 is a flowchart of the chip design method according to an embodiment of the present invention, as Figure 4 shown, the process includes the following steps:

[0062] Step S401, obtain the target number of bits of the carry-lookahead adder module.

[0063] The carry-lookahead adder can solve the problem of carry propagation delay by calculating carry generation and carry propagation signals in parallel. Increasing the number of stages of the carry-lookahead adder will cause a significant increase in the auxiliary logic resources required by the chip and exacerbate the computational delay within the chip. By obtaining the target number of bits of the carry-lookahead adder, the fan-out of each stage of carry in the carry-lookahead adder can be reasonably allocated according to the actual situation, thereby saving logic resources.

[0064] Among them, the target number of bits of the carry-lookahead adder can be determined according to the fan-out effect and area constraint of the chip. In practical applications, numbers such as 2, 4, 8, etc. are usually used as the target number of bits.

[0065] Step S402, based on the target number of bits, divide the carry-lookahead adder module into several adder sub-modules.

[0066] In order to reduce the complexity of the carry chain in the carry-lookahead adder module and improve the resource utilization rate, the carry-lookahead adder module is divided.

[0067] Among them, when dividing, the grouping strategy of the carry-lookahead adder can be determined according to the target number of bits and the performance requirements of the chip. Then, the input, output, and internal logic of each adder sub-module are determined to reasonably divide the carry-lookahead adder.

[0068] Step S403, establish a target relationship, and cascade several adder sub-modules based on the target relationship; the target relationship represents the corresponding relationship between the input signal and the signal receiving ends of each adder sub-module.

[0069] In order to be able to normally implement the function of the carry-lookahead adder module, a target relationship needs to be designed to determine the connection method, connection order, etc. of the adder sub-modules to avoid logical errors.

[0070] Among them, the target relational expression can be determined according to the number of adder sub-modules and the target number of bits. After obtaining the number of adder sub-modules and the target number of bits, determine the way of generating and transmitting carry signals between each adder sub-module.

[0071] Then, cascade the adder sub-modules according to the established target relational expression. It can improve the performance of the adder while optimizing the use of resources and reducing latency.

[0072] In some alternative embodiments, the number of adder sub-modules is 8, and the target relational expression can be set as y = 2x. Connect the input ends of 4 odd-level adder sub-modules directly to the signal input end, and connect the input ends of the other 4 even-level adder sub-modules to the output ends of the adder sub-modules connected to the signal input end respectively. Thus, the cascade of the adder sub-modules can be completed. After cascading in this way, the propagation delay of the adder can be effectively reduced, and the operation speed and response performance can be improved.

[0073] The chip design method provided in this embodiment obtains the target number of bits of the carry-lookahead adder module, then divides the carry-lookahead adder module into several adder sub-modules based on the target number of bits, and then cascades the adder sub-modules according to the target relational expression. In the above solution, by disassembling the carry-lookahead adder into multiple sub-modules, the implementation complexity can be reduced, the required logic resources and power consumption can be reduced, the circuit area requirement of the carry-lookahead adder can be reduced, and the performance and scalability of the chip can be improved.

[0074] In this embodiment, a chip design method is provided, and the chip includes a carry-lookahead adder module. Figure 5 It is a flowchart of the chip design method according to the embodiment of the present invention. As Figure 5 shown, the process includes the following steps:

[0075] Step S501, obtain the target number of bits of the carry-lookahead adder module.

[0076] For details, please refer to Figure 4 step S401 of the shown embodiment, which will not be elaborated here.

[0077] In some alternative embodiments, the above step S501 includes:

[0078] Step S5011, obtain the application parameters of the chip, and determine the target algorithm based on the application parameters.

[0079] By obtaining the application parameters of the chip, the requirements of the chip for the carry-lookahead adder can be determined. After clarifying the requirements for the carry-lookahead adder, a suitable target algorithm can be selected to improve the operation efficiency of the carry-lookahead adder.

[0080] Among them, the application parameters may include requirements for addition operation speed, power consumption, chip area, data bit width, etc.

[0081] After obtaining the application parameters of the chip, based on the application parameters, the usage scenario of the chip can be determined, and thus a suitable target algorithm can be determined.

[0082] Step S5012: Determine the target number of bits of the carry-lookahead adder module based on the target algorithm.

[0083] After determining the target algorithm, according to the characteristics of the target algorithm and application requirements, the target number of bits of the carry-lookahead adder module can be determined to split the carry-lookahead adder.

[0084] Among them, if the target number of bits is too small, the calculation speed of the adder sub-module can be increased, but the delay of carry processing between the adder sub-modules will increase. If the target number of bits is too large, it may cause an increase in the delay between the adder sub-modules, thus affecting the overall speed.

[0085] Step S502: Based on the target number of bits, divide the carry-lookahead adder module into several adder sub-modules.

[0086] For details, please refer to Figure 4 Step S402 of the illustrated embodiment, which will not be elaborated here.

[0087] In some alternative embodiments, the above step S502 includes:

[0088] Step S5021: Determine the grouping strategy based on the target number of bits.

[0089] The core of the carry-lookahead adder is to reduce the delay by generating carry signals in parallel. Therefore, the grouping strategy also needs to satisfy independent calculation of carry generation and carry propagation and hierarchical combination of carry logic to maintain the logical correctness of the carry-lookahead adder.

[0090] Based on the target number of bits, the number of adder sub-modules and the number of bits corresponding to each adder sub-module can be determined. Thus, the grouping strategy can be determined.

[0091] Step S5022: Based on the grouping strategy, determine the inputs and outputs of each adder sub-module to divide the carry-lookahead adder module into several adder sub-modules.

[0092] Based on the grouping strategy, the inputs and outputs of each adder sub-module can be directly determined.

[0093] In some alternative embodiments, the number of inputs and outputs of several adder sub-modules are not exactly the same, and the corresponding number of bits is not exactly the same either. Division can be carried out according to the actual situation, thereby improving the flexibility of the method.

[0094] Step S503: Establish a target relationship, and cascade several adder sub-modules based on the target relationship; the target relationship represents the corresponding relationship between the input signal and the signal receiving ends of each adder sub-module.

[0095] Specifically, the above step S503 includes:

[0096] Step S5031: Determine the carry input of each adder sub-module based on the target relationship.

[0097] In chip design, carry calculation usually involves the generation of carry signals and carry propagation signals, and then the intermediate carry is calculated through inter-group logic. Therefore, determining the carry input of each adder sub-module based on the target relationship can prevent logical errors.

[0098] Among them, the target relationship represents the corresponding relationship between the input signal and the signal receiving ends of each adder sub-module.

[0099] In some alternative embodiments, the above step S5031 includes:

[0100] Step a1: Obtain the target number of stages, and based on the target relationship, obtain the carry generation signal and carry propagation signal corresponding to the target number of stages;

[0101] Among them, the grouping level and the number of bits in each group can be determined based on the target number of stages. After determining the grouping level, the connection method between levels can be determined based on the target relationship. And define the way of forming the carry generation signal and carry propagation signal of the next level for each grouped level to form the carry generation signal and carry propagation signal of the current level.

[0102] Step a2: Determine the carry input of the adder sub-module based on the carry generation signal and carry propagation signal.

[0103] Among them, the carry input of the lowest bit of the adder sub-module can be directly obtained through the input signal. Based on the known carry input, the generation signal and propagation signal of each bit in the adder sub-module can be calculated, and according to the generation signal and propagation signal, the carry input formula of each bit can be deduced, so as to determine the carry input of the adder sub-module.

[0104] Step S5032: Determine the cascade link based on the carry input to cascade the adder sub-modules.

[0105] Based on the carry input, determine the cascading link to cascade the adder sub-modules. It can ensure that the cascaded adder sub-modules meet the requirements of the carry-lookahead adder for the carry input and avoid logical problems.

[0106] By reasonably distributing the fan-out of each level of carry, it is possible to effectively equalize the fan-out pressure of the carry output of each level, while reducing the fan-out burden at the carry input end. This optimization not only improves the driving ability of the circuit, but also supports the design of adders with higher bit widths under the same carry input fan-out conditions. Specifically, by reducing the load of each level of carry propagation, the signal delay is reduced, and when the number of levels remains the same, the calculation speed of the carry output can be accelerated, thereby improving the overall performance and operation efficiency of the adder.

[0107] In addition, this fan-out optimization effectively improves the timing characteristics of the circuit and enhances the stability of the system. Especially in high-frequency or large-scale addition operations, it can significantly reduce the delay and power consumption.

[0108] In some alternative embodiments, the number of signal receiving ends of the adder sub-module is a power of the number of target adder sub-modules; the target adder sub-module represents the adder sub-module connected to the input signal.

[0109] If the number of signal receiving ends of the adder sub-module is a power of the number of target adder sub-modules, the target relational expression can be determined as y = 2 x . The connection of the carry-lookahead adder is as Figure 6 shown, where c[0] represents the input end of the carry-lookahead adder and is connected to eight carry logic processing modules, and c[1] to c[8] respectively represent the output ends of each carry logic processing module.

[0110] In a specific implementation, when the number of signal receiving ends of the adder sub-module is a power of the number of input signals. The schematic diagram of the logic chain corresponding to a nine-bit carry-lookahead adder is as Figure 7 shown. The black square operator processes the adjacent carry propagation signals P (left,mid) P (mid,right) and the generation signals G (left,mid) G (mid,right) to obtain the new carry propagation signal P (left,right) and the generation signal G (left,right) for calculating the current carry output. The calculation method is as shown in the following formula:

[0111] (G (left,right) ,P (left,right) )=(G (left,mid) ,P (left,mid) )·(G (mid,right) ,P (mid,right) )

[0112] = (G (left,mid) ∨ (P (left,mid) ∧ G (mid,right) )), P (left,mid) ∧ G (mid,right) )

[0113] Wherein, G (left,right) represents a newly generated signal, P (left,right) represents a new carry propagation signal, G (left,mid) represents the left - hand generated signal of G (left,right) represents the left - hand carry propagation signal of P (left,mid) represents the right - hand generated signal of G (left,right) represents the right - hand carry propagation signal of P (mid,right) represents the right - hand generated signal of G (left,right) represents the right - hand carry propagation signal of P (mid,right) represents the right - hand carry propagation signal of P (left,right) .

[0114] Then, through C left = G (left,right) + P (left,right) C right , the carry output of the current level can be calculated. Wherein, C left represents the left - hand carry output, G (left,right) represents a newly generated signal, P (left,right) represents a new carry propagation signal, C right represents the right - hand carry input. The right - hand signal of this method does not necessarily end up as 0. In this case, the intermediate carry output C right is used. When the number of stages of the adder left = (2 * i + 1) * 2 j (i ≥ 0, j ≥ 0), use right = i * 2 j+1 as the carry input C right , wherein, (2 * i + 1) represents an odd number, 2 j represents a power of 2. For any left (carry output stage number), the unique i and j can be calculated, and right represents the carry input stage number. i has no practical meaning, and j represents the fan - out number of the carry output of this stage.

[0115] Using the carry output of the intermediate process to replace the carry input of some logic layers can optimize the logic chain structure, reduce the fan - out and driving pressure of the carry input. By changing the cascading delay from linear growth to logarithmic growth, the carry delay of high - digit addition can be significantly reduced, and the overall operation efficiency can be improved.

[0116] The chip design method provided in this embodiment can reduce the implementation complexity, reduce the required logic resources and power consumption, reduce the circuit area requirement of the carry-lookahead adder, and improve the performance and scalability of the chip by disassembling the carry-lookahead adder into multiple sub-modules. Based on the target expression, cascading the adder sub-modules can evenly distribute the fan-out of the carry input to each carry output terminal, effectively reducing the driving pressure on a single output terminal, thereby optimizing the circuit load balance and improving the overall delay performance.

[0117] In this embodiment, a chip design device is also provided. This device is used to implement the above-mentioned embodiments and preferred implementation manners, and those that have been described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that can achieve a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0118] This embodiment provides a chip design device, as Figure 8 shown, including:

[0119] An acquisition module 801, configured to acquire the target number of bits of the carry-lookahead adder module.

[0120] A partitioning module 802, configured to partition the carry-lookahead adder into a plurality of adder sub-modules based on the target number of bits.

[0121] A cascading module 803, configured to establish a target relational expression and cascade a plurality of adder sub-modules based on the target relational expression; the target relational expression characterizes the correspondence between the input signal and the signal receiving ends of each adder sub-module.

[0122] In some alternative implementation manners, the acquisition module 801 includes:

[0123] An algorithm determination unit, configured to acquire the application parameters of the chip and determine the target algorithm based on the application parameters.

[0124] A target number of bits determination unit, configured to determine the target number of bits of the carry-lookahead adder module based on the target algorithm.

[0125] In some alternative implementation manners, the partitioning module 802 includes:

[0126] A grouping strategy unit, configured to determine the grouping strategy based on the target number of bits.

[0127] A partitioning unit, configured to determine the inputs and outputs of each adder sub-module based on the grouping strategy to partition the carry-lookahead adder module into a plurality of adder sub-modules.

[0128] In some alternative embodiments, the cascade module 803 includes:

[0129] A carry input determination unit configured to determine the carry input of each adder sub-module based on a target relational expression.

[0130] A cascade unit configured to determine a cascade link based on the carry input to cascade the adder sub-modules.

[0131] In some alternative embodiments, the carry input determination unit includes:

[0132] A carry signal acquisition sub-unit configured to acquire a target number of stages and, based on the target relational expression, acquire a carry generation signal and a carry propagation signal corresponding to the target number of stages.

[0133] A carry input determination sub-unit configured to determine the carry input of the adder sub-module based on the carry generation signal and the carry propagation signal.

[0134] In some alternative embodiments, the number of signal receiving ends of the adder sub-module is a power of the number of target adder sub-modules; the target adder sub-module represents the adder sub-module connected to the input signal.

[0135] The further functional descriptions of the above-mentioned various modules and units are the same as those in the corresponding foregoing embodiments and will not be elaborated herein.

[0136] The chip design device in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0137] The embodiment of the present invention further provides a computer device having the above-mentioned Figure 8 shown chip design device.

[0138] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of a computer device provided by an alternative embodiment of the present invention. As shown in Figure 9As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. Each component communicates with each other using different buses and can be installed on a common motherboard or in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if needed, multiple processors and / or multiple buses can be used together with multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (such as an array of servers, a set of blade servers, or a multi-processor system). Figure 9 Take one processor 10 as an example in Figure 9 .

[0139] The processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above-mentioned hardware chip can be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above-mentioned programmable logic device can be a complex programmable logic device, a field-programmable gate array, a generic array logic, or any combination thereof.

[0140] Among them, the memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiments.

[0141] The memory 20 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 can include high-speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 can optionally include a memory remotely set relative to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0142] The memory 20 can include volatile memory, such as random access memory; the memory can also include non-volatile memory, such as flash memory, a hard disk, or a solid-state drive; the memory 20 can also include a combination of the above types of memory.

[0143] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 can be connected through a bus or other means.Figure 9 Take the bus connection as an example.

[0144] The input device 30 can receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED), and a haptic feedback device (e.g., a vibration motor), etc. The above display device includes, but is not limited to, a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some alternative embodiments, the display device may be a touch screen.

[0145] The embodiments of the present invention also provide a computer-readable storage medium. The methods according to the embodiments of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the methods described herein can be stored as such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0146] A part of the present invention can be applied as a computer program product, such as computer program instructions. When executed by a computer, through the operation of the computer, the methods and / or technical solutions according to the present invention can be invoked or provided. Those skilled in the art should be able to understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0147] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A chip design method, characterized in that: The chip includes a carry-lookahead adder module, and the method includes: Obtaining a target number of bits of the carry-lookahead adder module; Based on the target number of bits, dividing the carry-lookahead adder module into a plurality of adder submodules; A target relational expression is established, and based on the target relational expression, a plurality of adder submodules are cascaded; the target relational expression represents the corresponding relationship between the input signal and the signal receiving end of each of the adder submodules.

2. The method according to claim 1, characterized in that The step of obtaining the target number of bits of the carry lookahead adder module comprises: Acquiring application parameters of the chip, and determining a target algorithm based on the application parameters; Based on the target algorithm, a target number of bits of the carry lookahead adder module is determined.

3. The method according to claim 1, characterized in that: Based on the target number of bits, the carry lookahead adder module is divided into a plurality of adder submodules, including: Determining a grouping strategy based on the target number of bits; Based on the grouping strategy, the input and output of each of the adder sub-modules are determined to divide the carry look-ahead adder module into a plurality of adder sub-modules.

4. The method according to claim 1, characterized in that Based on the target relation, a plurality of adder submodules are cascaded, including: Based on the target relationship, determining the carry input of each of the adder submodules; Based on the carry input, a cascade link is determined to cascade the adder sub-modules.

5. The method according to claim 4, characterized in that The step of determining the carry input of each of the adder submodules based on the target relational expression includes: Obtaining a target number of stages, and based on the target relationship, obtaining a carry generation signal and a carry transmission signal corresponding to the target number of stages; A carry input of the adder submodule is determined based on the carry generate signal and the carry propagate signal.

6. The method according to claim 1, characterized in that The number of signal receiving ends of the adder submodule is a power of the number of target adder submodules; the target adder submodule represents the adder submodule connected to the input signal.

7. A chip design device, characterized in that: The device comprises: An acquisition module, used for acquiring the target number of bits of the carry-lookahead adder module; A division module, used for dividing the carry-lookahead adder into a plurality of adder sub-modules based on the target number of bits; The cascade module is used to establish a target relationship and cascade a plurality of adder submodules based on the target relationship; the target relationship represents the corresponding relationship between the input signal and the signal receiving end of each of the adder submodules.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the chip design method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the chip design method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the chip design method according to any one of claims 1 to 6.

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