Wiring method and device, electronic equipment and storage medium
By splitting the hard-core modules in the FPGA into submodules and wiring them separately, the problems of inflexible wiring and poor coupling of the hard-core modules are solved, and more flexible wiring results and better bitstream verification results are achieved.
Patent Information
- Application Number
- CN202510161180.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-06-13
AI Technical Summary
When wiring hardcore modules in FPGAs, the internal structure of the hardcore module is not clear, the wiring method is not flexible enough, the coupling with other modules is poor, and the bitstream verification effect is not good.
Split the hard-core module into multiple submodules, determine the signal path of each submodule based on the signal path of the hard-core module, and wiring each submodule separately to obtain the wiring results of each submodule, and then generate the wiring results of the hard-core module based on the wiring results of each submodule.
The internal structure of the hard core module is sorted out through the signal path of the submodule, and more flexible hard core module wiring results are generated, which enhances the coupling with other FPGA modules and improves the bitstream verification effect.
Smart Images
Figure CN120145965A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular, to a wiring method, device, electronic device, and storage medium. Background Art
[0002] Field Programmable Gate Arrays (FPGAs) usually have some dedicated hardcore modules for accelerating the processing of certain specific functions, such as digital signal processing modules, transceivers, and so on.
[0003] In the related art, when wiring the hardcore modules in an FPGA, since the internal structure of the hardcore modules is not clear, wiring can only be performed based on the corresponding relationship between their inputs and outputs. As a result, the wiring method of the hardcore modules is not flexible enough, and the coupling with other modules in the FPGA is relatively poor. Summary of the Invention
[0004] This application proposes a wiring method, device, electronic device, and storage medium.
[0005] In a first aspect, an embodiment of this application provides a wiring method, which includes: obtaining a hardcore module and the signal path of the hardcore module; splitting the hardcore module into multiple sub-modules, and determining the signal path of each sub-module among the multiple sub-modules based on the signal path of the hardcore module; for each sub-module among the multiple sub-modules, wiring the sub-module based on the signal path of the sub-module to obtain the wiring results of the multiple sub-modules; and wiring the hardcore module based on the wiring results of the multiple sub-modules to obtain the wiring result of the hardcore module.
[0006] In a second aspect, an embodiment of this application provides a wiring device, which includes: a first obtaining module for obtaining a hardcore module and the signal path of the hardcore module; a second obtaining module for splitting the hardcore module into multiple sub-modules and determining the signal path of each sub-module among the multiple sub-modules based on the signal path of the hardcore module; a pre-wiring module for wiring each sub-module among the multiple sub-modules based on the signal path of the sub-module to obtain the wiring results of the multiple sub-modules; and a wiring module for wiring the hardcore module based on the wiring results of the multiple sub-modules to obtain the wiring result of the hardcore module.
[0007] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory; one or more processors coupled to the memory; one or more programs, wherein one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to execute the method described in the first aspect.
[0008] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer program instructions are stored, and the computer program instructions can be called by a processor to execute the method described in the first aspect.
[0009] In a fifth aspect, an embodiment of the present application provides a computer program product, which is used to implement the method described in the first aspect when the instructions in the computer program product are executed.
[0010] Compared with the prior art, the technical solution provided by the embodiment of the present application first splits the hardcore module into multiple sub-modules, determines the signal path of each sub-module based on the signal path of the hardcore module, then routes each sub-module separately to obtain the routing result of each sub-module, and finally generates the routing result of the hardcore module based on the routing results of each sub-module. Since the sub-modules are virtualized from the various functions of the hardcore module, the routing result of the sub-module generated based on the signal path of the sub-module helps to sort out the internal structure of the hardcore module, and the subsequent generation of the routing result of the hardcore module is more flexible, which can enhance the coupling with other modules in the FPGA. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0012] Figure 1 is a flowchart of a routing method provided by an embodiment of the present application.
[0013] Figure 2 is a schematic diagram of the signal path of a hardcore module provided by an embodiment of the present application.
[0014] Figure 3 is a schematic diagram of splitting a hardcore module provided by an embodiment of the present application.
[0015] Figure 4 is a schematic diagram of the signal path of a sub-module provided by an embodiment of the present application.
[0016] Figure 5It is a flowchart of a wiring method provided by another embodiment of the present application.
[0017] Figure 6 It is a schematic diagram of wiring for a hard core module provided by an embodiment of the present application.
[0018] Figure 7 It is a flowchart of a wiring method provided by another embodiment of the present application.
[0019] Figure 8 It is a schematic diagram of wiring for a hard core module provided by an embodiment of the present application.
[0020] Figure 9 It is a flowchart of a wiring method provided by another embodiment of the present application.
[0021] Figure 10 It is a block diagram of a wiring device provided by an embodiment of the present application.
[0022] Figure 11 It is a block diagram of the structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners
[0023] The following details the implementation manners of the present application. Examples of the implementation manners are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The implementation manners described below with reference to the accompanying drawings are exemplary only for explaining the present application and should not be construed as a limitation of the present application.
[0024] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.
[0025] In the related art, a hard core module can be regarded as a black box, only knowing the corresponding relationship between its input and output, but not knowing its internal structure. Therefore, wiring can only be carried out based on the corresponding relationship between its input and output. In this way, the wiring method of the hard core module is not flexible enough, and the coupling with other modules in the FPGA is relatively poor. In addition, the bitstream verification effect of the hard core module is also not good.
[0026] Based on this, an embodiment of the present application provides a wiring method. First, the hard core module is split into multiple sub-modules. Based on the signal path of the hard core module, the signal path of each sub-module is determined. During the placement and routing stage, each sub-module is wired separately to obtain the wiring result of each sub-module. Finally, based on the wiring results of each sub-module, the wiring result of the hard core module is generated. Since the sub-modules are virtualized from the various functions of the hard core module, the wiring result of the sub-module generated based on the signal path of the sub-module helps to sort out the internal structure of the hard core module. Subsequently, the generation of the wiring result of the hard core module is more flexible, and the coupling with other modules in the FPGA can be enhanced. In addition, since the sub-module can implement the circuit characteristics of the hard core module, bitstream verification can be implemented based on the sub-module, thereby improving the bitstream verification effect of the hard core module.
[0027] It should be noted that during the placement and routing stage, the hard core module and the sub-modules split from the hard core module coexist, but in the actual product, only the hard core module exists and there are no sub-modules.
[0028] In the technical solution provided by the embodiment of the present application, the execution subject of each step is an electronic device, which can be a terminal device, such as a personal computer, a tablet computer, etc. Optionally, the electronic device is installed with a specified application program for implementing the wiring of the hard core module. The specified application program can be arc modeling software.
[0029] Please refer to Figure 1 , which shows a flowchart of the wiring method provided by an embodiment of the present application. The method includes the following processes.
[0030] S101, obtain the hard core module and the signal path of the hard core module.
[0031] The hard core module refers to a computing core that has been pre-implemented inside the FPGA chip, with the optimal performance and power consumption, but it is not customizable. The hard core module includes but is not limited to: embedded RAM, embedded multiplier, digital signal processing module, clock management module, etc.
[0032] The signal path of the hard core module represents the transmission path of the signal between the external input module, the hard core module, and the load. Please refer to Figure 2 , which shows a schematic diagram of the signal path of the hard core module provided by an embodiment of the present application. In Figure 2 , the signal path of the hard core module includes the path of the output pin PIN_A of the external input module - the input pin PIN_D of the hard core module - the output pin PIN_B of the hard core module - the input pin PIN_C of the load.
[0033] S102, split the hard core module into multiple sub-modules, and based on the signal path of the hard core module, determine the signal path of each sub-module among the multiple sub-modules.
[0034] The sub-module is a module virtualized based on the functions implemented by the hardcore module. In some embodiments, the process of splitting the hardcore module may include: obtaining the input-output characteristics of the hardcore module, determining multiple functions implemented by the hardcore module based on the input-output characteristics of the hardcore module; and dividing the hardcore module into sub-modules corresponding to the multiple functions respectively based on the multiple functions implemented by the hardcore module.
[0035] The input-output characteristics of the hardcore module include: the attribute information of the input data of the hardcore module, or / and, the attribute information of the output data of the hardcore module. The attribute information of the input data of the hardcore module includes the type and quantity of the input data of the hardcore module. For example, the input data of the hardcore module includes two types, one is enable data, and the other is data to be processed. The attribute information of the output data of the hardcore module includes the type and quantity of the output data of the hardcore module. For example, the output data of the hardcore module includes one type, which is processed data.
[0036] Determining multiple functions implemented by the hardcore module based on the input-output characteristics of the hardcore module can be input into the electronic device after being analyzed by a technician. Exemplarily, the hardcore module has three functions: data preprocessing, data processing, and enabling.
[0037] The electronic device virtualizes the multiple functions implemented by the hardcore module into corresponding sub-modules one by one, thereby realizing the division of the hardcore module into multiple sub-modules.
[0038] Combined with reference Figure 3 , it shows a schematic diagram of dividing the hardcore module into multiple sub-modules provided by an embodiment of the present application. Among them, in Figure 3 part (a), the hardcore module is divided into two sub-modules, namely sub-module A and sub-module B, based on the input data of the hardcore module. Among them, PIN_D of the hardcore module is equivalent to PIN_E of sub-module A and PIN_F of sub-module B. Before splitting the hardcore module, the signal is input from PIN_A to PIN_D. After splitting the hardcore module into sub-module A and sub-module B, the signal flows from PIN_A into PIN_E and PIN_F respectively. In Figure 3 part (b), the hardcore module is divided into one sub-module, namely sub-module C, based on the output data of the hardcore module. Among them, PIN_B of the hardcore module is equivalent to PIN_G of sub-module C. Before splitting the hardcore module, the signal is input from PIN_B to PIN_C. After splitting the hardcore module into sub-module C, the signal flows from PIN_G into PIN_C.
[0039] It should be noted that the hardcore module and the sub-modules split from the hardcore module all exist in the above-mentioned specified application program. In this specified application program, timing analysis can be implemented based on the hardcore module. In addition, bitstream verification can also be implemented based on the sub-modules split from the hardcore module.
[0040] The signal path of the sub-module is used to represent the transmission path of the signal between the external input device, the sub-module, and the load. The signal path of the sub-module can be automatically generated by the electronic device based on the signal path of the hardcore module. Specifically, the electronic device splits the signal path of the hardcore module to obtain the signal paths of multiple sub-modules. In addition, the electronic device also provides parameters for characterizing the selection logic according to the circuit connection to debug the input and output of the sub-module so that it meets the input and output characteristics of the actual circuit. In other possible implementation manners, the signal path of the sub-module can also be analyzed by the technician based on the signal path of the hardcore module and then input into the electronic device.
[0041] Refer to Figure 4 , which shows a schematic diagram of the signal path of the sub-module provided by an embodiment of the present application. Figure 4 Part (a) in Figure 4 shows the signal path of sub-module A, and the signal is input from PIN_A to PIN_E; Figure 4 Part (b) in
[0042] S103. For each sub-module among the multiple sub-modules, wire the sub-module based on the signal path of the sub-module to obtain the wiring results of the multiple sub-modules.
[0043] The wiring result of each sub-module includes the connection relationship of its input port, or / and, the connection relationship of its output port. In the embodiments of the present application, the electronic device regards each sub-module as an independent module and wires each sub-module separately. Among them, the order of wiring each sub-module in the embodiments of the present application is not limited.
[0044] S104. Wire the hardcore module based on the wiring results of the multiple sub-modules to obtain the wiring result of the hardcore module.
[0045] In the embodiments of the present application, the electronic device replaces the connection relationship of the specified port in the wiring result of each sub-module with the connection relationship in the hardcore module, so as to obtain the wiring result of the hardcore module. Among them, the specified port includes the port connecting the output pin of the external input module in the sub-module, or / and, the port connecting the input pin of the load in the sub-module. Generally speaking, the electronic device performs wire-changing modification processing on the wiring result of the sub-module.
[0046] In some embodiments, the multiple sub-modules include multiple first sub-modules and a second sub-module. The first sub-module refers to a sub-module that affects timing, and the second sub-module refers to a sub-module that does not affect timing.
[0047] In this embodiment, the electronic device first wires the hardcore module in sequence according to the timing order based on the wiring results of the first sub-modules, and then wires the hardcore module based on the wiring results of the second sub-module to obtain the wiring result of the hardcore module. In this way, the timing can be ensured to be correct when wiring the hardcore module subsequently.
[0048] It should be noted that if there are multiple second sub-modules, the embodiments of the present application do not limit the order of wiring the hardcore module based on the wiring results of the second sub-modules.
[0049] In summary, the technical solution provided by the embodiments of the present application first splits the hardcore module into multiple sub-modules, determines the signal paths of each sub-module based on the signal path of the hardcore module, then wires each sub-module separately to obtain the wiring results of each sub-module, and finally generates the wiring result of the hardcore module based on the wiring results of each sub-module. Since the sub-modules are virtualized from the various functions of the hardcore module, the wiring results of the sub-modules generated based on the signal paths of the sub-modules help to sort out the internal structure of the hardcore module, and the subsequent generation of the wiring result of the hardcore module is more flexible, which can enhance the coupling with other modules in the FPGA.
[0050] Please refer to Figure 5 , which shows a flowchart of the wiring method provided by an embodiment of the present application. In the optional embodiment of the Figure 1 embodiment, S104 is replaced with S504 - S505, and the method includes the following processes.
[0051] S501, obtain the hardcore module and the signal path of the hardcore module.
[0052] S502, split the hardcore module into multiple sub-modules, and determine the signal path of each sub-module in the multiple sub-modules based on the signal path of the hardcore module.
[0053] S503, for each sub-module in the multiple sub-modules, wire the sub-module based on the signal path of the sub-module to obtain the wiring results of the multiple sub-modules.
[0054] In the embodiments of the present application, the wiring results of the multiple sub-modules include the connection relationships of the input ports of the sub-modules. Optionally, in the above connection relationships, the external input module, the multiple first multiplexers, and the input ports of the sub-modules are connected in sequence. The number of the first multiplexers is actually determined according to the signal path of the sub-module.
[0055] Combined reference Figure 6 , which shows a schematic diagram of the wiring result of the sub-module provided by an embodiment of the present application. In Figure 6 part (a), it shows the wiring result of sub-module A. Among them, PIN_A of the external input module is connected to the input end of multiplexer MUX1 (i.e., the first multiplexer), the output end of multiplexer MUX1 is connected to the input end of multiplexer MUX2 (i.e., the first multiplexer), and the output end of multiplexer MUX2 is connected to PIN_E (i.e., the input port) of sub-module A.
[0056] S504. For each sub-module among multiple sub-modules, determine a first pin corresponding to the input port of the sub-module in the hard core module.
[0057] There is a first mapping relationship between the number of the first pins and the number of external input modules connected to the input port of the sub-module. The above first mapping relationship can be determined based on the connection relationship of the input port of the sub-module. The number of the first pins and the number of external input modules connected to the input port of the sub-module may be the same or different.
[0058] S505. Change the connection relationship of the input port of the sub-module to the connection relationship of the first pin.
[0059] In some embodiments, the electronic device connects the output end of the first designated multiplexer among multiple first multiplexers to the first pin.
[0060] The first designated multiplexer refers to the first multiplexer connected to the output end of the external input module. Referring again to Figure 6 , in Figure 6 part (b), the connection of the output end of the first designated multiplexer 610, which was originally replaced by MUX2, is replaced by the first pin 620 of the hard core module.
[0061] In summary, the technical solution provided by the embodiment of the present application changes the connection relationship of the input port of the sub-module to the connection relationship of the first pin on the hard core module, so as to determine the wiring result of the hard core module according to the wiring result of the sub-module.
[0062] Please refer to Figure 7 , which shows a flowchart of the wiring method provided by an embodiment of the present application. In the optional embodiment based on Figure 1 the embodiment, S104 is replaced and implemented as S704 - S705, and the method includes the following processes.
[0063] S701. Obtain the hard core module and the signal path of the hard core module.
[0064] S702. Split the hardcore module into multiple sub-modules, and determine the signal path of each sub-module among the multiple sub-modules based on the signal path of the hardcore module.
[0065] S703. For each sub-module among the multiple sub-modules, route the sub-module based on the signal path of the sub-module to obtain the routing results of the multiple sub-modules.
[0066] In the embodiments of the present application, the routing results of the multiple sub-modules include the connection relationships of the output ports of the sub-modules. Optionally, in the above connection relationships, the output ports of the sub-modules, multiple second multiplexers, and loads are sequentially connected. The number of second multiplexers is actually determined according to the signal path of the sub-module.
[0067] Combined with reference Figure 7 , which shows a schematic diagram of the routing result of the sub-module provided by an embodiment of the present application. In Figure 7 part (a), it shows the routing result of sub-module C. Among them, PIN_G (i.e., the output port) of sub-module C is connected to the input end of multiplexer MUX3 (i.e., the second multiplexer), the two output ends of multiplexer MUX3 correspond to the two input ends of multiplexer MUX4 (i.e., the second multiplexer), and the two output ends of multiplexer MUX4 are respectively connected to load 0 and load 1.
[0068] S704. For each sub-module among the multiple sub-modules, determine the second pin corresponding to the output port of the sub-module in the hardcore module.
[0069] There is a second mapping relationship between the number of second pins and the number of loads connected to the output port of the sub-module. The above second mapping relationship can be determined based on the connection relationship of the output port of the sub-module. The number of second pins and the number of loads connected to the output port of the sub-module may be the same or different. In the embodiments of the present application, only the case where the number of loads connected to the output port of the sub-module is the same is taken as an example for illustration.
[0070] S705. Change the connection relationship of the output port of the sub-module to the connection relationship of the second pin.
[0071] The electronic device connects the second pin to the input end of the second designated multiplexer among the multiple second multiplexers.
[0072] The second designated multiplexer refers to the second multiplexer connected to the input end of the load. Referring to Figure 8 again, in Figure 8 part (b), the electronic device correspondingly connects two second pins 810 to the two input ends of the second designated multiplexer 820.
[0073] In summary, the technical solution provided by the embodiments of the present application changes the connection relationship of the output ports of the sub-modules to the connection relationship of the second pins on the hard core module, so as to determine the wiring result of the hard core module according to the wiring result of the sub-modules.
[0074] Please refer to Figure 9 , which shows a flowchart of a wiring method provided by an embodiment of the present application. In the optional embodiment based on Figure 1 the embodiment, S104 is replaced and implemented as S904-S907, and the method includes the following processes.
[0075] S901, obtain the hard core module and the signal path of the hard core module.
[0076] S902, split the hard core module into multiple sub-modules, and determine the signal path of each sub-module in the multiple sub-modules based on the signal path of the hard core module.
[0077] S903, for each sub-module in the multiple sub-modules, perform wiring on the sub-module based on the signal path of the sub-module to obtain the wiring results of the multiple sub-modules.
[0078] S904, for each sub-module in the multiple sub-modules, determine the first pin corresponding to the input port of the sub-module in the hard core module.
[0079] There is a first mapping relationship between the number of the first pins and the number of external input modules connected to the input ports of the sub-module.
[0080] S905, change the connection relationship of the input ports of the sub-module to the connection relationship of the first pins.
[0081] S906, for each sub-module in the multiple sub-modules, determine the second pin corresponding to the output port of the sub-module in the hard core module.
[0082] There is a second mapping relationship between the number of the second pins and the number of loads connected to the output ports of the sub-module.
[0083] S907, change the connection relationship of the output ports of the sub-module to the connection relationship of the second pins.
[0084] Please refer to Figure 10 , which shows a schematic diagram of a wiring device provided by an embodiment of the present application. The wiring device includes: a first acquisition module 1010, a splitting module 1020, a second acquisition module 1030, a pre-wiring module 1040, and a wiring module 1050.
[0085] The first acquisition module 1010 is used to acquire the hard core module and the signal path of the hard core module.
[0086] The splitting module 1020 is used to split the hardcore module into multiple sub-modules.
[0087] The second obtaining module 1030 is used to determine the signal path of each sub-module among the multiple sub-modules based on the signal path of the hardcore module.
[0088] The pre-routing module 1040 is used to perform routing on each sub-module among the multiple sub-modules based on the signal path of the sub-module, and obtain the routing results of the multiple sub-modules.
[0089] The routing module 1050 is used to perform routing on the hardcore module based on the routing results of the multiple sub-modules, and obtain the routing result of the hardcore module.
[0090] In some embodiments, the routing result of the sub-module includes the input port of the sub-module and the connection relationship of the input port; the routing module 1050 is used to determine, for each sub-module among the multiple sub-modules, a first pin corresponding to the input port of the sub-module in the hardcore module, where the number of the first pins has a first mapping relationship with the number of external input modules connected to the input port of the sub-module; and change the connection relationship of the input port of the sub-module to the connection relationship of the first pins.
[0091] In some embodiments, the external input module, the multiple first multiplexers, and the input port of the sub-module are connected in sequence; the routing module 1050 is used to connect the output end of the first designated multiplexer among the multiple first multiplexers to the first pin, and the first designated multiplexer refers to the first multiplexer connected to the output end of the external input module.
[0092] In some embodiments, the routing result of the sub-module includes the output port of the sub-module and the connection relationship of the output port; the routing module 1050 is used to determine, for each sub-module among the multiple sub-modules, a second pin corresponding to the output port of the sub-module in the hardcore module, where the number of the second pins has a second mapping relationship with the number of loads connected to the output port of the sub-module; and change the connection relationship of the output port of the sub-module to the connection relationship of the second pins.
[0093] In some embodiments, the output port of the sub-module, the multiple second multiplexers, and the load are connected in sequence; the routing module 1050 is used to connect the second pin to the input end of the second designated multiplexer among the multiple second multiplexers, and the second designated multiplexer refers to the second multiplexer connected to the input end of the load.
[0094] In some embodiments, the splitting module 1020 is configured to obtain the input / output characteristics of the hard core module, where the input / output characteristics of the hard core module include: the attribute information of the input data of the hard core module, and / or the attribute information of the output data of the hard core module; determine multiple functions implemented by the hard core module based on the input / output characteristics of the hard core module; and divide the hard core module into sub-modules corresponding to the multiple functions respectively based on the multiple functions implemented by the hard core module.
[0095] In some embodiments, the multiple sub-modules include multiple first sub-modules and a second sub-module. The first sub-module refers to the sub-module that affects the timing, and the second sub-module refers to the sub-module that does not affect the timing. The routing module 1050 is configured to perform routing on the hard core module in sequence based on the routing results of the first sub-modules according to the timing sequence; and perform routing on the hard core module based on the routing results of the second sub-module to obtain the routing result of the hard core module.
[0096] In summary, the technical solution provided by the embodiments of the present application first splits the hard core module into multiple sub-modules, determines the signal paths of each sub-module based on the signal paths of the hard core module, then performs routing on each sub-module respectively to obtain the routing results of each sub-module, and finally generates the routing result of the hard core module based on the routing results of each sub-module. Since the sub-modules are virtualized based on the various functions of the hard core module, the routing results of the sub-modules generated based on the signal paths of the sub-modules are helpful for sorting out the internal structure of the hard core module, and the subsequent generation of the routing result of the hard core module is more flexible, which can enhance the coupling with other modules in the FPGA.
[0097] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.
[0098] In several embodiments provided in the present application, the coupling between modules can be electrical, mechanical or other forms of coupling.
[0099] In addition, in each embodiment of the present application, the various functional modules can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
[0100] Please refer to Figure 11, which shows that an embodiment of the present application further provides an electronic device 1100. The electronic device 1100 includes: one or more processors 1110, a memory 1120, and one or more applications. Among them, one or more applications are stored in the memory 1120 and are configured to be executed by one or more processors 1110. The one or more applications are configured to execute the methods described in the above embodiments.
[0101] The processor 1110 may include one or more processing cores. The processor 1110 connects various parts within the entire battery management system using various interfaces and lines. By running or executing instructions, programs, code sets, or instruction sets stored in the memory 1120, and by calling data stored in the memory 1120, it executes various functions of the battery management system and processes data. Optionally, the processor 1110 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 1110 may integrate one or several combinations of a central processing unit 1110 (CPU), a graphics processing unit 1110 (GPU), and a modem, etc. Among them, the CPU mainly processes the operating system, user interface, and application programs, etc.; the GPU is responsible for rendering and drawing the display content; the modem is used to process wireless communication. It can be understood that the above modem may not be integrated into the processor 1110 and may be implemented separately through a communication chip.
[0102] The memory 1120 may include a random access memory 1120 (RAM), and may also include a read-only memory 1120 (ROM). The memory 1120 can be used to store instructions, programs, codes, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area. Among them, the program storage area may store instructions for implementing the operating system, instructions for implementing at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the following various method embodiments, etc. The data storage area may also store data created during the use of the electronic device diagram (such as phone book, audio and video data, chat record data, etc.).
[0103] The embodiments of the present application further provide a computer-readable storage medium, in which computer program instructions are stored and can be called by a processor to execute the methods described in the above embodiments.
[0104] The computer-readable storage medium may be an electronic memory such as a flash memory, EEPROM (electrically erasable programmable read-only memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium includes a non-transitory computer-readable storage medium. The computer-readable storage medium has a storage space for computer program instructions for executing any method steps in the above methods. These computer program instructions can be read from or written into one or more computer program products. The computer program instructions can be compressed in a suitable form.
[0105] The above are only the preferred embodiments of the present application and do not impose any formal restrictions on the present application. Although the present application has been disclosed above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present application. However, as long as it does not depart from the content of the technical solution of the present application, any brief modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present application still fall within the scope of the technical solution of the present application.
Claims
1. A wiring method, characterized in that: The method comprises: Acquire a hard core module and a signal path of the hard core module; Splitting the hard core module into a plurality of sub-modules, and determining a signal path of each of the plurality of sub-modules based on a signal path of the hard core module; For each of the plurality of submodules, wiring is performed on the submodule based on a signal path of the submodule to obtain wiring results of the plurality of submodules; The hard core module is wired based on the wiring results of the multiple sub-modules to obtain the wiring result of the hard core module.
2. The method according to claim 1, characterized in that The wiring result of the submodule includes the input port of the submodule and the connection relationship of the input port; The wiring of the hard core module based on the wiring results of the multiple sub-modules to obtain the wiring result of the hard core module includes: For each of the plurality of submodules, determining in the hard core module a first pin corresponding to an input port of the submodule, wherein a first mapping relationship exists between the number of the first pins and the number of external input modules connected to the input port of the submodule; The connection relationship of the input port of the submodule is changed to the connection relationship of the first pin.
3. The method according to claim 2, characterized in that The external input module, the plurality of first multiplexers, and the input ports of the submodules are connected in sequence; The step of changing the connection relationship of the port of the submodule to the connection relationship of the first pin includes: An output terminal of a first designated multiplexer among the plurality of first multiplexers is connected to the first pin, wherein the first designated multiplexer is a first multiplexer connected to an output terminal of the external input module.
4. The method according to claim 1, characterized in that The wiring result of the submodule includes the output port of the submodule and the connection relationship of the output port; The wiring of the hard core module based on the wiring results of the multiple sub-modules to obtain the wiring result of the hard core module includes: For each of the plurality of submodules, determining in the hard core module a second pin corresponding to an output port of the submodule, wherein a second mapping relationship exists between the number of the second pins and the number of loads connected to the output port of the submodule; The connection relationship of the output port of the submodule is changed to the connection relationship of the second pin.
5. The method according to claim 4, characterized in that The output port of the submodule, the plurality of second multiplexers, and the load are connected in sequence; The step of changing the connection relationship of the output port of the submodule to the connection relationship of the second pin includes: The second pin is connected to an input terminal of a second designated multiplexer among the plurality of second multiplexers, where the second designated multiplexer is a second multiplexer connected to an input terminal of the load.
6. The method according to any one of claims 1 to 5, characterized in that The hard core module is divided into a plurality of sub-modules, including: Acquiring input and output characteristics of the hard core module, wherein the input and output characteristics of the hard core module include: attribute information of input data of the hard core module, and / or attribute information of output data of the hard core module; Determining multiple functions implemented by the hard core module based on the input and output characteristics of the hard core module; Based on the multiple functions implemented by the hard core module, the hard core module is divided into sub-modules corresponding to the multiple functions respectively.
7. The method according to any one of claims 1 to 5, characterized in that The multiple submodules include multiple first submodules and second submodules, the first submodules refer to submodules that affect the timing, and the second submodules refer to submodules that do not affect the timing; The wiring of the hard core module based on the wiring results of the multiple sub-modules to obtain the wiring result of the hard core module includes: According to the timing sequence, the hard core module is wired based on the wiring result of the first submodule; as well as, Based on the wiring result of the second submodule, the hard core module is wired to obtain the wiring result of the hard core module.
8. A wiring device, characterized in that: The device comprises: A first acquisition module, used to acquire a hard core module and a signal path of the hard core module; A splitting module, used for splitting the hard core module into multiple sub-modules; A second acquisition module, configured to determine a signal path of each of the plurality of submodules based on a signal path of the hard core module; A pre-wiring module, configured to perform wiring on each of the plurality of sub-modules based on a signal path of the sub-module to obtain wiring results of the plurality of sub-modules; A wiring module is used to perform wiring on the hard core module based on the wiring results of the multiple sub-modules to obtain the wiring result of the hard core module.
9. An electronic device, characterized in that: include: Memory; One or more processors coupled to the memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the method according to any one of claims 1-7.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and the computer program instructions can be called by a processor to execute the method according to any one of claims 1 to 7.