Preparation method of germanium-on-insulator substrate structure

Abstract

The invention discloses a preparation method of a germanium-on-insulator substrate structure, which belongs to the field of semiconductor design and manufacture, and comprises the following steps: preparing a first wafer and a second wafer, the first wafer being a germanium wafer substrate bare chip, and the second wafer being a silicon wafer substrate bare chip; carrying out surface modification treatment on the surface of the first wafer through an ion implantation process; performing hydrogen ion implantation and carbon ion implantation on the first wafer; performing thermal oxidation treatment on the surface of the second wafer; combining the surfaces of the first wafer and the second wafer through a bonding process; stripping the first wafer along the hydrogen injection layer, and recrystallizing the top germanium film through thermal annealing treatment; and etching the top-layer germanium film to be below the carbon injection layer through wet etching treatment, so that the top-layer germanium film reaches the required thickness. According to the method, the problem that the germanium-on-insulator structure with relatively good quality is difficult to obtain can be solved, and meanwhile, the problems that the thickness of the top layer germanium film of the substrate structure is difficult to prepare and control, the thickness of the crystal edge film is non-uniform and more surface defects exist are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and manufacturing, and particularly relates to a method for preparing a germanium-on-insulator substrate structure. Background Art

[0002] As the Bulk CMOS technology node reaches below 28 nm, during the continuous miniaturization of the feature size of MOSFET transistors, although their operating speed is getting faster and faster, the short channel effects (SCE) are becoming more and more significant. Based on the silicon material itself, it has also approached the physical and technical limits. Therefore, innovative technologies are needed for the manufacturing process and device structure to achieve further development. The traditional planar MOSFET structure is no longer applicable. Among potential technologies, the channel structure composed of heterogeneous material structures, especially silicon-germanium materials, due to the higher carrier mobility of germanium than silicon materials, the silicon-germanium material heterogeneous structure is one of the effective technologies and becomes a solution for advanced chips. For example, directly bonding germanium to a silicon wafer with a silicon dioxide insulating layer to form a germanium-on-insulator (GeOI) structure, which is a silicon-germanium material with high hole mobility and has excellent application development prospects. Germanium can also be used to realize photodetectors with common wavelengths of 1.3 μm and 1.55 μm. The germanium photodiode realized on the GeOI substrate can be applied with lower parasitics and higher quantum efficiency at a given wavelength. In this structure, the insulating Bragg reflector can be further improved to replace the insulator. Since silicon is transparent at these wavelengths, backside illumination of the silicon wafer with germanium diodes can be achieved.

[0003] The disadvantages of the prior art are that in GeOI technology, if a germanium material layer is directly formed on the insulating oxide layer, due to the poor quality of the germanium oxide contact interface generated between the germanium material and the insulating oxide, especially the high interface state density, it will cause serious scattering and leakage, thereby affecting device performance. Moreover, the adhesion between germanium and silicon dioxide is very poor, making it difficult to bond germanium to silicon dioxide by a direct bonding method. Another limiting factor for germanium oxide is that the melting point of germanium is relatively low (about 937 °C), which forces the use of a low bonding temperature (about 650 °C or below). Another problem with germanium oxide is that germanium oxide is soluble in water. Therefore, during the cleaning process in an aqueous solvent, germanium oxide will be removed. Therefore, germanium substrates have not yet been used to fabricate metal oxide semiconductor field effect transistors (MOSFETs). Therefore, an improved method to avoid the formation of germanium oxide is needed to fabricate a germanium-on-insulator substrate structure. Summary of the Invention

[0004] Based on the technical problems existing in the prior art, the present invention provides a method for preparing a germanium-on-insulator substrate structure, which solves the problem that it is difficult to obtain a germanium-on-insulator structure with good quality in the prior art, and at the same time solves the problems that the thickness of the top germanium thin film of the substrate structure is difficult to prepare and is not easy to control, the film thickness of the crystal edge is uneven, and there are many surface defects.

[0005] According to the technical solution of the present invention, the present invention provides a method for preparing a germanium-on-insulator substrate structure, including the following steps:

[0006] Step S1, prepare a first wafer and a second wafer, the first wafer is a germanium wafer substrate bare chip, and the second wafer is a silicon wafer substrate bare chip;

[0007] Step S2, perform surface modification treatment on the surface of the first wafer by an ion implantation process to form a surface modification layer;

[0008] Step S3, perform hydrogen ion implantation and carbon ion implantation processes on the first wafer, so that a hydrogen implantation layer is formed under the surface modification layer of the first wafer, and a carbon implantation layer is formed between the hydrogen implantation layer and the surface modification layer;

[0009] Step S4, perform thermal oxidation treatment on the surface of the second wafer to form an insulating oxide layer;

[0010] Step S5, after cleaning the surfaces of the first wafer and the second wafer, combine the surface of the surface modification layer of the first wafer with the surface of the insulating oxide layer of the second wafer through a bonding process;

[0011] Step S6, strip the first wafer along the hydrogen implantation layer, and the remaining part forms a top germanium thin film on the second wafer, and then perform recrystallization on the top germanium thin film through thermal annealing treatment;

[0012] Step S7, etch the top germanium thin film to below the carbon implantation layer through wet etching treatment so that the top germanium thin film reaches the required thickness.

[0013] In some embodiments, in step S2, the ions used in the ion implantation process are one or a combination of two or more of carbon ions, nitrogen ions, hydrogen ions, helium ions, and argon ions.

[0014] In some embodiments, in step S2, the ion implantation process is low-temperature ion implantation, and the temperature of the ion implantation process ≤ 0 °C.

[0015] In some embodiments, in step S3, the dose of hydrogen ion implantation is higher than the dose of carbon ion implantation.

[0016] In some embodiments, in step S3, the process parameters of hydrogen ion implantation include an implantation energy of 50 keV to 200 keV and an implantation dose of 1×1016 atoms / cm2 to 1×1018 atoms / cm2;

[0017] And / or, the process parameters of carbon ion implantation include an implantation energy of 50 eV to 10 keV and an implantation dose of 1×1014 atoms / cm2 to 1×1016 atoms / cm2.

[0018] In some embodiments, in step S3, the hydrogen ion implantation temperature ≤ 60°C;

[0019] And / or, the carbon ion implantation temperature ≤ 0°C.

[0020] In some embodiments, in step S5, the bonding process is a low-temperature bonding process, and the bonding process temperature ≤ 200°C.

[0021] In some embodiments, in step S6, the thermal annealing treatment is a high-temperature thermal annealing treatment, and the temperature of the thermal annealing treatment ≥ 500°C.

[0022] In some embodiments, after step S7, the top germanium thin film reaches the required ultra-thin thickness, and the ultra-thin thickness is ≤ 20 nm.

[0023] Compared with the prior art, the beneficial technical effects of the present invention are as follows:

[0024] In the method for preparing a germanium-on-insulator substrate structure of the present invention, surface modification treatment and a bonding process (preferably low-temperature bonding) are used to improve the contact interface between the germanium material and the insulating oxide; by implanting hydrogen ions, a relatively flat weakening layer is formed at a certain depth position in the wafer to facilitate subsequent peeling; then carbon ions are implanted to form a relatively flat barrier layer at another relatively shallow depth position. The large characteristics of carbon ions are used to block the diffusion of hydrogen ions to the wafer surface, and at the same time, carbon ions will not cause device changes to the top germanium thin film; and, in the subsequent wet etching process, when etching to the barrier layer, the etching rate will slow down a lot. The appearance of this phenomenon indicates that the etching has reached this layer position, and at this time, stopping the etching can retain the required film thickness. In this way, it is possible to effectively control the top germanium thin film to reach the required ultra-thin thickness, and the wet etching process makes the film uniformity consistent, the thickness difference can be less than 2%, and the surface is defect-free; the top germanium ultra-thin film of the germanium-on-insulator substrate structure prepared by the method of the present invention has controllable thickness, good film uniformity, a relatively flat surface of the substrate structure, few surface defects, and good single crystal properties are maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a flowchart of the method provided by the present invention.

[0026] Description of reference numerals in the accompanying drawings:

[0027] A, the first wafer; B, the second wafer; 1, surface modification layer; 2, hydrogen implantation layer; 3, carbon implantation layer; 4, insulating oxide layer; 5, top germanium thin film. Detailed implementation manners

[0028] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0029] In addition, it should be noted that for the convenience of description, only parts related to the relevant invention are shown in the accompanying drawings. Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0030] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the order or mutual dependence relationship of the functions executed by these devices, modules or units.

[0031] It should be noted that the modifications of "one" and "plural" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless clearly specified otherwise in the context, it should be understood as "one or more".

[0032] The present invention provides a method for preparing a germanium-on-insulator substrate structure, belonging to the field of semiconductor design and manufacturing. A typical preparation method includes: preparing two bare wafer substrates A and B, where the bare wafer substrate A is a germanium wafer and the bare wafer substrate B is a silicon wafer; performing an ion implantation process on the surface of wafer A to carry out surface modification treatment; performing hydrogen ion implantation and low-temperature carbon ion implantation processes on wafer A, and performing a thermal oxidation treatment on the surface of wafer B; first cleaning the surfaces of wafer A and wafer B, and then performing low-temperature bonding; peeling off wafer A to form a top germanium thin film, and then subjecting the top germanium thin film to recrystallization by high-temperature thermal annealing; using a wet etching process to etch the top germanium to an ultra-thin film thickness. Without changing the sandwich structure of GeOI, the present invention improves the preparation method of GeOI, aiming to solve the foregoing disadvantages of the prior art, and at the same time solve the problems in the prior art that it is difficult to prepare and control the ultra-thin film thickness of the top germanium of the GeOI substrate structure, the film thickness is uneven at the wafer edge, and there are many surface defects.

[0033] Please refer to Figure 1 , a method for preparing a germanium-on-insulator substrate structure of the present invention, includes the following steps.

[0034] Step S1, prepare a first wafer A and a second wafer B. The first wafer A is a bare germanium wafer substrate, and the second wafer B is a bare silicon wafer substrate.

[0035] Step S2, perform surface modification treatment on the surface of the first wafer A through an ion implantation process to form a surface modification layer 1. Specifically, in this step S2, the ions used in the ion implantation process are one or a combination of two or more of carbon ions, nitrogen ions, hydrogen ions, helium ions, and argon ions. And preferably, the ion implantation process is a low-temperature ion implantation, and the temperature of the ion implantation process is, for example, ≤0°C.

[0036] Step S3, perform hydrogen ion implantation and carbon ion implantation processes on the first wafer A, so that a hydrogen implantation layer 2 is formed below the surface modification layer 1 on the first wafer A, and a carbon implantation layer 3 is formed between the hydrogen implantation layer 2 and the surface modification layer 1. The relative positions of the hydrogen ions and carbon ions are close, and the hydrogen implantation layer 2 is located below the carbon implantation layer 3 (at a deeper position from the surface). In a typical embodiment, a high dose of hydrogen ions (at room temperature) and a low dose of carbon ions (at low temperature) are sequentially implanted into the first wafer A (germanium wafer).

[0037] Step S4, perform a thermal oxidation treatment on the surface of the second wafer B (silicon wafer) to form an insulating oxide layer 4. The insulating oxide layer 4 is specifically a high-quality, low-defect silicon dioxide layer.

[0038] Step S5, after surface cleaning of the first wafer A and the second wafer B, the surface of the surface modification layer 1 of the first wafer A is combined with the surface of the insulating oxide layer 4 of the second wafer B through a bonding process. In the embodiment, when performing the bonding process, the first wafer A is flipped and inverted on the upper surface of the second wafer B. Preferably, the bonding process is a low-temperature bonding process, and the bonding process temperature is, for example, ≤200°C.

[0039] Step S6, the first wafer A is peeled off along the hydrogen implantation layer 2, and the remaining part of the first wafer A forms the top germanium thin film 5 on the second wafer B, and then the top germanium thin film 5 is recrystallized through a thermal annealing process. Preferably, the thermal annealing process is a high-temperature thermal annealing process, and the temperature of the thermal annealing process is, for example, ≥500°C.

[0040] Step S7, the top germanium thin film 5 is etched below the carbon implantation layer 3 through a wet etching process to make the top germanium thin film 5 reach the required thickness. Among them, the carbon implantation layer 3 formed through wet etching and the previous process can accurately control the thickness of the top germanium thin film 5. Preferably, after step S7, the top germanium thin film 5 reaches the required ultra-thin thickness, and the ultra-thin thickness is ≤20 nm. After step S7, the germanium-on-insulator substrate structure is obtained, which is a silicon substrate (formed by the second wafer B), an insulating oxide layer 4, a surface modification layer 1 (serving as an interface layer in the structure), and a top germanium thin film 5 stacked in sequence.

[0041] It should be noted that in the present invention, hydrogen ions are first implanted in step S3. The hydrogen ions are relatively small and are implanted into a deeper position in the wafer to form a structure similar to bubbles, which is a weakened layer of the wafer structure. In subsequent steps, peeling can be accurately performed along this layer to initially obtain the top structure of the germanium-on-insulator substrate. Among them, the hydrogen ion implantation is preferably a high dose. Compared with low-dose implantation, high-dose implantation can make the hydrogen implantation layer 2 smoother, that is, the surface generated after peeling is smoother. After implanting hydrogen ions, carbon ions are implanted to form a barrier layer. The implanted hydrogen will diffuse, and a carbon implantation layer 3 is formed above the hydrogen implantation layer 2. Since the carbon ions are relatively large, they can block the diffusion of hydrogen, so that hydrogen cannot diffuse above the carbon implantation layer 3, ensuring that the part above the carbon implantation layer 3 (that is, the finally obtained top germanium thin film 5) does not contain hydrogen, avoiding affecting the device performance. Among them, the carbon ion implantation is preferably a low dose. A small amount of carbon has basically no effect on the device performance, but it also belongs to doping, and the effect can be achieved, and not too much is needed. Too much will also have negative effects, such as bringing negative electrical effects, large lattice damage, and affecting the recrystallization repair process of subsequent thermal annealing.

[0042] For the diffusion of hydrogen ions, the carbon implantation layer 3 serves as an ion diffusion barrier layer. For the wet etching step, the carbon implantation layer 3 also serves as a wet etching barrier layer. During the wet etching in step S7, the etching rate above the carbon implantation layer 3 (i.e., the etching rate for the germanium wafer) is very fast, and the etching rate significantly decreases when etching reaches the carbon implantation layer 3. Therefore, it is possible to know that the top germanium thin film 5 has been etched to the position of the carbon implantation layer 3 through the change in the etching rate (which will be directly reflected in the corresponding etching equipment or can be obtained in real time through data processing). This facilitates stopping the etching through manual control or system automatic control, so that the top germanium thin film 5 retains the required ultra-thin thickness.

[0043] As a supplementary explanation, the depths of the hydrogen implantation layer 2 and the carbon implantation layer 3 are based on the implantation energy. For the same type of ions, the greater the implantation energy, the deeper the ions penetrate below the substrate surface. When the implantation energy of the injected ions is the same, a layer structure with a specific depth will be formed. The implantation depths of the hydrogen implantation layer 2 and the carbon implantation layer 3 and the corresponding implantation energies are designed to achieve the required effects. Especially for carbon ion implantation, the position of the carbon implantation layer 3 is directly related to the thickness of the finally obtained top germanium thin film 5.

[0044] Preferably, in step S3, the dose of hydrogen ion implantation is higher than the dose of carbon ion implantation. Further, the process parameters of hydrogen ion implantation, for example, include an implantation energy of 50 keV to 200 keV and an implantation dose of 1×10^16 atoms / cm² to 1×10^18 atoms / cm²; and / or, the process parameters of carbon ion implantation, for example, include an implantation energy of 50 eV to 10 keV and an implantation dose of 1×10^14 atoms / cm² to 1×10^16 atoms / cm².

[0045] Preferably, in step S3, the temperature condition for hydrogen ion implantation is ≤60°C; and / or, the temperature condition for carbon ion implantation is ≤0°C. The carbon ion implantation uses a low-temperature ion implantation process, which can avoid the ion diffusion during ion implantation, control the carbon ions to be uniformly implanted into a certain position in the wafer, with precise position and narrow distribution range, that is, a carbon implantation layer 3 with precise position and flatness is formed. Similarly, the temperature for hydrogen ion implantation should not be too high. Furthermore, in the case of low-temperature implantation, a lower dose implantation can be selected to further avoid lattice damage and reduce defects.

[0046] In summary, in the method for preparing a germanium-on-insulator substrate structure of the present invention, surface modification treatment and a bonding process (preferably low-temperature bonding) are used to improve the contact interface between the germanium material and the insulating oxide; by implanting hydrogen ions, a relatively flat weakening layer is formed at a certain depth in the wafer to facilitate subsequent peeling; then carbon ions are implanted to form a relatively flat barrier layer at another relatively shallow depth position. The large size of the carbon ions is used to block the diffusion of hydrogen ions to the wafer surface, and at the same time, the carbon ions will not cause device changes to the top germanium thin film; and, when performing a wet etching process subsequently, when etching reaches the barrier layer, the etching rate will slow down significantly. The occurrence of this phenomenon indicates that the etching has reached this layer position, and at this time, stopping the etching can retain the required film thickness. In this way, it is possible to effectively control the top germanium thin film to reach the required ultra-thin thickness, and the wet etching process makes the film uniformity consistent, with a thickness difference of less than 2% achievable, and no surface defects; the thickness of the top germanium ultra-thin film of the germanium-on-insulator substrate structure prepared by the method of the present invention is controllable, the film has good uniformity, the surface of the substrate structure is relatively flat, has few surface defects, and maintains good single crystal properties.

[0047] In addition to having a high carrier mobility, germanium on insulator (GeOI) substrates also has some other advantages. For example, the contact resistance and the temperature required for dopant activation are lower than those required for silicon, which facilitates the formation of shallow junctions. For transistors fabricated using GeOI technology, the germanium thin film defines the source-drain junction depth and depletion region, which can improve short-channel effects such as DIBL (Drain Induced Barrier Lowering), further improve the subthreshold characteristics of the device, and reduce the static power consumption of the circuit. In addition, GeOI transistors do not require channel doping, which can avoid effects such as RDF (Random Dopants Fluctuation) and the reduction of carrier mobility, and maintain a stable threshold voltage (Vth). Different from the 3D transistor structure used in FinFET technology, GeOI is a planar process technology, which can effectively reduce the process complexity. Compared with the traditional Bulk Silicon technology, GeOI can provide better transistor electrostatic characteristics, and the buried oxide layer can reduce the parasitic capacitance between the source and the drain. In addition, this technology can effectively limit the electron flow between the source and the drain, significantly reducing the leakage current performance of the device. In addition to through the gate, GeOI can also control the transistor behavior through the bottom substrate of the device to achieve the back bias control function. Germanium can also be used to implement photodetectors with common wavelengths of 1.3 μm and 1.55 μm. The germanium photodiode implemented on the GeOI substrate can be applied with lower parasitics and higher quantum efficiency at a given wavelength. In this structure, the insulating Bragg reflector can be further improved to replace the insulator. Since silicon is transparent at these wavelengths, backside illumination of the silicon wafer with germanium diodes can be achieved.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a germanium-on-insulator substrate structure, characterized in that: The steps include: Step S1, preparing a first wafer (A) and a second wafer (B), wherein the first wafer (A) is a germanium wafer substrate bare die, and the second wafer (B) is a silicon wafer substrate bare die; Step S2, performing surface modification treatment on the surface of the first wafer (A) by an ion implantation process to form a surface modification layer (1); Step S3, performing hydrogen ion implantation and carbon ion implantation processes on the first wafer (A), so that a hydrogen implantation layer (2) is formed below the surface modification layer (1) of the first wafer (A), and a carbon implantation layer (3) is formed between the hydrogen implantation layer (2) and the surface modification layer (1); Step S4, performing thermal oxidation treatment on the surface of the second wafer (B) to form an insulating oxide layer (4); Step S5, after cleaning the surfaces of the first wafer (A) and the second wafer (B), the surface of the surface modified layer (1) of the first wafer (A) is bonded to the surface of the insulating oxide layer (4) of the second wafer (B) through a bonding process; Step S6, peeling off the first wafer (A) along the hydrogen implantation layer (2), and forming the remaining portion of the first wafer (A) as a top germanium film (5) on the second wafer (B), and then performing a thermal annealing treatment to recrystallize the top germanium film (5); Step S7, etching the top germanium film (5) to below the carbon injection layer (3) by wet etching, so that the top germanium film (5) reaches a desired thickness.

2. The method for preparing a germanium-on-insulator substrate structure according to claim 1, characterized in that: In step S2, the ions used in the ion implantation process are one or a combination of two or more of carbon ions, nitrogen ions, hydrogen ions, helium ions, and argon ions.

3. The method for preparing a germanium-on-insulator substrate structure according to claim 1, characterized in that: In step S2, the ion implantation process is low-temperature ion implantation, and the ion implantation process temperature is ≤0°C.

4. The method for preparing a germanium-on-insulator substrate structure according to claim 1, characterized in that: In step S3 , the dosage of hydrogen ion implantation is higher than the dosage of carbon ion implantation.

5. The method for preparing a germanium-on-insulator substrate structure according to claim 1, characterized in that: In step S3, the process parameters of hydrogen ion implantation include implantation energy: 50keV to 200keV, implantation dose: 1×1016atoms / cm2 to 1×1018atoms / cm2; And / or, the process parameters of carbon ion implantation include implantation energy: 50 eV to 10 keV, implantation dose: 1×1014 atoms / cm2 to 1×1016 atoms / cm2.

6. The method for preparing a germanium-on-insulator substrate structure according to claim 1, characterized in that: In step S3, the hydrogen ion implantation temperature is ≤ 60°C; And / or, the carbon ion implantation temperature is ≤ 0°C.

7. The method for preparing a germanium-on-insulator substrate structure according to claim 1, characterized in that: In step S5, the bonding process is a low-temperature bonding process, and the bonding process temperature is ≤200°C.

8. The method for preparing a germanium-on-insulator substrate structure according to claim 1, characterized in that: In step S6, the thermal annealing treatment is a high temperature thermal annealing treatment, and the temperature of the thermal annealing treatment is ≥500°C.

9. The method for preparing a germanium-on-insulator substrate structure according to claim 1, characterized in that: After step S7, the top germanium film (5) reaches the required ultra-thin thickness, which is ≤20 nm.

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