Adapter plate structure, preparation method thereof and packaging structure

Abstract

The invention provides an adapter plate structure, a preparation method thereof and a packaging structure. The adapter plate structure comprises a wafer, at least one first metal wiring layer, at least one second metal wiring layer and a plurality of conductive columns, the multiple conductive columns penetrate through the wafer, and the at least one first metal wiring layer and the at least one second metal wiring layer are located on the two sides of the wafer in the first direction; the non-active surface of the first sub-wafer is bonded with the non-active surface of the second sub-wafer; the plurality of first sub-conductive columns penetrate through the first sub-wafer, the plurality of second sub-conductive columns penetrate through the second sub-wafer, and the first sub-conductive columns and the second sub-conductive columns are correspondingly and electrically connected; the at least one first metal wiring layer is located on the active surface of the first sub-wafer and is electrically connected with the plurality of first sub-conductive columns; and the at least one second metal wiring layer is positioned on the active surface of the second sub-wafer and is electrically connected with the plurality of second sub-conductive columns.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to an interposer structure, a preparation method thereof, and a packaging structure. Background Art

[0002] As the chip manufacturing process approaches the physical limit, it is gradually difficult to reduce the size, and the advanced packaging technology using multi-chip stacking has become one of the best ways to continue Moore's Law. The advanced packaging technology refers to stacking multiple chips vertically or large-sized chips based on a silicon interposer, which can greatly reduce the interconnect length brought by traditional packaging and improve the interconnect density.

[0003] Due to the different coefficients of thermal expansion between different materials, in the process of forming the metal wiring layer, the wafer often warps due to the thermal expansion mismatch of the materials. In the field of integrated circuit packaging technology, the warping problem of the 2.5D silicon interposer is a common problem, which has an important impact on the reliability and production yield of products. Summary of the Invention

[0004] Embodiments of the present disclosure provide an interposer structure, a preparation method thereof, and a packaging structure.

[0005] In a first aspect, embodiments of the present disclosure provide an interposer structure, the interposer structure including a wafer, at least one first metal wiring layer, at least one second metal wiring layer, and a plurality of conductive pillars; the plurality of conductive pillars penetrate through the wafer, and the at least one first metal wiring layer and the at least one second metal wiring layer are located on two sides of the wafer along a first direction;

[0006] The wafer includes a first sub-wafer and a second sub-wafer stacked along the first direction, and the non-active surfaces of the first sub-wafer and the second sub-wafer are bonded; the conductive pillars include first sub-conductive pillars and second sub-conductive pillars, the plurality of first sub-conductive pillars penetrate through the first sub-wafer, the plurality of second sub-conductive pillars penetrate through the second sub-wafer, and the first sub-conductive pillars and the second sub-conductive pillars are correspondingly electrically connected;

[0007] The at least one first metal wiring layer is located on the active surface of the first sub-wafer and is electrically connected to the plurality of first sub-conductive pillars; the at least one second metal wiring layer is located on the active surface of the second sub-wafer and is electrically connected to the plurality of second sub-conductive pillars.

[0008] In some embodiments, the non-active surfaces of the first sub-wafer and the second sub-wafer are directly bonded; or,

[0009] The transfer board structure further includes a plurality of bonding structures located between the first sub-wafer and the second sub-wafer, and the non-active surfaces of the first sub-wafer and the second sub-wafer are bonded through the plurality of bonding structures.

[0010] In some embodiments, the bonding structure includes a first sub-bonding structure and a second sub-bonding structure;

[0011] On the non-active surface of the first sub-wafer, the plurality of first sub-bonding structures and the plurality of first sub-conductive pillars are correspondingly connected;

[0012] On the non-active surface of the second sub-wafer, the plurality of second sub-bonding structures and the plurality of second sub-conductive pillars are correspondingly connected.

[0013] In some embodiments, the difference between the first thickness of all the first metal wiring layers and the second thickness of all the second metal wiring layers satisfies a preset condition.

[0014] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a transfer board structure, the method including:

[0015] Providing a first initial sub-wafer and a second initial sub-wafer;

[0016] Forming a plurality of first sub-conductive pillars in the first initial sub-wafer and forming a plurality of second sub-conductive pillars in the second initial sub-wafer;

[0017] Forming at least one first metal wiring layer on the active surface of the first initial sub-wafer and forming at least one second metal wiring layer on the active surface of the second initial sub-wafer; the at least one first metal wiring layer is electrically connected to the plurality of first sub-conductive pillars, and the at least one second metal wiring layer is electrically connected to the plurality of second sub-conductive pillars;

[0018] Removing a part of the first initial sub-wafer to obtain a first sub-wafer, and the plurality of first sub-conductive pillars penetrate the first sub-wafer; and removing a part of the second initial sub-wafer to obtain a second sub-wafer, and the plurality of second sub-conductive pillars penetrate the second sub-wafer;

[0019] Performing a bonding process on the non-active surfaces of the first sub-wafer and the second sub-wafer; the first sub-conductive pillars and the second sub-conductive pillars are correspondingly electrically connected.

[0020] In some embodiments, the removing a part of the first initial sub-wafer includes:

[0021] Performing a bonding process on the first carrier wafer and the at least one first metal wiring layer;

[0022] Flip the first initial sub-wafer;

[0023] On the non-active surface of the first initial sub-wafer, remove a part of the first initial sub-wafer to expose a plurality of the first sub-conductive posts;

[0024] The removing a part of the second initial sub-wafer includes:

[0025] Perform a bonding process on the second carrier wafer and the at least one second metal wiring layer;

[0026] Flip the second initial sub-wafer;

[0027] On the non-active surface of the second initial sub-wafer, remove a part of the second initial sub-wafer to expose a plurality of the second sub-conductive posts.

[0028] In some embodiments, after performing the bonding process on the non-active surfaces of the first sub-wafer and the second sub-wafer, the method further includes:

[0029] Perform a debonding process on the first carrier wafer and the at least one first metal wiring layer, and / or perform a debonding process on the second carrier wafer and the at least one second metal wiring layer.

[0030] In some embodiments, the performing the bonding process on the non-active surfaces of the first sub-wafer and the second sub-wafer includes:

[0031] Directly bond the non-active surface of the first sub-wafer and the non-active surface of the second sub-wafer; or,

[0032] Bond the non-active surface of the first sub-wafer and the non-active surface of the second sub-wafer through a plurality of bonding structures.

[0033] In some embodiments, the bonding the non-active surface of the first sub-wafer and the non-active surface of the second sub-wafer through a plurality of bonding structures includes:

[0034] Form a plurality of first sub-bonding structures on the non-active surface of the first sub-wafer, and connect the plurality of first sub-bonding structures to the plurality of first sub-conductive posts correspondingly;

[0035] Form a plurality of second sub-bonding structures on the non-active surface of the second sub-wafer, and connect the plurality of second sub-bonding structures to the plurality of second sub-conductive posts correspondingly;

[0036] Bond the first sub-bonding structure and the second sub-bonding structure so that the non-active surfaces of the first sub-wafer and the second sub-wafer are bonded through the plurality of bonding structures; the first sub-bonding structure and the second sub-bonding structure constitute the bonding structure.

[0037] In a third aspect, an embodiment of the present disclosure provides a packaging structure, and the packaging structure includes the interposer structure according to any one of the first aspects.

[0038] The present disclosure provides an interposer structure, a preparation method thereof, and a packaging structure. The interposer structure includes a wafer, at least one first metal wiring layer, at least one second metal wiring layer, and a plurality of conductive posts; the plurality of conductive posts penetrate the wafer, and at least one first metal wiring layer and at least one second metal wiring layer are located on both sides of the wafer along a first direction; the wafer includes a first sub-wafer and a second sub-wafer stacked along the first direction, and the non-active surfaces of the first sub-wafer and the second sub-wafer are bonded; the conductive posts include first sub-conductive posts and second sub-conductive posts, the plurality of first sub-conductive posts penetrate the first sub-wafer, the plurality of second sub-conductive posts penetrate the second sub-wafer, and the first sub-conductive posts and the second sub-conductive posts are correspondingly electrically connected; at least one first metal wiring layer is located on the active surface of the first sub-wafer and is electrically connected to the plurality of first sub-conductive posts; at least one second metal wiring layer is located on the active surface of the second sub-wafer and is electrically connected to the plurality of second sub-conductive posts. In this way, not only can multiple layers of high-density metal wiring layers be formed on the surface of the wafer, increasing the number of wiring layers and the density of the metal wiring layers, but also the first metal wiring layer and the second metal wiring layer can be respectively formed on the upper and lower surfaces of the wafer, and the stresses on both sides of the wafer can cancel each other out, greatly improving the problem of wafer warping. Description of the Drawings

[0039] In the drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0040] Figure 1 Schematic diagram of the composition structure of an interposer structure provided by an embodiment of the present disclosure Figure 1 ;

[0041] Figure 2 Schematic diagram of the composition structure of an interposer structure provided by an embodiment of the present disclosure Figure 2 ;

[0042] Figure 3 Schematic flowchart of a preparation method of an interposer structure provided by an embodiment of the present disclosure;

[0043] Figure 4 Schematic of the preparation process of an adapter board structure provided by an embodiment of the present disclosure Figure 1 ;

[0044] Figure 5 Schematic of the preparation process of an adapter board structure provided by an embodiment of the present disclosure Figure 2 ;

[0045] Figure 6 Schematic of the preparation process of an adapter board structure provided by an embodiment of the present disclosure Figure 3 ;

[0046] Figure 7 Schematic of the preparation process of an adapter board structure provided by an embodiment of the present disclosure Figure 4 ;

[0047] Figure 8 Schematic of the preparation process of an adapter board structure provided by an embodiment of the present disclosure Figure 5 ;

[0048] Figure 9 Schematic of the preparation process of an adapter board structure provided by an embodiment of the present disclosure Figure 6 ;

[0049] Figure 10 Schematic of the preparation process of an adapter board structure provided by an embodiment of the present disclosure Figure 7 ;

[0050] Figure 11 Schematic of the preparation process of an adapter board structure provided by an embodiment of the present disclosure Figure 8 ;

[0051] Figure 12 Schematic of the component structure of a packaging structure Detailed implementation manners

[0052] Hereinafter, the exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0053] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known to the art are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0054] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. Throughout the drawings, like reference numerals indicate like elements.

[0055] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer or portion discussed below may be denoted as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present disclosure.

[0056] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0057] With the continuous progress of semiconductor processes and technologies, chips and electronic products are developing towards miniaturization, high density and high performance. Integrating chips with higher performance and more functions in a limited area has become an inevitable trend. At the same time, with the gradual slowdown of Moore's Law, chip stacking and advanced packaging technologies can not only make up for the limitations of Moore's Law slowdown to a certain extent, but also show significant advantages in some aspects. Among them, Moore's Law states that: "The number of circuits integrated on an integrated circuit chip doubles every 18 - 24 months; the performance of a microprocessor doubles, or the price is halved."

[0058] The main material of the wafer is silicon. The metal wiring layer includes metal, and the metal wiring layer is formed in the dielectric layer. In the process of forming the metal wiring layer, a heating and cooling process is required. Due to the different coefficients of thermal expansion between different materials, such as the different coefficients of thermal expansion between silicon and metal, and silicon and the dielectric layer, the wafer often warps due to the thermal expansion mismatch of the materials. Among them, warping can refer to overall warping, with the entire wafer warping upward or downward.

[0059] In the field of integrated circuit packaging technology, the warping problem of 2.5D silicon interposer is a common problem. Due to the particularity of the process, the wafer warping problem has become the main problem affecting the process accuracy and product yield. In the existing process, a single wafer is prone to warping after completing a certain number of metal wiring layers, which affects the subsequent process. Moreover, a single wafer cannot form multiple layers of high-density metal wiring layers, and generally cannot be achieved when exceeding 8 layers. That is to say, in the related technology, only a small number of metal wiring layers can be formed on one side of the wafer.

[0060] Based on this, the present disclosure provides an interposer structure, which includes a wafer, at least one layer of first metal wiring layer, at least one layer of second metal wiring layer, and a plurality of conductive pillars; the plurality of conductive pillars penetrate the wafer, and at least one layer of first metal wiring layer and at least one layer of second metal wiring layer are located on both sides of the wafer along the first direction; the wafer includes a first sub-wafer and a second sub-wafer stacked along the first direction, and the non-active surfaces of the first sub-wafer and the second sub-wafer are bonded; the conductive pillars include first sub-conductive pillars and second sub-conductive pillars, the plurality of first sub-conductive pillars penetrate the first sub-wafer, the plurality of second sub-conductive pillars penetrate the second sub-wafer, and the first sub-conductive pillars and the second sub-conductive pillars are correspondingly electrically connected; at least one layer of first metal wiring layer is located on the active surface of the first sub-wafer and is electrically connected to the plurality of first sub-conductive pillars; at least one layer of second metal wiring layer is located on the active surface of the second sub-wafer and is electrically connected to the plurality of second sub-conductive pillars. In this way, not only can multiple layers of high-density metal wiring layers be formed on the surface of the wafer, increasing the number of wiring layers and density of the metal wiring layer; in addition, the first metal wiring layer and the second metal wiring layer can be formed on the upper and lower surfaces of the wafer respectively, and the stresses on both sides of the wafer can cancel each other out, greatly improving the wafer warping problem.

[0061] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0062] In an embodiment of the present disclosure, as Figure 1 and Figure 2As shown, the adapter board structure 10 may include a wafer 11, at least one first metal wiring layer 12, at least one second metal wiring layer 13, and a plurality of conductive posts 14; the plurality of conductive posts 14 penetrate through the wafer 11, and at least one first metal wiring layer 12 and at least one second metal wiring layer 13 are located on both sides of the wafer 11 along the first direction;

[0063] The wafer 11 may include a first sub-wafer 111 and a second sub-wafer 112 stacked along the first direction, and the non-active surfaces of the first sub-wafer 111 and the second sub-wafer 112 are bonded; the conductive posts 14 may include first sub-conductive posts 141 and second sub-conductive posts 142, the plurality of first sub-conductive posts 141 penetrate through the first sub-wafer 111, the plurality of second sub-conductive posts 142 penetrate through the second sub-wafer 112, and the first sub-conductive posts 141 and the second sub-conductive posts 142 are electrically connected correspondingly;

[0064] At least one first metal wiring layer 12 is located on the active surface of the first sub-wafer 111 and is electrically connected to the plurality of first sub-conductive posts 141; at least one second metal wiring layer 13 is located on the active surface of the second sub-wafer 112 and is electrically connected to the plurality of second sub-conductive posts 142.

[0065] An embodiment of the present disclosure provides an adapter board structure 10, specifically a high-density silicon adapter board structure; wherein, high density means that the proportion of the volume of the metal wiring layers (the first metal wiring layer 12 and the second metal wiring layer 13) in the adapter board structure 10 is high. The greater the number of layers of the metal wiring layer, the greater the proportion, which can improve the heat dissipation effect of the adapter board structure 10 and improve signal integrity.

[0066] It should be noted that the wafer 11 may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when ignoring the flatness of the top surface and the bottom surface, the direction intersecting with the top surface and the bottom surface of the wafer 11 is defined as the first direction. In the embodiment of the present disclosure, the first direction intersects with the top surface and the bottom surface of the wafer 11, and the first direction and the top surface and the bottom surface of the wafer 11 may be perpendicular to each other or intersect at other angles, which is not specifically limited herein. Exemplarily, taking the first direction being perpendicular to the top surface and the bottom surface of the wafer 11 as an example, the specific implementation of the embodiment of the present disclosure is described in detail. It can be understood that at least one first metal wiring layer 12, the wafer 11, and at least one second metal wiring layer 13 are arranged in sequence along the first direction, and the first metal wiring layer 12 and the second metal wiring layer 13 are formed on the upper and lower surfaces of the wafer 11.

[0067] It should also be noted that in each wafer, the active surface and the non-active surface are opposite to each other. Among them, the active surface refers to the exposed surface where active semiconductor devices have been manufactured or will be manufactured. This surface usually requires precise lithography and exposure processes to form circuit patterns; the non-active surface generally does not directly participate in device manufacturing, but plays roles such as support and fixation during the wafer processing.

[0068] In this embodiment, the main material of the wafer 11 is silicon. The metal wiring layer may refer to a redistribution layer (RDL) for electrical extension and signal interconnection, and its material may be copper.

[0069] It should also be noted that in the interposer structure 10, the shapes and numbers of layers of each metal wiring layer, that is, the first metal wiring layer 12 and the second metal wiring layer 13, are not limited. Each redistribution layer can have different numbers of layers such as 1 layer, 2 layers, 3 layers, etc. according to actual needs; when the number of layers of each metal wiring layer is multiple, the structure of each layer can be the same or different, and no specific limitations are made thereto. Exemplarily, taking each metal wiring layer as 3 layers as an example, the specific implementation of the embodiments of the present disclosure will be described in detail.

[0070] In some embodiments, the difference between the first thickness of all the first metal wiring layers 12 and the second thickness of all the second metal wiring layers 13 satisfies a preset condition.

[0071] It should be noted that when the first metal wiring layer 12 includes multiple layers, the multiple first metal wiring layers 12 are stacked in sequence and connected to each other; when the second metal wiring layer 13 includes multiple layers, the multiple second metal wiring layers 13 are stacked in sequence and connected to each other. The number of layers of the first metal wiring layer 12 and the second metal wiring layer 13 is not limited, and they can be the same or different, as long as the difference between the first thickness and the second thickness satisfies the preset condition. Exemplarily, the first thickness and the second thickness are about several micrometers.

[0072] It should also be noted that the preset condition may include that the difference between the first thickness and the second thickness is basically 0. In this way, the embodiments of the present disclosure can form metal wiring layers of the same thickness on the upper and lower surfaces of the wafer 11, cancel the stress on the upper and lower surfaces, and improve the problem of wafer warping. In addition, the embodiments of the present disclosure can also prepare multiple layers of metal wiring layers on both the upper and lower surfaces of the wafer 11 to form a thicker metal wiring layer and reduce the warping of the interposer structure 10.

[0073] It should also be noted that if the wafer 11 is warped before the metal wiring layer is prepared, the warping of the interposer structure 10 can be reduced by improving the preset condition, that is, adjusting the difference between the first thickness and the second thickness, so that the thicknesses of the metal wiring layers on the upper and lower surfaces of the wafer 11 are different.

[0074] In some embodiments, the interposer structure 10 may further include a first dielectric layer 15 and a second dielectric layer 16;

[0075] At least one first metal wiring layer 12 is formed in the first dielectric layer 15, and at least one second metal wiring layer 13 is formed in the second dielectric layer 16.

[0076] It should be noted that the materials of the first dielectric layer 15 and the second dielectric layer 16 may be silicon dioxide, or polyimide, or other materials, etc., and no specific limitation is made thereto.

[0077] In this embodiment, the conductive posts 14 penetrate through the wafer 11, and the first metal wiring layer 12 and the second metal wiring layer 13 are located on both sides of the wafer 11 along the first direction. That is to say, the first metal wiring layer 12 and the second metal wiring layer 13 are electrically connected to the conductive posts 14 respectively. Here, the depth of the conductive posts 14 is generally about ten-odd micrometers.

[0078] It should be noted that no specific limitation is made to the number and position of the conductive posts 14. Exemplarily, taking the interposer structure 10 including 3 conductive posts 14 as an example, the specific implementation of the embodiments of the present disclosure will be described in detail. The conductive posts 14 may include a first sub-conductive post 141 and a second sub-conductive post 142, and the positions and numbers of the first sub-conductive post 141 and the second sub-conductive post 142 correspond one by one to ensure the electrical signal transmission in the vertical direction (i.e., the first direction).

[0079] In some embodiments, as Figure 2 shown, the non-active surfaces of the first sub-wafer 111 and the second sub-wafer 112 are directly bonded; or,

[0080] As Figure 1 shown, the interposer structure 10 may further include a plurality of bonding structures 17. The plurality of bonding structures 17 are located between the first sub-wafer 111 and the second sub-wafer 112, and the non-active surfaces of the first sub-wafer 111 and the second sub-wafer 112 are bonded through the plurality of bonding structures 17.

[0081] As Figure 1 shown, the plurality of bonding structures 17 are connected to the plurality of first sub-conductive posts 141 one by one, and the plurality of bonding structures 17 are connected to the plurality of second sub-conductive posts 142 one by one. That is to say, the first sub-conductive post 141 and the second sub-conductive post 142 are electrically connected through the bonding structure 17.

[0082] It should be noted that, as Figure 2As shown, the non-active surfaces of the first sub-wafer 111 and the second sub-wafer 112 can be bonded by means of silicon-silicon direct bonding or silicon oxide interface bonding, and no specific limitation is imposed thereon. Among them, silicon-silicon direct bonding means that two silicon wafers are directly bonded together through high-temperature treatment without any binder and external electric field, and the process is simple; silicon oxide interface bonding means that in semiconductor packaging or chip manufacturing, silicon oxide (SiO 2 ) is used as an interface medium, and the surfaces of two wafers are tightly connected through physical or chemical actions.

[0083] It should also be noted that, as Figure 1 shown, the bonding structure 17 can be a bump or a hybrid bonding structure, and no specific limitation is imposed thereon. That is to say, multiple bonding structures 17, multiple first sub-conductive posts 141, and multiple second sub-conductive posts 142 can be bonded through any bonding technology, and no specific limitation is imposed thereon. Exemplarily, a hybrid bonding technology can be adopted. The hybrid bonding technology is a method that combines physical bonding and chemical bonding, which can enable different types of bonding materials to form a bond. This bonding method can overcome the limitations of a single bonding method, and at the same time greatly reduce the bonding pitch and increase the bonding density; or an under-bump metallurgy (UBM) and a bump can be formed for bonding treatment.

[0084] In some embodiments, as Figure 1 shown, the bonding structure 17 can include a first sub-bonding structure 171 and a second sub-bonding structure 172 (not shown in the figure);

[0085] On the non-active surface of the first sub-wafer 111, multiple first sub-bonding structures 171 and multiple first sub-conductive posts 141 are correspondingly connected;

[0086] On the non-active surface of the second sub-wafer 112, multiple second sub-bonding structures 172 and multiple second sub-conductive posts 142 are correspondingly connected.

[0087] It should be noted that the first sub-bonding structure 171 and the second sub-bonding structure 172 are bonded to each other to form the bonding structure 17, so that multiple first sub-conductive posts 141 and multiple second sub-conductive posts 142 are correspondingly electrically connected through multiple bonding structures 17.

[0088] An embodiment of the present disclosure provides a silicon interposer structure with multiple layers of high-density metal wiring layers (i.e., the interposer structure 10). By using three-dimensional integrated circuit (3DIC) stacking technology, metal wiring layers are formed on the upper and lower surfaces of the wafer 11 respectively, which can increase the number of wiring layers and density of the metal wiring layers. At the same time, since there are metal wiring layers on both sides of the wafer 11, the stresses on both sides of the wafer 11 can cancel each other out, avoiding the problem of wafer warping caused by multiple layers of metal wiring layers.

[0089] In another embodiment of the present disclosure, refer to Figure 3 , which shows a schematic flowchart of a method for manufacturing an interposer structure provided by an embodiment of the present disclosure. As Figure 3 shown, the method may include:

[0090] S201: Provide a first initial sub-wafer and a second initial sub-wafer.

[0091] It should be noted that the manufacturing method provided by the embodiment of the present disclosure is applied to manufacture the aforementioned interposer structure 10.

[0092] Refer to Figure 4 , which shows a schematic diagram of the manufacturing process of an interposer structure provided by an embodiment of the present disclosure. Figure 1 As Figure 4 shown, when manufacturing the interposer structure 10, first provide a first initial sub-wafer 31 and a second initial sub-wafer 32.

[0093] It should be noted that the first initial sub-wafer 31 and the second initial sub-wafer 32 are incoming wafers. Among them, an incoming wafer refers to a standardized silicon wafer substrate provided by an external supplier during the semiconductor manufacturing process for subsequent chip processing.

[0094] S202: Form a plurality of first sub-conductive pillars in the first initial sub-wafer and a plurality of second sub-conductive pillars in the second initial sub-wafer.

[0095] As Figure 5 shown, after obtaining the incoming wafers, conductive pillars are fabricated in the two incoming wafers, and the depth is generally a dozen micrometers. That is to say, after obtaining the first initial sub-wafer 31 and the second initial sub-wafer 32, a plurality of first sub-conductive pillars 141 are fabricated in the first initial sub-wafer 31, and a plurality of second sub-conductive pillars 142 are fabricated in the second initial sub-wafer 32.

[0096] It should be noted that through-silicon via (TSV) technology can be used to form conductive posts; among them, TSV technology is a technology that realizes the interconnection between chips by fabricating vertical conduction structures between chips and between wafers. Specifically, etching can be performed in the first initial sub-wafer 31 to form a plurality of first deep holes, and after forming the plurality of first deep holes, a conductive material is filled in the first deep holes to form a plurality of first sub-conductive posts 141; and etching is performed in the second initial sub-wafer 32 to form a plurality of second deep holes, and after forming the plurality of second deep holes, a conductive material is filled in the second deep holes to form a plurality of second sub-conductive posts 142. The conductive material can include copper, tungsten, polysilicon, etc., and no specific limitation is made thereto; exemplarily, both the first sub-conductive post 141 and the second sub-conductive post 142 are copper posts. The process of filling the conductive material can include a deposition process, such as an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, etc., or can also include an electroplating process, and no specific limitation is made thereto in the embodiments of the present disclosure.

[0097] It should also be noted that no specific limitation is made to the number and positions of the first sub-conductive posts 141 and the second sub-conductive posts 142. Exemplarily, the specific implementation of the embodiments of the present disclosure will be described in detail by taking the first initial sub-wafer 31 including 3 first sub-conductive posts 141 and the second initial sub-wafer 32 including 3 second sub-conductive posts 142 as an example.

[0098] S203: Form at least one first metal wiring layer on the active surface of the first initial sub-wafer, and form at least one second metal wiring layer on the active surface of the second initial sub-wafer; at least one first metal wiring layer is electrically connected to the plurality of first sub-conductive posts, and at least one second metal wiring layer is electrically connected to the plurality of second sub-conductive posts.

[0099] As Figure 6As shown, after forming a plurality of first sub-conductive posts 141 in the first initial sub-wafer 31, a first metal wiring layer 12 is fabricated on the front surface of the first initial sub-wafer 31 for testing and signal interconnection; the number of layers of the first metal wiring layer 12 is at least one layer, and there is no limitation on the specific number of layers. Exemplarily, taking the first metal wiring layer 12 as 3 layers as an example, the specific implementation of the embodiments of the present disclosure will be described in detail. Similarly, after forming a plurality of second sub-conductive posts 142 in the second initial sub-wafer 32, a second metal wiring layer 13 is fabricated on the front surface of the second initial sub-wafer 32 for testing and signal interconnection; the number of layers of the second metal wiring layer 13 is at least one layer, and there is no limitation on the specific number of layers. Exemplarily, taking the second metal wiring layer 13 as 3 layers as an example, the specific implementation of the embodiments of the present disclosure will be described in detail. Here, the number of layers of the first metal wiring layer 12 and the number of layers of the second metal wiring layer 13 may be the same or different, and no specific limitation is made thereto.

[0100] It should be noted that in Figure 6 , the front surface of the wafer refers to the active surface; the surface opposite to the front surface is the back surface, that is, the non-active surface.

[0101] It should also be noted that the first metal wiring layer 12 and the second metal wiring layer 13 may specifically be redistribution layers, and their materials may be copper. In addition, the first metal wiring layer 12 and the second metal wiring layer 13 can be formed by the damascene process.

[0102] It should also be noted that the first dielectric layer 15 can be first formed by the CVD process, and then the first metal wiring layer 12 can be formed through processes such as photolithography, etching, filling, and chemical mechanical polish (CMP). Similarly, the second dielectric layer 16 can be first formed by the CVD process, and then the second metal wiring layer 13 can be formed through processes such as photolithography, etching, filling, and CMP.

[0103] S204: Remove a part of the first initial sub-wafer to obtain a first sub-wafer, and a plurality of first sub-conductive posts penetrate the first sub-wafer; and remove a part of the second initial sub-wafer to obtain a second sub-wafer, and a plurality of second sub-conductive posts penetrate the second sub-wafer.

[0104] After forming at least one layer of the first metal wiring layer 12 on the active surface of the first initial sub-wafer 31 and forming at least one layer of the second metal wiring layer 13 on the active surface of the second initial sub-wafer 32, the first sub-wafer 111 is obtained from the first initial sub-wafer 31, and the second sub-wafer 112 is obtained from the second initial sub-wafer 32.

[0105] Specifically, in some embodiments, removing a part of the first initial sub-wafer includes:

[0106] Perform a bonding process on the first carrier wafer and at least one layer of the first metal wiring layer;

[0107] Flip the first initial sub-wafer;

[0108] On the non-active surface of the first initial sub-wafer, remove a part of the first initial sub-wafer to expose a plurality of first sub-conductive posts.

[0109] Remove a part of the second initial sub-wafer, including:

[0110] Perform a bonding process on the second carrier wafer and at least one layer of the second metal wiring layer;

[0111] Flip the second initial sub-wafer;

[0112] On the non-active surface of the second initial sub-wafer, remove a part of the second initial sub-wafer to expose a plurality of second sub-conductive posts.

[0113] As Figure 7 As shown, bond the first initial sub-wafer 31 with the first metal wiring layer 12 prepared to the first carrier wafer 33, that is, bond the first carrier wafer 33 on the first metal wiring layer 12; similarly, bond the second initial sub-wafer 32 with the second metal wiring layer 13 prepared to the second carrier wafer 34, that is, bond the second carrier wafer 34 on the second metal wiring layer 13.

[0114] It should be noted that the carrier wafer is a key support material in semiconductor manufacturing and advanced packaging processes, mainly used to protect the device wafer and provide mechanical stability for subsequent process flows, such as the back thinning process.

[0115] It should also be noted that a temporary bonding process can be used for the bonding process. Specifically, the carrier wafer can have a temporary bonding adhesive layer and a debonding layer (not shown in the figure) to bond the first carrier wafer 33 and the first metal wiring layer 12 to each other, and the second carrier wafer 34 and the second metal wiring layer 13 to each other.

[0116] As Figure 8As shown, after bonding the first carrier wafer 33 and the first metal wiring layer 12, the first initial sub-wafer 31 is flipped so that the first carrier wafer 33 is located below the first initial sub-wafer 31, and the non-active surface of the first initial sub-wafer 31 faces upward; then, the redundant silicon substrate in the first initial sub-wafer 31 is removed using a back thinning process, exposing a plurality of first sub-conductive posts 141 to provide a circuit connection channel. Similarly, after bonding the second carrier wafer 34 and the second metal wiring layer 13, the second initial sub-wafer 32 is flipped so that the second carrier wafer 34 is located below the second initial sub-wafer 32, and the non-active surface of the second initial sub-wafer 32 faces upward; then, the redundant silicon substrate in the second initial sub-wafer 32 is removed using a back thinning process, exposing a plurality of second sub-conductive posts 142 to provide a circuit connection channel. Here, after removing a part of the first initial sub-wafer 31, the first sub-wafer 111 is obtained, and after removing a part of the second initial sub-wafer 32, the second sub-wafer 112 is obtained. The first sub-wafer 111 and the second sub-wafer 112 form the wafer 11.

[0117] It should also be noted that various processes can be used to expose the first sub-conductive posts 141 and the second sub-conductive posts 142. For example, CMP process and etching process can be used. Among them, the etching can be a dry etching process or a wet etching process. The gas used in dry etching can be trifluoromethane (CHF 3 ), carbon tetrafluoride (CF 4 ), difluoromethane (CH 2 F 2 ), hydrobromic acid (HBr), chlorine (Cl 2 ) or sulfur hexafluoride (SF 6 ) or any combination thereof. Wet etching can be carried out using strong acids such as concentrated sulfuric acid, hydrofluoric acid, and concentrated nitric acid.

[0118] S205: Bond the non-active surfaces of the first sub-wafer and the second sub-wafer; the first sub-conductive posts and the second sub-conductive posts are electrically connected correspondingly.

[0119] It should be noted that the first sub-wafer 111 and the second sub-wafer 112 are bonded through the surface containing conductive posts (i.e., the non-active surface), so that the conductive posts in the two are connected, that is, the first sub-conductive posts 141 and the second sub-conductive posts 142 are connected.

[0120] Specifically, in some embodiments, bonding the non-active surfaces of the first sub-wafer and the second sub-wafer includes:

[0121] Directly bonding the non-active surfaces of the first sub-wafer and the second sub-wafer; or,

[0122] Bond the non-active surfaces of the first sub-wafer and the second sub-wafer through a plurality of bonding structures.

[0123] As Figure 9 shown, after exposing a plurality of first sub-conductive posts 141 in the first sub-wafer 111 and exposing a plurality of second sub-conductive posts 142 in the second sub-wafer 112, flip the first sub-wafer 111 so that the first carrier wafer 33 is located above the first sub-wafer 111, and the non-active surface of the first sub-wafer 111 faces downward, so that the non-active surface of the first sub-wafer 111 and the non-active surface of the second sub-wafer 112 face each other, and then directly bond the non-active surface of the first sub-wafer 111 and the non-active surface of the second sub-wafer 112.

[0124] It should be noted that the non-active surfaces of the first sub-wafer 111 and the second sub-wafer 112 can be bonded by means of silicon-silicon direct bonding or silicon oxide interface bonding, and the comparison is not specifically limited.

[0125] Alternatively, in some embodiments, bonding the non-active surfaces of the first sub-wafer and the second sub-wafer through a plurality of bonding structures includes:

[0126] Form a plurality of first sub-bonding structures on the non-active surface of the first sub-wafer, and the plurality of first sub-bonding structures are correspondingly connected to the plurality of first sub-conductive posts;

[0127] Form a plurality of second sub-bonding structures on the non-active surface of the second sub-wafer, and the plurality of second sub-bonding structures are correspondingly connected to the plurality of second sub-conductive posts;

[0128] Bond the first sub-bonding structures and the second sub-bonding structures so that the non-active surfaces of the first sub-wafer and the second sub-wafer are bonded through a plurality of bonding structures; the first sub-bonding structures and the second sub-bonding structures form a bonding structure.

[0129] As Figure 10 shown, after exposing a plurality of first sub-conductive posts 141 in the first sub-wafer 111, form a plurality of first sub-bonding structures 171 on the non-active surface of the first sub-wafer 111, that is, above the plurality of first sub-conductive posts 141; and after exposing a plurality of second sub-conductive posts 142 in the second sub-wafer 112, form a plurality of second sub-bonding structures 172 on the non-active surface of the second sub-wafer 112, that is, above the plurality of second sub-conductive posts 142.

[0130] As Figure 11As shown, after forming a plurality of first sub-bonding structures 171 and a plurality of second sub-bonding structures 172, the first sub-wafer 111 is flipped so that the first carrier wafer 33 is located on top of the first sub-wafer 111, and the plurality of first sub-bonding structures 171 face downward. In this way, the plurality of first sub-bonding structures 171 and the plurality of second sub-bonding structures 172 are opposite to each other, and the plurality of first sub-bonding structures 171 and the plurality of second sub-bonding structures 172 are in one-to-one correspondence. Then, the corresponding first sub-bonding structures 171 and second sub-bonding structures 172 are subjected to a bonding process.

[0131] It should be noted that a bump process can be used to form a plurality of first sub-bonding structures 171 and a plurality of second sub-bonding structures 172, or a hybrid bonding process can be used to form a plurality of first sub-bonding structures 171 and a plurality of second sub-bonding structures 172, and no specific limitation is made thereto. That is to say, the first sub-bonding structures 171 and the second sub-bonding structures 172 can be bumps or hybrid bonding structures, and no specific limitation is made thereto.

[0132] In some embodiments, after bonding the non-active surface of the first sub-wafer and the non-active surface of the second sub-wafer, the method further includes:

[0133] Performing a debonding process on the first carrier wafer and at least one layer of first metal wiring layer, and / or performing a debonding process on the second carrier wafer and at least one layer of second metal wiring layer.

[0134] As Figure 1 shown, after bonding the non-active surface of the first sub-wafer 111 and the non-active surface of the second sub-wafer 112 through a plurality of first sub-bonding structures 171 and a plurality of second sub-bonding structures 172, a debonding process is performed on the first carrier wafer 33 and at least one layer of first metal wiring layer 12, and a debonding process is performed on the second carrier wafer 34 and at least one layer of second metal wiring layer 13.

[0135] As Figure 2 shown, after directly bonding the non-active surface of the first sub-wafer 111 and the non-active surface of the second sub-wafer 112, a debonding process is performed on the first carrier wafer 33 and at least one layer of first metal wiring layer 12, and a debonding process is performed on the second carrier wafer 34 and at least one layer of second metal wiring layer 13.

[0136] It should be noted that generally, one of the carrier wafers can be removed through a debonding process, and subsequently, it can be stacked with other wafers (such as device wafers) as needed. Specifically, one carrier wafer, such as the first carrier wafer 33, can be debonded first, then a device wafer can be stacked above the first metal wiring layer 12, and then the obtained structure can be flipped to make the second carrier wafer 34 face upward, and then the second carrier wafer 34 can be debonded. Finally, a device wafer can be stacked above the second metal wiring layer 13 as needed.

[0137] An embodiment of the present disclosure provides a method for manufacturing an interposer structure 10. In the interposer structure 10, by bonding two wafers, namely the first sub-wafer 111 and the second sub-wafer 112, not only can a multi-layer high-density metal wiring layer be formed on the surface of the wafer 11, but also metal wiring layers are present on both the upper and lower surfaces of the wafer 11, and the stresses can cancel each other out, greatly improving the problem of wafer warping.

[0138] In another embodiment of the present disclosure, refer to Figure 12 , which shows a schematic diagram of the composition structure of a packaging structure provided by an embodiment of the present disclosure. As Figure 12 shown, the packaging structure 20 may include an interposer structure 10.

[0139] In an embodiment of the present disclosure, for the packaging structure 20, since it includes the aforementioned interposer structure 10, it has at least the same advantages as the interposer structure 10, can effectively increase the number of metal wiring layers in the interposer structure 10, and improve the warping problem of the interposer structure 10.

[0140] For details not disclosed in the embodiments of the present disclosure, reference can be made to the description of the foregoing embodiments for understanding.

[0141] The above is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0142] It should be noted that in the present disclosure, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0143] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the superiority or inferiority of the embodiments.

[0144] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0145] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0146] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0147] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A transfer plate structure, characterized in that: The adapter plate structure includes a wafer, at least one first metal wiring layer, at least one second metal wiring layer and a plurality of conductive pillars; the plurality of conductive pillars penetrate the wafer, and the at least one first metal wiring layer and the at least one second metal wiring layer are located on both sides of the wafer along a first direction; The wafer comprises a first sub-wafer and a second sub-wafer stacked along the first direction, the inactive surface of the first sub-wafer is bonded to the inactive surface of the second sub-wafer; the conductive pillar comprises a first sub-conductive pillar and a second sub-conductive pillar, a plurality of the first sub-conductive pillars penetrate the first sub-wafer, a plurality of the second sub-conductive pillars penetrate the second sub-wafer, and the first sub-conductive pillars and the second sub-conductive pillars are electrically connected correspondingly; The at least one first metal wiring layer is located on the active surface of the first sub-wafer and is electrically connected to the first sub-conductive pillars; the at least one second metal wiring layer is located on the active surface of the second sub-wafer and is electrically connected to the second sub-conductive pillars.

2. The adapter plate structure according to claim 1, characterized in that: The inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer are directly bonded; or, The adapter plate structure also includes a plurality of bonding structures, and the plurality of bonding structures are located between the first sub-wafer and the second sub-wafer, and the inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer are bonded through the plurality of bonding structures.

3. The adapter plate structure according to claim 2, characterized in that: The bonding structure includes a first sub-bonding structure and a second sub-bonding structure; On the inactive surface of the first sub-wafer, a plurality of the first sub-bonding structures and a plurality of the first sub-conductive pillars are connected correspondingly; On the inactive surface of the second sub-wafer, a plurality of the second sub-bonding structures and a plurality of the second sub-conductive pillars are connected correspondingly.

4. The adapter plate structure according to claim 1, characterized in that: A difference between the first thickness of all the first metal wiring layers and the second thickness of all the second metal wiring layers satisfies a preset condition.

5. A method for preparing an adapter plate structure, characterized in that: The method comprises: Providing a first initial sub-wafer and a second initial sub-wafer; forming a plurality of first sub-conductive pillars in the first initial sub-wafer, and forming a plurality of second sub-conductive pillars in the second initial sub-wafer; At least one first metal wiring layer is formed on the active surface of the first initial sub-wafer, and at least one second metal wiring layer is formed on the active surface of the second initial sub-wafer; the at least one first metal wiring layer is electrically connected to the plurality of first sub-conductive pillars, and the at least one second metal wiring layer is electrically connected to the plurality of second sub-conductive pillars; Removing part of the first initial sub-wafer to obtain a first sub-wafer, wherein a plurality of the first sub-conductive pillars penetrate the first sub-wafer; and removing part of the second initial sub-wafer to obtain a second sub-wafer, wherein a plurality of the second sub-conductive pillars penetrate the second sub-wafer; The inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer are bonded; the first sub-conductive pillars and the second sub-conductive pillars are electrically connected correspondingly.

6. The method according to claim 5, characterized in that The removing part of the first initial sub-wafer comprises: Performing a bonding process on the first carrier wafer and the at least one first metal wiring layer; turning over the first initial sub-wafer; On the inactive surface of the first initial sub-wafer, removing a portion of the first initial sub-wafer to expose the plurality of first sub-conductive pillars; The removing part of the second initial sub-wafer comprises: Performing a bonding process on the second carrier wafer and the at least one second metal wiring layer; turning over the second initial sub-wafer; On the inactive surface of the second initial sub-wafer, a portion of the second initial sub-wafer is removed to expose a plurality of the second sub-conductive pillars.

7. The method according to claim 6, characterized in that After bonding the inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer, the method further includes: The first carrier wafer and the at least one first metal wiring layer are subjected to a debonding process, and / or the second carrier wafer and the at least one second metal wiring layer are subjected to a debonding process.

8. The method according to claim 5, characterized in that The bonding process of the inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer comprises: directly bonding the inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer; or, The inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer are bonded together through a plurality of bonding structures.

9. The method according to claim 8, characterized in that The step of bonding the inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer by using a plurality of bonding structures comprises: forming a plurality of first sub-bonding structures on the inactive surface of the first sub-wafer, wherein the plurality of first sub-bonding structures and the plurality of first sub-conductive pillars are correspondingly connected; forming a plurality of second sub-bonding structures on the inactive surface of the second sub-wafer, wherein the plurality of second sub-bonding structures and the plurality of second sub-conductive pillars are connected correspondingly; The first sub-bonding structure and the second sub-bonding structure are bonded so that the inactive surface of the first sub-wafer and the inactive surface of the second sub-wafer are bonded through a plurality of the bonding structures; the first sub-bonding structure and the second sub-bonding structure constitute the bonding structure.

10. A packaging structure, characterized in that: The packaging structure includes the transfer plate structure according to any one of claims 1 to 4.

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