Terahertz waveguide structure and preparation method thereof

Abstract

The invention provides a terahertz waveguide structure and a preparation method thereof, and the preparation method comprises the steps: arranging a layer of mask on a plurality of wafers, and enabling the mask to comprise one or more mask patterns corresponding to half waveguide structures; performing deep reactive ion etching on each wafer based on the mask, so that one or more half-waveguide structures are formed on each wafer; bonding the plurality of wafers together in a pairwise opposite manner to obtain one or more complete waveguide structures; wherein the waveguide structure is a terahertz waveguide structure.

Description

Technical Field

[0001] The present invention relates to the field of micro-nano processing technology, and particularly to a terahertz waveguide structure and a preparation method thereof. Background Art

[0002] As a structure for guiding electromagnetic waves directionally, the terahertz waveguide structure can effectively conduct electromagnetic waves and is an important key component in the application of terahertz waves. Due to its small structure and high dimensional accuracy, waveguides are usually prepared by microfabrication technology.

[0003] However, the existing microfabrication technologies mainly rely on complex machining or other micro-nano manufacturing methods. For the preparation of more complex terahertz waveguide structures, the process is difficult and the accuracy is limited, making it difficult to meet the preparation requirements of high aspect ratio and high precision of terahertz waveguides. Summary of the Invention

[0004] In view of this, the present application provides a preparation method for a terahertz waveguide structure with high depth ratio and high precision.

[0005] In a first aspect, the present application provides a preparation method for a terahertz waveguide structure, and the preparation method includes:

[0006] Providing a layer of mask on a plurality of wafers; wherein, the mask includes mask patterns corresponding to one or more semi-waveguide structures;

[0007] Performing deep reactive ion etching on each wafer based on the mask to form one or more semi-waveguide structures on each wafer;

[0008] Bonding the plurality of wafers pairwise to obtain one or more complete waveguide structures; wherein, the waveguide structure is a terahertz waveguide structure.

[0009] In a second aspect, the present application provides a terahertz waveguide structure, and the terahertz waveguide structure is prepared by using the preparation method for a terahertz waveguide structure.

[0010] The above preparation method for a terahertz waveguide structure and the terahertz waveguide structure are based on deep reactive ion etching technology to prepare a terahertz waveguide structure with high precision and high aspect ratio, so as to be used for the testing and assembly of high-frequency circuits. Brief Description of the Drawings

[0011] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0012] Figure 1 It is a schematic flowchart of the preparation method of the terahertz waveguide structure provided in this embodiment.

[0013] Figure 2 It is a schematic flowchart of the first sub-process of the preparation method of the terahertz waveguide structure provided in this embodiment.

[0014] Figure 3 It is a schematic flowchart of the second sub-process of the preparation method of the terahertz waveguide structure provided in this embodiment.

[0015] Figure 4 It is a schematic flowchart of the third sub-process of the preparation method of the terahertz waveguide structure provided in this embodiment.

[0016] Figure 5 It is a schematic flowchart of the mask setting process on the wafer provided in this embodiment.

[0017] Figure 6 It is a schematic flowchart of the etching process of the wafer provided in this embodiment.

[0018] Figure 7 It is a schematic flowchart of the bonding process of the wafer provided in this embodiment.

[0019] Figure 8 It is a schematic flowchart of the splitting process of the wafer provided in this embodiment.

[0020] Figure 9 It is a schematic perspective view of a part of the waveguide structure provided in this embodiment.

[0021] Figure 10 It is a schematic plan view of the waveguide structure provided in this embodiment.

[0022] Figure 11 It is a schematic perspective view of the whole waveguide structure provided in this embodiment.

[0023] Description of reference numerals in the figures: 1 - wafer, silicon layer; 11 - etched surface; 12 - non - etched surface; A - etched part; 111 - first window to be etched; 112 - second window to be etched; B - non - etched part; 2 - silicon dioxide layer, barrier layer; 3 - photoresist layer; 3' - mask; 4 - metal thin film; 13 - waveguide structure; 130 - half - waveguide structure; 131 - waveguide structure body; 132 - electron injection channel; 5 - mask plate; 100 - terahertz waveguide structure; 200 - electronic device.

[0024] The realization of the purpose of this application, its functional features and advantages will be further described in conjunction with the embodiments with reference to the accompanying drawings. Detailed implementation manners

[0025] In order to make the purpose, technical solutions and advantages of this application more clear and understandable, the following further details this application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of this application.

[0026] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of this application and the above - mentioned drawings are used to distinguish similar planned objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances. In other words, the described embodiments can be implemented in an order other than that illustrated or described here. In addition, the terms "including" and "having" and any variations thereof can also include other contents. For example, a process, method, system, product or device including a series of steps or units does not necessarily only include those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0027] It should be noted that the descriptions involving "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include one or more of the said features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0028] Please refer to Figure 1 , Figure 1Schematically shows the process of a method for fabricating a terahertz waveguide structure. The present application provides a method for fabricating a terahertz waveguide structure. This fabrication method is based on Deep Reactive Ion Etching (DRIE) to fabricate a waveguide structure 13 in the frequency band above 1.0 THz, and this waveguide structure 13 is applicable to the testing and assembly of high-frequency circuits in electronic devices. Among them, this fabrication method includes step S101 - step S105.

[0029] Step S101, a mask layer is set on a plurality of wafers. Among them, the mask includes mask patterns corresponding to one or more half-waveguide structures.

[0030] Please refer to Figure 2 and Figure 5 , Figure 2 which schematically shows the first sub-process of the method for fabricating a terahertz waveguide structure. Figure 5 Schematically shows the process of setting a mask on a wafer. In step S101, step S101 includes step S1011 - step S1015.

[0031] Step S1011, a barrier layer is set on the wafer surface. In this embodiment, wafer 1 is a silicon wafer obtained by surface treatment (including processes such as grinding, polishing, acid boiling, and alkali washing) of the original silicon wafer and meeting the predetermined requirements (the surface is pollution-free and suitable for subsequent processes), that is, wafer 1 corresponds to silicon wafer layer 1. In addition, wafer 1 includes an etching surface 11 and a non-etching surface 12 opposite to the etching surface 11. As the name implies, the etching surface 11 is used for etching, and the non-etching surface 12 is not used for etching. In the present application, a silicon dioxide layer 2 is prepared on the wafer surface by thermal oxidation, and the silicon dioxide layer 2 is used as the barrier layer 2 of the wafer to prevent external impurities from invading the surface of wafer 1. Among them, the silicon dioxide layer 2 is prepared on both the etching surface 11 and the non-etching surface 12 of wafer 1.

[0032] Step S1013, a photoresist layer is coated on the barrier layer, and the mask plate is placed above the photoresist layer. Among them, the mask plate includes mask patterns corresponding to one or more half-waveguide structures. Specifically, a photoresist layer 3 is coated on the barrier layer 2 on the side of the etching surface 11, and the photoresist layer 3 is used for the subsequent preparation of mask 3'. Among them, the thickness of the photoresist layer 3 is set according to actual needs to meet the requirements of subsequent etching processes. The mask plate 5 is designed and fabricated by using L-EDIT software according to the simulation design parameters of one or more half-waveguide structures 130. It can be understood that the coating of the photoresist layer 3 and the placement of the mask plate 5 are both preparatory work before the preparation of mask 3'.

[0033] Step S1015, a mask layer is set on the wafer through exposure. Specifically, the light source is irradiated onto the photoresist layer 3 through the mask plate 5, so that the photoresist layer 3 is divided into an exposed area and a non-exposed area, where the exposed area corresponds to the mask pattern in the mask plate 5, and the non-exposed area corresponds to the area other than the mask pattern in the mask plate 5. Then, the exposed area of the photoresist layer 3 is washed away through a developing process, and the mask pattern of the mask plate 5 is shown on the photoresist layer 3 on the wafer 1 in the concave and convex shape with or without photoresist, thereby realizing the setting of a mask layer 3' on the wafer 1. The mask layer 3' includes mask patterns corresponding to one or more semi-waveguide structures 130. The subsequent etching process is carried out based on this mask pattern to obtain the one or more semi-waveguide structures 130. It can be understood that the mask pattern appears in the concave shape without photoresist, and the blocking layer 2 under the mask layer 3' is exposed through this mask pattern. At this time, the mask layer 3', the blocking layer 2, and the silicon wafer layer 1 are divided according to the presence or absence of the mask pattern to obtain an etched part A and a non-etched part B. The etched part A successively includes the blocking layer 2 and the silicon wafer layer 1, and the non-etched part B successively includes the photoresist layer 3, the blocking layer 2, and the silicon wafer layer 1.

[0034] Step S103, based on the mask, each wafer is subjected to deep reactive ion etching to form one or more semi-waveguide structures on each wafer.

[0035] Please refer to Figure 9 , Figure 9 , which schematically shows the three-dimensional structure of a part of the waveguide structure. Before step S103, step S102 is further included. Specifically, the blocking layer corresponding to the mask pattern is subjected to reactive ion etching (RIE) to expose the first etching window 111, where the first etching window 111 is used for etching the waveguide structure body 131. Specifically, the semi-waveguide structure 130 includes a waveguide structure body 131 and an electron injection channel 132 located on the axis of the waveguide structure body 131. It can be understood that the purpose of the reactive ion etching is to remove the blocking layer 2 from the etched part A to expose the deeper silicon wafer layer 1, and this exposed silicon wafer layer 1 is the first etching window 111. Therefore, after the reactive ion etching, the etched part A only includes the silicon wafer layer 1, and the non-etched part B still includes the photoresist layer 3, the silicon dioxide layer 2, and the silicon wafer layer 1. The photoresist layer 3 and the silicon dioxide layer 2 in the non-etched part B jointly block the etching gas from directly contacting the silicon wafer layer 1 in the non-etched part B, thereby protecting the silicon wafer layer 1 in the non-etched part B from being etched, and ensuring that during the etching process of the silicon wafer layer 1 in the etched part A, the etching is always carried out according to the predetermined mask pattern and depth, and maintaining the perpendicularity and stability of the side wall of the silicon wafer layer 1 to obtain a semi-waveguide structure 130 with a high aspect ratio.

[0036] In step S103, the present application uses deep reactive ion etching technology to achieve high-precision processing of the semi-waveguide structure. Specifically, the Bosch process is used to perform deep reactive ion etching on the silicon wafer layer 1 of the etched part A on a deep etching device, so as to gradually realize a high aspect ratio semi-waveguide structure 130 on the wafer 1, so as to meet the high aspect ratio requirements of the microstructures of the terahertz waveguide structure 100. Deep reactive ion etching includes passivation and etching. In the present application, the passivation and etching of deep reactive ion etching are alternately performed. Among them, C4F8 is used as the protective gas for passivation and SF6 is used as the etching gas for etching. At the same time, the Bosch process controls the alternating injection period and gas flow rate of C4F8 and SF6 to ensure the accuracy of anisotropic etching.

[0037] Please refer to Figure 3 and Figure 6 , Figure 3 which shows the second sub-process of the preparation method of the terahertz waveguide structure. Figure 6 which shows the process of etching the wafer. Step S103 includes steps S1031 - S1035.

[0038] Step S1031, use deep reactive ion etching to etch the waveguide structure body on the first window to be etched. Specifically. Perform the first deep reactive ion etching on the window to be etched, so as to gradually etch the waveguide structure body 131 with a high aspect ratio on the silicon wafer layer 1 of the etched part A.

[0039] Step S1033, when the etching of the waveguide structure body reaches a certain depth, the second window to be etched is exposed, where the second window to be etched is used for etching the electron injection channel.

[0040] Please refer to Figure 10 , Figure 10 which shows the planar structure of the waveguide structure. Step S1035, use deep reactive ion etching to simultaneously etch the electron injection channel and the waveguide structure body. In this embodiment, the etching of both the waveguide structure body 131 and the electron injection channel 132 is obtained based on deep reactive ion etching. However, due to the different mask patterns corresponding to the waveguide structure body 131 and the electron injection channel 132, the structures of the etched waveguide structure body 131 and the electron injection channel 132 are different.

[0041] Step S105, bond several wafers together in pairs.

[0042] Please refer to Figure 4 and Figure 7 , Figure 4 which shows the third sub-process of the preparation method of the terahertz waveguide structure. Figure 7Illustrates the process of bonding wafers. In this embodiment, before step S105, steps S1041 - S1043 are further included. Step S1041 includes removing the mask 3' (i.e., the photoresist layer 3 of the non - etched part B). After removing the mask 3', the non - etched part B only includes the silicon dioxide layer 2 and the silicon wafer layer 1. At this time, a metal thin film 4 is sputtered omnidirectionally on the surface of one or more semi - waveguide structures 130 (i.e., step S1043) to make one or more semi - waveguide structures 130 conductive. In addition, step S105 includes steps S1051 - S1053.

[0043] Step S1051, align all the electron injection channels of one of the two wafers to be bonded with all the electron injection channels of the other one, so that all the semi - waveguide structures of one of the two wafers are aligned with all the semi - waveguide structures of the other one.

[0044] Please refer to Figure 11 , Figure 11 which illustrates the overall three - dimensional structure of the waveguide structure. Step S1053, bond the two wafers together using a bonding process. Specifically, wafer 1 includes one or more semi - waveguide structures 130 and a bonding surface surrounding the one or more semi - waveguide structures 130. After the two wafers to be bonded are aligned, bond the bonding surfaces between the two wafers 1 using a bonding process. On the one hand, make the semi - waveguide structures 130 between the two wafers 1 firmly bonded together to obtain one or more complete waveguide structures 13. On the other hand, ensure the airtightness of the complete waveguide structure 13 through bonding.

[0045] Please refer to Figure 8 , Figure 8 which illustrates the process of dividing the wafers. In this embodiment, if there are multiple complete waveguide structures 13 between the two wafers bonded together, after step S105, step S106 is further included. Specifically, scribe and divide the two wafers bonded together to separate one or more complete / cyclic waveguide structures 13, so as to obtain the required terahertz waveguide structure 100. It can be understood that during the division process, according to the period of the terahertz waveguide structure, the corresponding number of waveguide structures 13 can be cut out, which is convenient for the subsequent application of the electronic device 200. Further, if the terahertz waveguide structure is set to one cycle, one waveguide structure is cut out; if the terahertz waveguide structure is set to two cycles, two waveguide structures are cut out; and so on. If the terahertz waveguide structure is set to N cycles, N waveguide structures are cut out. In addition, it should be noted that Figures 5-8 the waveguide structure in Figures 9-11 is only for illustration, and for the structure of the waveguide structure, please refer to

[0046] Please refer toFigures 9-11 , Figure 11 shows an application scenario of the terahertz waveguide structure 100 in the electronic device 200. The terahertz waveguide structure 100 is prepared by using the preparation method of the terahertz waveguide structure, and the preparation method has been described in detail in the foregoing text and will not be repeated here. In this embodiment, the terahertz waveguide structure 100 may include a plurality of waveguide structures 13, wherein the number of the waveguide structures 13 may be specifically determined according to the period of the terahertz waveguide structure 100 required by the applied electronic device.

[0047] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.

[0048] The foregoing are only preferred embodiments of this application, and of course, the scope of rights of this application cannot be limited thereby. Therefore, equivalent changes made according to the claims of this application still fall within the scope covered by this application.

Claims

1. A method for preparing a terahertz waveguide structure, characterized in that: The preparation method comprises: A mask layer is provided on a plurality of wafers; wherein the mask includes a mask pattern corresponding to one or more half-waveguide structures; Performing deep reactive ion etching on each wafer based on the mask to form one or more half-waveguide structures on each wafer; The plurality of wafers are bonded together in pairs to obtain one or more complete waveguide structures; wherein the waveguide structure is a terahertz waveguide structure.

2. The method for preparing a terahertz waveguide structure according to claim 1, characterized in that: The preparation method is used to prepare a waveguide structure in a frequency band above 1.0 THz.

3. The method for preparing a terahertz waveguide structure according to claim 1, characterized in that: The step of setting a mask layer on a plurality of wafers specifically includes: Disposing a barrier layer on the surface of the wafer; Coating a photoresist layer on the barrier layer, and placing a mask plate on the photoresist layer; wherein the mask plate includes a mask plate pattern corresponding to one or more half-waveguide structures; A mask is disposed on the wafer by exposure.

4. The method for preparing a terahertz waveguide structure according to claim 3, characterized in that: The half-waveguide structure comprises a waveguide structure body and an electron injection channel located on the central axis of the waveguide structure body. Before performing deep reactive ion etching on each wafer based on the mask to form one or more half-waveguide structures on each wafer, the method further comprises: Reactive ion etching is performed on the barrier layer corresponding to the mask pattern to expose a first window to be etched; wherein the first window to be etched is used to etch the waveguide structure body.

5. The method for preparing a terahertz waveguide structure according to claim 4, characterized in that: The performing deep reactive ion etching on each wafer based on the mask to form one or more half-waveguide structures on each wafer specifically includes: Using the deep reactive ion etching to etch the first window to be etched to form a waveguide structure body; When the waveguide structure body is etched to a certain depth, a second window to be etched is exposed; wherein the second window to be etched is used for etching the electron injection channel; The deep reactive ion etching is used to simultaneously perform the etching of the electron injection channel and the etching of the waveguide structure body.

6. The method for preparing a terahertz waveguide structure according to claim 5, characterized in that: The deep reactive ion etching includes passivation and etching, and the passivation and etching of the deep reactive ion etching are performed alternately, wherein C4F8 is used as a protective gas for passivation and SF6 is used as an etching gas for etching.

7. The method for preparing a terahertz waveguide structure according to claim 6, characterized in that: Before bonding the plurality of wafers together in pairs, the preparation method further includes: A layer of metal film is sputtered on the surface of the one or more half-waveguide structures to make the one or more half-waveguide structures conductive.

8. The method for preparing a terahertz waveguide structure according to claim 7, characterized in that: The step of bonding the plurality of wafers together in pairs to obtain one or more complete waveguide structures specifically includes: Aligning all electron injection channels of one of the two wafers to be bonded with all electron injection channels of the other wafer one by one, so that all half-waveguide structures of one of the two wafers are aligned with all half-waveguide structures of the other wafer one by one; The two wafers are bonded together using a bonding process.

9. The method for preparing a terahertz waveguide structure according to claim 8, characterized in that: After bonding the plurality of wafers together in pairs, the method further includes: The two wafers bonded together are diced and divided to obtain one or more periodic terahertz waveguide structures.

10. A terahertz waveguide structure, characterized in that: The terahertz waveguide structure is prepared by the method for preparing a terahertz waveguide structure according to any one of claims 1 to 9.

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