Bidirectional crosstalk suppression circuit based on SiC MOSFET module

Abstract

The invention discloses a bidirectional crosstalk suppression circuit based on a SiC MOSFET module, and the circuit comprises a state monitoring circuit, the input end of the state monitoring circuit is connected with a SiC MOSFET, the output end of the state monitoring circuit is connected with the input end of a logic circuit, the output end of the logic circuit is connected with the input end of a level shift circuit and the input end of a Miller clamping branch circuit, and the input end of the Miller clamping branch circuit is connected with the input end of the level shift circuit. The output end of the level shift circuit is connected with the input end of the buffer, the output end of the buffer is connected with the input end of the Miller clamping branch, and the output end of the Miller clamping branch is connected with the SiC MOSFET. According to the two-way crosstalk suppression circuit based on the SiC MOSFET module, the whole crosstalk suppression process only works when crosstalk is generated, effective suppression of two-way crosstalk is guaranteed, meanwhile, additional switching loss is not increased, the problem of mistaken switching-on caused by crosstalk when a SiC MOSFET half-bridge module works is solved, the working reliability of the module is enhanced, and the service life of the SiC MOSFET module is prolonged.

Description

Technical Field

[0001] The present invention belongs to the technical field of crosstalk suppression circuits and relates to a bidirectional crosstalk suppression circuit based on SiC MOSFET modules. Background Art

[0002] With the continuous growth of global electricity demand, the development of renewable energy sources such as solar, wind, and geothermal energy has been highly regarded by countries around the world. To meet the needs of terminal applications with different power levels, various power conversion systems have emerged one after another. In the past few decades, significant breakthroughs have been made in improving power conversion efficiency and reducing costs. The development of power electronic devices has been nearly 60 years. Each time a new type of power electronic device is introduced, it will drive profound changes in the industry.

[0003] As the core component of high-voltage high-power electronic equipment, the performance of high-voltage power devices directly determines the key indicators of the equipment. In the high-voltage field, early semiconductor devices were mainly based on the first-generation materials (such as germanium Ge and silicon Si ) and the second-generation compound semiconductor materials (such as GaAs , GaP , InP , etc.). However, with the continuous increase in market demand for higher current capacity, higher breakdown voltage, and higher packaging density, the performance of silicon-based devices has approached its physical limit. Therefore, the development of new semiconductor materials has become an inevitable direction for technological development. The third-generation wide-bandgap semiconductor materials such as silicon carbide SiC and gallium nitride GaN exhibit excellent performance in high-temperature, high-frequency, high-voltage and other application scenarios due to their unique physical properties, including a relatively large bandgap width, high breakdown electric field, high thermal conductivity, etc. They have advantages such as low on-state loss and high current density, and have become a hot research field in semiconductor technology. The application of such wide-bandgap power devices can not only improve the efficiency and reliability of power conversion, but also effectively reduce the volume of the equipment, promoting the efficient utilization and green development of electric energy.

[0004] However, a faster switching speed and a higher energy density mean a greater dv / dt , which will cause negative effects during device switching. SiC Crosstalk between devices in the

[0005] In summary, the prior art has SiC the problem that crosstalk between devices in the module interferes with the operation of its complementary devices. Summary of the Invention

[0006] The purpose of the present invention is to provide a bidirectional crosstalk suppression circuit based on SiC MOSFET the module, which solves the problem that exists in the prior art SiC where crosstalk between devices in the module interferes with the operation of its complementary devices.

[0007] The technical solution adopted by the present invention is a bidirectional crosstalk suppression circuit based on SiC MOSFET the module, including a state monitoring circuit. The input end of the state monitoring circuit is connected to SiC MOSFET , and the output end of the state monitoring circuit is connected to the input end of a logic circuit. The output end of the logic circuit is respectively connected to the input end of a level shift circuit and the input end of a Miller clamping branch. The output end of the level shift circuit is connected to the input end of a buffer buffer , and the output end of the buffer buffer is connected to the input end of the Miller clamping branch. The output end of the Miller clamping branch is connected to SiC MOSFET .

[0008] The features of the present invention also lie in that the state monitoring circuit includes V d the state monitoring circuit, V d the input end of the state monitoring circuit is connected to the drain of SiC MOSFET , V d and the output end of the state monitoring circuit is connected to the input end of the logic circuit.

[0009] V d The state monitoring circuit includes a voltage dividing circuit. The voltage dividing circuit includes a number of series-connected RC parallel voltage dividing networks. The input end of the voltage dividing circuit is connected to the drain of SiC MOSFET , and the output end of the voltage dividing circuit is connected to the positive input end of a comparator A 1 . The negative input end of the device A 1 is connected to a reference voltage V ref2 . The output end of the comparator A 1 is connected to the input end of the logic circuit.

[0010] The positive input end of the comparator A 1 , the output end of the voltage dividing circuit and the diode D1 is connected to the input terminal, and the diode D 1 's output terminal is connected to the low operating voltage V DDL ; The comparator A 1 's positive input terminal, the output terminal of the voltage dividing circuit, and the diode D 1 's input terminal is connected to the diode D 2 's output terminal, and the diode D 2 's input terminal is grounded.

[0011] The status monitoring circuit further includes V g a status monitoring circuit, V g The input terminal of the status monitoring circuit is connected to the SiC MOSFET gate, V g The output terminal of the status monitoring circuit is connected to the input terminal of the logic circuit.

[0012] V g The status monitoring circuit includes a comparator A 2 , and the comparator A 2 's positive input terminal is connected to the SiC MOSFET gate, the comparator A 2 's negative input terminal is connected to the reference voltage V ref1 , and the comparator A 2 's output terminal is connected to the input terminal of the logic circuit; The comparator A 2 's positive input terminal, SiC MOSFET 's gate and the diode D 3 's input terminal are connected, and the diode D 3 's output terminal is connected to the low operating voltage V DDL ; The comparator A 2 's positive input terminal, SiC MOSFET 's gate, the diode D 3 's input terminal is connected to the diode D 4 's output terminal, and the diode D 4 's input terminal is grounded.

[0013] The logic circuit includes a NOR gate N 1 , and the input terminals of the NOR gate N 1 are respectively connected to the output terminals of the comparator A 1 , the output terminals of the comparator A 2 . The output terminal of the NOR gate N 1 is connected to the input terminal of the inverter N 2 . The output terminal of the inverter N 2 is connected to the input terminal of the NAND gate N 4 . The input terminal of the NAND gate N 4 is also connected to the output terminal of the inverter N 3 . The input terminal of the inverter N 2 is connected to SiC MOSFET the gate drive signal V drive . The output terminal of the NAND gate N 4 is connected to the input terminal of the level shift circuit.

[0014] The logic circuit also includes a NOR gate N 6 , and the input terminals of the NOR gate N 6 are respectively connected to the gate drive signal V drive , the output terminal of the inverter N 5 . The input terminal of the inverter N 5 is connected to the output terminal of the comparator A 2 . The output terminal of the NOR gate N 6 is connected to the input terminal of the Miller clamping branch. The output terminal of the NOR gate N 6 generates a control signal V ctrl .

[0015] The level shift circuit includes a triode Q 3 and an inverter N 5 . The gate of the triode Q 3 , the inverterN 5 The input terminal of N 4 is connected to the output terminal of the NAND gate, and the inverter N 5 The output terminal of Q 4 is connected to the gate of the triode Q 3 The source of Q 4 is connected to the source of the triode Q 3 The drain of Q 1 is connected to the drain of the triode, the triode Q 2 The gate of Q 4 The drain of Q 2 is connected to the drain of the triode, the triode Q 1 The gate of buffer is connected to the input terminal of the buffer Q 1 The source of Q 2 is connected to the high operating voltage V DDH connection.

[0016] The Miller clamping branch includes a switching transistor M switch , the switching transistor M switch The gate of buffer is connected to the output terminal of the buffer M switch The drain of SiC MOSFET is connected to the source of M switch The source of M 1 is connected to the drain of the triode, the capacitor C MC One end of the capacitor C MC is connected to the other end of the capacitor M 1 is grounded to the source of the triode, the triode M 1 The gate of V ctrl connection.

[0017] The beneficial effect of the present invention is that the present invention is to suppress SiC MOSFET ((END]] Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor, For the positive crosstalk and negative crosstalk generated when a silicon carbide metal-oxide-semiconductor field effect transistor (MOSFET) half-bridge module operates normally, a Miller clamping and zero-voltage turn-off scheme is adopted. When positive crosstalk occurs, the Miller clamping branch is turned on, and the energy generated by the positive crosstalk is stored in a capacitor. When negative crosstalk occurs, the stored energy is released to suppress the negative crosstalk. In addition, the entire crosstalk suppression process only works when crosstalk occurs. While effectively suppressing bidirectional crosstalk, it does not increase additional switching losses, solving SiC MOSFTE the problem of false turn-on caused by crosstalk when the half-bridge module is operating, enhancing the reliability of the module operation and improving SiC MOSFET the service life of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic structural diagram of the bidirectional crosstalk suppression circuit of the present invention based on SiC MOSFET the module.

[0019] In the figure, 1, V d status monitoring circuit; 2, V g status monitoring circuit; 3, logic circuit; 4, level shift circuit; 5, Miller clamping branch; DETAILED DESCRIPTION OF THE EMBODIMENTS The present invention will be described in detail below with reference to the drawings and specific embodiments.

[0020] Embodiment 1 This embodiment provides a bidirectional crosstalk suppression circuit based on SiC MOSFET the module. As shown in Figure 1 , it includes a status monitoring circuit. The input end of the status monitoring circuit is connected to SiC MOSFET , and the output end of the status monitoring circuit is connected to the input end of the logic circuit 3. The output end of the logic circuit 3 is respectively connected to the input end of the level shift circuit 4 and the input end of the Miller clamping branch 5. The output end of the level shift circuit 4 is connected to the input end of the buffer buffer , and the output end of the buffer buffer is connected to the input end of the Miller clamping branch 5. The output end of the Miller clamping branch 5 is connected to SiC MOSFET .

[0021] Embodiment 2 This embodiment provides a bidirectional crosstalk suppression circuit based on SiC MOSFET the module. As shown in Figure 1 , it includes a status monitoring circuit. The input end of the status monitoring circuit is connected to SiC MOSFETConnected, the output terminal of the status monitoring circuit is connected to the input terminal of logic circuit 3, and the output terminal of logic circuit 3 is respectively connected to the input terminal of level shift circuit 4 and the input terminal of Miller clamping branch 5. The output terminal of level shift circuit 4 is connected to the input terminal of buffer buffer and the output terminal of buffer buffer is connected to the input terminal of Miller clamping branch 5. The output terminal of Miller clamping branch 5 is connected to SiC MOSFET Connected.

[0022] The status monitoring circuit includes V d status monitoring circuit 1, V d The input terminal of status monitoring circuit 1 is connected to the drain of SiC MOSFET , V d The output terminal of status monitoring circuit 1 is connected to the input terminal of logic circuit 3.

[0023] V d Status monitoring circuit 1 includes a voltage dividing circuit, and the voltage dividing circuit includes several series-connected RC parallel voltage dividing networks. The input terminal of the voltage dividing circuit is connected to the drain of SiC MOSFET , and the output terminal of the voltage dividing circuit is connected to the positive input terminal of comparator A 1 . The negative input terminal of A 1 is connected to the reference voltage V ref2 Connected. The output terminal of comparator A 1 is connected to the input terminal of logic circuit 3. The positive input terminal of comparator A 1 , the output terminal of the voltage dividing circuit and the input terminal of diode D 1 are connected. The output terminal of diode D 1 is connected to the low operating voltage V DDL Connected; the positive input terminal of comparator A 1 , the output terminal of the voltage dividing circuit, the input terminal of diode D 1 are connected to the output terminal of diode D 2 . The input terminal of diode D 2 is grounded.

[0024] Embodiment 3 This embodiment proposes a bidirectional crosstalk suppression circuit based on SiC MOSFET module, such asFigure 1 As shown, it includes a status monitoring circuit. The input end of the status monitoring circuit is connected to SiC MOSFET , the output end of the status monitoring circuit is connected to the input end of logic circuit 3, the output end of logic circuit 3 is respectively connected to the input end of level shift circuit 4 and the input end of Miller clamping branch 5, the output end of level shift circuit 4 is connected to the input end of buffer buffer , the output end of buffer buffer is connected to the input end of Miller clamping branch 5, and the output end of Miller clamping branch 5 is connected to SiC MOSFET .

[0025] The status monitoring circuit includes V d status monitoring circuit 1, V d The input end of status monitoring circuit 1 is connected to the drain of SiC MOSFET , V d The output end of status monitoring circuit 1 is connected to the input end of logic circuit 3.

[0026] V d Status monitoring circuit 1 includes a voltage dividing circuit. The voltage dividing circuit includes several series-connected RC parallel voltage dividing networks. The input end of the voltage dividing circuit is connected to the drain of SiC MOSFET , the output end of the voltage dividing circuit is connected to the positive input end of comparator A 1 , the negative input end of A 1 is connected to the reference voltage V ref2 , the output end of comparator A 1 is connected to the input end of logic circuit 3. The positive input end of comparator A 1 , the output end of the voltage dividing circuit and the input end of diode D 1 are connected. The output end of diode D 1 is connected to the low operating voltage V DDL ; The positive input end of comparator A 1 , the output end of the voltage dividing circuit, the input end of diode D 1 are connected to the output end of diode D 2 , and the input end of diode D 2 is grounded.

[0027] The status monitoring circuit also includesV g State monitoring circuit 2 V g The input terminal of the state monitoring circuit 2 is connected to SiC MOSFET the gate of V g The output terminal of the state monitoring circuit 2 is connected to the input terminal of the logic circuit 3. V g The state monitoring circuit 2 includes a comparator A 2 , and the positive input terminal of the comparator A 2 is connected to the gate of SiC MOSFET , the negative input terminal of the comparator A 2 is connected to the reference voltage V ref1 , and the output terminal of the comparator A 2 is connected to the input terminal of the logic circuit 3; the positive input terminal of the comparator A 2 , SiC MOSFET the gate of D 3 is connected to the input terminal of the diode D 3 , and the output terminal of the diode V DDL is connected to the low operating voltage A 2 , SiC MOSFET the gate of D 3 , the positive input terminal of the comparator D 4 is connected to the output terminal of the diode D 4 , and the input terminal of the diode

[0028] Example 4 This example proposes a bidirectional crosstalk suppression circuit based on the SiC MOSFET module, as shown in Figure 1 . It includes a state monitoring circuit. The input terminal of the state monitoring circuit is connected to SiC MOSFET , the output terminal of the state monitoring circuit is connected to the input terminal of the logic circuit 3, the output terminal of the logic circuit 3 is respectively connected to the input terminal of the level shifting circuit 4 and the input terminal of the Miller clamping branch 5, the output terminal of the level shifting circuit 4 is connected to the input terminal of the buffer buffer , the output terminal of the buffer buffer is connected to the input terminal of the Miller clamping branch 5, and the output terminal of the Miller clamping branch 5 is connected to SiC MOSFET .

[0029] The status monitoring circuit includes V d status monitoring circuit 1, V d The input end of status monitoring circuit 1 is connected to the SiC MOSFET drain of V d The output end of status monitoring circuit 1 is connected to the input end of logic circuit 3. V d Status monitoring circuit 1 includes a voltage dividing circuit, and the voltage dividing circuit includes several series-connected RC parallel voltage dividing networks. The input end of the voltage dividing circuit is connected to the SiC MOSFET drain of A 1 The output end of the voltage dividing circuit is connected to the positive input end of comparator A 1 The negative input end of V ref2 is connected to the reference voltage A 1 The output end of comparator A 1 The positive input end of, the output end of the voltage dividing circuit, and the input end of diode D 1 are connected. The output end of diode D 1 is connected to the low operating voltage V DDL ; The positive input end of comparator A 1 The positive input end of, the output end of the voltage dividing circuit, and the input end of diode D 1 are connected to the output end of diode D 2 The input end of diode D 2 is grounded. The status monitoring circuit also includes V g status monitoring circuit 2, V g The input end of status monitoring circuit 2 is connected to the SiC MOSFET gate of V g The output end of status monitoring circuit 2 is connected to the input end of logic circuit 3. V g Status monitoring circuit 2 includes comparator A 2 , comparator A 2 The positive input end of is connected to the SiC MOSFET gate of A 2The negative input terminal is connected to the reference voltage V ref1 and the output terminal of the comparator A 2 is connected to the input terminal of logic circuit 3; the positive input terminal of the comparator A 2 , SiC MOSFET the gate of D 3 is connected to the input terminal of the diode D 3 and the output terminal of the diode V DDL is connected to the low operating voltage A 2 ; the positive input terminal of the comparator SiC MOSFET the gate of D 3 the input terminal of the diode D 4 is connected to the output terminal of the diode D 4 and the input terminal of the diode

[0030] is grounded. Logic circuit 3 includes a NOR gate N 1 , N 1 the input terminals of the NOR gate A 1 are respectively connected to the output terminal of the comparator A 2 , N 1 the output terminal of the NOR gate N 2 is connected to the input terminal of the inverter N 2 ; the output terminal of the inverter N 4 is connected to the input terminal of the NAND gate N 4 and the input terminal of the NAND gate N 3 is also connected to the output terminal of the inverter N 2 ; the input terminal of the inverter SiC MOSFET is connected to the gate drive signal of V drive ; the output terminal of the NAND gate N 4 is connected to the input terminal of the level shift circuit 4. Logic circuit 3 also includes a NOR gate N 6 , N 6The input ends are respectively connected to the gate drive signal V drive , the output end of the inverter N 5 . The input end of the inverter N 5 is connected to the output end of the comparator A 2 . The output end of the NOR gate N 6 is connected to the input end of the Miller clamping branch 5. The output end of the NOR gate N 6 generates the control signal V ctrl .

[0031] Embodiment 5 This embodiment proposes a bidirectional crosstalk suppression circuit based on the SiC MOSFET module, as shown in Figure 1 . It includes a state monitoring circuit. The input end of the state monitoring circuit is connected to SiC MOSFET . The output end of the state monitoring circuit is connected to the input end of the logic circuit 3. The output end of the logic circuit 3 is respectively connected to the input end of the level shift circuit 4 and the input end of the Miller clamping branch 5. The output end of the level shift circuit 4 is connected to the input end of the buffer buffer . The output end of the buffer buffer is connected to the input end of the Miller clamping branch 5. The output end of the Miller clamping branch 5 is connected to SiC MOSFET .

[0032] The state monitoring circuit includes V d the state monitoring circuit 1, V d The input end of the state monitoring circuit 1 is connected to the drain of SiC MOSFET . V d The output end of the state monitoring circuit 1 is connected to the input end of the logic circuit 3. V d The state monitoring circuit 1 includes a voltage dividing circuit. The voltage dividing circuit includes several series-connected RC parallel voltage dividing networks. The input end of the voltage dividing circuit is connected to the drain of SiC MOSFET . The output end of the voltage dividing circuit is connected to the positive input end of the comparator A 1 . The negative input end of the A 1 is connected to the reference voltage V ref2 . The output end of the comparator A 1 is connected to the input end of the logic circuit 3. The output end of the comparator A1 The positive input terminal, the output terminal of the voltage dividing circuit are connected to the diode D 1 's input terminal, and the diode D 1 's output terminal is connected to the low operating voltage V DDL ; The positive input terminal of the comparator A 1 The positive input terminal, the output terminal of the voltage dividing circuit, the diode D 1 's input terminal is connected to the diode D 2 's output terminal, and the diode D 2 's input terminal is grounded. The status monitoring circuit further includes V g Status monitoring circuit 2, V g The input terminal of status monitoring circuit 2 is connected to the SiC MOSFET 's gate, V g The output terminal of status monitoring circuit 2 is connected to the input terminal of logic circuit 3. V g Status monitoring circuit 2 includes a comparator A 2 , and the comparator A 2 's positive input terminal is connected to the SiC MOSFET 's gate, the comparator A 2 's negative input terminal is connected to the reference voltage V ref1 , and the comparator A 2 's output terminal is connected to the input terminal of logic circuit 3; The comparator A 2 's positive input terminal, SiC MOSFET 's gate is connected to the diode D 3 's input terminal, and the diode D 3 's output terminal is connected to the low operating voltage V DDL ; The comparator A 2 's positive input terminal, SiC MOSFET 's gate, the diode D 3 's input terminal is connected to the diode D 4 's output terminal, and the diode D 4 's input terminal is grounded.

[0033] The logic circuit 3 includes a NOR gate N 1 , the NOR gate N 1 's input terminals are respectively connected to the output terminals of the comparator A 1 , the comparator A 2 's output terminal. The output terminal of the NOR gate N 1 is connected to the input terminal of the inverter N 2 . The output terminal of the inverter N 2 is connected to the input terminal of the NAND gate N 4 . The input terminal of the NAND gate N 4 is also connected to the output terminal of the inverter N 3 . The input terminal of the inverter N 2 is connected to the SiC MOSFET gate drive signal V drive . The output terminal of the NAND gate N 4 is connected to the input terminal of the level shift circuit 4. The logic circuit 3 also includes a NOR gate N 6 , the NOR gate N 6 's input terminals are respectively connected to the gate drive signal V drive , the output terminal of the inverter N 5 . The input terminal of the inverter N 5 is connected to the output terminal of the comparator A 2 . The output terminal of the NOR gate N 6 is connected to the input terminal of the Miller clamping branch 5. The output terminal of the NOR gate N 6 generates a control signal V ctrl .

[0034] The level shift circuit 4 includes a triode Q 3 and an inverter N 5 . The gate of the triode Q 3 , the input terminal of the inverter N 5 and the NAND gate N4 The output terminal of the inverter is connected to N 5 The output terminal of the is connected to the triode Q 4 The gate of the triode is connected to Q 3 The source of the triode is connected to the triode Q 4 The source of the triode is connected to Q 3 The drain of the triode is connected to the triode Q 1 The drain of the triode, the triode Q 2 The gate of the triode is connected; the triode Q 4 The drain of the triode is connected to the triode Q 2 The drain of the triode, the triode Q 1 The gate of the triode, the buffer buffer The input terminal of the is connected; the triode Q 1 The source of the triode, the triode Q 2 The source of the triode is connected to the high operating voltage V DDH connected.

[0035] Embodiment 6 This embodiment proposes a bidirectional crosstalk suppression circuit based on SiC MOSFET module, as shown in Figure 1 shown, including a state monitoring circuit, the input terminal of the state monitoring circuit is connected to SiC MOSFET connected, the output terminal of the state monitoring circuit is connected to the input terminal of logic circuit 3, the output terminal of logic circuit 3 is respectively connected to the input terminal of level shift circuit 4 and the input terminal of Miller clamping branch 5, the output terminal of level shift circuit 4 is connected to the input terminal of buffer buffer connected, the output terminal of buffer buffer is connected to the input terminal of Miller clamping branch 5, and the output terminal of Miller clamping branch 5 is connected to SiC MOSFET connected.

[0036] The state monitoring circuit includes V d State monitoring circuit 1, V d The input terminal of state monitoring circuit 1 is connected to the SiC MOSFET drain of V d The output terminal of state monitoring circuit 1 is connected to the input terminal of logic circuit 3. V d State monitoring circuit 1 includes a voltage dividing circuit, and the voltage dividing circuit includes a number of series-connectedRC A parallel voltage-dividing network, the input end of the voltage-dividing circuit is connected to SiC MOSFET the drain of A 1 , the output end of the voltage-dividing circuit is connected to the positive input end of the comparator A 1 , the negative input end of V ref2 is connected to the reference voltage A 1 , the output end of the comparator A 1 is connected to the input end of logic circuit 3. The positive input end of the comparator D 1 , the output end of the voltage-dividing circuit are connected to the input end of the diode D 1 , the output end of the diode V DDL is connected to the low operating voltage A 1 , the positive input end of the comparator D 1 , the output end of the voltage-dividing circuit, the input end of the diode D 2 are connected to the output end of the diode D 2 , the input end of the diode V g is grounded. The status monitoring circuit further includes V g status monitoring circuit 2, SiC MOSFET the input end of status monitoring circuit 2 is connected to the gate of V g , the output end of status monitoring circuit 2 is connected to the input end of logic circuit 3. V g Status monitoring circuit 2 includes a comparator A 2 , the positive input end of the comparator A 2 is connected to the gate of SiC MOSFET , the negative input end of the comparator A 2 is connected to the reference voltage V ref1 , the output end of the comparator A 2 is connected to the input end of logic circuit 3; the positive input end of the comparator A 2 , the gate of SiC MOSFET are connected to the input end of the diode D 3 , the output end of the diode D 3The output terminal is connected to the low operating voltage V DDL ; The comparator A 2 The positive input terminal of, SiC MOSFET The gate of, the diode D 3 The input terminal of is connected to the diode D 4 The output terminal of, the diode D 4 The input terminal of is grounded.

[0037] The logic circuit 3 includes a NOR gate N 1 , the NOR gate N 1 The input terminals of are respectively connected to the output terminal of the comparator A 1 , the output terminal of the comparator A 2 The output terminal of, the NOR gate N 1 The output terminal of is connected to the input terminal of the inverter N 2 , the inverter N 2 The output terminal of and the input terminal of the NAND gate N 4 , the NAND gate N 4 The input terminal of is also connected to the output terminal of the inverter N 3 , the inverter N 2 The input terminal of is connected to SiC MOSFET The gate drive signal of V drive Connected, the NAND gate N 4 The output terminal of is connected to the input terminal of the level shift circuit 4. The logic circuit 3 also includes a NOR gate N 6 , the NOR gate N 6 The input terminals of are respectively connected to the gate drive signal V drive , the output terminal of the inverter N 5 , the inverter N 5 The input terminal of is connected to the output terminal of the comparator A 2 , the NOR gate N 6 The output terminal of is connected to the input terminal of the Miller clamp branch 5, the NOR gate N6 The output terminal generates a control signal V ctrl .

[0038] The level shift circuit 4 includes a triode Q 3 and an inverter N 5 , the gate of the triode Q 3 , the input terminal of the inverter N 5 and the output terminal of the NAND gate are connected. The output terminal of the inverter N 4 is connected to the gate of the triode N 5 . The output terminal of the triode Q 4 is connected to the gate of the triode Q 3 . The source of the triode Q 4 is connected to the source of the triode Q 3 . The drain of the triode Q 1 is connected to the drain of the triode Q 2 and the gate of the triode Q 4 . The drain of the triode Q 2 is connected to the drain of the triode Q 1 , the gate of the buffer buffer and the input terminal. The source of the triode Q 1 , the source of the triode Q 2 are connected to the high operating voltage V DDH .

[0039] The Miller clamping branch 5 includes a switching transistor M switch , the gate of the switching transistor M switch is connected to the output terminal of the buffer buffer . The drain of the switching transistor M switch is connected to the SiC MOSFET source. The source of the switching transistor M switch is connected to the drain of the triode M 1 , one end of the capacitor C MC . One end of the capacitor CMC The other end is connected to a triode M 1 whose source is grounded, and the triode M 1 has its gate connected to a control signal V ctrl .

[0040] In the present invention V d the state monitoring circuit 1 is used to monitor SiC MOSFET the drain voltage V d and its circuit includes RC a parallel voltage division network and a comparator. Through RC the voltage division network, the drain voltage V d is converted from several hundred volts to within 5V required by the comparator input, and then compared with a reference voltage V ref2 to generate a digital signal d 2 so as to judge the stage at which crosstalk occurs.

[0041] V g The state monitoring circuit 2 is used to detect SiC MOSFET the gate voltage V g The state monitoring circuit 2 consists of a comparator A 2 which SiC MOSFET compares the V g gate voltage V g and when forward crosstalk occurs, the gate voltage V ref1 is greater than the reference voltage d 1 , then a digital signal V d is generated. The logic circuit 3 is used to perform combinational logic operations on g the logic signals generated by the state monitoring circuit 1 and V d the state monitoring circuit 2. The logic circuit 3 combines V g the two digital signals generated by the state monitoring circuit 1 and d 1 the d 2 gate drive signal SiC MOSFET combined with V drive to perform combinational logic operations and output a pulse square waveY This signal can be used to identify the start and end of the two-way crosstalk generated by the power device, and control the switch of the Miller clamping branch 5 through the finally output signal. In addition, the logic circuit 3 also generates a control signal V ctrl connected to the triode in the double discharge path in the Miller clamping branch 5 M 1 The level shift circuit 4 is used to shift the signal output by the logic circuit 3 from 0 - 5V V DDL to 0 - 20V V DDH This circuit changes the signal generated by the logic circuit 3 into a pulse square wave signal of 0 - 20V to control the switch of the Miller clamping branch 5

[0042] The Miller clamping branch 5 is used to suppress the two-way crosstalk and serves as an auxiliary path for suppressing crosstalk. This circuit includes a switching transistor M switch and a double discharge path. The switching transistor M switch is controlled by a logic control signal to turn on and off. When positive crosstalk occurs, the switching transistor M switch is turned on, and the charge generated by the positive crosstalk is stored in the capacitor C MC in the discharge path and stored. In this way, when positive crosstalk occurs, a discharge path is provided, suppressing the positive crosstalk and at the same time providing a charge extraction source for negative crosstalk. When the positive crosstalk ends, the switching transistor M switch is turned off. When negative crosstalk occurs, the switching transistor M of the Miller clamping branch 5 switch is turned on, and the previously stored charge is released to cancel the generation of negative crosstalk. When the negative crosstalk ends, the Miller clamping branch 5 is turned off. In addition, the Miller clamping branch 5 adopts a branch discharge strategy, using two paths for discharge when crosstalk occurs, reducing the capacitance value of the capacitor, realizing the integration of the capacitor, and improving the overall crosstalk suppression effect

[0043] The present invention generates two digital signals V d and V g through the state monitoring circuit 1 d 1 and d 2 the state monitoring circuit 2, and through the combinational logic operation of the logic circuit 3 with the gate drive signal, generates a pulse signal of 0 - 5V Y, this signal can accurately determine the beginning and end of crosstalk. On this basis, the pulse signal is shifted from 0 - 5V to 0 - 20V by the level - shifting circuit 4, and then passes through a buffer composed of three inverters buffer to drive the on - off of the switching transistor in the Miller clamping branch 5. The present invention only operates when crosstalk occurs and will not increase SiC MOSFET extra losses.

[0044] Starting from the SiC MOSFET generation of crosstalk, the present invention proposes an integrated active IC Miller clamping bidirectional crosstalk suppression circuit. By SiC MOSFT monitoring the drain voltage V d and the gate voltage V g of the state monitoring circuit to identify the beginning and end of positive crosstalk and negative crosstalk, the Miller clamping branch 5 is only turned on during crosstalk. Without increasing SiC MOSFET switching losses, the effective suppression of bidirectional crosstalk is achieved.

Claims

1. Based on SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: A state monitoring circuit is included, wherein the input terminal of the state monitoring circuit is connected to SiC MOSFET The output end of the state monitoring circuit is connected to the input end of the logic circuit (3), the output end of the logic circuit (3) is respectively connected to the input end of the level shift circuit (4) and the input end of the Miller clamp branch (5), and the output end of the level shift circuit (4) is connected to the buffer buffer The input terminals of the buffer are connected buffer The output end of the Miller clamp branch (5) is connected to the input end of the Miller clamp branch (5). SiC MOSFET connect.

2. According to claim 1, based on SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: The state monitoring circuit includes V d The state monitoring circuit (1) V d The input terminal of the state monitoring circuit (1) is connected to SiC MOSFET The drain connection of the V d The output end of the state monitoring circuit (1) is connected to the input end of the logic circuit (3).

3. According to claim 2 based on SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: Said V d The state monitoring circuit (1) comprises a voltage divider circuit, wherein the voltage divider circuit comprises a plurality of RC A voltage divider network is connected in parallel, the input end of the voltage divider circuit is connected to SiC MOSFET The drain of the voltage divider circuit is connected to the output of the comparator A 1 is connected to the positive input terminal of the A 1 negative input terminal and reference voltage V ref2 connection, the comparator A The output terminal of 1 is connected to the input terminal of the logic circuit (3).

4. The method according to claim 3 SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: The comparator A 1, the positive input terminal, the output terminal of the voltage divider circuit and the diode D 1 is connected to the input terminal, the diode D 1 output with low operating voltage V DDL Connection; the comparator A 1's positive input terminal, the output terminal of the voltage divider circuit, and the diode D 1 input terminal and diode D 2 output terminals are connected, the diode D 2's input terminal is grounded.

5. The method according to claim 4 SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: The state monitoring circuit also includes V g The state monitoring circuit (2) V g The input terminal of the state monitoring circuit (2) is connected to SiC MOSFET The gate connection of the V g The output end of the state monitoring circuit (2) is connected to the input end of the logic circuit (3).

6. The method according to claim 5 SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: Said V g The state monitoring circuit (2) includes a comparator A 2. The comparator A 2's positive input terminal is connected to SiC MOSFET The gate connection of the comparator A 2. The negative input terminal is connected to the reference voltage V ref1 connection, the comparator A The output terminal of 2 is connected to the input terminal of the logic circuit (3); The comparator A 2's positive input terminal, SiC MOSFET The gate and diode D 3. The input terminal is connected to the diode D 3 output terminals with low operating voltage V DDL Connection; the comparator A 2's positive input terminal, SiC MOSFET Gate, diode D 3. The input terminal and diode D 4 output terminals are connected, the diode D The input terminal of 4 is grounded.

7. The method according to claim 6 SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: The logic circuit (3) comprises a NOR gate N 1. The NOR gate N 1 input terminals are connected to the comparator A 1 output, comparator A 2 output terminals are connected to the NOR gate N 1 output terminal and inverter N 2 input terminals are connected to the inverter N 2 output and NAND gate N 4 input terminals are connected to the NAND gate N The input of 4 is also connected to an inverter N 3 output terminal, the inverter N 2 input terminal and SiC MOSFET The gate drive signal V drive connection, the NAND gate N The output end of 4 is connected to the input end of the level shift circuit (4).

8. The method according to claim 7 SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: The logic circuit (3) further comprises a NOR gate N 6. The NOR gate N The input terminals of 6 are respectively connected to the gate drive signal V drive , Inverter N 5 output terminal is connected to the inverter N 5 input terminal and comparator A 2 output terminals are connected to the NOR gate N The output end of 6 is connected to the input end of the Miller clamp branch (5), and the NOR gate N The output terminal of 6 generates a control signal V ctrl .

9. The method according to claim 8 SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: The level shift circuit (4) comprises a transistor Q 3 and inverter N 5. The transistor Q 3 gate, inverter N 5 input and NAND gate N 4 output terminals are connected to the inverter N The output terminal of 5 and the transistor Q 4 is connected to the gate of the transistor Q 3 source and transistor Q 4 source connection, the transistor Q 3. The drain and transistor Q 1's drain, transistor Q 2 is connected to the gate of the transistor; Q 4's drain and transistor Q 2's drain, transistor Q 1 gate, buffer buffer The input end of the transistor is connected; Q 1 source, transistor Q 2 source with high operating voltage V DDH connect.

10. The method according to claim 9 SiC MOSFET The bidirectional crosstalk suppression circuit of the module is characterized in that: The Miller clamp branch (5) includes a switch tube M switch , the switch tube M switch Gate and buffer buffer The output end of the switch is connected to M switch The drain and SiC MOSFET The source of the switch is connected M switch The source and transistor M 1's drain, capacitance C MC One end is connected to the capacitor C MC The other end of the transistor M 1 has its source grounded, the transistor M 1 gate and control signal V ctrl connect.

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