A multi-level inverter suitable for energy storage grid system and its modulation method

Abstract

This invention provides a multilevel inverter and its modulation method suitable for energy storage grid systems. The inverter includes a main circuit unit and a main modulation unit, employing three DC power supplies, ten switching transistors, and a load, achieving an eleven-level output voltage through different combinations of switching transistors. The main modulation unit uses multi-carrier level phase-shifted SPWM modulation technology, ensuring stable operation in multi-energy input and energy storage systems through precise phase control and power calculation. This invention significantly improves power conversion efficiency and dynamic response, adapts to multi-energy collaborative power supply scenarios, solves the application bottleneck of existing multilevel inverters in energy storage grid systems, and enhances system reliability and flexibility.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a multilevel inverter and its modulation method suitable for energy storage grid systems, particularly suitable for wind-solar-storage co-power supply and efficient power conversion and grid connection control in energy storage systems. Background Technology

[0002] With the continuous increase in the proportion of new energy sources, energy storage grid systems place higher demands on the multi-mode operation capabilities of power electronic converters. Traditional multilevel inverters face significant bottlenecks in meeting the control requirements of grid-based systems: their circuit topologies generally adopt a single DC input design, making it difficult to adapt to the differentiated access requirements of various power sources in wind-solar-storage co-power supply scenarios, leading to frequent power coupling phenomena; on the other hand, traditional modulation strategies are prone to causing output voltage phase jumps during the switching between islanded operation and grid-connected mode, resulting in excessive harmonic distortion rate at the grid connection point, and in severe cases, triggering protective grid disconnection. Although existing cascaded H-bridge topologies can increase the number of levels through module stacking, this brings problems such as a surge in the number of switching devices and increased complexity of capacitor voltage equalization logic. Especially in the inertia support stage of the grid system, the delay characteristics of multi-module collaborative control will degrade the dynamic response of frequency regulation. In addition, under the power surge conditions caused by frequent charging and discharging of energy storage systems, traditional PI controllers are unable to achieve rapid current tracking, causing the DC bus voltage fluctuation rate to exceed the safety threshold, directly affecting the power supply reliability of the grid system.

[0003] To address the aforementioned pain points, there is an urgent need to develop an inverter architecture that combines topology simplification with dynamic performance to meet the dual requirements of energy storage grid systems for efficient power conversion and active grid support. Summary of the Invention

[0004] This invention discloses a multilevel inverter and its modulation method suitable for energy storage grid systems. By employing a combination design of multiple DC power supplies and switching transistors, a multilevel output voltage is provided, achieving efficient power conversion. In terms of control, a multi-carrier level phase-shifting SPWM modulation module is used. Through precise phase control and power calculation, the inverter ensures stable operation in environments with multiple energy inputs and supports efficient energy conversion for energy storage systems. This invention not only improves power conversion efficiency and dynamic response but also enhances the system's adaptability in wind-solar-storage co-power supply scenarios, effectively solving the application bottlenecks of traditional inverters in energy storage grid systems and improving system reliability and flexibility.

[0005] A multilevel inverter suitable for energy storage grid systems is characterized by comprising a main circuit unit and a main modulation unit:

[0006] The main circuit unit includes a DC power supply V dc1 、V dc2 、V dc3Switches S1, S2, ..., S 10 Load Z L ;

[0007] The main modulation unit includes: a phase-locked loop module, a phase angle calculation module, a power calculation module, a phase compensation module, a multiplier MUL, an adder SUM, a PR controller, a multi-carrier level phase-shifting SPWM modulation module, and a drive circuit;

[0008] This multilevel inverter includes three DC power supplies with clearly defined voltage level relationships: DC power supply V dc1 、V dc2 、V dc3 The voltage level meets V dc1 :V dc2 :V dc3 = 1:2:2, and V dc1 =V dc ;

[0009] This multilevel inverter can generate eleven different output levels in each duty cycle through the control of the switching network, namely: a forward voltage of 5V. dc 4V dc 3V dc 2V dc 、V dc Zero voltage 0, reverse voltage -V dc -2V dc -3V dc -4V dc -5V dc .

[0010] The output voltage is a positive voltage of 5V. dc When the circuit is open, switches S1, S2, S7, and S8 are turned on, while the other switches are turned off, resulting in an output voltage V0 of 5V. dc ;

[0011] The output voltage is a positive voltage of 4V. dc At that time, switching transistors S1, S2, S7, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is 4V. dc ;

[0012] The output voltage is a positive voltage of 3V. dc When the circuit is open, switches S1, S2, S5, S6, and S8 are turned on, while the other switches are turned off, resulting in an output voltage V0 of 3V. dc ;

[0013] The output voltage is a positive voltage of 2V. dc At that time, switching transistors S1, S2, S5, S6, S9 and S 10When the transistor is turned on, all other switches are turned off, and the output voltage V0 is 2V. dc ;

[0014] The output voltage is a positive voltage V dc When the switching transistors S1, S4, and S8 are turned on, and the other switching transistors are turned off, the output voltage V0 is V dc ;

[0015] When the output voltage is zero, switches S3, S7 and S8 are turned on, and the other switches are turned off, so the output voltage V0 is 0.

[0016] The output voltage is the reverse voltage -V dc At that time, switching transistors S3, S7, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is -V. dc ;

[0017] The output voltage is reverse voltage -2V dc When the circuit is open, switches S3, S5, S6, and S8 are turned on, while the other switches are turned off, resulting in an output voltage V0 of -2V. dc .

[0018] The output voltage is reverse voltage -3V dc At that time, switching transistors S3, S5, S6, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is -3V. dc ;

[0019] The output voltage is reverse voltage -4V dc When the circuit is open, switches S2, S3, S4, and S8 are turned on, while the other switches are turned off, resulting in an output voltage V0 of -4V. dc ;

[0020] The output voltage is reverse voltage -5V. dc At that time, switching transistors S2, S3, S4, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is -5V. dc .

[0021] The main circuit unit of this multilevel inverter is suitable for cascading multiple additional circuit units with the main circuit unit. Each additional circuit unit is the same as the main circuit unit, with the same components and configuration.

[0022] A modulation method for a multilevel inverter suitable for energy storage grid systems is implemented through a multi-carrier level phase-shifting SPWM modulation module, which performs the following modulation steps:

[0023] S1: Generate five sets of triangular carrier signals with equal amplitude and consistent frequency. Each set of carrier signals is arranged in a horizontal phase-shifted manner in the vertical direction. The amplitudes of each set of carrier signals are adjacent and do not overlap.

[0024] S2: Generates a sinusoidal modulated wave signal with an amplitude comparable to the overall peak-to-peak value of the carrier signal;

[0025] S3: The sinusoidal modulation wave signal is compared with five sets of triangular carrier signals in real time to generate corresponding switching trigger signals, control the switching transistors of the multilevel inverter to obtain the required eleven-level output voltage waveform.

[0026] A method for overall modulation of the main modulation unit of a multilevel inverter suitable for energy storage grid systems includes:

[0027] S1: The input terminal of the phase-locked loop module receives the output voltage V from the main circuit. o The phase loop module extracts the load voltage phase θ and transmits the load voltage phase θ to the phase compensation module at its output. The phase angle calculation module receives the given reactive power reference value Q. ref and active power reference value P ref The phase angle calculation module calculates the target reference current i. ref The phase angle φ, the output of the phase angle calculation module is used to calculate the target reference current i. ref The value φ is transmitted to the phase compensation module; the power calculation module receives the given active power reference value P. ref The power calculation module receives a given reactive power reference value Q. ref The power calculation module calculates the required output current amplitude i. o,m The power calculation module will output the current amplitude i. o,m Passed to the multiplier MUL;

[0028] S2: The input terminal of the phase compensation module receives the load voltage phase θ output from the output terminal of the phase-locked loop module, and combines it with the calculated target reference current i. ref Given the phase angle φ, calculate the output current i. o The phase compensation signal, the output terminal of the phase compensation module will output current i o The phase compensation signal is transmitted to the multiplier MUL;

[0029] S3: Output current amplitude i at the output terminal of the multiplier MUL receiving power calculation module o,m The multiplier MUL receives the output current i from the output terminal of the phase compensation module. o The phase offset signal, the output of the multiplier MUL will be the target reference current i ref Passed to adder SUM;

[0030] S4: Adder SUM receives the target reference current i from the output of multiplier MUL. ref The adder SUM receives the output current i from the main circuit unit. o The output of the adder SUM will calculate the current error signal e. i The data is transmitted to the input of the PR controller;

[0031] S5: The input terminal of the PR controller receives the current error signal e from the output terminal of the adder SUM. i The output of the PR controller will be the target reference voltage V. ref The signal is transmitted to the input of the multi-carrier level phase-shift SPWM modulation module;

[0032] S6: The input terminal of the multi-carrier level phase-shift SPWM modulation module receives the target reference voltage V from the output terminal of the PR controller. ref The ten output terminals of the multi-carrier level phase-shift SPWM modulation module output modulation signals P1, P2, ..., P1, P2, ..., P3 respectively. 10 To the drive circuit;

[0033] S7: The ten input terminals of the drive circuit respectively receive the ten modulation signals P1, P2, ..., P from the ten output terminals of the multi-carrier level phase-shift SPWM modulation module. 10 The ten output terminals of the drive circuit output control signals to control the switching transistors S1, S2, ..., S... 10 Duty cycle.

[0034] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0035] (1) Improved power conversion efficiency: By adopting a multi-level output voltage design, the present invention significantly improves the power conversion efficiency, especially in energy storage systems with multiple energy inputs, which can more efficiently convert electrical energy into the required power output.

[0036] Enhanced system stability and dynamic response capability: This invention utilizes precise phase control and power calculation to optimize dynamic response capability, ensuring stable operation of the inverter in multi-energy collaborative power supply scenarios, and is particularly suitable for the frequent power fluctuations in energy storage network systems.

[0037] Addressing the bottlenecks of traditional multilevel inverters: Existing inverters face numerous challenges in energy storage grid systems, such as power coupling, harmonic distortion, and frequency regulation. This invention solves these problems through multilevel voltage output and precise modulation control, improving system reliability and flexibility.

[0038] Multi-energy input compatibility: The inverter designed in this invention is compatible with multiple energy inputs such as wind, solar and energy storage, effectively avoiding the power coupling problem of traditional inverters when multiple energy inputs are used, and adapting to the needs of modern energy storage grid systems.

[0039] Improve grid connection control accuracy: Through multi-carrier level phase-shifting SPWM modulation technology, the output voltage of the inverter is precisely controlled during grid connection switching, reducing phase jumps and harmonic distortions during grid connection, thereby improving grid connection quality and stability.

[0040] Optimizing energy storage system performance: This invention optimizes the charging and discharging process of the energy storage system. Through rapid current tracking control, it reduces the fluctuation of the DC bus voltage of the energy storage system, further improving the power supply reliability and efficiency of the system.

[0041] The multilevel inverter for energy storage grid systems provided by this invention has the following advantages:

[0042] S1: It adopts a combination topology of three DC power supplies with specific voltage ratios and ten switching transistors, and achieves eleven-level output through switching network control. Compared with the traditional cascaded H-bridge structure, it significantly reduces the number of switching devices, and reduces hardware cost and system complexity while avoiding the problem of capacitor voltage equalization.

[0043] S2: The main circuit unit adopts a standardized isomorphic design, which supports cascading with multiple expansion units with the same configuration to form a modular power unit chain. The number of output voltage levels can be flexibly expanded through unit replication to meet the expansion needs of different power levels of energy storage grid systems.

[0044] S3: Equipped with multiple types of DC power supply compatible interfaces, it can adapt to the collaborative access of different power sources such as photovoltaic arrays, energy storage batteries, and supercapacitors. In the event of a single energy source failure, it automatically switches to backup power supply, significantly improving system redundancy and fault tolerance.

[0045] The multilevel inverter modulation method provided by this invention has the following advantages:

[0046] S1: Innovatively adopts a multi-carrier level phase-shifting SPWM modulation strategy, which compares the triangular carrier waves with the sinusoidal modulation wave in real time through phase-interleaved arrangement to accurately generate multi-level output waveforms, effectively reducing the total harmonic distortion rate and meeting the stringent power quality requirements of the grid system.

[0047] S2: Construct a three-level regulation architecture of phase-locked loop-phase compensation-PR controller. Through dynamic phase tracking and power parameter mapping, the output current can quickly and synchronously track the load voltage. It can effectively suppress phase jump during mode switching and avoid the risk of system disconnection caused by excessive harmonics.

[0048] S3: Employing power calculation and dynamic compensation closed-loop control, it significantly improves dynamic response speed under sudden power changes in the energy storage system, effectively controls DC bus voltage fluctuations, and enhances the system's anti-disturbance capability and operational stability. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings will be briefly introduced below. The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the structure of a multilevel inverter suitable for an energy storage grid system according to an embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram illustrating the working principle of a multilevel inverter suitable for energy storage grid systems in an embodiment of the present invention.

[0052] Figure 3 This is a schematic diagram and the expected output voltage waveform of a multi-level inverter with multi-carrier level phase-shifting SPWM modulation suitable for energy storage grid systems, as shown in an embodiment of the present invention.

[0053] Figure 4 This is a flowchart illustrating a multilevel inverter main modulation unit suitable for an energy storage grid system, as described in an embodiment of the present invention.

[0054] Figure 5 This is a schematic diagram of a cascaded multilevel inverter circuit for a multilevel inverter suitable for an energy storage grid system, as described in an embodiment of the present invention.

[0055] Figure 6 This is a schematic diagram of the eleven-level output waveform of a multilevel inverter suitable for energy storage grid systems, as described in an embodiment of the present invention. Detailed Implementation

[0056] To clearly illustrate the objectives, technical solutions, and features of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be further described below in conjunction with the prior art and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0057] Please refer to Figure 1 , Figure 1This is a schematic diagram of a multilevel inverter topology suitable for an energy storage grid system according to the present invention, including: a main circuit unit and a main control unit;

[0058] The main circuit unit includes a DC power supply V dc1 、V dc2 、V dc3 Switches S1, S2, ..., S 10 Load Z L ;

[0059] The emitter of the switching transistor S1 is connected to the DC power supply V. dc3 The negative terminal of transistor S1 is connected to the emitter of transistor S4, and the collector of transistor S1 is connected to the DC power supply V. dc1 The positive terminal of the transistor is connected to the collector of the switching transistor S9;

[0060] The emitter of the switching transistor S2 is connected to the DC power supply V. dc2 The negative terminal of transistor S5 is connected to the collector of transistor S5, and the collector of transistor S2 is connected to the DC power supply V. dc3 The positive electrode;

[0061] The emitter of the switching transistor S3 is connected to the DC power supply V. dc1 The negative terminal of transistor S3 is connected to the emitter of transistor S8, and the collector of transistor S3 is connected to the DC power supply V. dc2 The positive terminal of the transistor is connected to the collector of the switching transistor S7;

[0062] The collectors of switching transistors S4 and S6, the emitter of switching transistor S7, and the load Z. L The positive terminal connection;

[0063] The emitter of switch S5 is connected to the emitter of switch S6;

[0064] collector of switching transistor S8 and load Z L negative terminal, switching transistor S 10 collector connection;

[0065] The emitter of switch S9 is connected to switch S. 10 The emitter.

[0066] The main modulation unit includes: a phase-locked loop module, a phase angle calculation module, a power calculation module, a phase compensation module, a multiplier MUL, an adder SUM, a PR controller, a multi-carrier level phase-shifting SPWM modulation module, and a drive circuit;

[0067] The input terminal of the phase-locked loop module is connected to the load Z. L Between the positive and negative terminals, the output terminal of the phase-locked loop module is connected to the input terminal of the phase compensation module;

[0068] The phase angle calculation module receives the given reactive power reference value Q.ref and active power reference value P ref The output of the phase angle calculation module is connected to the input of the phase compensation module;

[0069] The power calculation module receives a given active power reference value P. ref and reactive power reference value Q ref The output of the power calculation module is connected to the input of the multiplier MUL;

[0070] The output of the phase compensation module is connected to the input of the multiplier MUL;

[0071] The output of multiplier MUL is connected to the input of adder SUM;

[0072] The input of adder SUM receives the output current i from the load terminal. o The output of adder SUM is connected to the input of PR controller;

[0073] The output of the PR controller is connected to the input of the multi-carrier level phase-shift SPWM modulation module;

[0074] The ten output terminals of the multi-carrier level phase-shift SPWM modulation unit are respectively connected to the ten input terminals of the drive circuit.

[0075] Please refer to Figure 2 , Figure 2 This is a schematic diagram illustrating the working principle of a multilevel inverter suitable for energy storage grid systems according to the present invention.

[0076] The output voltage is a positive voltage of 5V. dc When the circuit is open, switches S1, S2, S7, and S8 are turned on, while the other switches are turned off, resulting in an output voltage V0 of 5V. dc ;

[0077] The output voltage is a positive voltage of 4V. dc At that time, switching transistors S1, S2, S7, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is 4V. dc ;

[0078] The output voltage is a positive voltage of 3V. dc When the circuit is open, switches S1, S2, S5, S6, and S8 are turned on, while the other switches are turned off, resulting in an output voltage V0 of 3V. dc ;

[0079] The output voltage is a positive voltage of 2V. dc At that time, switching transistors S1, S2, S5, S6, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is 2V. dc ;

[0080] The output voltage is a positive voltage V dc When the switching transistors S1, S4, and S8 are turned on, and the other switching transistors are turned off, the output voltage V0 is V dc ;

[0081] When the output voltage is zero, switches S3, S7 and S8 are turned on, and the other switches are turned off, so the output voltage V0 is 0.

[0082] The output voltage is the reverse voltage -V dc At that time, switching transistors S3, S7, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is -V. dc ;

[0083] The output voltage is reverse voltage -2V dc When the circuit is open, switches S3, S5, S6, and S8 are turned on, while the other switches are turned off, resulting in an output voltage V0 of -2V. dc .

[0084] The output voltage is reverse voltage -3V dc At that time, switching transistors S3, S5, S6, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is -3V. dc ;

[0085] The output voltage is reverse voltage -4V dc When the circuit is open, switches S2, S3, S4, and S8 are turned on, while the other switches are turned off, resulting in an output voltage V0 of -4V. dc ;

[0086] The output voltage is reverse voltage -5V. dc At that time, switching transistors S2, S3, S4, S9 and S 10 When the transistor is turned on, all other switches are turned off, and the output voltage V0 is -5V. dc .

[0087] Please refer to Figure 3 , Figure 3 The schematic diagram and expected output voltage waveform of the multi-carrier level phase-shift SPWM modulation module are shown. This module performs the following modulation steps:

[0088] S1: Generate five sets of triangular carrier signals with equal amplitude and consistent frequency. Each set of carrier signals is arranged in a horizontal phase-shifted manner in the vertical direction. The amplitudes of each set of carrier signals are adjacent and do not overlap.

[0089] S2: Generates a sinusoidal modulated wave signal with an amplitude comparable to the overall peak-to-peak value of the carrier signal;

[0090] S3: The sinusoidal modulation wave signal is compared with five sets of triangular carrier signals in real time to generate corresponding switching trigger signals, control the switching transistors of the multilevel inverter to obtain the required eleven-level output voltage waveform.

[0091] Please refer to Figure 4 , Figure 4 A flowchart of the main modulation unit, based on Figure 4 This paper analyzes the multilevel inverter applicable to energy storage grid systems, and the specific modulation method is as follows:

[0092] S1: The input terminal of the phase-locked loop module receives the output voltage V from the main circuit. o The phase-locked loop (PLL) module extracts the load voltage phase θ and transmits this phase θ to the input of the phase compensation module. Since the load voltage phase may fluctuate over time, the PLL module is used to track and provide a stable phase reference in real time. The load voltage phase θ is used to calculate the phase compensation of the output current to ensure synchronization between the output current and the load voltage. The phase angle calculation module receives a given reactive power reference value Q at its input. ref and active power reference value P ref The phase angle calculation module calculates the target reference current i. ref The phase angle φ, the output of the phase angle calculation module is used to calculate the target reference current i. ref The φ is transmitted to the input of the phase compensation module to adjust the output current i. o The phase is adjusted to adapt to the power factor requirements of the load; the power calculation module input receives a given active power reference value P. ref and reactive power reference value Q ref The power calculation module calculates the required output current amplitude i. o,m The power calculation module will output the current amplitude i. o,m The current i is passed to the input of the multiplier MUL to determine the required output current i. o To meet the power requirements of the load;

[0093] S2: The input terminal of the phase compensation module receives the load voltage phase θ output from the output terminal of the phase-locked loop module, and combines it with the calculated target reference current i. ref Given the phase angle φ, calculate the output current i. o The phase compensation signal, the output terminal of the phase compensation module will output current i o The phase compensation signal is transmitted to the input of the multiplier MUL to adjust the phase of the output current so that it matches the load voltage and optimizes the power transmission efficiency.

[0094] S3: The input terminal of the multiplier MUL receives the output current amplitude i from the output terminal of the power calculation module. o,mThe input of the multiplier MUL receives the output current i from the output of the phase compensation module. o The phase offset signal, the output of the multiplier MUL will be the target reference current i ref The signal is passed to the input of the adder SUM for subsequent control, ensuring that the output current has the correct amplitude and phase;

[0095] S4: The input of adder SUM receives the target reference current i from the output of multiplier MUL. ref The input of adder SUM receives the output current i from the main circuit unit. o The output of the adder SUM will calculate the current error signal e. i This information is transmitted to the input of the PR controller to ensure the main circuit output current i. o Approaching the target reference current i step by step ref ;

[0096] S5: The input terminal of the PR controller receives the current error signal e from the output terminal of the adder SUM. i The output of the PR controller will be the target reference voltage V. ref The signal is transmitted to the input of the multi-carrier level phase-shift SPWM modulation module to guide the modulation process of the inverter, so as to accurately adjust the output voltage and thus achieve the desired current control.

[0097] S6: The input terminal of the multi-carrier level phase-shift SPWM modulation module receives the target reference voltage V from the output terminal of the PR controller. ref The ten output terminals of the multi-carrier level phase-shift SPWM modulation module output modulation signals P1, P2, ..., P1, P2, ..., P3 respectively. 10 This signal is sent to the drive circuit to generate the SPWM signal.

[0098] S7: The ten input terminals of the drive circuit respectively receive the ten modulation signals P1, P2, ..., P from the ten output terminals of the multi-carrier level phase-shift SPWM modulation module. 10 The ten output terminals of the drive circuit output control signals to control the switching transistors S1, S2, ..., S... 10 The duty cycle is adjusted to achieve current regulation and voltage output.

[0099] Please refer to Figure 5 This embodiment illustrates a cascaded structure comprising one main circuit unit and n additional circuit units. The connections between these units are as follows:

[0100] The positive output terminal of the main circuit unit is connected to the negative output terminal of auxiliary unit 1; the negative output terminal of the main circuit unit is directly connected to the load Z. L The negative electrode.

[0101] The positive output terminal of the additional unit n is connected to the load Z. L The positive terminal of the additional unit 1 is connected to the positive terminal of the previous additional circuit unit. In this embodiment, if there are three additional units, the negative terminal of the additional unit 2 is connected to the positive terminal of the additional unit 1.

[0102] For the remaining additional circuit units, the positive output terminal is connected to the negative output terminal of the next adjacent additional circuit unit. For example, in this embodiment, the positive output terminal of "additional unit 1" is connected to the negative output terminal of "additional unit 2".

[0103] Through this cascaded connection method, the output voltage of each circuit unit can be superimposed, thereby achieving a higher voltage across the load Z. L This allows for the acquisition of multi-level output voltage waveforms. Each additional circuit unit has the same structure as the main circuit unit, and the number of additional circuit units can be flexibly increased or decreased to meet the requirements for the number of output voltage levels in different application scenarios.

[0104] Please refer to Figure 6 In a specific embodiment of the multilevel inverter suitable for energy storage grid systems proposed in this invention, the DC power supply V dc1 、V dc2 、V dc3 The voltage level meets V dc1 :V dc2 :V dc3 = 1:2:2, and V dc1 =V dc The inverter employs multi-carrier phase-shift SPWM modulation technology. By changing the modulation pulse pattern, the duty cycle of the pulse width is arranged according to a sinusoidal law, thereby adjusting the on-time of the switching transistors. Ultimately, this results in a voltage waveform with 11 levels at the output, such as... Figure 6 V in o As shown. These 11 voltage levels are: 5V dc 4V dc 3V dc 2V dc 、V dc , 0, -V dc -2V dc -3V dc -4V dc and -5V dc , corresponding to Figure 6 State 1 to State 11. This modulation method allows the output voltage waveform to more closely resemble a sine wave, and after appropriate filtering, harmonic content can be effectively reduced. Assuming the load is inductive, such as... Figure 6 As shown, the load current i oIt will lag slightly behind the output voltage V o .

[0105] It should be noted that in this specification, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0106] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. The description of the embodiments disclosed in the present invention enables those skilled in the art to use or implement the present invention, and they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Such substitutions or modifications do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A multilevel inverter suitable for energy storage grid systems, characterized in that, Includes the main circuit unit and the main modulation unit: The main circuit unit includes a first DC power supply. V dc1 Second DC power supply V dc2 Third DC power supply V dc3 First switching transistor S 1. Second switching transistor S 2. Third switching transistor S 3. Fourth switching transistor S 4. Fifth switching transistor S 5. Sixth switching transistor S 6. Seventh switching transistor S 7. Eighth switching transistor S 8. Ninth Switching Transistor S 9. Tenth switching transistor S 10 ,load Z L ; First DC power supply V dc1 The second DC power supply V dc2 The third DC power supply V dc3 The voltage level meets V dc1 : V dc2 : V dc3 =1:2:2, and V dc1 = V dc ; The first switching transistor S The emitter of 1 and the third DC power supply V dc3 The negative terminal, the fourth switching transistor S The emitter connection of 4, the first switching transistor S The collector of 1 is connected to the first DC power supply. V dc1 The positive electrode, the ninth switch transistor S 9 collector connection; Second switching transistor S The emitter of 2 is connected to the second DC power supply. V dc2 The negative terminal, the fifth switching transistor S 5's collector connection, the second switching transistor S The collector of 2 is connected to the third DC power supply. V dc3 The positive electrode; The third switching transistor S The emitter of 3 is connected to the first DC power supply. V dc1 The negative terminal, the eighth switch transistor S The emitter connection of 8, the third switching transistor S The collector of 3 and the second DC power supply V dc2 The positive electrode, the seventh switch transistor S 7. Collector connection; The fourth switching transistor S The collector of 4 and the sixth switching transistor S The collector of 6, the seventh switch transistor S 7's emitter, the load Z L The positive terminal connection; The fifth switching transistor S The emitter of 5 is connected to the sixth switching transistor. S The emitter of 6; The eighth switching transistor S The collector of 8 and the load Z L The negative terminal, the tenth switch transistor S 10 collector connection; The ninth switching transistor S The emitter of 9 is connected to the tenth switching transistor. S 10 The emitter.

2. A multilevel inverter suitable for energy storage grid systems according to claim 1, characterized in that, The main modulation unit includes: a phase-locked loop module, a phase angle calculation module, a power calculation module, a phase compensation module, a multiplier MUL, an adder SUM, a PR controller, a multi-carrier level phase-shifting SPWM modulation module, and a drive circuit; The input terminal of the phase-locked loop module is connected to the load. Z L The positive electrode and the load Z L Between the negative terminals, the output terminal of the phase-locked loop module is connected to the first input terminal of the phase compensation module; The first input terminal of the phase angle calculation module receives a given reactive power reference value. Q ref The second input terminal of the phase angle calculation module receives a given active power reference value. P ref The output of the phase angle calculation module is connected to the second input of the phase compensation module; The first input terminal of the power calculation module receives a given active power reference value. P ref The second input terminal of the power calculation module receives a given reactive power reference value. Q ref The output of the power calculation module is connected to the first input of the multiplier MUL; The output of the phase compensation module is connected to the second input of the multiplier MUL. The output of the multiplier MUL is connected to the first input of the adder SUM. The second input terminal of the adder SUM receives the output current from the load terminal. i o The output of the adder SUM is connected to the input of the PR controller; The output of the PR controller is connected to the input of the multi-carrier level phase-shift SPWM modulation module; The first output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the first input terminal of the driving circuit; the second output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the second input terminal of the driving circuit; the third output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the third input terminal of the driving circuit; the fourth output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the fourth input terminal of the driving circuit; the fifth output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the fifth input terminal of the driving circuit; the sixth output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the sixth input terminal of the driving circuit; the seventh output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the seventh input terminal of the driving circuit; the eighth output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the eighth input terminal of the driving circuit; the ninth output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the ninth input terminal of the driving circuit; and the tenth output terminal of the multi-carrier level phase-shift SPWM modulation unit is connected to the tenth input terminal of the driving circuit.

3. A multilevel inverter suitable for energy storage grid systems according to claim 2, characterized in that, The multilevel inverter also includes the switching transistor. S 1, S 2, ..., S 10 The switching network, by controlling different combinations of the switching transistors, enables the DC power supplies to be superimposed or reversed. Eleven different output levels can be generated during each duty cycle through the control of the switching network, namely: positive first voltage 5 V dc , positive second voltage 4 V dc , positive third voltage 3 V dc , positive fourth voltage 2 V dc Forward fifth voltage V dc Zero voltage 0, reverse first voltage - V dc Reverse second voltage -2 V dc Reverse third voltage -3 V dc Reverse fourth voltage -4 V dc Reverse fifth voltage -5 V dc .

4. A multilevel inverter suitable for energy storage grid systems according to claim 3, characterized in that, The output voltage is the first positive voltage 5. V dc At that time, the first switching transistor S 1. The second switching transistor S 2. The seventh switch transistor S 7 and the eighth switch tube S With 8 transistors on and the others off, the output voltage is... V 0 is 5 V dc ; The output voltage is the positive second voltage 4 V dc At that time, the first switching transistor S 1. The second switching transistor S 2. The seventh switch transistor S 7. The ninth switching transistor S 9 and the tenth switch tube S 10 When the transistor is turned on, other switches are turned off, and the output voltage... V 0 is 4 V dc ; The output voltage is the positive third voltage 3 V dc At that time, the first switching transistor S 1. The second switching transistor S 2. The fifth switching transistor S 5. The sixth switching transistor S 6 and the eighth switch tube S 8 is on, other switches are off, output voltage V 0 is 3 V dc ; The output voltage is the positive fourth voltage 2. V dc At that time, the first switching transistor S 1. The second switching transistor S 2. The fifth switching transistor S 5. The sixth switching transistor S 6. The ninth switching transistor S 9 and the tenth switch tube S 10 When the transistor is turned on, other switches are turned off, and the output voltage... V 0 is 2 V dc ; The output voltage is the fifth positive voltage. V dc At that time, the first switching transistor S 1. The fourth switching transistor S 4 and the eighth switch tube S With 8 transistors on and the others off, the output voltage is... V 0 is V dc ; When the output voltage is zero, the third switching transistor... S 3. The seventh switch transistor S 7 and the eighth switch tube S 8 is on, other switches are off, output voltage V 0 is 0; The output voltage is the reverse first voltage - V dc At that time, the third switch tube S 3. The seventh switch transistor S 7. The ninth switching transistor S 9 and the tenth switch tube S 10 When the transistor is turned on, other switches are turned off, and the output voltage... V 0 is - V dc ; The output voltage is the inverted second voltage -2. V dc At that time, the third switch tube S 3. The fifth switching transistor S 5. The sixth switching transistor S 6 and the eighth switch tube S 8 is on, other switches are off, output voltage V 0 is -2 V dc ; The output voltage is the reverse third voltage -3. V dc At that time, the third switch tube S 3. The fifth switching transistor S 5. The sixth switching transistor S 6. The ninth switching transistor S 9 and the tenth switch tube S 10 When the transistor is turned on, other switches are turned off, and the output voltage... V 0 is -3 V dc ; The output voltage is the inverted fourth voltage -4. V dc At that time, the second switching transistor S 2. The third switching transistor S 3. The fourth switching transistor S 4 and the eighth switch tube S 8 is on, other switches are off, output voltage V 0 is -4 V dc ; The output voltage is the reverse fifth voltage -5. V dc At that time, the second switching transistor S 2. The third switching transistor S 3. The fourth switching transistor S 4. The ninth switching transistor S 9 and the tenth switch tube S 10 When the transistor is turned on, all other switches are turned off, and the output voltage is... V 0 is -5 V dc .

5. A multilevel inverter suitable for energy storage grid systems according to claim 2, characterized in that, The main circuit unit is suitable for cascading multiple additional circuit units with the main circuit unit, each additional circuit unit being the same as the main circuit unit, having the same components and configuration; The connection method between the additional circuit unit and the main circuit unit includes: The positive output terminal of the main circuit unit is connected to the negative output terminal of the adjacent auxiliary circuit unit, and the negative output terminal of the main circuit unit is connected to the load. Z L The negative electrode; The positive terminal of the last additional circuit unit is connected to the load. Z L The positive terminal of the last additional circuit unit is connected to the negative terminal of the adjacent additional circuit unit; The positive terminal of the output of the remaining additional circuit unit is connected to the negative terminal of the output of the adjacent additional circuit unit.

6. A modulation method for a multilevel inverter suitable for energy storage grid systems, characterized in that, The multilevel inverter according to any one of claims 2-5 is implemented by the multi-carrier level phase-shift SPWM modulation module, which performs the following modulation steps: S1: Generate five sets of triangular carrier signals with equal amplitude and consistent frequency. Each set of carrier signals is arranged in a horizontal phase-shifted manner in the vertical direction. The amplitudes of each set of carrier signals are adjacent and do not overlap. S2: Generates a sinusoidal modulated wave signal; S3: The sinusoidal modulation wave signal is compared with the five sets of triangular carrier signals in real time to generate a corresponding switching trigger signal, which controls the switching transistor of the multilevel inverter to obtain the required eleven-level output voltage waveform.

7. A multilevel inverter suitable for energy storage grid systems, characterized in that, The overall modulation method of the main modulation unit for the multilevel inverter according to any one of claims 2-5 includes: S1: The input terminal of the phase-locked loop module receives the output voltage of the main circuit. V o And extract the load voltage phase θ The output of the phase-locked loop module will phase the load voltage. i The reactive power is transmitted to the first input terminal of the phase compensation module; the first input terminal of the phase angle calculation module receives the given reactive power reference value. Q ref The second input terminal of the phase angle calculation module receives a given active power reference value. P ref The phase angle calculation module calculates the target reference current. i ref phase angle The output of the phase angle calculation module is used to calculate the target reference current. i ref phase angle The active power is transmitted to the second input terminal of the phase compensation module; the first input terminal of the power calculation module receives the given active power reference value. P ref The second input terminal of the power calculation module receives a given reactive power reference value. Q ref The power calculation module calculates the required output current amplitude. i o,m The output terminal of the power calculation module will output the current amplitude. i o,m The signal is passed to the first input of the multiplier MUL; S2: The input terminal of the phase compensation module receives the load voltage phase output from the output terminal of the phase-locked loop module. i Combined with the calculated target reference current i ref phase angle Calculate the output current i o The phase compensation signal, the output terminal of the phase compensation module will output current. i o The phase compensation signal is transmitted to the second input terminal of the multiplier MUL; S3: The first input terminal of the multiplier MUL receives the output current amplitude from the output terminal of the power calculation module. i o,m The second input terminal of the multiplier MUL receives the output current from the output terminal of the phase compensation module. i o The phase offset signal, the output of the multiplier MUL will be the target reference current. i ref The signal is passed to the first input of the adder SUM; S4: The first input terminal of the adder SUM receives the target reference current from the output terminal of the multiplier MUL. i ref The second input terminal of the adder SUM receives the output current of the main circuit unit. i o The output of the adder SUM will calculate the current error signal. e i The data is transmitted to the input terminal of the PR controller; S5: The input terminal of the PR controller receives the current error signal from the output terminal of the adder SUM. e i The output of the PR controller will be the target reference voltage. V ref The signal is transmitted to the input of the multi-carrier level phase-shift SPWM modulation module; S6: The input terminal of the multi-carrier level phase-shift SPWM modulation module receives the target reference voltage from the output terminal of the PR controller. V ref The ten output terminals of the multi-carrier level phase-shift SPWM modulation module respectively output the first modulation signal. P 1. Second modulation signal P 2. Third modulation signal P 3. Fourth modulation signal P 4. Fifth Modulation Signal P 5. Sixth Modulation Signal P 6. Seventh Modulation Signal P 7. Eighth Modulation Signal P 8. Ninth Modulation Signal P 9. Tenth Modulation Signal P 10 To the driving circuit; S7: The ten input terminals of the driving circuit respectively receive the ten modulation signals from the ten output terminals of the multi-carrier level phase-shift SPWM modulation module. P 1, P 2, ..., P 10 The ten output terminals of the drive circuit output control signals to control the first switching transistor respectively. S 1. The second switching transistor S 2. The third switching transistor S 3. The fourth switching transistor S 4. The fifth switching transistor S 5. The sixth switching transistor S 6. The seventh switch transistor S 7. The eighth switch transistor S 8. The ninth switching transistor S 9. The tenth switching transistor S 10 Duty cycle.

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