Switching signal generation circuit with hardware dead zone control

Abstract

The invention relates to the technical field of switching signal generation circuits, and discloses a switching signal generation circuit with hardware dead zone control, which is characterized in that signal transmission of the switching signal generation circuit with hardware dead zone control is delayed by using a NOT gate, and specifically, the switching signal generation circuit with hardware dead zone control comprises an input square wave signal, the system is composed of 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, 2n, executing a fault detection strategy on the circuit, and judging whether a fault NOT gate exists in the circuit; if no fault gate exists in the circuit; executing a first circuit delay control strategy, controlling the delay time of each NOT gate, and enabling the delay time of the output signal of the whole circuit to be the target delay time; if a fault exists in the circuit, the NOT gate; and a coordination repair strategy is executed, and the influence of the fault NOT gate on the circuit delay duration and the dead time is reduced. The reliability is improved, and the flexibility and adjustability of the system are enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of switch signal generation circuits, and specifically to a switch signal generation circuit with hardware dead zone control. Background Art

[0002] In modern digital circuits and high-speed signal processing systems, the precise generation and control of signals are crucial. Especially in the case of high-frequency signals, the design of switch signal generation circuits requires special attention to key parameters such as signal delay and dead time. The NOT gate, as a common logic gate, is widely used in various digital circuits and undertakes the functions of signal inversion and delay.

[0003] Traditional switch signal generation circuits have obvious deficiencies in delay and dead time control. First of all, most traditional circuits rely on fixed-delay designs, and the delay time of each NOT gate is determined during design and cannot be adjusted according to the conditions in the actual working environment. This leads to large delay and dead time deviations in the circuit in high-frequency signals and large-scale applications, affecting the stability and accuracy of the circuit. Secondly, traditional designs usually do not have a fault detection mechanism. If a NOT gate in the circuit fails, the signal propagation delay and dead time of the entire system will be significantly affected, reducing the fault tolerance and reliability of the circuit. In addition, traditional circuits have limitations in dealing with dead time and cannot flexibly adjust the dead time according to different working conditions. The change of dead time often leads to unnecessary power consumption and signal distortion, thus affecting the overall performance of the system.

[0004] This solution proposes a switch signal generation circuit with hardware dead zone control, which solves various deficiencies in traditional circuits by precisely controlling the delay time and dead time. It not only improves the performance and reliability of the circuit, but also significantly enhances the flexibility and adjustability of the system, and is particularly suitable for high-speed and efficient switch signal generation applications. Summary of the Invention

[0005] The present invention provides a switch signal generation circuit with hardware dead zone control, which helps to solve the problems mentioned in the above background art.

[0006] In a first aspect, the present application provides a switch signal generation circuit with hardware dead zone control, adopting the following technical solution: A switch signal generation circuit with hardware dead zone control, comprising: Using a NOT gate delay to control the propagation of the switch signal generation circuit signal with hardware dead zone, specifically: The switch signal generation circuit with hardware dead zone control includes an input square wave signal, 2n - 1 serially connected NOT gates, 2n odd jumper terminals, 2n even jumper terminals, AND gate 1 and AND gate 2; Sort the NOT gates in ascending order of their distances from the input square wave signal. For each odd-numbered signal path, the two input terminals of AND gate 1 can be connected respectively using odd-numbered jumper terminals, and for each even-numbered signal path, the two input terminals of AND gate 2 can be connected respectively using even-numbered jumper terminals; Output a positive signal through AND gate 1; Output a negative signal through AND gate 2; By introducing the NOT gate delay and hardware dead zone control technology, the present invention effectively solves the problems caused by inconsistent signal propagation delays and dead zone times in traditional circuits. By precisely controlling the delay time of each NOT gate, the delay time of the circuit output signal can be matched with the target delay time, avoiding problems such as signal distortion or timing errors. In multi-path signal control applications, precise adjustment of the delay time is particularly important. Especially in high-speed and real-time data transmission systems, signal delay fluctuations often affect the stability and response speed of the system. This circuit design can ensure that the signal transmission delay is within the preset range, avoiding problems such as signal interleaving or repeated transmission, thereby improving the reliability and stability of the system. By controlling the dead zone time, the circuit can maintain the integrity of the signal within the specified time window, further optimizing the performance of the circuit in practical applications.

[0007] Execute a fault detection strategy for the circuit to determine whether there are faulty NOT gates in the circuit; If there are no faulty NOT gates in the circuit; Obtain the delay time and dead zone time of the output positive signal and negative signal, denoted as the target delay time and target dead zone time respectively; Execute the first circuit delay control strategy to control the delay time of each NOT gate so that the delay time of the entire circuit output signal is the target delay time; If there are faulty NOT gates in the circuit; Obtain the propagation delay duration of the faulty NOT gate; According to the propagation delay duration of the faulty NOT gate, execute a coordinated repair strategy to reduce the impact of the faulty NOT gate on the circuit delay duration and dead zone time.

[0008] Preferably, the step of executing a fault detection strategy for the circuit to determine whether there are faulty NOT gates in the circuit includes: For any one NOT gate, when the input signal of the NOT gate is x i , where i is the serial number of the NOT gate, i = 1, 2,... 2n - 1; Then the output signal of the NOT gate is y i = -x i ; When there are 2n - 1 NOT gates connected in series in the circuit, it satisfies x 1 = y 2n-1 ; Detect whether each NOT gate is faulty where f i is the fault state of the i-th NOT gate; Establish a fault propagation model Faulty NOT gate location: Obtain the state f of each NOT gate i , where f i = 1 indicates that the NOT gate is faulty, then the i-th NOT gate is a faulty NOT gate, and f i = 0 indicates that the NOT gate is normal.

[0009] By implementing a fault detection strategy for the circuit, the present invention can monitor the working state of each NOT gate in the circuit in real time, promptly determine whether there is a faulty NOT gate, and accurately locate the faulty component by establishing a fault propagation model. This strategy establishes a state correlation between each series-connected NOT gate in the circuit by obtaining the state information of each NOT gate, ensuring efficient monitoring and rapid response during circuit operation. If there is a faulty NOT gate in the circuit, the system can obtain the propagation delay duration of the faulty NOT gate and coordinate the repair based on this, minimizing the impact of the fault on the circuit delay and dead time. Through intelligent fault detection and repair, this circuit can improve the reliability and fault tolerance of the entire system, ensuring that the circuit can still operate normally even in the event of a fault, reducing the system downtime and maintenance costs caused by the fault.

[0010] Preferably, the implementation of the first circuit delay control strategy to control the delay time of each NOT gate so that the delay time of the output signal of the entire circuit is the target delay time includes: Obtain the input square wave signal V in (t) at time t; Denote the output positive signal of AND gate 1 as V out1 (t); Denote the output inverted signal of AND gate 2 as V out2 (t); Denote the delay time of each NOT gate as t delay,i , where i represents the i-th NOT gate; The delay propagation of the input square wave signal is expressed as Obtain the target delay time t target ; Establish a delay optimization target Establish a dead time optimization target f 2 = max(0, t dead - t actual-dead ), where t dead , t actual-dead represent the target dead time and the actual dead time respectively.

[0011] By using the gradient descent method to optimize the objective function, the present invention can effectively control the delay time of each NOT gate in the circuit, thereby ensuring that the delay time of the output signal of the circuit meets the preset target delay requirement. This method utilizes a step-by-step optimization strategy to continuously adjust the delay time of each NOT gate to achieve the ideal system performance. By optimizing the objective function and adding a dead time penalty term, the circuit can not only control the delay time but also minimize the impact of dead time, further improving the response speed and stability of the system. Through this precise control strategy, the system can adaptively adjust the signal transmission characteristics under changing working environments to ensure efficient and stable operation, especially suitable for complex circuit systems with extremely high requirements for delay and timing.

[0012] Preferably, implementing the first circuit delay control strategy to control the delay time of each NOT gate such that the delay time of the output signal of the entire circuit is the target delay time includes: Optimizing the objective based on the gradient descent method; The said objective is f 1 +λ×f 2 where λ is the weight coefficient for controlling the dead time penalty term; Initializing the delay time of each NOT gate Setting the learning rate η and the maximum number of iterations N max ; Calculating the gradient of the objective function with respect to the delay of each NOT gate i: Δ is the time increment value; Updating the delay time Calculating, and recording the result as the change amount of the objective function; Setting the change amount threshold; Comparing the change amount of the objective function with the change amount threshold. If the change rate of the objective function is less than the change amount threshold or the number of iterations is equal to N max , then stop the iteration.

[0013] By using the genetic algorithm to optimize the objective function, the present invention can find the best solution among various delay configurations, further improving the performance of the circuit. As a global optimization method, the genetic algorithm can continuously generate more suitable delay configurations through steps such as initializing the population, fitness evaluation, selection operation, crossover, and mutation in a complex system, and finally find the optimal solution. This optimization method not only improves the delay control accuracy of the circuit but also can effectively handle the complex relationship between delay and dead time, maximizing the performance of the system. Through the adaptive optimization process of the genetic algorithm, the present invention can dynamically adjust for different fault situations in the actual application of the circuit to ensure that the circuit can achieve the best performance under various working environments.

[0014] Preferably, executing a coordinated repair strategy according to the propagation delay duration of the faulty NOT gate to reduce the impact of the faulty NOT gate on the circuit delay duration and dead time includes: Obtain the faulty NOT gate N k 's propagation delay Calculate the dead time of the faulty NOT gate under normal conditions Calculate the change in dead time caused by the faulty NOT gate Adjust the NOT gates N k+1 , N k+2 , …, N 2n-1 's delay duration after the faulty NOT gate, where N k+1 's delay duration is Calculate the adjusted dead time: Calculate the objective function to minimize the impact of the adjusted dead time:

[0015] By executing a coordinated repair strategy according to the propagation delay duration of the faulty NOT gate, the present invention can quickly respond when a fault occurs and optimize the circuit delay and dead time. In a traditional circuit, a faulty NOT gate may cause the performance of the entire circuit to degrade, increase the delay, and expand the dead time. However, the present invention can effectively reduce the impact of the fault on the circuit performance by calculating the dead time of the faulty NOT gate under normal conditions, adjusting the delay duration of the subsequent NOT gates, and calculating the adjusted dead time. This strategy ensures that the impact of the faulty NOT gate on the delay of the entire circuit is minimized, avoids performance degradation caused by the fault, and ensures the stability and efficiency of the circuit. This coordinated repair mechanism improves the fault tolerance of the circuit when facing a fault, enables the circuit to still operate stably under less-than-healthy conditions, and reduces the downtime caused by the fault.

[0016] Preferably, executing a coordinated repair strategy according to the propagation delay duration of the faulty NOT gate to reduce the impact of the faulty NOT gate on the circuit delay duration and dead time includes: Optimize the objective function: Define the constraint conditions: Wherein, respectively represent the minimum and maximum physical limits of the delay duration of the i-th NOT gate.

[0017] By optimizing the objective function and defining the constraints, when adjusting the circuit performance, the present invention can take into account the minimum and maximum physical limitations of each NOT gate. This optimization method based on physical limitations ensures that the circuit will not exceed the working range of the hardware or cause unnecessary losses in practical applications. The optimization of the objective function enables precise control of the circuit delay and dead time. At the same time, through the constraints, it is avoided that the design parameters exceed the tolerance range of the hardware, ensuring that the circuit maintains the best performance within the physical limitations. This optimization strategy effectively improves the applicability and durability of the circuit. Especially in high-density and high-demand systems, it can ensure the stable operation of the circuit in extreme working environments, increasing the reliability and long-term stability of the system.

[0018] Preferably, according to the propagation delay duration of the faulty NOT gate, performing a coordinated repair strategy to reduce the impact of the faulty NOT gate on the circuit delay duration and dead time, including: Using a genetic algorithm to optimize the objective function, specifically: Initializing the population: Generating an initial population Each individual in the population represents a propagation delay configuration, and the size of the population is P; Calculating the fitness function of each individual Selection operation Where P i , f i are the fitness of the i-th individual and the i-th individual respectively; Crossover operation, randomly selecting two individuals P x , P y to generate new individuals C xy1 , C xy2 ; Where k is the crossover point; Mutation operation: Where Δt i is a random value; Setting the mutation probability Where ρ mutation is the mutation probability; Setting the fitness threshold; When the number of iterations reaches the maximum number or the target fitness is less than the fitness threshold, terminate the genetic algorithm and output the best individual.

[0019] By using a genetic algorithm to optimize the objective function, the present invention can quickly find the optimal solution among multiple possible delay configurations. The application of the genetic algorithm enables global search in a complex delay control system, overcoming the local optimum problem that traditional optimization methods may face. Through operations such as evolution, crossover, and mutation on the initial population, the algorithm can continuously generate delay configurations that better meet the system requirements. This enables the circuit to maintain optimal performance when facing various complex environments and changing conditions. Through the optimization of the genetic algorithm, the system can adapt to different working conditions, dynamically adjust the delay and dead time, and maximize the response speed and stability of the circuit. In addition, the adaptive characteristics of the genetic algorithm make it very efficient in solving practical problems, especially in the design and optimization processes of large-scale and complex circuits.

[0020] The present invention has the following beneficial effects: 1. The switch signal generation circuit with hardware dead zone control can precisely control the signal delay and dead time through the design of connecting multiple NOT gates and AND gates in series, enabling the circuit to operate under precisely controlled conditions. This design can effectively avoid signal conflicts and false triggering, ensuring the circuit operates more stably and reliably. By adjusting the delay of the NOT gates, the timing of the output signal can be accurately adjusted to ensure that the circuit can operate synchronously during high-frequency operations and avoid instability caused by delay problems. This feature is particularly important in high-precision control systems. By introducing hardware dead zone control, the phenomenon of false triggering caused by signal interference can be reduced. Through fine timing control, the circuit can ensure signal stability within a specific time and is not affected by external noise, thereby improving the anti-interference ability of the system.

[0021] 2. The switch signal generation circuit with hardware dead zone control can timely detect and locate the faulty NOT gates in the circuit through a fault detection strategy, ensuring the stability of the circuit operation. This fault monitoring can improve the self-diagnosis ability of the circuit, enabling the system to automatically adjust when a fault occurs and reducing manual intervention. By locating the faulty NOT gates, the faults can be repaired targeted and the circuit performance can be optimized without affecting the operation of the entire system. This local repair method can reduce the impact of faults and maintain the high-efficiency operation of the system. By establishing a fault propagation model, the circuit can predict the fault propagation path and take preventive measures in advance to prevent the spread of faults. This predictive repair strategy effectively improves the fault tolerance and reliability of the system and reduces the losses caused by faults.

[0022] 3. The switch signal generation circuit with hardware dead zone control can ensure that the delay time of the entire circuit is consistent with the target delay time by precisely controlling the delay time of each NOT gate, thus avoiding timing errors during signal transmission. Especially in systems that require high timing accuracy, this control strategy is particularly important. By achieving control of the target delay time, it can ensure that the response time of the system to input signals is always consistent. This precise delay control can improve the response speed of the system, avoid problems of untimely control caused by excessive signal delay, and thus enhance the overall performance of the system. By combining delay control with optimization of the dead zone time, it can ensure that when the circuit processes signals, it can not only maintain high-precision delay control but also avoid an overly long dead zone time. In this way, the system can operate efficiently during high-frequency operation, avoiding control errors caused by an overly long dead zone time.

[0023] 4. The switch signal generation circuit with hardware dead zone control can efficiently find the optimal configuration of circuit parameters by using the gradient descent method to optimize the objective function, avoiding the time waste caused by manual adjustment and trial and error. The iterative process of the gradient descent method can quickly approach the optimal solution, thus achieving the required delay control effect in a relatively short time. By optimizing the objective function and adjusting the delay time of each NOT gate, it can ensure that the overall performance of the circuit meets the expectations. This optimization process can precisely control the delay time of the circuit, avoid performance losses caused by overly long or short delays, and thus improve the overall efficiency of the circuit.

[0024] By controlling the optimization of the dead zone time, it can reduce the impact of the dead zone time on system response while ensuring the delay accuracy of the circuit. Optimization of the dead zone time can further improve the real-time performance of the system, ensuring that the circuit can maintain an efficient operating state during high-frequency signal transmission.

[0025] 5. The switch signal generation circuit with hardware dead zone control can effectively reduce the impact of faults on circuit performance by calculating the dead zone time of faulty NOT gates under normal conditions and adjusting the delay of subsequent NOT gates. When a fault occurs, the delay time and dead zone time of the circuit are often significantly affected. This coordinated repair strategy can quickly restore the circuit performance and reduce system downtime. By finely adjusting the delay of subsequent NOT gates in the circuit, it can ensure that the circuit still maintains high stability even in the presence of faulty NOT gates. This adjustment strategy ensures that the system does not exhibit large performance fluctuations in the face of faults, thus avoiding circuit failure. By combining the fault repair strategy with circuit scheduling, it can improve the intelligent management ability of the circuit and reduce the need for manual intervention. This strategy can not only reduce interruptions caused by faults but also enhance the intelligent level of the system through an automated adjustment process and strengthen the adaptive ability of the circuit.

[0026] 6. The switch signal generation circuit with hardware dead zone control optimizes the objective function, enabling the circuit to achieve optimal delay and dead time in practical applications while keeping the circuit operating within reasonable physical limits. This can avoid the circuit performance exceeding the feasible range due to over-optimization and ensure the stability of the circuit during long-term operation. By introducing physical constraints into the objective function optimization process, it is possible to prevent circuit parameters from exceeding the maximum tolerance of the hardware, thereby reducing the potential risk of damage. This optimization method effectively improves the reliability of the circuit, especially suitable for complex or high-power application scenarios. Through this optimization strategy, the circuit can achieve the best performance without exceeding the hardware tolerance range. This not only improves the working efficiency of the circuit but also extends the service life of the circuit, providing guarantee for the long-term stable operation of the system.

[0027] 7. The switch signal generation circuit with hardware dead zone control can avoid the local optimal solutions that may occur in traditional optimization methods through the global search characteristics of the genetic algorithm, thereby finding the most suitable delay configuration. This global optimization method is suitable for dealing with complex problems with multiple objectives and multiple constraints, enabling the circuit to maintain optimal performance in various environments. Through the crossover and mutation operations of the genetic algorithm, the most suitable delay configuration can be quickly found among various possible solutions. This mechanism can dynamically adjust the circuit delay and dead time, maximizing the response speed and stability of the system and adapting to changing working conditions. Through the adaptive characteristics of the genetic algorithm, the algorithm can be adjusted according to real-time feedback to ensure that the circuit can still maintain high efficiency when facing changing working environments. This makes the optimization process of the circuit more flexible and efficient, suitable for long-term operation in practical applications, providing higher reliability and adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic flow chart of the method of the present invention.

[0029] Figure 2 It is a schematic flow chart of the genetic algorithm of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] Embodiment 1, referring to Figure 1 , a switch signal generation circuit with hardware dead zone control includes using a NOT gate delay to propagate the switch signal with hardware dead zone control. Specifically: The switching signal generation circuit with hardware dead zone control includes an input square wave signal, 2n - 1 cascaded NOT gates, 2n odd jumper terminals and 2n even jumper terminals, AND gate 1 and AND gate 2; Sort the NOT gates in ascending order of distance from the input square wave signal, and each odd - numbered signal path can be connected to two input terminals of AND gate 1 using odd jumper terminals, and each even - numbered signal path can be connected to two input terminals of AND gate 2 using even jumper terminals; Output a positive signal through AND gate 1; Output a negative signal through AND gate 2; Execute a fault detection strategy for the circuit to determine whether there is a faulty NOT gate in the circuit; If there is no faulty NOT gate in the circuit; Obtain the delay time and dead zone time of the output positive signal and negative signal, denoted as the target delay time and target dead zone time respectively; Execute the first circuit delay control strategy to control the delay time of each NOT gate so that the delay time of the output signal of the entire circuit is the target delay time; If there is a faulty NOT gate in the circuit; Obtain the propagation delay duration of the faulty NOT gate; According to the propagation delay duration of the faulty NOT gate, execute a coordinated repair strategy to reduce the impact of the faulty NOT gate on the circuit delay duration and dead zone time.

[0032] By introducing multiple cascaded NOT gates, the circuit can effectively delay the signal propagation, thereby precisely controlling the timing of the output signal. For systems that require precise timing, this design is of great significance and can avoid system failures caused by timing errors.

[0033] By sorting the NOT gates in ascending order of distance from the input signal, the circuit can optimize the delay process and ensure that the order and time interval of signal transmission meet the design requirements. This sorting method can further improve the response speed and stability of the circuit, especially in the case of high - frequency signal processing.

[0034] Through hardware dead zone control, the circuit can avoid interference and reduce misoperations caused by external signals. The system can better resist the influence of external noise or unstable factors, maintain normal operation, and improve the overall anti - interference ability.

[0035] The execution of the fault detection strategy for the circuit to determine whether there is a faulty NOT gate in the circuit includes: For any NOT gate, when the input signal of the NOT gate is x i , where i is the serial number of the NOT gate, i = 1, 2, … 2n - 1; Then the output signal of the NOT gate is yi = -x i ; When 2n - 1 NOT gates are connected in series in the circuit, x satisfies 1 = y 2n-1 ; Detect whether each NOT gate is faulty where f i is the fault status of the i-th NOT gate; Establish a fault propagation model Faulty NOT gate location: Obtain the status f of each NOT gate i , where f i = 1 indicates that the NOT gate is faulty, then the i-th NOT gate is a faulty NOT gate, and f i = 0 indicates that the NOT gate is normal.

[0036] By introducing a fault detection strategy, the circuit can react immediately when a fault occurs, avoiding the long downtime of traditional circuits when problems arise. The real-time detection and location of faults improve the self-diagnosis ability of the system, ensuring the continuity and stability of equipment operation.

[0037] Through the location of faulty NOT gates, faults can be repaired targeted without affecting the operation of the entire system. This enables the system to recover quickly, while avoiding interference with other normal components, reducing maintenance costs and time.

[0038] By constructing a fault propagation model, the circuit can not only detect faults in a timely manner, but also predict the potential impact of faults on the system and take preventive measures in advance. This preventive fault handling mechanism can significantly improve the reliability and fault tolerance of the system, avoiding the spread of faults.

[0039] The implementation of the first circuit delay control strategy to control the delay time of each NOT gate so that the delay time of the output signal of the entire circuit is the target delay time includes: Obtain the input square wave signal V in (t) at time t; Denote the positive output signal of AND gate 1 as V out1 (t); Denote the negative output signal of AND gate 2 as V out2 (t); Denote the delay time of each NOT gate as t delay,i , where i represents the i-th NOT gate; The delay propagation of the input square wave signal is expressed as Obtain the target delay time t target ; Establish a delay optimization goal Establish the dead time optimization objective f 2 = max(0, t dead - t actual-dead ), where t dead , t actual-dead represent the target dead time and the actual dead time respectively.

[0040] By precisely controlling the delay of each NOT gate, the circuit can make fine adjustments based on the input signal to ensure that the timing of the output signal exactly meets the expectations. This delay control can greatly reduce the timing error and improve the timing accuracy of the system, which is crucial especially in complex signal processing systems.

[0041] By aligning the delay time of the circuit with the target delay time, the synchronization of the circuit can be effectively improved, and the timing problems caused by too long or too short delays can be reduced. This can enhance the response speed and stability of the system while ensuring the normal operation of the system.

[0042] By combining the optimization of the dead time, the dead time in the circuit can be further reduced, and the delay problem caused by too long dead time can be alleviated. This dual optimization mechanism enables the circuit to maintain a low delay and a short dead time when processing high-frequency signals, thus enhancing the overall performance and response efficiency of the system.

[0043] Performing the first circuit delay control strategy to control the delay time of each NOT gate so that the delay time of the output signal of the entire circuit is the target delay time includes: Optimizing the objective based on the gradient descent method; The said objective is f 1 + λ × f 2 , where λ is the weight coefficient for controlling the dead time penalty term; Initialize the delay time of each NOT gate Set the learning rate η and the maximum number of iterations N max ; Calculate the gradient of the objective function with respect to the delay of each NOT gate i: Δ is the time increment; Update the delay time Calculate, and record the result as the change amount of the objective function; Set the change amount threshold; Compare the change amount of the objective function with the change amount threshold. If the change rate of the objective function is less than the change amount threshold or the number of iterations is equal to N max , then stop the iteration.

[0044] Execute a coordinated repair strategy based on the propagation delay duration of the faulty NOT gate to reduce the impact of the faulty NOT gate on the circuit delay duration and dead time, including: Obtain the faulty NOT gate N k 's propagation delay Calculate the dead time under normal conditions of the faulty NOT gate Calculate the change in dead time caused by the faulty NOT gate Adjust the NOT gates N k+1 , N k+2 , …, N 2n-1 's delay duration after the faulty NOT gate, where N k+1 's delay duration is Calculate the adjusted dead time: Calculate the objective function to minimize the impact of the adjusted dead time:

[0045] Through the coordinated repair of the propagation delay of the faulty NOT gate, the system can timely adjust the delays of other NOT gates, thereby reducing the impact of the faulty NOT gate on the overall system delay and dead time. This repair strategy ensures that the system can still maintain a stable working state after a fault occurs, avoiding the shutdown of the entire system due to individual faulty components.

[0046] By adjusting the delays of the NOT gates after the faulty NOT gate, the signal transmission timing of the system can be accurately controlled to prevent long delays or increased dead time caused by faults. This repair process can restore the normal operation of the system in the shortest time, improving the fault tolerance and self-recovery capabilities of the system.

[0047] By optimizing the adjusted dead time, the system can reduce unnecessary delays, making signal transmission more efficient. This optimization can ensure that the system can operate continuously and stably during high-frequency operations, thereby improving the reliability and efficiency of the circuit.

[0048] Execute a coordinated repair strategy based on the propagation delay duration of the faulty NOT gate to reduce the impact of the faulty NOT gate on the circuit delay duration and dead time, including: Optimize the objective function: Define the constraint conditions: where respectively represent the minimum and maximum physical limits of the delay duration of the i-th NOT gate.

[0049] By defining the minimum and maximum physical limits of each NOT gate delay, it is possible to ensure that the system remains within a reasonable delay range during fault repair, avoiding irreparable faults caused by exceeding the physical limits. This optimization constraint can effectively improve the reliability of the system and ensure that no new problems are introduced after fault repair.

[0050] By optimizing the objective function, it is possible to minimize the impact of faulty NOT gates on system performance while maintaining physical constraints. Such an optimization method can accurately find the most suitable delay setting, enabling the entire circuit to maintain good performance in both normal and faulty states.

[0051] By optimizing the objective function, it is possible to find the optimal solution in a shorter time and improve the efficiency of fault repair. This optimization process helps to reduce system downtime and maintain the high efficiency of circuit operation, especially in applications that require high availability and high reliability.

[0052] Performing a coordinated repair strategy based on the propagation delay duration of the faulty NOT gate to reduce the impact of the faulty NOT gate on the circuit delay duration and dead time includes: Using a genetic algorithm to optimize the objective function, specifically: Initializing the population: Generating an initial population Each individual in the population represents a propagation delay configuration, and the size of the population is P; Calculating the fitness function of each individual Selection operation Where P i , f i Are the fitness of the i-th individual and the i-th individual respectively; Crossover operation, randomly selecting two individuals P x , P y For generating a new individual C xy1 , C xy2 ; Where k is the crossover point; Mutation operation: Where Δt i Is a random value; Setting the mutation probability Where ρ mutation Is the mutation probability; Setting the fitness threshold; When the number of iterations reaches the maximum number or the objective fitness is less than the fitness threshold, terminate the genetic algorithm and output the best individual.

[0053] In this embodiment, refer to Figure 2 .

[0054] By using the genetic algorithm, it is possible to efficiently find the optimal solution for fault repair in a large search space. The selection, crossover, and mutation operations of the genetic algorithm can help the circuit find a suitable delay configuration in complex repair scenarios, thereby improving the self-adaptability of the system.

[0055] Through the iterative process of the genetic algorithm, various parameters of the circuit can be quickly optimized, avoiding the local optimum problem that may exist in traditional optimization methods. The global search ability of this algorithm ensures that the system can achieve the overall optimal performance and avoids problems caused by the failure of local adjustment.

[0056] By setting the fitness threshold and termination conditions, the genetic algorithm can control the computational amount while ensuring the optimization quality, and improve the computational efficiency of the system. This efficient optimization method is particularly crucial for real-time systems, ensuring that the fault repair process does not consume excessive resources.

[0057] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device.

[0058] The above is only the preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A switch signal generating circuit with hardware dead zone control, characterized in that: include, The switch signal using the NOT gate delay band hardware dead zone control generates the circuit signal propagation, specifically: The switch signal generating circuit with hardware dead zone control comprises an input square wave signal, 2n-1 serially connected NOT gates, 2n odd-numbered jumper terminals and 2n even-numbered jumper terminals, and AND gates 1 and 2; Arrange the NOT gates according to the distance from the input square wave signal from near to far, and each odd-numbered signal can be connected to the two input ends of AND gate 1 using the odd-numbered jumper terminals, and each even-numbered signal can be connected to the two input ends of AND gate 2 using the even-numbered jumper terminals; Output the positive signal through AND gate 1; Output the inverse signal through AND gate 2; Implement a fault detection strategy on the circuit to determine whether there is a faulty NOT gate in the circuit; If there is no faulty NOT gate in the circuit; Obtain the delay time and dead time of the output forward signal and reverse signal, and record them as target delay time and target dead time respectively; Execute the first circuit delay control strategy to control the delay time of each NOT gate so that the delay time of the output signal of the entire circuit is the target delay time; If there is a faulty NOT gate in the circuit; Get the propagation delay time of the faulty NOT gate; According to the propagation delay time of the faulty NOT gate, a coordinated repair strategy is executed to reduce the impact of the faulty NOT gate on the circuit delay time and dead time.

2. The switch signal generating circuit with hardware dead zone control according to claim 1, characterized in that: The method of executing a fault detection strategy on a circuit to determine whether there is a faulty NOT gate in the circuit includes: For any NOT gate, when the input signal of the NOT gate is x i , where i is the serial number of the NOT gate, i = 1, 2, ... 2n-1; The output signal of the NOT gate is y i =-x i ; When 2n-1 NOT gates are connected in series in the circuit, x1=y 2n-1 ; Check if each NOT gate is faulty Among them, f i is the fault state of the i-th NOT gate; Building a fault propagation model Faulty NOT gate location: Get the state f of each NOT gate i , where f i =1 indicates a NOT gate fault, then the i-th NOT gate is a faulty NOT gate, f i =0 means the NOT gate is normal.

3. The switch signal generating circuit with hardware dead zone control according to claim 1, characterized in that: The step of executing the first circuit delay control strategy to control the delay time of each NOT gate so that the delay time of the output signal of the entire circuit is the target delay time includes: Get the input square wave signal V at time t in (t); The output positive signal of AND gate 1 is recorded as V out1 (t); The output inverse signal of AND gate 2 is recorded as V out2 (t); The delay time of each NOT gate is t delay,i , where i represents the i-th NOT gate; The delay propagation of the input square wave signal is expressed as Get the target delay time t target ; Establishing latency optimization goals Establish the dead time optimization target f2=max(0,t dead -t actual-dead ), t dead ,t actual-dead Represent the target dead time and actual dead time respectively.

4. The switch signal generating circuit with hardware dead zone control according to claim 3, characterized in that: The step of executing the first circuit delay control strategy to control the delay time of each NOT gate so that the delay time of the output signal of the entire circuit is the target delay time includes: Optimize the target based on the gradient descent method; The objective is f1+λ×f2, where λ is the weight coefficient of the dead time penalty term; Initialize the delay time of each NOT gate Set the learning rate η and the maximum number of iterations N max ; Compute the gradient of the objective function for each NOT gate i delay: Δ is the time growth value; Update delay time Calculate, and record the result as the change of objective function; Set the change threshold; Compare the change of the objective function with the change threshold. If the change rate of the objective function is less than the change threshold or the number of iterations is equal to N, max , the iteration stops.

5. The switch signal generating circuit with hardware dead zone control according to claim 1, characterized in that: The coordinated repair strategy is executed according to the propagation delay time of the faulty NOT gate to reduce the influence of the faulty NOT gate on the circuit delay time and dead time, including: Get the faulty NOT gate N k Propagation delay Calculate the dead time of the faulty NOT gate under normal conditions Calculate the change in dead time caused by the faulty NOT gate: Adjust the NOT gate N after the faulty NOT gate k+1 ,N k+2 ,…,N 2n-1 The delay time is N k+1 The delay time is Calculate the adjusted dead time: Calculate the objective function to minimize the impact of the adjusted dead time:

6. The switch signal generating circuit with hardware dead zone control according to claim 5, characterized in that: The coordinated repair strategy is executed according to the propagation delay time of the faulty NOT gate to reduce the influence of the faulty NOT gate on the circuit delay time and dead time, including: Optimization objective function: Define the constraints: in, They represent the minimum and maximum physical limits of the delay time of the i-th NOT gate.

7. The switch signal generating circuit with hardware dead zone control according to claim 6, characterized in that: The coordinated repair strategy is executed according to the propagation delay time of the faulty NOT gate to reduce the influence of the faulty NOT gate on the circuit delay time and dead time, including: The genetic algorithm is used to optimize the objective function, specifically: Initialize the population: Generate initial population Each individual in the population represents a propagation delay configuration, and the size of the population is P; Calculate the fitness function of each individual Select an action Among them, P i ,f i are the fitness of the ith individual and the ith individual respectively; Crossover operation, arbitrarily select two individuals P x ,P y To generate a new individual C xy1 ,C xy2 ; Among them, k is the intersection point; Mutation operation: Among them, Δt i is a random value; Set mutation probability Among them, ρ mutation is the mutation probability; Set fitness threshold; When the number of iterations reaches the maximum or the target fitness is less than the fitness threshold, the genetic algorithm is terminated and the best individual is output.

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