DVB and NR LDPC common-mode encoder device and method
By designing DVB and NR LDPC common mode encoder devices, a total of LDPC encoding processes under two systems were designed, which solved the problem of high consumption of LDPC encoding resources in common mode scenarios, and achieved resource reuse and coding efficiency improvement.
Patent Information
- Application Number
- CN202510054435.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-06-13
AI Technical Summary
In common-mode scenarios, the LDPC encoding of DVB and NR systems is implemented independently, resulting in a large resource consumption.
Design a DVB and NR LDPC common mode encoder device, and through the design of LDPC encoding processes under two systems, the bit width conversion module, ping pong RAM module, LDPC encoding module, bit interleaving module and other components are used to realize resource multiplexing.
By co-designing the LDPC encoding process, the resource consumption required for channel encoding is reduced and the encoding efficiency is improved.
Smart Images
Figure CN120150718A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of wireless communication technologies, and particularly to a DVB and NR LDPC common-mode encoder device and method. Background Art
[0002] Channel coding technology has an important impact on the performance of wireless communication systems. In the NTN system, the downlink and uplink service channels both adopt Quasi-Cyslic Low-Density Parity-Check Codes (QC-LDPC) as the channel coding method. In the NR standard 3GPP TS 38.212, the bit-level engineering processing flow of the NR system service channel is specified. First, the transmission block CRC is added, then the code block segmentation and code block CRC are added. After that, LDPC coding is performed on a code block basis. Considering pipelining processing, a ping-pong RAM is required to cache the code blocks. For compatibility in engineering implementation, the RAM is uniformly reserved according to the maximum code block of 22*Zc, where Zc is at most 384. Then, the coding process is parallel processed with a bit width of 384 bits. After coding, an over-rate matching is required to adapt to the air interface resources. Among them, the encoded output needs to be cached first, and then after bit selection, the corresponding bits are output to the subsequent module after bit interleaving. The interleaving process is related to the modulation order. In the DVB-S2 / S2X system, the data adopts BCH+LDPC coding, where the LDPC coding uses eIRA-LDPC (extended Irregular Repeat Accumulate-LDPC) as the channel coding method. The DVB-S2 / S2X standard defines the DVB-S2 / S2X bit-level processing flow. The payload bit stream first undergoes BCH coding, then the bit width conversion is performed with an output bit width of 360 bits and cached in the ping-pong RAM. Subsequently, LDPC coding processing is performed in sequence. The coding process includes QSN cyclic shift, check bit P calculation, and checksum bit calculation, and the check bit P and the checksum are stored. After all payload bits have completed LDPC coding, the checksum is differentially encoded, and then the check bits are taken row by row and XORed with the checksum to obtain the final check bits. Subsequently, bit interleaving is performed, and the interleaving process is related to the modulation order.
[0003] Currently, as the mainstream satellite protocols, DVB and NTN have a scenario of common mode for two systems in order to reduce costs and support scalability. In the common mode scenario, if the channel coding for the two systems is independently implemented, the channel coding for the two systems does not interfere with each other, but two independent sets of channel coding implementation resources are required, resulting in relatively high resource consumption. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a DVB and NR LDPC common-mode encoder device and method, which can co-design the LDPC encoding process under two systems and reduce the consumption of encoding resources to a certain extent.
[0005] The technical solution adopted by the present invention to solve its technical problems is: to provide a DVB and NR LDPC common-mode encoder device, including:
[0006] A bit-width conversion module, used to convert the bit-width to the required bit-width Zc;
[0007] A first ping-pong RAM module, used to store the required bit-width Zc;
[0008] An LDPC encoding module, including a shift unit, an NTN encoding part, and a DVB encoding part. The shift unit is used to perform QSN shift on the Zc bits output from the first ping-pong RAM module; the NTN encoding part is used to encode the QSN-shifted Zc bits based on the NTN LDPC check matrix; the DVB encoding part is used to encode the QSN-shifted Zc bits based on the DVB LDPC check matrix;
[0009] A second ping-pong RAM module, used to store the encoding results of the NTN encoding part and the DVB encoding part;
[0010] A PSum RAM module, used to store the PSum calculation results of the DVB encoding part;
[0011] A BIT extraction module, used to perform bit selection on the encoding results of the NTN encoding part;
[0012] A post-processing module, used to perform post-processing on the encoding results of the DVB encoding part in the second ping-pong RAM module and the PSum calculation results in the PSum RAM module;
[0013] A bit interleaving module, used to perform bit interleaving on the bit selection results of the BIT extraction module and the processing results of the post-processing module.
[0014] The NTN encoding part includes a calculation unit, and the calculation unit sequentially performs calculations of Acalcu, B calcu, C calcu, and D calcu on the QSN-shifted Zc bits based on the NTN LDPC check matrix.
[0015] The DVB encoding part includes a Pbits calculation unit and a PSum calculation unit. The Pbits calculation unit is used to perform Pbits calculation on the data read from the second ping-pong RAM module according to the DVB LDPC check matrix and the Zc bits after QSN shift, and rewrite the result into the second ping-pong RAM module according to the DVB LDPC check matrix. The PSum calculation unit is used to perform modulo-two addition on the Zc bits after QSN shift, superimpose the obtained result on the PSum calculation result stored in the PSum RAM module, and store the superimposed result in the PSum RAM module.
[0016] The post-processing module includes a differential encoding unit and a modulo-two addition unit. The differential encoding unit is used to perform differential encoding on the PSum calculation result in the PSum RAM module. The modulo-two addition unit is used to perform modulo-two addition calculation on each row of the differential encoding result of the differential encoding unit and the encoding result of the DVB encoding part in the second ping-pong RAM module.
[0017] The first ping-pong RAM module is opened up according to 22 * 384.
[0018] The technical solution adopted by the present invention to solve its technical problems is to provide a usage method of the above DVB and NR LDPC common-mode encoder device, including the following steps:
[0019] Determine the current encoding mode;
[0020] When the current encoding mode is the NTN LDPC encoding mode, the shift unit and the NTN encoding part in the LDPC encoding module, as well as the second ping-pong RAM module and the BIT extraction module cooperate to complete LDPC encoding;
[0021] When the current encoding mode is the DVB LDPC encoding mode, the shift unit and the DVB encoding part in the LDPC encoding module, as well as the second ping-pong RAM module, the PSum RAM module and the post-processing module cooperate to complete LDPC encoding.
[0022] The shift unit and the NTN encoding part in the LDPC encoding module, as well as the second ping-pong RAM module and the BIT extraction module cooperate to complete LDPC encoding, specifically including:
[0023] The input Zc bits are subjected to QSN shift by the shift unit, and the Zc bits after QSN shift are successively subjected to Acalcu, B calcu, C calcu, and Dcalcu calculations by the calculation unit NTN LDPC check matrix in the NTN encoding part, and the calculation results are output to the second ping-pong RAM module for storage. The bit selection of the encoding result of the NTN encoding part in the second ping-pong RAM module is performed by the BIT extraction module.
[0024] The shift unit in the LDPC encoding module, the DVB encoding part, the second ping-pong RAM module, the PSumRAM module, and the post-processing module cooperate to complete LDPC encoding, specifically including:
[0025] The input Zc bits are subjected to QSN shift by the shift unit. The Pbits calculation unit in the DVB encoding part performs Pbits calculation on the data read from the second ping-pong RAM module according to the DVB LDPC check matrix and the Zc bits after QSN shift, and rewrites the result into the second ping-pong RAM module according to the DVB LDPC check matrix. The PSum calculation unit in the DVB encoding part performs modulo-two addition on the Zc bits after QSN shift, and superimposes the obtained result on the PSum calculation result stored in the PSumRAM module, and stores the superimposed result in the PSum RAM module. After all the input Zc bit streams are processed by the DVB encoding part, the differential encoding unit of the post-processing module performs differential encoding on the PSum calculation result in the PSum RAM module, and the modulo-two addition unit of the post-processing module performs modulo-two addition calculation on the differential encoding result and each row of data of the encoding result of the DVB encoding part in the second ping-pong RAM module.
[0026] Beneficial effects
[0027] Due to the adoption of the above technical solutions, compared with the prior art, the present invention has the following advantages and positive effects: The present invention co-designs the LDPC encoding processes under two systems according to their respective encoding processes, and through the reuse of processing flows and control resources, the resource consumption required for channel encoding can be greatly reduced to a certain extent. Brief description of the drawings
[0028] Figure 1 It is a schematic diagram of the DVB and NR LDPC common-mode encoder device according to the embodiment of the present invention. Detailed implementation manners
[0029] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.
[0030] An embodiment of the present invention relates to a DVB and NR LDPC common-mode encoder device, as Figure 1 shown, including:
[0031] A bit-width conversion module for converting the bit-width to the required bit-width Zc.
[0032] A first ping-pong RAM module for storing the required bit-width Zc, wherein the first ping-pong RAM module is opened up according to 22*384.
[0033] An LDPC encoding module includes a shift unit, an NTN encoding part, and a DVB encoding part. The shift unit is used for performing QSN shift on the Zc bits output from the first ping-pong RAM module; the NTN encoding part is used for encoding the QSN-shifted Zc bits based on the NTN LDPC check matrix; the DVB encoding part is used for encoding the QSN-shifted Zc bits based on the DVB LDPC check matrix.
[0034] In this embodiment, the NTN encoding part includes a calculation unit, and the calculation unit sequentially performs calculations of Acalcu, B calcu, C calcu, and D calcu on the QSN-shifted Zc bits based on the NTN LDPC check matrix.
[0035] In this embodiment, the DVB encoding part includes a Pbits calculation unit and a PSum calculation unit. The Pbits calculation unit is used for performing Pbits calculation on the data read from the second ping-pong RAM module according to the DVB LDPC check matrix and the QSN-shifted Zc bits, and rewriting the result into the second ping-pong RAM module according to the DVB LDPC check matrix; the PSum calculation unit is used for performing modulo-two addition on the QSN-shifted Zc bits, and superimposing the obtained result on the PSum calculation result stored in the PSum RAM module, and storing the superimposed result in the PSum RAM module.
[0036] A second ping-pong RAM module for storing the encoding results of the NTN encoding part and the DVB encoding part.
[0037] A PSum RAM module for storing the PSum calculation result of the DVB encoding part.
[0038] A BIT extraction module is used to perform bit selection on the encoding result of the NTN encoding part.
[0039] A post-processing module is used to perform post-processing on the encoding result of the DVB encoding part in the second ping-pong RAM module and the PSum calculation result in the PSum RAM module.
[0040] The post-processing module in this embodiment includes: a differential encoding unit and an exclusive-OR unit. The differential encoding unit is used to perform differential encoding on the PSum calculation result in the PSum RAM module; the exclusive-OR unit is used to perform an exclusive-OR calculation on each row of data of the differential encoding result of the differential encoding unit and the encoding result of the DVB encoding part in the second ping-pong RAM module.
[0041] A bit interleaving module is used to perform bit interleaving on the bit selection result of the BIT extraction module and the processing result of the post-processing module. The bit interleaving module in this embodiment is set according to the modulation order Qm, where the maximum value of Qm is 8. In this embodiment, 8 FIFO RAMs are opened, and Qm is actually used. After interleaving is completed, the Qm FIFOs are output in sequence.
[0042] When the DVB and NR LDPC common-mode encoder device in this embodiment performs encoding, it specifically includes the following steps:
[0043] Step 1, determine the current encoding mode.
[0044] Step 2, when the current encoding mode is the NTN LDPC encoding mode, the shift unit and the NTN encoding part in the LDPC encoding module, as well as the second ping-pong RAM module and the BIT extraction module cooperate to complete LDPC encoding. Specifically:
[0045] The input Zc bits are subjected to QSN shift through the shift unit, and the QSN-shifted Zc bits are sequentially subjected to Acalcu, B calcu, C calcu, and Dcalcu calculations through the calculation unit NTN LDPC check matrix in the NTN encoding part, and the calculation results are output to the second ping-pong RAM module for storage, where the size of the second ping-pong RAM module is 66*Zc. Then, the BIT extraction module performs bit selection on the encoding result of the NTN encoding part in the second ping-pong RAM module. Finally, the bit width is converted through the FIFO module, and then bit interleaving is performed. After interleaving is completed, the Qm FIFO modules are output in sequence.
[0046] Step 3, when the current coding mode is the DVB LDPC coding mode, the shift unit and the DVB coding part in the LDPC coding module, as well as the second ping-pong RAM module, the PSum RAM module, and the post-processing module cooperate to complete LDPC coding. Specifically:
[0047] The input Zc bits are subjected to QSN shift by the shift unit. The Pbits calculation unit in the DVB coding part calculates Pbits for the data read from the second ping-pong RAM module according to the DVB LDPC parity-check matrix and the QSN-shifted Zc bits, and rewrites the result into the second ping-pong RAM module according to the DVB LDPC parity-check matrix. In this mode, the second ping-pong RAM module is used in the form of 140*360. The PSum calculation unit in the DVB coding part performs modulo-two addition on the QSN-shifted Zc bits, and superimposes the obtained result on the PSum calculation result stored in the PSum RAM module, and stores the superimposed result in the PSum RAM module. After all the input Zc bit streams are processed by the DVB coding part, the differential coding unit of the post-processing module performs differential coding on the PSum calculation result in the PSum RAM module, and the modulo-two addition unit of the post-processing module performs modulo-two addition calculation on the differential coding result and each row of data of the coding result of the DVB coding part in the second ping-pong RAM module. Finally, interleaving is performed according to the modulation method, and the interleaving process can reuse the interleaving process of the NTN LDPC coding mode.
[0048] The present invention is further illustrated by an embodiment below.
[0049] The DVB-S2 / S2X LDPC coding is performed with a parallelism of 360. The maximum value of Zc in the NTN LDPC coding is 384. In this embodiment, Zc = 256 is used for illustration.
[0050] The pre-stage module converts the bit width to the required bit width Zc through the bit-width conversion module. That is, in the NTN mode, the bit width of the bit stream is converted to 256 bits, and in the DVB mode, the bit width needs to be converted to 360 bits. Then it enters the first ping-pong RAM module, which is opened up in the form of 22*384. In the NTN mode, only 22*256 is occupied, and in the DVB mode, 1*360 bits are occupied.
[0051] In the NTN LDPC coding mode, Zc = 256 bits enter the LDPC coding module, the NTN LDPC check matrix is read, and the input Zc = 256 bits are subjected to QSN shift. Subsequently, calculations of Acalcu, Bcalcu, C calcu, and D calcu are sequentially performed based on the NTN LDPC check matrix, and the output is directly stored in the second ping-pong RAM module. The size of this second ping-pong RAM module is 66 * Zc. Subsequently, Zc bits of the second ping-pong RAM module enter the BIT extraction module to complete bit selection, and the bit width conversion is performed through the FIFO module. After that, bit interleaving is carried out. After the interleaving is completed, the Qm FIFO modules output sequentially.
[0052] In the DVB LDPC coding mode, 360 bits enter the LDPC coding module, and the DVB LDPC check matrix, that is, the corresponding address parameter AddressValue, is read. First, the input 360 bits are subjected to QSN shift. Subsequently, data is read from the second ping-pong RAM module according to the address parameter AddressValue. Among them, when the second ping-pong RAM module is used in the DVB mode, it is used as 140 * 360. The data read is subjected to Pbits calculation with the result of QSN shift, and is rewritten into the second ping-pong RAM module according to the address parameter AddressValue. Subsequently, PSum is read from the PSum RAM module, the result of QSN shift is subjected to modulo-two addition, and the obtained result is superimposed with PSum. Subsequently, the superimposed structure is rewritten into the PSum RAM module. After all the bit streams of the payload are processed by the LDPC coding module, PSum differential coding is performed on the PSum in the PSum RAM module, and modulo-two addition calculation is performed with each row of data in the second ping-pong RAM module to obtain the encoded data. Finally, interleaving is performed according to the modulation method.
[0053] It is not difficult to find that the present invention co-designs the LDPC coding processes under the two systems according to their respective coding processes. Through the reuse of processing flows and control resources, the resource consumption required for channel coding can be greatly reduced to a certain extent.
Claims
1. A DVB and NR LDPC common mode encoder device, characterized in that: include: A bit width conversion module, used for converting the bit width into a required bit width Zc; A first ping-pong RAM module, used for storing the required bit width Zc; An LDPC encoding module, comprising a shift unit, an NTN encoding part and a DVB encoding part, wherein the shift unit is used to perform a QSN shift on the Zc bit output from the first ping-pong RAM module; and the NTN encoding part is used to encode the QSN-shifted Zc bit based on the NTN LDPC check matrix; The DVB encoding part is used to encode the Zc bits after the QSN shift based on the DVB LDPC check matrix; A second ping-pong RAM module, used to store the encoding result of the NTN encoding part and the encoding result of the DVB encoding part; A PSum RAM module, used to store the PSum calculation result of the DVB encoding part; A BIT extraction module, used for performing bit selection on the encoding result of the NTN encoding part; A post-processing module, used for post-processing the encoding result of the DVB encoding part in the second ping-pong RAM module and the PSum calculation result in the PSumRAM module; The bit interleaving module is used to perform bit interleaving on the bit selection result of the BIT extraction module and the processing result of the post-processing module.
2. The DVB and NR LDPC common mode encoder device according to claim 1, characterized in that The NTN encoding part includes a calculation unit, which sequentially calculates Acalcu, B calcu, C calcu and D calcu on the Zc bits after the QSN shift based on the NTN LDPC check matrix.
3. The DVB and NR LDPC common mode encoder device according to claim 1, characterized in that: The DVB encoding part includes a Pbits calculation unit and a PSum calculation unit. The Pbits calculation unit is used to perform Pbits calculation on the data read from the second ping-pong RAM module according to the DVB LDPC check matrix and the Zc bit after the QSN shift, and rewrite it into the second ping-pong RAM module according to the DVB LDPC check matrix; the PSum calculation unit is used to calculate the modulo-two sum of the Zc bit after the QSN shift, and superimpose the obtained result with the PSum calculation result stored in the PSum RAM module, and store the superimposed result in the PSum RAM module.
4. The DVB and NR LDPC common mode encoder device according to claim 1, characterized in that The post-processing module includes a differential encoding unit and a modulo-2 addition unit, wherein the differential encoding unit is used to perform differential encoding on the PSum calculation result in the PSum RAM module; The modulo-2 addition unit is used to perform modulo-2 addition calculation on the differential encoding result of the differential encoding unit and each row of data of the encoding result of the DVB encoding part in the second ping-pong RAM module.
5. The DVB and NR LDPC common mode encoder device according to claim 1, characterized in that: The first ping-pong RAM module is developed according to 22*384.
6. A method for using the DVB and NR LDPC common mode encoder device as described in claims 1-5, characterized in that: The following steps are involved: Determine the current encoding mode; If the current coding mode is the NTN LDPC coding mode, the shift unit and the NTN coding part in the LDPC coding module, as well as the second ping-pong RAM module and the BIT extraction module cooperate to complete the LDPC coding; If the current coding mode is the DVB LDPC coding mode, the shift unit and the DVB coding part in the LDPC coding module, as well as the second ping-pong RAM module, the PSum RAM module and the post-processing module cooperate to complete the LDPC coding.
7. The method of use according to claim 6, characterized in that: The shift unit and the NTN encoding part in the LDPC encoding module, as well as the second ping-pong RAM module and the BIT extraction module cooperate to complete the LDPC encoding, specifically including: The shift unit performs QSN shift on the input Zc bit, and the calculation unit NTNLDPC check matrix in the NTN coding part sequentially performs A calcu, B calcu, C calcu and D calcu on the QSN-shifted Zc bit, outputs the calculation result to the second ping-pong RAM module for storage, and the BIT extraction module performs bit selection on the coding result of the NTN coding part in the second ping-pong RAM module.
8. The method of use according to claim 6, characterized in that: The shift unit and the DVB encoding part in the LDPC encoding module, as well as the second ping-pong RAM module, the PSum RAM module and the post-processing module cooperate to complete the LDPC encoding, specifically including: The shift unit performs QSN shift on the input Zc bit, and the Pbits calculation unit in the DVB encoding part performs Pbits calculation on the data read from the second ping-pong RAM module according to the DVB LDPC check matrix and the Zc bit after the QSN shift, and rewrites it into the second ping-pong RAM module according to the DVB LDPC check matrix; the PSum calculation unit in the DVB encoding part calculates a modulo-2 sum of the Zc bit after the QSN shift, and superimposes the obtained result with the PSum calculation result stored in the PSum RAM module, and stores the superimposed result in the PSum RAM module; after all the input Zc bit streams are processed by the DVB encoding part, the differential encoding unit of the post-processing module performs differential encoding on the PSum calculation result in the PSumRAM module, and the modulo-2 addition unit of the post-processing module performs modulo-2 addition calculation on the differential encoding result and each row of data of the encoding result of the DVB encoding part in the second ping-pong RAM module.