Optical fiber transmission system and method with multi-module synchronization and FPGA logic remote upgrade

Abstract

The invention provides an optical fiber transmission system and method with multi-module synchronization and FPGA logic remote upgrading, belongs to the technical field of data transmission, and solves the problems that an existing optical fiber transmission system is provided with a small number of optical modules, the interface rate is low, and the data transmission efficiency is low. The invention discloses an optical fiber transmission system which solves the problems that in the prior art, the requirement for high-speed data transmission cannot be met, the FPGA logic program updating time consumption is large, extra interface resource overhead exists, and the transmission distance is limited in the prior art, and the optical fiber transmission system comprises N PCIe optical fiber data transmission modules which are connected with one another through synchronous interfaces, each PCIe optical fiber data transmission module comprises an FPGA control chip, a DDR cache, a FLASH chip, a clock, a synchronous interface, a power supply conversion unit, a PCIe interface and at least one optical fiber interface.

Description

Technical Field

[0001] The present invention relates to an optical fiber transmission system and method with multi-module synchronization and remote FPGA logic upgrade, belonging to the technical field of data transmission. Background Art

[0002] With the development trend of high temporal resolution, high spatial resolution, and high spectral resolution of remote sensing data sources, the types of remote sensing satellite payload data are increasing, and the data volume is getting larger. The bandwidth requirements for data transmission by the payload data simulation system are also gradually increasing. Traditional payload interfaces such as LVDS, TLK2711, and CXP can no longer meet the requirements of large-capacity and high-speed transmission. In high-speed data transmission, the transmission medium plays a key role. Optical fiber communication has gradually become the dominant form of high-speed data transmission at home and abroad with its higher channel bandwidth and transmission capacity, longer relay distance, and better confidentiality. Optical fiber interfaces have become a mainstream payload interface.

[0003] In addition, the development of bus technology also has a profound impact on high-speed data transmission. The third-generation bus technology PCI Express adopts a serial communication method, and each peripheral does not need to share the system bandwidth, greatly improving the transmission bandwidth of the bus. Compared with the previous two generations, it has significant improvements in bandwidth, performance, power consumption, and reliability, and is currently the most widely used bus form.

[0004] The existing optical fiber transmission systems have fewer optical module channels and lower interface rates, which cannot meet the requirements of high-speed data transmission. The data transmission of satellite payloads often requires multiple modules to work simultaneously, and high requirements are put forward for the synchronization between multiple channels of data, and the optical fiber transmission system needs to overcome the problem of synchronous transmission between multiple modules.

[0005] Currently, when updating the FPGA logic program, the product needs to be disassembled and then completed through a dedicated cable and downloader, which consumes time and reduces the reliability of the device. Other update forms such as using serial ports, PCIe interfaces, etc. have problems such as additional interface resource overhead and limited transmission distance. An optical module can achieve duplex communication and can receive optical fiber data while not affecting optical fiber transmission. Therefore, the interface resources of the module can be utilized to achieve remote online upgrade of FPGA logic through optical fiber. The present invention proposes a better FPGA remote logic upgrade solution. Summary of the Invention

[0006] The present invention aims to solve the problems that the existing optical fiber transmission systems have fewer optical module channels and lower interface rates, which cannot meet the requirements of high-speed data transmission, and the update time of the FPGA logic program is time-consuming, with additional interface resource overhead and limited transmission distance, and further proposes an optical fiber transmission system and method with multi-module synchronization and remote FPGA logic upgrade.

[0007] The technical solution adopted by the present invention to solve the above problems is: The optical fiber transmission system with multi-module synchronization and FPGA logic remote upgrade proposed by the present invention includes:

[0008] N PCIe optical fiber data transmission modules, and each PCIe optical fiber data transmission module is interconnected through a synchronization interface.

[0009] Preferably, each PCIe optical fiber data transmission module includes an FPGA control chip, a DDR cache, a FLASH chip, a clock, a synchronization interface, a power supply conversion unit, a PCIe interface, and at least one optical fiber interface;

[0010] The DDR cache, the FLASH chip, the clock, the PCIe interface, the optical fiber interface, and the synchronization interface are all connected to the FPGA control chip;

[0011] The FPGA control chip is used to store the firmware program of the FPGA;

[0012] The DDR cache is used to store the effective large-capacity high-speed payload data transmitted by the host computer;

[0013] The clock consists of multiple crystal oscillators and is used to provide the required frequency clocks for the FPGA control chip, the PCIe interface, and the optical fiber interface;

[0014] The power supply conversion unit consists of multiple power conversion chips and is used to supply power to the optical fiber transmission system.

[0015] Preferably, the synchronization interface of the PCIe optical fiber data transmission module includes a transmit port and a receive port, and the modules are cascaded in a ring manner through the transmit port and the receive port in a daisy chain.

[0016] Preferably, the optical fiber interface is a QSFP optical module, which is used to realize the conversion between optical and electrical signals. The PCIe optical fiber data transmission module receives the upgrade file through the QSFP optical module and uses the optical fiber for FPGA remote logic upgrade;

[0017] The PCIe interface connects the host computer and the FPGA control chip and is used for data transmission between the PCIe optical fiber data transmission module and the host computer.

[0018] An optical fiber transmission method with multi-module synchronization and FPGA logic remote upgrade includes:

[0019] Step 1: Each PCIe optical fiber data transmission module receives the large-capacity high-speed payload data transmitted by the host computer through the PCIe interface and transmits the large-capacity high-speed payload data to the FPGA control chip;

[0020] Step 2: The FPGA control chip parses the large-capacity high-speed payload data according to the PCIe protocol and stores the parsed valid large-capacity high-speed payload data in the DDR cache;

[0021] Step 3: Read the valid large-capacity high-speed payload data from the DDR cache and encode the valid large-capacity high-speed payload data according to the corresponding frame format, then transmit the encoded data to the optical fiber interface. The optical fiber interface encodes and serial-to-parallel converts the data according to the optical fiber protocol and outputs it through the QSFP optical module;

[0022] Step 4: N PCIe optical fiber data transmission modules are cascaded in a ring manner through the synchronization interface in a daisy chain. Any PCIe optical fiber data transmission module is used as the initiator of the synchronization signal, and the sender sends a ready signal to the next-level PCIe optical fiber data transmission module;

[0023] Step 5: After receiving the ready signal, the next-level PCIe optical fiber data transmission module ANDs it with its own ready signal and then sends it to the next level;

[0024] Step 6: Repeat Step 5. The N PCIe optical fiber data transmission modules AND each other in turn, and send the ready signal of the Nth-level PCIe optical fiber data transmission module to the initiator. The initiator sends a synchronization signal, and through the transmission of each level, the synchronous transmission of the N PCIe optical fiber data transmission modules is realized;

[0025] Step 7: The optical fiber transmission system receives the upgrade file through the QSFP optical module and performs FPGA remote logic upgrade using the optical fiber.

[0026] Preferably, Step 7 specifically includes:

[0027] Step 7.1: Build a logic upgrade system by instantiating the internal core of the FPGA. Among them, the internal core of the FPGA at least includes a MicroBlaze soft core, an AXI Quad SPI controller core, and an Aurora IP core;

[0028] Step 7.2: The QSFP optical module receives the bin file that needs to be burned into the FLASH chip and writes it into a specific storage area in the DDR cache;

[0029] Step 7.3: Use the Multiboot function to perform online upgrade in combination with the stored bin file.

[0030] Preferably, Step 7.3 specifically includes:

[0031] Download the golden image and the update image as initialization images to the FLASH chip. Among them, the storage address of the golden image is between 0x00000000 and 0x01FFFFFF, and the starting storage address of the update image is 0x02000000. The host computer sends an update instruction by writing to the register through PCIe, erases the update image area of the FLASH chip, and writes the bin file cached in the DDR cache to the update image area. After the programming is completed, a completion signal is returned to the host computer through the register. After the PCIe optical fiber data transmission module is powered off and restarted, the updated program can be run.

[0032] The beneficial effects of the present invention are as follows:

[0033] 1. The present invention uses a PCIe interface and an optical fiber interface to achieve payload data transmission. The theoretical bandwidth of PCIe 3.0 x8 can reach 8 GB / s. The module has multiple QSFP-type optical fiber interfaces, and the single-channel interface rate is 40 Gbps. The system can achieve multi-module synchronous transmission, so as to achieve high-speed data transmission of N * 40 Gbps and above;

[0034] 2. The present invention proposes a synchronization method in a multi-module scenario. This synchronization method refers to the ring cascade mode of a daisy chain, and uses the least number of synchronization signal transmission lines to connect multiple modules. For a single module, only one sending port and one receiving port are required to achieve interconnection with other N - 1 modules, which greatly improves the simplicity of the synchronization signal transmission line in the physical topology and saves wiring resources. The synchronization delay of this synchronization method only depends on the delay t of a single line and the number of modules N, and the total delay is (N - 1) * t. Since the wiring delay is fixed and usually a very small value, the synchronization accuracy (N - 1) * t of the system is an ideal value;

[0035] 3. The present invention realizes remote logic upgrade of the FPGA based on optical fiber. Using the existing interface resources, the upgrade file is received through the optical module. Without affecting the optical fiber sending function, the advantages of stable and long-distance transmission of the optical fiber are fully utilized. The optical module of the module is used to receive the upgrade file, which fully utilizes the existing interface resources of the module. And compared with the previous solutions for logical upgrade using serial ports, PCIe interfaces, etc., it can better ensure the long-distance stable transmission of the program file. The FPGA can complete the reading and writing of the firmware program in the configuration chip under the control of the logic program, and realizes the update of the FPGA logic with extremely low resource requirements, solving the problem that the program can only be upgraded by disassembling the product and then using a special cable and a downloader in the past. Description of the Drawings

[0036] Figure 1Block diagram of the optical fiber transmission system with multi-module synchronization and FPGA logic remote upgrade provided by the present invention;

[0037] Figure 2 Block diagram of a single PCIe optical fiber data transmission module provided by the present invention;

[0038] Figure 3 Overall schematic diagram of a 6-channel optical fiber transmission system provided by the present invention;

[0039] Figure 4 Firmware logic design diagram of the PCIe optical fiber data transmission module provided by the present invention;

[0040] Figure 5 Flowchart of FPGA remote logic upgrade provided by the present invention;

[0041] Figure 6 Firmware logic design diagram of FPGA remote logic upgrade provided by the present invention. Detailed implementation manners

[0042] In combination with Figure 1 、 Figure 2 and Figure 5 describe this implementation manner. As Figure 1 shown, the structure of the optical fiber transmission system with multi-module synchronization and FPGA logic remote upgrade described in this implementation manner includes:

[0043] N PCIe optical fiber data transmission modules, and each PCIe optical fiber data transmission module is interconnected through a synchronization interface.

[0044] As Figure 2 shown, each PCIe optical fiber data transmission module includes an FPGA control chip, a DDR cache, a FLASH chip, a clock, a synchronization interface, a power supply conversion unit, a PCIe interface, and at least one optical fiber interface. Among them, the DDR cache, the FLASH chip, the clock, the PCIe interface, the optical fiber interface, and the synchronization interface are all connected to the FPGA control chip; the FPGA control chip is used to store the firmware program of the FPGA; the DDR cache is used to store the effective large-capacity high-speed payload data transmitted by the host computer; the clock consists of multiple crystal oscillators and is used to provide the required frequency clocks for the FPGA control chip, the PCIe interface, and the optical fiber interface; the power supply conversion unit consists of multiple power conversion chips and is used to supply power to the optical fiber transmission system.

[0045] The PCIe interface connects the host computer and the FPGA control chip, and is used for data transmission between the PCIe optical fiber data transmission module and the host computer; the synchronization interface of the PCIe optical fiber data transmission module includes a sending port and a receiving port, and the modules are cascaded in a ring manner through the sending port and the receiving port in a daisy chain; the optical fiber interface is a QSFP optical module, which is used to realize the conversion between optical and electrical signals. The PCIe optical fiber data transmission module receives the upgrade file through the QSFP optical module and uses the optical fiber for remote logic upgrade of the FPGA;

[0046] The steps of the optical fiber transmission method with multi-module synchronization and FPGA logic remote upgrade include:

[0047] S1: Each PCIe optical fiber data transmission module receives the large-capacity high-speed payload data transmitted by the host computer through the PCIe interface, and transmits the large-capacity high-speed payload data to the FPGA control chip;

[0048] S2: The FPGA control chip analyzes the large-capacity high-speed payload data according to the PCIe protocol, stores the obtained effective large-capacity high-speed payload data in the DDR cache, reads the effective large-capacity high-speed payload data from the DDR cache and encodes the effective large-capacity high-speed payload data according to the corresponding frame format, and transmits the encoded data to the optical fiber interface. The optical fiber interface encodes and serial-to-parallel converts the data according to the optical fiber protocol and outputs it through the QSFP optical module;

[0049] S3: N PCIe optical fiber data transmission modules are cascaded in a ring manner through the synchronization interface in a daisy chain. Any PCIe optical fiber data transmission module is used as the initiator of the synchronization signal, and the sending end sends a preparation signal to the next-level PCIe optical fiber data transmission module;

[0050] S4: After receiving the preparation signal, the next-level PCIe optical fiber data transmission module ANDs its own preparation signal and then sends it to the next level;

[0051] S5: Repeat S4, and N PCIe optical fiber data transmission modules AND in turn. The preparation signal of the Nth-level PCIe optical fiber data transmission module is sent to the initiator, and the initiator sends a synchronization signal, and the synchronization sending of N PCIe optical fiber data transmission modules is realized through transmission at all levels;

[0052] S6: The optical fiber transmission system receives the upgrade file through the QSFP optical module and uses the optical fiber for remote logic upgrade of the FPGA. The logic upgrade is as Figure 5 shown, and specifically includes:

[0053] S601: Build a logic upgrade system by instantiating a MicroBlaze soft core, an AXI Quad SPI controller core, an Aurora IP core, etc. inside the FPGA;

[0054] S602: The QSFP optical module receives the bin file that needs to be burned into the FLASH chip and writes it into a specific storage area in the DDR cache;

[0055] S603: Use the Multiboot function to perform an online upgrade in combination with the stored bin file;

[0056] Download the golden image and the update image as initialization images into the FLASH chip. Among them, the storage address of the golden image is between 0x00000000 and 0x01FFFFFF, and the starting storage address of the update image is 0x02000000. The host computer sends an update instruction in the way of writing registers through PCIe, erases the update image area of the FLASH chip, and writes the bin file cached in the DDR cache into the update image area. After the burning is completed, a completion signal is returned to the host computer through the register. After the PCIe optical fiber data transmission module is powered off and then powered on again, the updated program can be run.

[0057] Example: Combine Figures 3 - 6 To illustrate this embodiment, as Figure 3 shown, in this embodiment, the optical fiber transmission system consists of three PCIe optical fiber data transmission modules. The PCIe optical fiber data transmission module 1 is used as the main module, and the PCIe optical fiber data transmission modules 2 and 3 are used as slave modules. The modules are cascaded in a ring manner through an SMA-type synchronous interface in a daisy chain to achieve the transfer of synchronous enabling. Each single module has two optical fiber interfaces, so as to complete the synchronous data transmission of 6 optical fiber interfaces.

[0058] As Figure 4 shown, the parameter configuration, enabling control and data interaction between the PCIe optical fiber data transmission module and the host computer are completed through the PCIe interface. The specific interface standard is PCIe3.0×8; the PCIe optical fiber data transmission module takes the FPGA chip as the control core, PCIe is implemented based on the XDMA scheme, and the optical fiber communication adopts the Aurora6466B transmission protocol.

[0059] Based on the above 6-channel optical fiber transmission system and parameter configuration, perform optical fiber transmission. The specific steps include:

[0060] S1: The FPGA communicates with the host computer through XDMA. The configuration information of the module received from the host computer is stored in the register, and the large-capacity high-speed payload data sent by the host computer is cached into the DDR3 in the way of DMA.

[0061] S2: After the data is cached in DDR3 through XDMA, it needs to be read out through DMA and cached in the asynchronous FIFO for bit-width and clock-domain conversion, and then the data is encoded.

[0062] S3: The data encoding module is responsible for controlling the reading and writing of the asynchronous FIFO, the transceiver scheduling of the Aurora data interface, and framing the data according to the corresponding protocol; after receiving the synchronous enable and completing the data framing, the Aurora 64B / 66B IP core will perform 64B / 66B encoding and serial-to-parallel conversion on the data from the user interface, and finally synchronously send the 3×2 channels of data through the optical fiber interface.

[0063] S4: As Figure 5 shown, the optical fiber transmission system realizes the remote logic upgrade of the FPGA based on the optical fiber. The specific steps include:

[0064] S401: As Figure 6 shown, build a logic upgrade system by instantiating the MicroBlaze soft core, AXI Quad SPI controller core, Aurora IP core, etc. inside the FPGA;

[0065] S402: The QSFP optical module receives the bin file that needs to be burned into the FLASH chip and writes it into a specific storage area in the DDR cache;

[0066] S403: Use the Multiboot technology to achieve online upgrade:

[0067] Download the golden image and update image as the initialization images to the FLASH chip. Among them, the storage address of the golden image is between 0x00000000 and 0x01FFFFFF, and the starting storage address of the update image is 0x02000000. The host computer sends an update instruction in the way of writing registers through PCIe, erases the update image area of the FLASH chip, and writes the bin file cached in the DDR cache into the update image area. After the burning is completed, a completion signal is returned to the host computer through the register. After the PCIe optical fiber data transmission module is powered off and restarted, the updated program can be run.

[0068] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modifications, equivalent replacements, and improvements made to the above embodiments based on the technical essence of the present invention within the spirit and principles of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A fiber optic transmission system with multi-module synchronization and FPGA logic remote upgrade, characterized in that: The structure of the optical fiber transmission system with multi-module synchronization and FPGA logic remote upgrade includes: N PCIe optical fiber data transmission modules, each PCIe optical fiber data transmission module is connected to each other through a synchronous interface.

2. The optical fiber transmission system with multi-module synchronization and FPGA logic remote upgrade according to claim 1, characterized in that: Each PCIe optical fiber data transmission module includes an FPGA control chip, a DDR cache, a FLASH chip, a clock, a synchronization interface, a power supply conversion unit, a PCIe interface, and at least one optical fiber interface; The DDR cache, FLASH chip, clock, PCIe interface, optical fiber interface and synchronization interface are all connected to the FPGA control chip; The FPGA control chip is used to store the FPGA firmware program; DDR cache is used to store effective large-capacity and high-speed load data transmitted by the host computer; The clock is composed of multiple crystal oscillators, which are used to provide the required frequency clock for the FPGA control chip, PCIe interface and optical fiber interface; The power conversion unit is composed of multiple power conversion chips and is used to provide power to the optical fiber transmission system.

3. The optical fiber transmission system with multi-module synchronization and FPGA logic remote upgrade according to claim 2, characterized in that: The synchronous interface includes a transmitting port and a receiving port, and the modules are cascaded in a daisy chain manner through the transmitting port and the receiving port.

4. The optical fiber transmission system with multi-module synchronization and FPGA logic remote upgrade according to claim 2, characterized in that: The optical fiber interface is a QSFP optical module, which is used to realize the conversion of optical and electrical signals. The PCIe optical fiber data transmission module receives the upgrade file through the QSFP optical module and uses optical fiber to perform remote logic upgrade of FPGA. The PCIe interface connects the host computer and the FPGA control chip and is used for data transmission between the PCIe optical fiber data transmission module and the host computer.

5. An optical fiber transmission method with multi-module synchronization and FPGA logic remote upgrade, applied to an optical fiber transmission system with multi-module synchronization and FPGA logic remote upgrade as claimed in any one of claims 1 to 4, characterized in that: include: Step 1: Each PCIe optical fiber data transmission module receives large-capacity and high-speed payload data transmitted by the host computer through the PCIe interface, and transmits the large-capacity and high-speed payload data to the FPGA control chip; Step 2: The FPGA control chip parses the large-capacity, high-speed payload data according to the PCIe protocol, and stores the parsed valid large-capacity, high-speed payload data into the DDR cache; Step 3: Read the effective large-capacity high-speed payload data from the DDR cache and encode the effective large-capacity high-speed payload data according to the corresponding frame format, and transmit the encoded data to the optical fiber interface. The optical fiber interface encodes and converts the data into parallel and serial data according to the optical fiber protocol and outputs it through the QSFP optical module; Step 4: N PCIe optical fiber data transmission modules are daisy-chained in a ring manner through a synchronization interface, and any PCIe optical fiber data transmission module is used as the initiator of the synchronization signal, and the sending end sends a preparation signal to the next level PCIe optical fiber data transmission module; Step 5: After receiving the ready signal, the next-level PCIe optical fiber data transmission module sends the ready signal to the next level together with its own ready signal; Step 6: Repeat step 5, N PCIe optical fiber data transmission modules are sequentially ANDed, and the preparation signal of the Nth level PCIe optical fiber data transmission module is sent to the initiator, and the initiator sends a synchronization signal, which is transmitted at each level to realize the synchronous transmission of the N PCIe optical fiber data transmission modules; Step 7: The optical fiber transmission system receives the upgrade file through the QSFP optical module and uses optical fiber to perform remote logic upgrade of the FPGA.

6. The optical fiber transmission method with multi-module synchronization and FPGA logic remote upgrade according to claim 5, characterized in that: Step 7 specifically includes: Step 7.1: Build a logic upgrade system by instantiating the FPGA internal core; Step 7.2: The QSFP optical module receives the bin file that needs to be burned into the FLASH chip and writes it into a specific storage area in the DDR cache; Step 7.3: Use the Multiboot function to perform online upgrade in combination with the stored bin file.

7. The optical fiber transmission method with multi-module synchronization and FPGA logic remote upgrade according to claim 6, characterized in that: Step 7.3 specifically includes: Download the golden image and update image as initialization images to the FLASH chip, where the storage address of the golden image is between 0x00000000 and 0x01FFFFFF, and the update image storage start address is 0x02000000. The host computer sends an update instruction through the PCIe write register method to erase the update image area of ​​the FLASH chip and write the bin file cached in the DDR cache to the update image area. After the burning is completed, the completion signal is returned to the host computer through the register. After the PCIe optical fiber data transmission module is powered off and then powered on again, the updated program can be run.

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