High-gain active pixel circuit and image sensor

Abstract

The invention discloses a high-gain active pixel circuit and an image sensor, relates to the technical field of electronic circuits, and is used for reducing the time required by the pixel circuit to complete exposure of a frame of image. The high-gain active pixel circuit comprises a photosensitive circuit, a feedback circuit and an amplifying circuit, wherein a first end of the photosensitive circuit is coupled to a grounding end, and the photosensitive circuit is configured to generate an exposure current according to the intensity of received illumination; the first end of the feedback circuit is coupled to the second end of the photosensitive circuit, and the feedback circuit is configured to input exposure current and clamp the voltage at the second end of the photosensitive circuit; the output end of the amplification circuit is coupled to the second end of the feedback circuit, the input end of the amplification circuit is coupled to the second end of the photosensitive circuit, and the amplification circuit is configured to clamp the voltage at the second end of the photosensitive circuit to a preset voltage through the feedback circuit.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technologies, and particularly to a high-gain active pixel circuit and an image sensor. Background Art

[0002] An image sensor consists of multiple pixel circuits. Each pixel circuit converts an incident optical signal into an electrical signal through photoelectric conversion to generate image information.

[0003] However, the pixel circuits in related technologies require a long time to complete photoelectric conversion, resulting in difficulty in achieving high-speed image acquisition and limiting the improvement of the frame rate of the image sensor. Summary of the Invention

[0004] This application provides a high-gain active pixel circuit and an image sensor, which are used to reduce the duration required for the pixel circuit to complete the exposure of one frame of an image and improve the frame rate of the image sensor.

[0005] To achieve the above object, this application adopts the following technical solutions: In a first aspect, a high-gain active pixel circuit is provided. The high-gain active pixel circuit includes: a photosensitive circuit, a feedback circuit, and an amplification circuit. Among them, the first end of the photosensitive circuit is coupled to the ground terminal. The photosensitive circuit is configured to: generate an exposure current according to the intensity of the received light. The first end of the feedback circuit is coupled to the second end of the photosensitive circuit. The feedback circuit is configured to: input the exposure current and clamp the voltage at the second end of the photosensitive circuit. The output end of the amplification circuit is coupled to the second end of the feedback circuit, and the input end of the amplification circuit is coupled to the second end of the photosensitive circuit. The amplification circuit is configured to: clamp the voltage at the second end of the photosensitive circuit to a preset voltage through the feedback circuit. Among them, the feedback circuit includes: a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first end of the first capacitor serves as the first end of the feedback circuit. The first end of the second capacitor is coupled to the second end of the first capacitor, and the second end of the second capacitor serves as the second end of the feedback circuit. The first end of the third capacitor is coupled to the second end of the first capacitor, and the second end of the third capacitor is coupled to the ground terminal. The first end of the fourth capacitor is coupled to the second end of the first capacitor, and the second end of the fourth capacitor is used to be coupled to a voltage regulation circuit and is configured to: receive an applied voltage to make the second end of the fourth capacitor at a corresponding potential.

[0006] In this embodiment, on the one hand, the pixel circuit precisely clamps the voltage at the second end of the photosensitive circuit to a preset voltage value through the feedback mechanism of the amplifier circuit, forcing the photosensitive circuit to quickly discharge through the feedback circuit, thereby realizing the regulation of the exposure time. Thus, by setting the feedback circuit, the exposure period of a single-frame image is shortened, the overall exposure time of the image sensor is effectively reduced, and the frame rate performance is improved. On the other hand, the feedback circuit adopts a multi-capacitor coupling structure (the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor). The fourth capacitor receives the external voltage applied by the voltage regulation circuit to dynamically adjust the potential of the feedback node (the second end of the first capacitor), thereby realizing the precise control of the discharge characteristics of the photosensitive circuit. At the same time, the voltage regulation circuit realizes a large control range through the injection mechanism of the fourth capacitor, thereby greatly improving the dynamic range of the pixel.

[0007] In a possible implementation, the capacitance values of the first capacitor, the second capacitor, and the fourth capacitor are a first capacitance value, and the capacitance value of the third capacitor is a second capacitance value, and the second capacitance value is greater than the first capacitance value.

[0008] In this embodiment, through the differential capacitor configuration of the feedback circuit, the small-capacitance first capacitor and second capacitor ensure the fast response of the signal, improving the bandwidth and regulation accuracy of the feedback circuit; the large-capacitance third capacitor provides a low-impedance grounding path, significantly absorbing node noise and improving signal integrity; the small-capacitance design of the fourth capacitor allows the voltage regulation circuit to inject control signals with higher efficiency, and together with the voltage stabilization effect of the large-capacitance third capacitor, realizes the exposure regulation with a wide dynamic range.

[0009] In a possible implementation, the high-gain active pixel circuit further includes: a first branch and a first switch; the first branch is coupled between the second end of the photosensitive circuit and the output end of the amplifier circuit; the first switch is disposed on the first branch, and the first switch is configured to: be in a closed state between a first time point and a second time point, and reset the amplifier circuit and the photosensitive circuit through the first branch. The first time point is the starting moment when the high-gain active pixel circuit works, and the second time point is the end moment when the amplifier circuit and the photosensitive circuit are reset.

[0010] In this embodiment, by adding a first branch and a first switch to the pixel circuit, the first switch is closed within the first time point to the second time point, and the amplifier circuit and the photosensitive circuit are quickly reset through the first branch, effectively clearing the residual charges of the photosensitive circuit and the amplifier circuit, ensuring the consistency of the circuit state before each exposure, and improving the signal accuracy.

[0011] In a possible implementation, the high-gain active pixel circuit further includes: a reset sampling circuit, a second branch, and a second switch; a first end of the reset sampling circuit is coupled to an output end of the amplifying circuit, and a second end of the reset sampling circuit is coupled to a ground end; the reset sampling circuit is configured to: store voltage information input by the amplifying circuit; the second branch is coupled between the first end of the reset sampling circuit and the output end of the amplifying circuit; the second switch is disposed on the second branch, and the second switch is configured to: be in a closed state between a first time point and a second time point, and the amplifying circuit resets the reset sampling circuit through the second branch; the second switch is further configured to: until the change amount of the output voltage of the amplifying circuit is within a first preset range from the closed state to a third time point, disconnect the second switch; the third time point is the moment when the second switch switches from the closed state to the open state.

[0012] In this embodiment, the pixel circuit realizes more accurate reset control and signal sampling through the collaborative design of the reset sampling circuit in combination with the second branch and the second switch. The second switch is closed between the first time point and the second time point, so that the amplifying circuit resets the reset sampling circuit and stores the reference voltage information. In addition, by judging the change amount of the output voltage of the amplifying circuit (disconnecting the switch when it reaches the first preset range at the third time point), it not only ensures sufficient reset but also avoids over-discharge, significantly reducing the reset noise and offset voltage.

[0013] In a possible implementation, the reset sampling circuit includes: a reset sampling capacitor, a first end of the reset sampling capacitor serves as the first end of the reset sampling circuit, and a second end of the reset sampling capacitor serves as the second end of the reset sampling circuit.

[0014] In this embodiment, the pixel circuit uses the reset sampling capacitor as the core component of the reset sampling circuit. Through its structure with the first end connected to the output end of the amplifying circuit and the second end grounded, it realizes the function of efficiently and reliably storing the reset voltage. The reset sampling capacitor can accurately store the reference voltage information of the amplifying circuit during the reset stage and maintain the stability of the reference potential during the signal readout stage, thereby effectively eliminating the influence of reset noise and circuit offset voltage.

[0015] In a possible implementation, light is generated by a light source at a fourth time point and the light illumination stops until a fifth time point; the fourth time point is the starting moment of the operation of the light source, and the fifth time point is the ending moment of the operation of the light source; wherein, the fourth time point occurs after the third time point.

[0016] In this embodiment, the pixel circuit precisely controls the illumination timing (from the fourth time point to the fifth time point), ensuring that illumination starts only after the reset sampling is completed (after the third time point), enabling the photosensitive circuit to perform exposure under stable initial conditions. This timing design effectively isolates the reset process from the optical signal acquisition stage, avoiding reset noise interference during the exposure process and ensuring the accuracy of signal sampling during exposure.

[0017] In a possible implementation, the high-gain active pixel circuit further includes: an exposure sampling circuit, a third branch, and a third switch; the first end of the exposure sampling circuit is coupled to the output end of the amplification circuit, and the second end of the exposure sampling circuit is coupled to the ground terminal; the exposure sampling circuit is configured to: store the voltage information input by the amplification circuit; the third branch is coupled between the first end of the exposure sampling circuit and the output end of the amplification circuit; the third switch is disposed on the third branch, and the third switch is configured to: be in a closed state between the first time point and the second time point, and the amplification circuit resets the exposure sampling circuit through the third branch; the third switch is further configured to: until the change amount of the output voltage of the amplification circuit is within a second preset range from the closed state to the sixth time point, the third switch is turned off; the sixth time point is the moment when the third switch switches from the closed state to the open state; wherein, the sixth time point occurs after the fifth time point, and the voltage in the second preset range is greater than the voltage in the first preset range.

[0018] In this embodiment, the pixel circuit realizes high-precision acquisition and processing of optical signals by introducing an exposure sampling circuit, a third branch, and a third switch. The third switch is closed between the first time point and the second time point, enabling the amplification circuit to reset the exposure sampling circuit; then, at the sixth time point (after the illumination ends), the third switch is turned off according to the change amount of the output voltage, ensuring complete recording of the signal change generated by the illumination. By separating the voltage ranges of reset sampling and exposure sampling (the second preset range > the first preset range), the reset noise and the real optical signal are effectively distinguished, significantly improving the signal-to-noise ratio; at the same time, the illumination timing is strictly matched (sampling continues until the sixth time point after the illumination ends), completely capturing the voltage change during the exposure and avoiding signal omission.

[0019] In a possible implementation, the exposure sampling circuit includes: an exposure sampling capacitor, the first end of the exposure sampling capacitor serves as the first end of the exposure sampling circuit, and the second end of the exposure sampling capacitor serves as the second end of the exposure sampling circuit.

[0020] In this embodiment, the pixel circuit uses an exposure sampling capacitor as the core component of the exposure sampling circuit. Through the structure where its first end is connected to the output end of the amplification circuit and its second end is grounded, a high-precision optical signal acquisition function is achieved. The exposure sampling capacitor can accurately record the voltage change generated by the optical signal during the exposure stage and maintain signal integrity during the readout stage. Its collaborative work with the reset sampling capacitor realizes double sampling of reset and exposure. In addition, by strictly controlling the sampling period of the exposure sampling capacitor after the end of illumination (the sixth time point), all photo-generated charges are ensured to be completely captured.

[0021] In a possible implementation, starting from the fourth time point, the voltage at the second end of the fourth capacitor rises from the first voltage to the second voltage until starting from the seventh time point, the voltage at the second end of the fourth capacitor drops from the second voltage to the first voltage; the seventh time point is the moment when the voltage at the second end of the fourth capacitor starts to drop; wherein, the seventh time point occurs after the sixth time point.

[0022] In this embodiment, the pixel circuit realizes dynamic optimization control of the photosensitive circuit by precisely controlling the voltage modulation timing of the fourth capacitor (from the fourth time point to the seventh time point). During the exposure stage (starting from the fourth time point), the voltage of the fourth capacitor is increased from the first voltage to the second voltage to enhance the charge collection efficiency of the photosensitive circuit; after the end of the signal readout stage (the seventh time point, that is, after the sixth time point), the voltage is restored to the first voltage to prepare for the next exposure. This voltage modulation with timing matching, on the one hand, the high voltage (the second voltage) during exposure can expand the full well capacity of the photosensitive node and improve the pixel dynamic range; on the other hand, the voltage rise and fall are strictly synchronized with the exposure / readout timing to avoid signal interference; on the other hand, through capacitive coupling, a potential adjustment without DC power consumption is achieved, maintaining low power consumption characteristics while improving performance.

[0023] In a possible implementation, after the seventh time point, exposure information is obtained according to the voltage information stored in the exposure sampling circuit and the voltage information stored in the reset sampling circuit.

[0024] In this embodiment, the pixel circuit realizes high-precision optoelectronic signal extraction by comparing the voltage information stored in the exposure sampling capacitor and the reset sampling capacitor after the seventh time point.

[0025] In a possible implementation, the photosensitive circuit includes: a photosensitive diode, the anode of the photosensitive diode is used as the first end of the photosensitive circuit, and the cathode of the photosensitive diode is used as the second end of the photosensitive circuit.

[0026] In this embodiment, the pixel circuit uses a photosensitive diode as the core component of the photosensitive circuit. Through the simple structure of grounding its anode and connecting the cathode to the feedback circuit, an efficient photoelectric conversion function is achieved. Among them, the structure with the cathode as the signal output terminal is naturally adapted to the subsequent feedback control loop, facilitating the implementation of voltage clamping and rapid reset.

[0027] In a possible implementation, the amplifier circuit includes: a first P-type metal-oxide-semiconductor transistor and a first N-type metal-oxide-semiconductor transistor; wherein, the drain of the first P-type metal-oxide-semiconductor transistor is coupled to the power supply terminal; the drain of the first N-type metal-oxide-semiconductor transistor serves as the output terminal of the amplifier circuit and is coupled to the source of the first P-type metal-oxide-semiconductor transistor; the source of the first N-type metal-oxide-semiconductor transistor is coupled to the ground terminal, and the gate of the first N-type metal-oxide-semiconductor transistor serves as the input terminal of the amplifier circuit.

[0028] In this embodiment, the pixel circuit uses a first P-type metal-oxide-semiconductor transistor and a first N-type metal-oxide-semiconductor transistor to form a common-source amplifier circuit. Through the simple two-transistor design with the first P-type metal-oxide-semiconductor transistor as the active load and the first N-type metal-oxide-semiconductor transistor forming the common-source amplifier circuit, a high-performance signal amplification function is achieved. In addition, the high-impedance characteristic of the gate input of the first N-type metal-oxide-semiconductor transistor ensures no interference with the photocurrent, and the push-pull output structure provides fast signal transmission ability. At the same time, the compact design with only 2 transistors saves layout area and supports the integration of high-density pixel arrays.

[0029] In a possible implementation, the amplifier circuit includes: a second P-type metal-oxide-semiconductor transistor, a third P-type metal-oxide-semiconductor transistor, a second N-type metal-oxide-semiconductor transistor, and a third N-type metal-oxide-semiconductor transistor; wherein, the drain of the second P-type metal-oxide-semiconductor transistor is coupled to the power supply terminal; the drain of the third P-type metal-oxide-semiconductor transistor is coupled to the source of the second P-type metal-oxide-semiconductor transistor; the drain of the second N-type metal-oxide-semiconductor transistor serves as the output terminal of the amplifier circuit and is coupled to the source of the third P-type metal-oxide-semiconductor transistor; the drain of the third N-type metal-oxide-semiconductor transistor is coupled to the source of the second N-type metal-oxide-semiconductor transistor; the source of the third N-type metal-oxide-semiconductor transistor is coupled to the ground terminal; the gate of the third N-type metal-oxide-semiconductor transistor serves as the input terminal of the amplifier circuit.

[0030] In this embodiment, the pixel circuit adopts a cascode amplifier circuit composed of two pairs of P-type metal-oxide-semiconductor transistors and N-type metal-oxide-semiconductor transistors, and realizes a high-performance signal amplification function through the collaborative work of four-stage transistors. The second P-type metal-oxide-semiconductor transistor and the third P-type metal-oxide-semiconductor transistor constitute an active load stage, which cooperates with the cascode amplification stage formed by the second N-type metal-oxide-semiconductor transistor and the third N-type metal-oxide-semiconductor transistor. While maintaining ultra-high gain, the bandwidth is extended through the isolation effect of the cascode structure. In addition, the current buffering effect of the cascode stage reduces the input noise and significantly improves the signal-to-noise ratio in low-light environments. At the same time, the high-impedance characteristic of the gate input of the third N-type metal-oxide-semiconductor transistor ensures no interference with the optical signal, and the multi-stage negative feedback structure controls the temperature drift within a small range.

[0031] In a second aspect, an image sensor is provided, which includes: a light source; a pixel array including a plurality of high-gain active pixel circuits as in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of a pixel circuit provided by an embodiment of the present application Figure 1 ; Figure 2 Schematic diagram of a pixel circuit provided by an embodiment of the present application Figure 2 ; Figure 3 Schematic diagram of the working timing of a pixel circuit provided by an embodiment of the present application; Figure 4 Schematic diagram of a high-gain active pixel circuit provided by an embodiment of the present application Figure 1 ; Figure 5 Schematic diagram of a high-gain active pixel circuit provided by an embodiment of the present application Figure 2 ; Figure 6 Schematic diagram of a high-gain active pixel circuit provided by an embodiment of the present application Figure 3 ; Figure 7 Schematic diagram of the working timing of a high-gain active pixel circuit provided by an embodiment of the present application.

[0033] Reference numerals: In the figure, PD1 is the first photosensitive diode, 101 is the first parasitic capacitance, 201 is the photosensitive circuit, 202 is the amplification circuit, 203 is the amplifier feedback capacitance, 204 is the amplifier reset switch, 205 is the reset sampling switch, 206 is the exposure sampling switch, 207 is the reset sampling circuit, 2071 is the reset sampling capacitance, 208 is the exposure sampling circuit, 2081 is the exposure sampling capacitance, 209 is the output circuit, PD2 is the second photosensitive diode, 2011 is the second parasitic capacitance, 401 is the feedback circuit, 402 is the first switch, 403 is the second switch, 404 is the third switch, C1 is the first capacitor, C2 is the second capacitor, C3 is the third capacitor, C4 is the fourth capacitor, MP1 is the first P-type metal-oxide-semiconductor transistor, MN1 is the first N-type metal-oxide-semiconductor transistor, MP2 is the second P-type metal-oxide-semiconductor transistor, MP3 is the third P-type metal-oxide-semiconductor transistor, MN2 is the second N-type metal-oxide-semiconductor transistor, MN3 is the third N-type metal-oxide-semiconductor transistor, MP4 is the fourth P-type metal-oxide-semiconductor transistor, MP5 is the fifth P-type metal-oxide-semiconductor transistor, MN4 is the fourth N-type metal-oxide-semiconductor transistor, MN5 is the fifth N-type metal-oxide-semiconductor transistor, MN6 is the sixth N-type metal-oxide-semiconductor transistor, MN7 is the seventh N-type metal-oxide-semiconductor transistor, MN8 is the eighth N-type metal-oxide-semiconductor transistor, MN9 is the ninth N-type metal-oxide-semiconductor transistor, MN10 is the tenth N-type metal-oxide-semiconductor transistor, 501 is the first terminal, 502 is the second terminal, C5 is the fifth capacitor, C6 is the sixth capacitor, C7 is the seventh capacitor, C8 is the eighth capacitor, C9 is the ninth capacitor, C10 is the tenth capacitor. Detailed implementation manners

[0034] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0035] In the description of the present application, unless otherwise specified, " / " means "or". For example, A / B may represent A or B. Herein, "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, "at least one" and "a plurality of" refer to two or more. The words such as "first" and "second" do not limit the quantity and execution order, and the words such as "first" and "second" do not necessarily limit to be different.

[0036] Image sensors are widely used in fields such as photography, video surveillance, medical imaging, and industrial inspection. An image sensor is composed of multiple pixel circuits, such as including but not limited to 3T pixel circuits and 4T pixel circuits, etc.

[0037] As Figure 1 shown, in the 3T pixel circuit, the anode of the first photodiode (PD) PD1 is coupled to the ground terminal, the cathode of the first photodiode PD1 is coupled to the first end of the first parasitic capacitor 101, and the second end of the first parasitic capacitor 101 is coupled to the ground terminal. The base of the first photodiode PD1 is also coupled to the drain of the eighth N-type metal oxide semiconductor transistor MN8, and the base of the first photodiode PD1 is also coupled to the gate of the ninth N-type metal oxide semiconductor transistor MN9. Moreover, the first end of the first parasitic capacitor 101 is also coupled to the drain of the eighth N-type metal oxide semiconductor transistor MN8, and the first end of the first parasitic capacitor 101 is also coupled to the gate of the ninth N-type metal oxide semiconductor transistor MN9. The gate of the eighth N-type metal oxide semiconductor transistor MN8 is used to receive a reset signal, and the source of the eighth N-type metal oxide semiconductor transistor MN8 is coupled to the power supply terminal. The source of the ninth N-type metal oxide semiconductor transistor MN9 is coupled to the power supply terminal, and the drain of the ninth N-type metal oxide semiconductor transistor MN9 is coupled to the source of the tenth N-type metal oxide semiconductor transistor MN10. The gate of the tenth N-type metal oxide semiconductor transistor MN10 is used to receive a row selection signal, and the drain of the tenth N-type metal oxide semiconductor transistor MN10 is the output terminal.

[0038] In the 3T pixel circuit, due to the pixel photosensitive current output by the first photodiode PD1, it is necessary to discharge the first parasitic capacitor 101 in the pixel photosensitive area to obtain an exposure signal. However, the capacitance value of the first parasitic capacitor 101 is affected by the size of the pixel photosensitive area. When the capacitance value of the first parasitic capacitor 101 is relatively large (for example, 50fF+), it will cause the 3T pixel circuit to require a longer exposure time. Therefore, the current pixel circuit takes a longer time to complete the exposure of one frame of the image, resulting in a lower frame rate of the image sensor.

[0039] To solve the problem of too long exposure time in the 3T pixel circuit, the present disclosure provides an implementation manner, as Figure 2 shown, the pixel circuit includes: a photosensitive circuit 201, an amplifying circuit 202, an amplifier feedback capacitor 203, an amplifier reset switch 204, a reset sampling switch 205, an exposure sampling switch 206, a reset sampling circuit 207, an exposure sampling circuit 208, and an output circuit 209. The reset sampling circuit 207 and the exposure sampling circuit 208 constitute a dual-sampling circuit.

[0040] Among them, the photosensitive circuit 201 includes: a second photosensitive diode PD2 and a second parasitic capacitor 2011. The anode of the second photosensitive diode PD2 is coupled to the ground terminal, the cathode of the second photosensitive diode PD2 is coupled to the first terminal of the second parasitic capacitor 2011, and the second terminal of the second parasitic capacitor 2011 is coupled to the ground terminal.

[0041] The amplifier circuit 202 can be a cascode amplifier, including: a second P-type metal oxide semiconductor transistor MP2, a third P-type metal oxide semiconductor transistor MP3, a second N-type metal oxide semiconductor transistor MN2, and a third N-type metal oxide semiconductor transistor MN3. The drain of the second P-type metal oxide semiconductor transistor MP2 is coupled to the power supply terminal, and the gate of the second P-type metal oxide semiconductor transistor MP2 is used to receive a bias signal. The drain of the third P-type metal oxide semiconductor transistor MP3 is coupled to the source of the second P-type metal oxide semiconductor transistor MP2, and the gate of the third P-type metal oxide semiconductor transistor MP3 is used to receive a bias signal. The drain of the second N-type metal oxide semiconductor transistor MN2 is coupled to the source of the third P-type metal oxide semiconductor transistor MP3, and the gate of the second N-type metal oxide semiconductor transistor MN2 is used to receive a bias signal. The drain of the third N-type metal oxide semiconductor transistor MN3 is coupled to the source of the second N-type metal oxide semiconductor transistor MN2, the gate of the third N-type metal oxide semiconductor transistor MN3 is coupled to the cathode of the second photosensitive diode PD2 and the first terminal of the second parasitic capacitor 2011, and the source of the third N-type metal oxide semiconductor transistor MN3 is coupled to the ground terminal.

[0042] The first terminal of the amplifier feedback capacitor 203 is coupled to the cathode of the second photosensitive diode PD2 and the first terminal of the second parasitic capacitor 2011, and the second terminal of the amplifier feedback capacitor 203 is coupled to the drain of the second N-type metal oxide semiconductor transistor MN2 and the source of the third P-type metal oxide semiconductor transistor MP3.

[0043] The first terminal of the amplifier reset switch 204 is coupled to the cathode of the second photosensitive diode PD2 and the first terminal of the second parasitic capacitor 2011, and the second terminal of the amplifier reset switch 204 is coupled to the drain of the second N-type metal oxide semiconductor transistor MN2 and the source of the third P-type metal oxide semiconductor transistor MP3.

[0044] The first terminal of the reset sampling switch 205 is coupled to the drain of the second N-type metal oxide semiconductor transistor MN2 and the source of the third P-type metal oxide semiconductor transistor MP3.

[0045] The first terminal of the exposure sampling switch 206 is coupled to the drain of the second N-type metal oxide semiconductor transistor MN2 and the source of the third P-type metal oxide semiconductor transistor MP3.

[0046] The reset sampling circuit 207 includes: a fourth P-type metal oxide semiconductor transistor MP4 and a reset sampling capacitor 2071. The drain of the fourth P-type metal oxide semiconductor transistor MP4 is coupled to the power supply terminal, the source of the fourth P-type metal oxide semiconductor transistor MP4 is coupled to the first terminal of the reset sampling capacitor 2071 and the second terminal of the reset sampling switch 205, and the second terminal of the reset sampling capacitor 2071 is coupled to the ground terminal.

[0047] The exposure sampling circuit 208 includes: a fifth P-type metal oxide semiconductor transistor MP5 and an exposure sampling capacitor 2081. The drain of the fifth P-type metal oxide semiconductor transistor MP5 is coupled to the power supply terminal, the source of the fifth P-type metal oxide semiconductor transistor MP5 is coupled to the first terminal of the exposure sampling capacitor 2081 and the second terminal of the exposure sampling switch 206, and the second terminal of the exposure sampling capacitor 2081 is coupled to the ground terminal.

[0048] The gate of the fifth P-type metal oxide semiconductor transistor MP5 is coupled to the gate of the fourth P-type metal oxide semiconductor transistor MP4.

[0049] The output circuit 209 includes: a fourth N-type metal oxide semiconductor transistor MN4, a fifth N-type metal oxide semiconductor transistor MN5, a sixth N-type metal oxide semiconductor transistor MN6, and a seventh N-type metal oxide semiconductor transistor MN7. The drain of the fourth N-type metal oxide semiconductor transistor MN4 is coupled to the power supply terminal, the gate of the fourth N-type metal oxide semiconductor transistor MN4 is coupled to the source of the fourth P-type metal oxide semiconductor transistor MP4, the first terminal of the reset sampling capacitor 2071, and the second terminal of the reset sampling switch 205. The source of the fourth N-type metal oxide semiconductor transistor MN4 is coupled to the drain of the fifth N-type metal oxide semiconductor transistor MN5, the gate of the fifth N-type metal oxide semiconductor transistor MN5 is used to receive a row selection signal, and the source of the fifth N-type metal oxide semiconductor transistor MN5 is coupled to the negative output terminal. The drain of the sixth N-type metal oxide semiconductor transistor MN6 is coupled to the power supply terminal, the gate of the sixth N-type metal oxide semiconductor transistor MN6 is coupled to the source of the fifth P-type metal oxide semiconductor transistor MP5, the first terminal of the exposure sampling capacitor 2081, and the second terminal of the exposure sampling switch 206. The source of the sixth N-type metal oxide semiconductor transistor MN6 is coupled to the drain of the seventh N-type metal oxide semiconductor transistor MN7, the gate of the seventh N-type metal oxide semiconductor transistor MN7 is used to receive a row selection signal, and the source of the seventh N-type metal oxide semiconductor transistor MN7 is coupled to the positive output terminal.

[0050] It should be noted that Figure 2 In the pixel circuit shown, an amplifier circuit 202 is introduced between the photosensitive circuit 201 and the output circuit 209. The amplifier circuit 202 can clamp the potential of the photosensitive area, and adjust the discharge of the parasitic capacitance by the pixel photosensitive current in the original 3T pixel circuit to the discharge of the amplifier feedback capacitance 203. Since the amplifier feedback capacitance 203 is artificially added, the amplifier feedback capacitance 203 can be designed to have a very small capacitance value, thereby greatly reducing the exposure time.

[0051] Combined with Figure 2 the pixel circuit shown, as Figure 3 shown, at the first moment t1, the amplifier reset switch 204, the reset sampling switch 205, and the exposure sampling switch 206 are simultaneously closed, so that the amplifier circuit 202 is in a reset state. At the second moment t2, the amplifier reset switch 204 is opened to end the reset state of the amplifier circuit 202. After waiting for the output of the amplifier circuit 202 to stabilize, at the third moment t3, the reset sampling switch 205 is opened, and the reset voltage of the amplifier circuit 202 and the influence voltage introduced by the amplifier reset switch 204 are stored in the reset sampling capacitor 2071. Subsequently, at the fourth moment t4, a light-emitting diode (LED) is lit, and the LED is turned off at the fifth moment t5 after being exposed for a period of time. After waiting for the amplifier circuit 202 to stabilize, at the sixth moment t6, the exposure sampling switch 206 is opened, and the exposure result (exposure voltage) is stored in the exposure sampling capacitor 2081.

[0052] In this way, after all the pixels in the pixel matrix perform the above operations synchronously, the reset voltage and the exposure voltage of the pixels will be stored in the corresponding capacitors. Subsequently, the voltages stored in the two capacitors can be read out sequentially or synchronously, and the difference between the two voltages (i.e., the reset voltage and the exposure voltage) is calculated to obtain the actual pixel exposure value.

[0053] However, for Figure 2 the pixel circuit shown, since the capacitance value of the amplifier feedback capacitance 203 needs to be small enough to obtain a high enough pixel gain. However, due to the large matrix characteristic of the image sensor, the distances between the pixel circuits at different positions are relatively far, resulting in certain differences in the amplifier feedback capacitances 203 in different pixel circuits. This difference will cause gain mismatch between pixels. The smaller the capacitance value of the amplifier feedback capacitance 203, the greater the gain mismatch between pixels. Therefore, Figure 2 the pixel circuit shown is difficult to be applied in a large matrix and high-sensitivity image sensor.

[0054] Based on this, the embodiments of the present application provide a high-gain active pixel circuit. The high-gain active pixel circuit accurately clamps the voltage at the second end of the photosensitive circuit to a preset voltage value through the feedback mechanism of the amplification circuit, forcing the photosensitive circuit to quickly discharge through the feedback circuit, thereby realizing the regulation of the exposure time. Thus, the exposure cycle of a single-frame image can be shortened by setting the feedback circuit, effectively reducing the overall exposure time of the image sensor, and further improving the frame rate performance.

[0055] The high-gain active pixel circuit provided by the embodiments of the present application is introduced below in conjunction with the accompanying drawings. The high-gain active pixel circuit provided by the embodiments of the present application is applicable to the pixel array in the image sensor and can be used to extract image data. In the embodiments of the present application, the image sensor can be applicable to photographic equipment, video surveillance equipment, medical imaging equipment, industrial inspection equipment, optical mice, etc., and the present application does not make specific limitations on this.

[0056] As Figure 4 shown, it is a schematic diagram of a high-gain active pixel circuit provided by the embodiments of the present application. The high-gain active pixel circuit includes: a photosensitive circuit 201, an amplification circuit 202, a feedback circuit 401, a first switch 402, a second switch 403, a third switch 404, a reset sampling circuit 207, an exposure sampling circuit 208, and an output circuit 209. The reset sampling circuit 207 and the exposure sampling circuit 208 constitute a dual-sampling circuit.

[0057] Among them, the first end of the photosensitive circuit 201 is coupled to the ground terminal, and the photosensitive circuit 201 is configured to generate an exposure current according to the intensity of the received light.

[0058] In the embodiments of the present application, the photosensitive circuit 201 includes: a second photosensitive diode PD2 and a second parasitic capacitor 2011. The anode of the second photosensitive diode PD2 serves as the first end of the photosensitive circuit 201, and the cathode of the second photosensitive diode PD2 serves as the second end of the photosensitive circuit 201.

[0059] That is, the anode of the second photosensitive diode PD2 is coupled to the ground terminal, the cathode of the second photosensitive diode PD2 is coupled to the first end of the second parasitic capacitor 2011, and the second end of the second parasitic capacitor 2011 is coupled to the ground terminal.

[0060] In this embodiment, the pixel circuit uses a photosensitive diode as the core component of the photosensitive circuit. Through the simple structure of grounding its anode and connecting the cathode to the feedback circuit, an efficient photoelectric conversion function is realized. Among them, the structure with the cathode as the signal output terminal is naturally adapted to the subsequent feedback control loop, facilitating voltage clamping and rapid reset.

[0061] The first end of the feedback circuit 401 is coupled to the second end of the photosensitive circuit 201 , and the feedback circuit 401 is configured to input an exposure current and clamp the voltage at the second end of the photosensitive circuit 201 .

[0062] That is, the first terminal of the feedback circuit 401 is coupled to the cathode of the second photodiode PD2 and the first terminal of the second parasitic capacitor 2011 .

[0063] In the embodiment of the present application, the feedback circuit 401 includes: a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. Among them, the first end of the first capacitor C1 serves as the first end of the feedback circuit 401; the first end of the second capacitor C2 is coupled to the second end of the first capacitor C1, and the second end of the second capacitor C2 serves as the second end of the feedback circuit 401; the first end of the third capacitor C3 is coupled to the second end of the first capacitor C1, and the second end of the third capacitor C3 is coupled to the ground end; the first end of the fourth capacitor C4 is coupled to the second end of the first capacitor C1, and the second end of the fourth capacitor C4 is used to couple the voltage regulation circuit, and the fourth capacitor C4 is configured to: receive an applied voltage so that the second end of the fourth capacitor C4 is at a corresponding potential.

[0064] That is, the first end of the first capacitor C1 is coupled to the cathode of the second photodiode PD2 and the first end of the second parasitic capacitor 2011, the first end of the third capacitor C3 is coupled to the first end of the second capacitor C2, and the first end of the fourth capacitor C4 is coupled to the first end of the second capacitor C2.

[0065] In this embodiment, the feedback circuit adopts a multi-capacitor coupling structure (first capacitor, second capacitor, third capacitor and fourth capacitor), receives the external voltage applied by the voltage regulation circuit through the fourth capacitor, and dynamically adjusts the potential of the feedback node (the second end of the first capacitor), thereby realizing precise control of the discharge characteristics of the photosensitive circuit. At the same time, the voltage regulation circuit realizes a large control range through the injection mechanism of the fourth capacitor, thereby greatly improving the dynamic range of the pixel.

[0066] In the embodiment of the present application, the capacitances of the first capacitor C1 , the second capacitor C2 , and the fourth capacitor C4 are the first capacitance, the capacitance of the third capacitor C3 is the second capacitance, and the second capacitance is greater than the first capacitance.

[0067] In this embodiment, the feedback circuit uses differentiated capacitor configurations. The small-capacitance first and second capacitors ensure rapid signal response and improve the bandwidth and adjustment accuracy of the feedback circuit. The large-capacitance third capacitor provides a low-impedance grounding path, significantly absorbs node noise, and improves signal integrity. The small-capacitance design of the fourth capacitor allows the voltage regulation circuit to inject control signals with higher efficiency, and cooperates with the voltage stabilizing effect of the large-capacitance third capacitor to achieve exposure adjustment over a wide dynamic range.

[0068] In the embodiments of the present application, as Figure 5 shown, it is an equivalent diagram of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 from the star connection mode to the delta connection mode. Among them, the first terminal 501 is the output terminal of the amplifier circuit 202, and the second terminal 502 is the second terminal of the photosensitive circuit 201.

[0069] The fifth capacitor C5 is the equivalent capacitor between the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2. The sixth capacitor C6 is the equivalent capacitor between the second terminal of the first capacitor C1 and the first terminal of the third capacitor C3. The seventh capacitor C7 is the equivalent capacitor between the second terminal of the first capacitor C1 and the first terminal of the fourth capacitor C4. The eighth capacitor C8 is the equivalent capacitor between the first terminal of the second capacitor C2 and the first terminal of the third capacitor C3. The ninth capacitor C9 is the equivalent capacitor between the first terminal of the second capacitor C2 and the first terminal of the fourth capacitor C4. The tenth capacitor C10 is the equivalent capacitor between the first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4.

[0070] In the embodiments of the present application, the capacitance value of the first capacitor C1 is C1, the capacitance value of the second capacitor C2 is C2, the capacitance value of the third capacitor C3 is C3, and the capacitance value of the fourth capacitor C4 is C4. Then the capacitance value of the fifth capacitor C5 is C12 = C1 × C2 ÷ (C1 + C2 + C3 + C4), the capacitance value of the sixth capacitor C6 is C13 = C1 × C3 ÷ (C1 + C2 + C3 + C4), the capacitance value of the seventh capacitor C7 is C14 = C1 × C4 ÷ (C1 + C2 + C3 + C4), the capacitance value of the eighth capacitor C8 is C23 = C2 × C3 ÷ (C1 + C2 + C3 + C4), the capacitance value of the ninth capacitor C9 is C24 = C2 × C4 ÷ (C1 + C2 + C3 + C4), and the capacitance value of the tenth capacitor C10 is C34 = C3 × C4 ÷ (C1 + C2 + C3 + C4).

[0071] In the embodiment of the present application, when C1 = C2 = C4 = C, C3 = nC (n is a constant, C is the first preset capacitance value), and the voltage regulation circuit coupled to the second terminal of the fourth capacitor C4 is always grounded, the tenth capacitor C10 is short-circuited and ineffective. The sixth capacitor C6 and the seventh capacitor C7 are the ground capacitors of the pixel, and the eighth capacitor C8 and the ninth capacitor C9 are the output ground capacitors of the amplifier circuit 202, all of which do not affect the current gain of the amplifier circuit 202. At this time, the capacitance value of the fifth capacitor C5 in the circuit is C12 = C1×C2÷(C1 + C2 + C3 + C4) = C÷(3 + n). If the capacitance value C12 of the fifth capacitor C5 is made to reach the second preset capacitance value Cf (the second preset capacitance value is less than the first preset capacitance value), then the first preset capacitance value C = (3 + n)×Cf. Therefore, as long as the capacitance value C3 of the third capacitor C3 is large enough, n is large enough, and the capacitance values C1 of the first capacitor C1, C2 of the second capacitor C2, C3 of the third capacitor C3, and C4 of the fourth capacitor C4 can equivalently achieve the effect of a small capacitor with a relatively large capacitance value. And the relatively large capacitance value can ensure the consistency between pixels, enabling the pixel matrix to have a low pixel gain mismatch, thereby achieving low noise and high sensitivity of the pixels.

[0072] The output terminal of the amplifier circuit 202 is coupled to the second terminal of the feedback circuit 401, and the input terminal of the amplifier circuit 202 is coupled to the second terminal of the photosensitive circuit 201. The amplifier circuit 202 is configured to clamp the voltage at the second terminal of the photosensitive circuit 201 to a preset voltage through the feedback circuit 401.

[0073] In this embodiment, the pixel circuit accurately clamps the voltage at the second terminal of the photosensitive circuit to a preset voltage value through the feedback mechanism of the amplifier circuit, forcing the photosensitive circuit to quickly discharge through the feedback circuit, thereby realizing the regulation of the exposure time. Thus, by setting the feedback circuit, the exposure period of a single-frame image is shortened, the overall exposure time of the image sensor is effectively reduced, and the frame rate performance is improved.

[0074] In the embodiment of the present application, the amplifier circuit 202 is a common-source amplifier, as Figure 4 shown, the amplifier circuit 202 includes: a first P-type metal oxide semiconductor transistor MP1 and a first N-type metal oxide semiconductor transistor MN1.

[0075] Among them, the drain of the first P-type metal oxide semiconductor transistor MP1 is coupled to the power supply terminal; the drain of the first N-type metal oxide semiconductor transistor MN1 serves as the output terminal of the amplifier circuit 202 and is coupled to the source of the first P-type metal oxide semiconductor transistor MP1; the source of the first N-type metal oxide semiconductor transistor MN1 is coupled to the ground terminal, and the gate of the first N-type metal oxide semiconductor transistor MN1 serves as the input terminal of the amplifier circuit 202.

[0076] That is, the source of the first P-type metal oxide semiconductor transistor MP1 is coupled to the second terminal of the second capacitor C2, and the drain of the first N-type metal oxide semiconductor transistor MN1 is coupled to the second terminal of the second capacitor C2. The gate of the first N-type metal oxide semiconductor transistor MN1 is coupled to the second terminal of the photosensitive circuit 201 (i.e., the cathode of the second photosensitive diode PD2 and the first terminal of the second parasitic capacitor 2011).

[0077] Moreover, the gate of the first P-type metal oxide semiconductor transistor MP1 is used to receive a bias signal.

[0078] In this embodiment, the pixel circuit uses the first P-type metal oxide semiconductor transistor and the first N-type metal oxide semiconductor transistor to form a common-source amplifier circuit. By using the first P-type metal oxide semiconductor transistor as an active load and the first N-type metal oxide semiconductor transistor to form a common-source amplifier circuit, with the first P-type metal oxide semiconductor transistor as an active load and the first N-type metal oxide semiconductor transistor as the input stage, a simple two-transistor design realizes a high-performance signal amplification function. In addition, the high-impedance characteristic of the gate input of the first N-type metal oxide semiconductor transistor ensures no interference with the photocurrent, and the push-pull output structure provides a fast signal transmission ability. At the same time, the compact design with only 2 transistors saves layout area and supports the integration of a high-density pixel array.

[0079] In the embodiment of the present application, the amplifier circuit 202 is a cascode amplifier, as Figure 6 shown, the amplifier circuit 202 includes: a second P-type metal oxide semiconductor transistor MP2, a third P-type metal oxide semiconductor transistor MP3, a second N-type metal oxide semiconductor transistor MN2, and a third N-type metal oxide semiconductor transistor MN3.

[0080] Among them, the drain of the second P-type metal oxide semiconductor transistor MP2 is coupled to the power supply terminal; the drain of the third P-type metal oxide semiconductor transistor MP3 is coupled to the source of the second P-type metal oxide semiconductor transistor MP2; the drain of the second N-type metal oxide semiconductor transistor MN2 serves as the output terminal of the amplifier circuit 202, and the drain of the second N-type metal oxide semiconductor transistor MN2 is coupled to the source of the third P-type metal oxide semiconductor transistor MP3; the drain of the third N-type metal oxide semiconductor transistor MN3 is coupled to the source of the second N-type metal oxide semiconductor transistor MN2; the source of the third N-type metal oxide semiconductor transistor MN3 is coupled to the ground terminal; the gate of the third N-type metal oxide semiconductor transistor MN3 serves as the input terminal of the amplifier circuit 202.

[0081] That is, the source of the third P-type metal oxide semiconductor transistor MP3 is coupled to the second terminal of the second capacitor C2, and the drain of the second N-type metal oxide semiconductor transistor MN2 is coupled to the second terminal of the second capacitor C2. The gate of the third N-type metal oxide semiconductor transistor MN3 is coupled to the second terminal of the photosensitive circuit 201 (i.e., the cathode of the second photosensitive diode PD2 and the first terminal of the second parasitic capacitor 2011).

[0082] Moreover, the gate of the second P-type metal oxide semiconductor transistor MP2 is used to receive a bias signal, and the gate of the second N-type metal oxide semiconductor transistor MN2 is used to receive a bias signal.

[0083] In this embodiment, the pixel circuit adopts a cascode amplifier circuit composed of two pairs of P-type metal oxide semiconductor transistors and N-type metal oxide semiconductor transistors, and realizes a high-performance signal amplification function through the collaborative work of four-stage transistors. The second P-type metal oxide semiconductor transistor and the third P-type metal oxide semiconductor transistor constitute an active load stage, which cooperates with the cascode amplification stage formed by the second N-type metal oxide semiconductor transistor and the third N-type metal oxide semiconductor transistor. While maintaining ultra-high gain, the bandwidth is extended through the isolation effect of the cascode structure. In addition, the current buffering effect of the cascode stage reduces the input noise and significantly improves the signal-to-noise ratio in low-light environments. At the same time, the high-impedance characteristic of the gate input of the third N-type metal oxide semiconductor transistor ensures no interference with the optical signal, and the multi-stage negative feedback structure controls the temperature drift within a small range.

[0084] In the embodiment of the present application, the high-gain active pixel circuit further includes: a first branch, and the first branch is coupled between the second terminal of the photosensitive circuit 201 and the output terminal of the amplifier circuit 202.

[0085] In the embodiment of the present application, a first switch 402 is disposed on the first branch, and the first switch 402 is configured to: be in a closed state between a first time point and a second time point, and reset the amplifier circuit 202 and the photosensitive circuit 201 through the first branch. The first time point is the starting moment when the high-gain active pixel circuit works, and the second time point is the end moment when the amplifier circuit 202 and the photosensitive circuit 201 are reset.

[0086] That is, the first terminal of the first switch 402 is coupled to the cathode of the second photosensitive diode PD2 and the first terminal of the second parasitic capacitor 2011, and the second terminal of the first switch 402 is coupled to the output terminal of the amplifier circuit 202. That is, when the amplifier circuit 202 is a common-source amplifier, the second terminal of the first switch 402 is coupled to the drain of the first N-type metal oxide semiconductor transistor MN1; when the amplifier circuit 202 is a cascode amplifier, the second terminal of the first switch 402 is coupled to the drain of the second N-type metal oxide semiconductor transistor MN2.

[0087] In this embodiment, the pixel circuit adds a first branch and a first switch. The first switch is closed from the first time point to the second time point, and the first branch is used to quickly reset the amplifier circuit and the photosensitive circuit, effectively clearing the residual charges in the photosensitive circuit and the amplifier circuit, ensuring the consistency of the circuit state before each exposure, and improving the signal accuracy.

[0088] In the embodiment of the present application, the high-gain active pixel circuit further includes: a second branch, which is coupled between the first end of the reset sampling circuit 207 and the output end of the amplifier circuit 202. The first end of the reset sampling circuit 207 is coupled to the output end of the amplifier circuit 202, and the second end of the reset sampling circuit 207 is coupled to the ground terminal; the reset sampling circuit 207 is configured to: store the voltage information input by the amplifier circuit 202.

[0089] In the embodiment of the present application, a second switch 403 is provided on the second branch. The second switch 403 is configured to: be in a closed state between the first time point and the second time point, and the amplifier circuit 202 resets the reset sampling circuit 207 through the second branch; the second switch 403 is further configured to: until the change amount of the output voltage of the amplifier circuit 202 is within a first preset range from the closed state to the third time point, disconnect the second switch 403; the third time point is the moment when the second switch 403 switches from the closed state to the open state.

[0090] The first end of the second switch 403 is coupled to the output end of the amplifier circuit 202. That is, when the amplifier circuit 202 is a common-source amplifier, the first end of the second switch 403 is coupled to the drain of the first N-type metal oxide semiconductor transistor MN1; when the amplifier circuit 202 is a cascode amplifier, the first end of the second switch 403 is coupled to the drain of the second N-type metal oxide semiconductor transistor MN2.

[0091] In this embodiment, through the collaborative design of the reset sampling circuit, the second branch, and the second switch, the pixel circuit realizes more accurate reset control and signal sampling. The second switch is closed between the first time point and the second time point, so that the amplifier circuit resets the reset sampling circuit and stores the reference voltage information. In addition, by judging the change amount of the output voltage of the amplifier circuit (disconnecting the switch when it reaches the first preset range at the third time point), it not only ensures sufficient reset but also avoids over-discharge, significantly reducing the reset noise and offset voltage.

[0092] In the embodiment of the present application, the reset sampling circuit 207 includes: a fourth P-type metal oxide semiconductor transistor MP4 and a reset sampling capacitor 2071. The first end of the reset sampling capacitor 2071 is used as the first end of the reset sampling circuit 207, and the second end of the reset sampling capacitor 2071 is used as the second end of the reset sampling circuit 207.

[0093] The drain of the fourth P-type metal-oxide semiconductor transistor MP4 is coupled to the power supply terminal. The source of the fourth P-type metal-oxide semiconductor transistor MP4 is coupled to the first terminal of the reset sampling capacitor 2071 and the second terminal of the second switch 403. The first terminal of the reset sampling capacitor 2071 is coupled to the second terminal of the second switch 403, and the second terminal of the reset sampling capacitor 2071 is coupled to the ground terminal.

[0094] In this embodiment, the pixel circuit uses a reset sampling capacitor as the core component of the reset sampling circuit. Through the structure where its first terminal is connected to the output terminal of the amplifying circuit and its second terminal is grounded, an efficient and reliable reset voltage storage function is achieved. The reset sampling capacitor can accurately store the reference voltage information of the amplifying circuit during the reset phase and maintain the reference potential stable during the signal readout phase, thereby effectively eliminating the influence of reset noise and circuit offset voltage.

[0095] In the embodiment of the present application, light is generated by the light source at the fourth time point and the light illumination stops until the fifth time point; wherein, the fourth time point occurs after the third time point. The fourth time point is the starting moment of the light source's operation, and the fifth time point is the ending moment of the light source's operation.

[0096] In this embodiment, the pixel circuit ensures that the light illumination only starts after the reset sampling is completed (after the third time point) by precisely controlling the light illumination timing (from the fourth time point to the fifth time point), enabling the photosensitive circuit to perform exposure under stable initial conditions. This timing design effectively isolates the reset process from the optical signal acquisition stage, avoids reset noise interfering with the exposure process, and at the same time ensures the accuracy of signal sampling during exposure.

[0097] In the embodiment of the present application, the high-gain active pixel circuit further includes: a third branch, and the third branch is coupled between the first terminal of the exposure sampling circuit 208 and the output terminal of the amplifying circuit 202. The first terminal of the exposure sampling circuit 208 is coupled to the output terminal of the amplifying circuit 202, and the second terminal of the exposure sampling circuit 208 is coupled to the ground terminal; the exposure sampling circuit 208 is configured to: store the voltage information input by the amplifying circuit 202.

[0098] In the embodiment of the present application, the third switch 404 is disposed on the third branch, and the third switch 404 is configured to be in a closed state between the first time point and the second time point, and the amplifier circuit 202 resets the exposure sampling circuit 208 through the third branch; the third switch 404 is further configured to: until the change amount of the output voltage of the amplifier circuit 202 is within the second preset range from the closed state to the sixth time point, the third switch 404 is turned off. Wherein, the sixth time point occurs after the fifth time point, and the voltage in the second preset range is greater than the voltage in the first preset range. The sixth time point is the moment when the third switch 404 switches from the closed state to the open state.

[0099] The first end of the third switch 404 is coupled to the output end of the amplifier circuit 202. That is, when the amplifier circuit 202 is a common-source amplifier, the first end of the third switch 404 is coupled to the drain of the first N-type metal oxide semiconductor transistor MN1; when the amplifier circuit 202 is a cascode amplifier, the first end of the third switch 404 is coupled to the drain of the second N-type metal oxide semiconductor transistor MN2.

[0100] In this embodiment, by introducing the exposure sampling circuit, the third branch, and the third switch, the pixel circuit realizes high-precision acquisition and processing of optical signals. The third switch is closed between the first time point and the second time point, so that the amplifier circuit resets the exposure sampling circuit; then at the sixth time point (after the light exposure ends), the third switch is turned off according to the change amount of the output voltage, ensuring that the signal change generated by the light exposure is completely recorded. By separating the voltage ranges of the reset sampling and the exposure sampling (the second preset range > the first preset range), the reset noise and the real optical signal are effectively distinguished, and the signal-to-noise ratio is greatly improved; at the same time, the light exposure timing is strictly matched (the sampling continues until the sixth time point after the light exposure ends), and the voltage change during the exposure is completely captured to avoid signal omission.

[0101] In the embodiment of the present application, the exposure sampling circuit 208 includes: a fifth P-type metal oxide semiconductor transistor MP5 and an exposure sampling capacitor 2081. The first end of the exposure sampling capacitor 2081 serves as the first end of the exposure sampling circuit 208, and the second end of the exposure sampling capacitor 2081 serves as the second end of the exposure sampling circuit 208.

[0102] The drain of the fifth P-type metal oxide semiconductor transistor MP5 is coupled to the power supply terminal, the source of the fifth P-type metal oxide semiconductor transistor MP5 is coupled to the first end of the exposure sampling capacitor 2081 and the second end of the third switch 404, the first end of the exposure sampling capacitor 2081 is coupled to the second end of the third switch 404, and the second end of the exposure sampling capacitor 2081 is coupled to the ground terminal.

[0103] In this embodiment, the pixel circuit uses an exposure sampling capacitor as the core component of the exposure sampling circuit. Through the structure where its first end is connected to the output end of the amplifying circuit and the second end is grounded, a high-precision optical signal acquisition function is achieved. The exposure sampling capacitor can accurately record the voltage change generated by the optical signal during the exposure stage and maintain signal integrity during the readout stage. Its collaborative work with the reset sampling capacitor realizes double sampling of reset and exposure. In addition, by strictly controlling the sampling period of the exposure sampling capacitor after the end of illumination (the sixth time point), all photo-generated charges are ensured to be completely captured.

[0104] In the embodiment of the present application, starting from the fourth time point, the voltage at the second end of the fourth capacitor C4 rises from the first voltage to the second voltage until starting from the seventh time point, the voltage at the second end of the fourth capacitor C4 drops from the second voltage to the first voltage; wherein, the seventh time point occurs after the sixth time point. The seventh time point is the moment when the voltage at the second end of the fourth capacitor starts to drop.

[0105] In this embodiment, the pixel circuit realizes dynamic optimization control of the photosensitive circuit by precisely controlling the voltage modulation timing of the fourth capacitor (from the fourth time point to the seventh time point). During the exposure stage (starting from the fourth time point), the voltage of the fourth capacitor is increased from the first voltage to the second voltage to enhance the charge collection efficiency of the photosensitive circuit; after the end of the signal readout stage (the seventh time point, that is, after the sixth time point), the voltage is restored to the first voltage to prepare for the next exposure. This voltage modulation with timing matching, on the one hand, the high voltage (the second voltage) during exposure can expand the full well capacity of the photosensitive node and improve the pixel dynamic range; on the other hand, the voltage rise and fall are strictly synchronized with the exposure / readout timing to avoid signal interference; and on the other hand, through capacitive coupling, a potential adjustment without DC power consumption is achieved, maintaining low power consumption characteristics while improving performance.

[0106] In the embodiment of the present application, after the seventh time point, exposure information is obtained according to the voltage information stored in the exposure sampling circuit 208 and the voltage information stored in the reset sampling circuit 207.

[0107] In this embodiment, the pixel circuit realizes high-precision extraction of optoelectronic signals by comparing the voltage information stored in the exposure sampling capacitor and the reset sampling capacitor after the seventh time point.

[0108] In the embodiment of the present application, the output circuit 209 includes: a fourth N-type metal oxide semiconductor transistor MN4, a fifth N-type metal oxide semiconductor transistor MN5, a sixth N-type metal oxide semiconductor transistor MN6, and a seventh N-type metal oxide semiconductor transistor MN7.

[0109] The drain of the fourth N-type metal-oxide semiconductor transistor MN4 is coupled to the power supply terminal, and the gate of the fourth N-type metal-oxide semiconductor transistor MN4 is coupled to the output terminal of the amplifier circuit 202. The source of the fourth N-type metal-oxide semiconductor transistor MN4 is coupled to the drain of the fifth N-type metal-oxide semiconductor transistor MN5. The gate of the fifth N-type metal-oxide semiconductor transistor MN5 is used to receive the row selection signal, and the source of the fifth N-type metal-oxide semiconductor transistor MN5 is coupled to the negative output terminal.

[0110] That is, when the amplifier circuit 202 is a common-source amplifier, the gate of the fourth N-type metal-oxide semiconductor transistor MN4 is coupled to the drain of the first N-type metal-oxide semiconductor transistor MN1; when the amplifier circuit 202 is a cascode amplifier, the gate of the fourth N-type metal-oxide semiconductor transistor MN4 is coupled to the drain of the second N-type metal-oxide semiconductor transistor MN2.

[0111] The drain of the sixth N-type metal-oxide semiconductor transistor MN6 is coupled to the power supply terminal, and the gate of the sixth N-type metal-oxide semiconductor transistor MN6 is coupled to the output terminal of the amplifier circuit 202. The source of the sixth N-type metal-oxide semiconductor transistor MN6 is coupled to the drain of the seventh N-type metal-oxide semiconductor transistor MN7. The gate of the seventh N-type metal-oxide semiconductor transistor MN7 is used to receive the row selection signal, and the source of the seventh N-type metal-oxide semiconductor transistor MN7 is coupled to the positive output terminal.

[0112] That is, when the amplifier circuit 202 is a common-source amplifier, the gate of the sixth N-type metal-oxide semiconductor transistor MN6 is coupled to the drain of the first N-type metal-oxide semiconductor transistor MN1; when the amplifier circuit 202 is a cascode amplifier, the gate of the sixth N-type metal-oxide semiconductor transistor MN6 is coupled to the drain of the second N-type metal-oxide semiconductor transistor MN2.

[0113] The operation of the high-gain active pixel circuit will be described in more detail below. Based on Figure 6 , as Figure 7 shown, it is a schematic diagram of the working timing of a high-gain active pixel circuit provided by an embodiment of the present application.

[0114] As Figure 7 shown, when C1 = C2 = C4 = C and C3 = nC, the voltage of the voltage regulation circuit coupled to the second end of the fourth capacitor C4 provides a voltage signal according to the Figure 7 working timing shown.

[0115] First, close the first switch 402, the second switch 403, and the third switch 404 at the first time point T1, so that the amplifier circuit 202 is in a reset state. Then, open the first switch 402 at the second time point T2 to end the reset of the amplifier circuit 202. After waiting for the output of the amplifier circuit 202 to stabilize, open the second switch 403 at the third time point T3 to save the reset voltage of the amplifier circuit 202 and the influence voltage introduced by the first switch 402 to the reset sampling capacitor 2071.

[0116] At the fourth time point T4 after the third time point T3, turn on the LED. At the same time, the voltage (Vsub) of the voltage regulation circuit coupled to the second end of the fourth capacitor C4 is raised from 0 to the common-mode reduction voltage. When the LED is exposed for a period of time, turn off the LED to stop the exposure at the fifth time point T5. After waiting for a period of time for the amplifier circuit 202 to stabilize, open the third switch 404 at the sixth time point T6 and save the exposure result to the exposure sampling capacitor 2081. Then, at the seventh time point T7, reduce the voltage of the voltage regulation circuit coupled to the second end of the fourth capacitor C4 from the common-mode reduction voltage to 0.

[0117] It should be noted that at this time, the tenth capacitor C10 is the ground capacitor of the voltage regulation circuit coupled to the second end of the fourth capacitor C4, the sixth capacitor C6 is the ground capacitor of the photosensitive circuit 201, the eighth capacitor C8 is the ground capacitor of the output end of the amplifier circuit 202, and the ninth capacitor C9 is the capacitor between the output end of the amplifier circuit 202 and the voltage regulation circuit. These capacitors do not affect the output result of the amplifier circuit 202. The fifth capacitor C5 is equivalent to the feedback capacitor of the amplifier circuit 202 and can still be equivalent to a smaller capacitance value with a larger capacitance value, ensuring the low noise and high sensitivity of the pixel.

[0118] Finally, the change value of the voltage of the voltage regulation circuit at the start of exposure (i.e., the common-mode reduction voltage) can be understood as the voltage regulation circuit injecting charge into the photosensitive circuit 201 through the seventh capacitor C7, and the charge quantity is Vsub×C÷(3 + n). Therefore, after the start of exposure, the photosensitive current needs to first draw away the injected charge before it can return to the reset state. Also, since the capacitance value C14 of the seventh capacitor C7 is equal to the capacitance value C12 of the fifth capacitor C5, the charge drawn away by the photosensitive current to restore the reset state can theoretically cause a voltage change Vsub in the output of the amplifier circuit 202. The whole process can be equivalent to: by changing the voltage of the voltage regulation circuit, the pixel exposure value is reduced by Vsub. It can be seen that compared with the working mode where the voltage regulation circuit is often grounded, this operation can increase the pixel dynamic range by Vsub. And the voltage of Vsub can be controlled by an additional circuit to achieve a large control range, thereby greatly improving the pixel dynamic range.

[0119] The present application also provides an image sensor, which includes a light source and a pixel array. The pixel array includes a plurality of high-gain active pixel circuits as shown in Figure 4 or the high-gain active pixel circuit as shown in Figure 6 . Among them, the light source is used to provide illumination for the high-gain active pixel circuits in the pixel array. Since the image sensor in the embodiments of the present application includes the above-mentioned high-gain active pixel circuits, therefore, the technical effects that can be obtained can also refer to the embodiments of the above-mentioned high-gain active pixel circuits, and the embodiments of the present application will not be elaborated herein.

[0120] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered within the protection scope of the present application.

Claims

1. A high-gain active pixel circuit, characterized in that: include: A photosensitive circuit, wherein a first terminal of the photosensitive circuit is coupled to a ground terminal and is configured to: generate an exposure current according to the intensity of the received light; A feedback circuit, wherein a first end of the feedback circuit is coupled to a second end of the photosensitive circuit and is configured to: input the exposure current and clamp the voltage at the second end of the photosensitive circuit; an amplifier circuit, wherein the output end of the amplifier circuit is coupled to the second end of the feedback circuit, the input end of the amplifier circuit is coupled to the second end of the photosensitive circuit, and is configured to: clamp the voltage at the second end of the photosensitive circuit to a preset voltage through the feedback circuit; Wherein, the feedback circuit includes: a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; the first end of the first capacitor serves as the first end of the feedback circuit; the first end of the second capacitor is coupled to the second end of the first capacitor, and the second end of the second capacitor serves as the second end of the feedback circuit; the first end of the third capacitor is coupled to the second end of the first capacitor, and the second end of the third capacitor is coupled to the ground end; the first end of the fourth capacitor is coupled to the second end of the first capacitor, and the second end of the fourth capacitor is used to couple to a voltage regulation circuit, and is configured to: receive an applied voltage so that the second end of the fourth capacitor is at a corresponding potential.

2. The high-gain active pixel circuit according to claim 1, characterized in that: The capacitances of the first capacitor, the second capacitor and the fourth capacitor are first capacitances, the capacitance of the third capacitor is second capacitance, and the second capacitance is greater than the first capacitance.

3. The high-gain active pixel circuit according to claim 1 or 2, characterized in that: The high-gain active pixel circuit further comprises: A first branch, coupled between the second end of the photosensitive circuit and the output end of the amplifier circuit; The first switch is arranged on the first branch and is configured to be in a closed state between a first time point and a second time point, and to reset the amplifier circuit and the photosensitive circuit through the first branch, the first time point being the starting time of the operation of the high-gain active pixel circuit, and the second time point being the end time of resetting the amplifier circuit and the photosensitive circuit.

4. The high-gain active pixel circuit according to claim 3, characterized in that: The high-gain active pixel circuit further comprises: A reset sampling circuit, wherein a first terminal of the reset sampling circuit is coupled to the output terminal of the amplifier circuit, and a second terminal of the reset sampling circuit is coupled to the ground terminal; and is configured to: store voltage information inputted by the amplifier circuit; A second branch, coupled between the first terminal of the reset sampling circuit and the output terminal of the amplifier circuit; The second switch is arranged on the second branch and is configured to be in a closed state between the first time point and the second time point, and the amplifier circuit resets the reset sampling circuit through the second branch; and is also configured to be in a closed state until a third time point, when the change amount of the output voltage of the amplifier circuit is within a first preset range, the second switch is disconnected; the third time point is the moment when the second switch is switched from a closed state to an open state.

5. The high-gain active pixel circuit according to claim 4, characterized in that: The reset sampling circuit comprises: A reset sampling capacitor, wherein a first end of the reset sampling capacitor serves as a first end of the reset sampling circuit, and a second end of the reset sampling capacitor serves as a second end of the reset sampling circuit.

6. The high-gain active pixel circuit according to claim 4 or 5, characterized in that: The illumination is generated by the light source at a fourth time point and stops at a fifth time point; the fourth time point is the start time of the operation of the light source, and the fifth time point is the end time of the operation of the light source; The fourth time point occurs after the third time point.

7. The high-gain active pixel circuit according to claim 6, characterized in that: The high-gain active pixel circuit further comprises: An exposure sampling circuit, wherein a first terminal of the exposure sampling circuit is coupled to the output terminal of the amplifier circuit, and a second terminal of the exposure sampling circuit is coupled to the ground terminal; and is configured to: store voltage information inputted by the amplifier circuit; A third branch, coupled between the first end of the exposure sampling circuit and the output end of the amplifier circuit; A third switch is disposed on the third branch and is configured to: be in a closed state between the first time point and the second time point, and the amplifying circuit resets the exposure sampling circuit through the third branch; and is further configured to: be in a closed state until a sixth time point, and when the change amount of the output voltage of the amplifying circuit is within a second preset range, the third switch is disconnected; the sixth time point is the moment when the third switch is switched from a closed state to an open state; The sixth time point occurs after the fifth time point, and the voltage in the second preset range is greater than the voltage in the first preset range.

8. The high-gain active pixel circuit according to claim 7, characterized in that: The exposure sampling circuit comprises: An exposure sampling capacitor, wherein a first end of the exposure sampling capacitor serves as a first end of the exposure sampling circuit, and a second end of the exposure sampling capacitor serves as a second end of the exposure sampling circuit.

9. The high-gain active pixel circuit according to claim 7 or 8, characterized in that: Starting from the fourth time point, the voltage at the second end of the fourth capacitor increases from the first voltage to the second voltage, until starting from the seventh time point, the voltage at the second end of the fourth capacitor decreases from the second voltage to the first voltage; the seventh time point is the moment when the voltage at the second end of the fourth capacitor starts to decrease from the second voltage; Wherein, the seventh time point occurs after the sixth time point.

10. The high-gain active pixel circuit according to claim 9, characterized in that: After the seventh time point, exposure information is obtained according to the voltage information stored in the exposure sampling circuit and the voltage information stored in the reset sampling circuit.

11. The high-gain active pixel circuit according to claim 1, characterized in that: The photosensitive circuit includes a photosensitive diode, wherein the anode of the photosensitive diode serves as the first end of the photosensitive circuit, and the cathode of the photosensitive diode serves as the second end of the photosensitive circuit.

12. The high-gain active pixel circuit according to claim 1, characterized in that: The amplifying circuit comprises: A first P-type metal oxide semiconductor transistor, wherein a drain of the first P-type metal oxide semiconductor transistor is coupled to a power supply terminal; a first N-type metal oxide semiconductor transistor, wherein the drain of the first N-type metal oxide semiconductor transistor serves as the output terminal of the amplifier circuit and is coupled to the source of the first P-type metal oxide semiconductor transistor; the source of the first N-type metal oxide semiconductor transistor is coupled to the ground terminal, and the gate of the first N-type metal oxide semiconductor transistor serves as the input terminal of the amplifier circuit.

13. The high-gain active pixel circuit according to claim 1, characterized in that: The amplifying circuit comprises: A second P-type metal oxide semiconductor transistor, wherein a drain of the second P-type metal oxide semiconductor transistor is coupled to a power supply terminal; a third P-type metal oxide semiconductor transistor, wherein a drain of the third P-type metal oxide semiconductor transistor is coupled to a source of the second P-type metal oxide semiconductor transistor; a second N-type metal oxide semiconductor transistor, wherein a drain of the second N-type metal oxide semiconductor transistor serves as an output terminal of the amplifier circuit and is coupled to a source of the third P-type metal oxide semiconductor transistor; a third N-type metal oxide semiconductor transistor, wherein the drain of the third N-type metal oxide semiconductor transistor is coupled to the source of the second N-type metal oxide semiconductor transistor; the source of the third N-type metal oxide semiconductor transistor is coupled to the ground terminal; and the gate of the third N-type metal oxide semiconductor transistor serves as the input terminal of the amplifier circuit.

14. An image sensor, characterized in that: include: light source; A pixel array comprising a plurality of high-gain active pixel circuits as described in any one of claims 1 to 13.

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