Preparation method of SRAM (Static Random Access Memory) device and gate structure
By using the etching rate difference between the polysilicon doped layer and the undoped layer in the SRAM device of the high-voltage display driving platform, the gate morphology is changed, and the problems of insufficient filling between the dielectric layer and contact hole bridge are solved, and the performance of the device is improved.
Patent Information
- Application Number
- CN202510330689.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2025-06-13
AI Technical Summary
In the SRAM device of the high-voltage display driving platform, the thicker polysilicon layer causes insufficient filling of the interlayer dielectric layer, resulting in a void, which in turn causes a short-circuit problem between adjacent contact holes.
By forming a polysilicon doped layer and an undoped polysilicon layer on the substrate, and using the etching rate difference of different doped layers, the morphology of the polysilicon gate is changed to form first and second gates with different widths to improve the filling capability of the interlayer dielectric layer.
The gap filling of the interlayer dielectric layer is improved, and the formation of voids is avoided, thereby preventing the bridging short circuit of adjacent shared contact holes, improving the read and write functions and overall performance of SRAM devices.
Smart Images
Figure CN120152265A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a preparation method and a gate structure of a SRAM device. Background Art
[0002] The high-voltage display driver platform is a process platform specifically used for display panel driver integrated circuits. In the high-voltage display driver platform, high-energy ion implantation technology is usually used to optimize the device's voltage resistance and electrical performance due to the need to process high-voltage signals. However, although high-energy ion implantation can improve device performance, it also introduces more lattice damage. In order to compensate for these damages and ensure the stability of the device, the thickness of polysilicon on the high-voltage display driver platform is usually thicker than that on the logic platform.
[0003] In the static random access memory (SRAM) area of the high-voltage display driver platform, when the storage unit area is small, the gaps between the thicker polysilicon become narrower accordingly. This makes it difficult for the interlayer dielectric layer to completely fill these gaps when depositing the interlayer dielectric material, and it is easy to be insufficiently filled, thus forming voids. In the subsequent process, after the contact holes are etched in the interlayer dielectric layer, these voids may be located between adjacent contact holes, causing bridges between adjacent contact holes. This bridging phenomenon will introduce additional electrical paths, resulting in short circuits or leakage, which seriously affects the read and write functions and overall performance of the SRAM device.
[0004] Therefore, how to provide a method for manufacturing an SRAM device and a gate structure to avoid the problem of insufficient filling of the interlayer dielectric layer and bridging between adjacent contact holes has become an important issue that needs to be solved urgently by those skilled in the art.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for preparing an SRAM device and a gate, so as to solve the problem of insufficient filling of the interlayer dielectric layer of the SRAM device in the prior art, resulting in bridging between adjacent contact holes.
[0007] To achieve the above object and other related objects, the present invention provides a method for preparing a SRAM device, comprising the following steps:
[0008] A substrate is provided, and a polysilicon doped layer is formed on one side of the substrate;
[0009] An undoped polysilicon layer is formed on the polysilicon doped layer;
[0010] The undoped polysilicon layer and the polysilicon doped layer are etched to obtain a first gate and a second gate which are arranged at intervals. Among them, the etching rate of the undoped polysilicon layer is greater than that of the polysilicon doped layer. The top width of the first gate is smaller than the bottom width of the first gate, and the top width of the second gate is smaller than the bottom width of the second gate.
[0011] Optionally, a plurality of separated active regions are provided in the substrate, and the active regions include P-type active regions and N-type active regions.
[0012] Optionally, forming the polysilicon doped layer includes the following steps:
[0013] A first polysilicon layer is formed on one side of the substrate;
[0014] The first polysilicon layer is ion-implanted to form the polysilicon doped layer.
[0015] Optionally, the doping elements in the polysilicon doped layer include one or more of carbon, phosphorus, indium, and gallium.
[0016] Optionally, the thickness of the undoped polysilicon layer is greater than that of the polysilicon doped layer, and the thickness range of the polysilicon doped layer is
[0017] Optionally, before etching the undoped polysilicon layer and the polysilicon doped layer, the following steps are further included:
[0018] A hard mask layer is formed on the undoped polysilicon layer;
[0019] The hard mask layer is patterned so that the patterned hard mask layer presents a strip-shaped pattern distributed at intervals;
[0020] Using the patterned hard mask layer as a mask, the undoped polysilicon layer and the polysilicon doped layer are etched to obtain the first gate and the second gate.
[0021] Optionally, there is a first width difference between the top width and the bottom width of the first gate, and the first width difference ranges from 10 nm to 25 nm. There is a second width difference between the top width and the bottom width of the second gate, and the second width difference ranges from 10 nm to 25 nm.
[0022] Optionally, it further includes the step of forming an interlayer dielectric layer on one side of the substrate.
[0023] Optionally, it further includes the step of forming a shared contact hole in the interlayer dielectric layer, where the shared contact hole is located in the interlayer dielectric layer between the first gate and the second gate and extends above the first gate or the second gate.
[0024] The present invention also provides a gate structure of an SRAM device, including:
[0025] A substrate, in which a plurality of separated active regions are provided;
[0026] A gate oxide layer, located on one side of the substrate;
[0027] A first gate and a second gate, which are spaced apart and disposed on the gate oxide layer. The first gate includes a first polysilicon doped portion and a first polysilicon undoped portion located on the first polysilicon doped portion. The second gate includes a second polysilicon doped portion and a second polysilicon undoped portion located on the second polysilicon doped portion. Moreover, the bottom width of the first polysilicon doped portion is greater than the top width of the first polysilicon undoped portion, and the bottom width of the second polysilicon doped portion is greater than the top width of the second polysilicon undoped portion.
[0028] As described above, the preparation method of the SRAM device of the present invention includes: providing a substrate, forming a polysilicon doped layer on one side of the substrate, forming an undoped polysilicon layer on the polysilicon doped layer, etching the undoped polysilicon layer and the polysilicon doped layer to obtain a first gate and a second gate which are spaced apart. Among them, the etching rate corresponding to the undoped polysilicon layer is greater than the etching rate corresponding to the polysilicon doped layer. The top width of the first gate is smaller than the bottom width of the first gate, and the top width of the second gate is smaller than the bottom width of the second gate. The preparation method of the SRAM device of the present invention can improve the gap filling of the interlayer dielectric layer by changing the gate morphology, avoid the occurrence of voids in the interlayer dielectric layer, and thus prevent the adjacent shared contact holes from bridging and short-circuiting. Description of the Drawings
[0029] Figure 1 It shows a schematic diagram of a storage cell of an SRAM device.
[0030] Figure 2 It shows Figure 1 A partial structural schematic diagram of the shown storage cell.
[0031] Figure 3 It shows Figure 2 A cross-sectional view in the A-A' direction in
[0032] Figure 4 It shows inFigure 3 Schematic diagram of the structure obtained after filling the interlayer dielectric layer on the shown structure.
[0033] Figure 5 Shown as Figure 2 Cross-sectional electron microscope picture in the B - B’ direction in
[0034] Figure 6 Process flow chart showing the preparation method of the SRAM device of the present invention.
[0035] Figure 7 Schematic diagram of the structure obtained after providing a substrate and forming a polysilicon doped layer in the preparation method of the SRAM device of the present invention.
[0036] Figure 8 Shown as Figure 7 Top view of the shown substrate.
[0037] Figure 9 Schematic diagram of the structure obtained after forming the first polysilicon layer in the preparation method of the SRAM device of the present invention.
[0038] Figure 10 Schematic diagram of the structure obtained after forming an undoped polysilicon layer in the preparation method of the SRAM device of the present invention.
[0039] Figure 11 Schematic diagram of the structure obtained after obtaining the first gate and the second gate arranged at intervals in the preparation method of the SRAM device of the present invention.
[0040] Figure 12 Shown as Figure 11 Top view of a structure of the shown structure.
[0041] Figure 13 Schematic diagram of the structure obtained after forming a patterned hard mask layer in the preparation method of the SRAM device of the present invention.
[0042] Figure 14 Shown as Figure 13 Top view of the shown structure.
[0043] Figure 15 Schematic diagram of the structure obtained after forming an interlayer dielectric layer in the preparation method of the SRAM device of the present invention.
[0044] Figure 16 Shown as a capacitance - voltage characteristic curve graph of an SRAM device.
[0045] Explanation of reference numerals
[0046] 1, 8 Substrate
[0047] 801 P - type active region
[0048] 802 N-type active region
[0049] 2 First pull-up transistor
[0050] 201 First active region
[0051] 202 First polysilicon gate
[0052] 3 Second pull-up transistor
[0053] 301 Second active region
[0054] 302 Second polysilicon gate
[0055] 4 First contact hole
[0056] 5 Second contact hole
[0057] 6, 19 Interlayer dielectric layer
[0058] 7 Void
[0059] 9 First polysilicon layer
[0060] 10 Polysilicon doped layer
[0061] 11 Undoped polysilicon layer
[0062] 12 First gate
[0063] 121 First polysilicon doped part
[0064] 122 First polysilicon undoped part
[0065] 13 Second gate
[0066] 131 Second polysilicon doped part
[0067] 132 Second polysilicon undoped part
[0068] 14 First pull-up region
[0069] 15 Second pull-up region
[0070] 16 First pull-down region
[0071] 17 Second pull-down region
[0072] 18 First control region
[0073] 19 Second control region
[0074] 20 Hard mask layer
[0075] 21 Gate oxide layer
[0076] 22 Oxide layer
[0077] D Diffusion region
[0078] L1 Top width of the first gate
[0079] L2 Bottom width of the first gate
[0080] L3 Top width of the second gate
[0081] L4 Bottom width of the second gate
[0082] S1 - S3 Steps Detailed implementation mode
[0083] The SRAM device is a semiconductor memory used for high - speed data storage and access. It uses a flip - flop composed of a group of transistors (usually 6 transistors) to store data for each bit. As long as there is power supply, the data can remain unchanged. Please refer to Figure 1 , which shows a schematic diagram of a storage cell of an SRAM device. Each storage cell of the SRAM consists of 6 transistors, forming a stable bistable flip - flop. This structure includes two inverters (composed of Q1, Q3 and Q2, Q4) and two control transistors (T1 and T2), which are respectively connected to the bit line and the word line for controlling data reading and writing.
[0084] Please refer to Figure 2 , which shows Figure 1 a partial structural schematic diagram of the storage cell shown. Among them, on the substrate 1, there are a first pull - up transistor 2 (Q1) and a second pull - up transistor 3 (Q2). The first pull - up transistor 2 (Q1) includes a first active region 201 and a first polysilicon gate 202. The second pull - up transistor 3 (Q2) includes a second active region 301 and a second polysilicon gate 302. As the integrated circuit line width decreases and the integration degree increases, in order to reduce the layout area of the SRAM device, shared contact holes are usually introduced. Figure 2 The shared contact holes in include a first contact hole 4 and a second contact hole 5. The first contact hole 4 connects the input end (i.e., the first polysilicon gate 202) of the first pull - up transistor 2 (Q1) to the output end (i.e., the source) of the second pull - up transistor 3 (Q2). The second contact hole 5 connects the input end (i.e., the second polysilicon gate 302) of the second pull - up transistor 3 (Q2) to the output end (i.e., the source) of the first pull - up transistor 2 (Q1).
[0085] Please refer to again Figures 3 to 4, before forming the shared contact hole, an interlayer dielectric layer 6 covering the first polysilicon gate 202 and the second polysilicon gate 302 is first formed on the substrate 1. Due to the small storage cell area and the relatively thick polysilicon, the gap between the first polysilicon gate 202 and the second polysilicon gate 302 becomes correspondingly narrow, making it difficult for the deposited interlayer dielectric layer 6 to completely fill these gaps, and voids 7 are likely to occur. After etching the shared contact hole in the interlayer dielectric layer 6 having the voids 7, the adjacent first contact hole 4 and the second contact hole 5 are likely to be short-circuited due to the existence of the voids 7, where, Figure 3 Shown as Figure 2 A cross-sectional view in the A-A' direction in, Figure 4 Shown as in Figure 3 A schematic diagram of the structure obtained after filling the interlayer dielectric layer 6 on the structure shown.
[0086] Finally, please refer to Figure 5 Shown as Figure 2 A cross-sectional electron microscope picture in the B-B' direction in. After filling the first contact hole 4 and the second contact hole 5, the tungsten metal in the first contact hole 4 and the second contact hole 5 will diffuse at the voids 7 to form a diffusion region D, and the diffusion region D will cause a bridging short-circuit problem between the first contact hole 4 and the second contact hole 5 (i.e., adjacent shared contact holes).
[0087] The inventors of the present application provide a method for manufacturing an SRAM device. By changing the single-growth polysilicon layer to polysilicon layers of at least two different dopings and using the etching rate difference between the polysilicon layers of different dopings to change the morphology of the polysilicon gate, the gap filling ability of the interlayer dielectric layer can be improved, voids in the interlayer dielectric layer can be avoided, and thus bridging short-circuits between adjacent shared contact holes can be prevented.
[0088] The following illustrates the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0089] It should be emphasized that the term "including / comprising" when used herein refers to the presence of features, whole things, steps or components, but does not exclude the presence or addition of one or more other features, whole things, steps or components.
[0090] Features described and / or illustrated for one embodiment can be used in the same or similar way in one or more other embodiments, combined with features in other embodiments, or instead of features in other embodiments.
[0091] When detailing the embodiments of the present invention, for ease of explanation, the schematic diagrams showing the device structure may be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions of length, width and depth should be included.
[0092] For convenience of description, spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.
[0093] In the context of the present application, the structure in which the first feature is "above" the second feature described may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0094] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0095] Please refer to Figure 6 , which shows a process flow diagram of a method for manufacturing an SRAM device of the present invention, including the following steps:
[0096] S1: Provide a substrate and form a polysilicon doped layer on one side of the substrate;
[0097] S2: Form an undoped polysilicon layer on the polysilicon doped layer;
[0098] S3: Etching the undoped polysilicon layer and the polysilicon doped layer to obtain a first gate and a second gate that are spaced apart, wherein an etching speed corresponding to the undoped polysilicon layer is greater than an etching speed corresponding to the polysilicon doped layer, a top width of the first gate is smaller than a bottom width of the first gate, and a top width of the second gate is smaller than a bottom width of the second gate.
[0099] The following will be combined Figures 7 to 15 , detailing each step of the method for preparing the SRAM device of the present invention.
[0100] First see Figure 7 , performing step S1: providing a substrate 8 and forming a polysilicon doping layer 10 on one side of the substrate 8 .
[0101] As an example, see Figure 8 , displayed as Figure 7 The top view of the substrate 8 is shown in FIG. 1 , wherein the substrate 8 is provided with a plurality of separate active regions, the active regions including a P-type active region 801 and an N-type active region 802. In this embodiment, the P-type active region 801 is used to form Figure 1 The first pull-down transistor (Q1), the second pull-down transistor (Q2) and the two control transistors (T1 and T2) in the N-type region are used to form Figure 1 The first pull-up transistor 2 (Q3) and the second pull-up transistor 3 (Q4) in.
[0102] As an example, the thickness of the polysilicon doping layer 10 is in the range of The thickness of the polysilicon doping layer 10 can be adjusted according to the location where the void may appear. In this embodiment, the thickness of the polysilicon doping layer 10 is set to In other embodiments, the thickness of the polysilicon doping layer 10 may be set to or
[0103] As an example, the doping concentration range of the polysilicon doping layer 10 is 10 19 cm -3 ~10 21 cm -3 , preferably 10 19 cm -3 ~10 20 cm -3 .
[0104] As an example, forming the polysilicon doping layer 10 includes the following steps:
[0105] (1) Please refer to Figure 9, which shows a schematic diagram of the structure obtained after forming the first polysilicon layer in the method for manufacturing the SRAM device of the present invention. The first polysilicon layer is formed on one side of the substrate;
[0106] (2) Ion implant the first polysilicon layer 9 to form the polysilicon doped layer 10.
[0107] As an example, it further includes the step of annealing the polysilicon doped layer 10. The annealing can adopt processes such as spike annealing or laser annealing.
[0108] As an example, the doping elements in the polysilicon doped layer 10 include one or more of carbon, phosphorus, indium, and gallium. In this embodiment, the first polysilicon layer 9 is doped with carbon element by ion implantation to form the polysilicon carbon doped layer 10, and the etching rate corresponding to the polysilicon carbon doped layer 10 is slow. In other embodiments, the first polysilicon layer 9 can also be doped with carbon element by in-situ doping to form the polysilicon carbon doped layer 10. During the growth of polysilicon, the flow rate range of the doped carbon element is 10 SCCM to 20 SCCM. The in-situ doping method does not require subsequent annealing treatment.
[0109] Please refer to again Figure 10 , and perform step S2: Form an undoped polysilicon layer 11 on the polysilicon doped layer 10.
[0110] As an example, the thickness of the undoped polysilicon layer 11 is greater than the thickness of the polysilicon doped layer 10.
[0111] Please refer to again Figure 11 , and perform step S3: Etch the undoped polysilicon layer 11 and the polysilicon doped layer 10 to obtain the first gate 12 and the second gate 13 which are spaced apart. Among them, the etching rate corresponding to the undoped polysilicon layer 11 is greater than the etching rate corresponding to the polysilicon doped layer 10. The top width of the first gate 12 is smaller than the bottom width of the first gate 12, and the top width of the second gate 13 is smaller than the bottom width of the second gate 13.
[0112] As an example, please refer to Figure 12 , which shows as Figure 11A top view of the structure shown, where the substrate 8 includes a first pull-down region 14, a second pull-down region 15, a first pull-up region 16, a second pull-up region 17, a first control region 18, and a second control region 19. Among them, the first pull-down region 14 is used to form the first pull-down transistor (Q1), the second pull-down region 15 is used to form the second pull-down transistor (Q2), the first pull-up region 16 is used to form the first pull-up transistor 2 (Q3), the second pull-up region 17 is used to form the second pull-up transistor 3 (Q4), the first control region 18 is used to form the first control transistor (T1), and the second control region 19 is used to form the second control transistor (T2). Figure 12 Shown as Figure 11 A structure of the structure shown. In other embodiments, Figure 11 The structure shown may also have other structures, and different settings can be made according to the specific needs of the SRAM region.
[0113] As an example, please refer to Figures 13 to 14 , before etching the undoped polysilicon layer 11 and the polysilicon doped layer 10, the following steps are further included:
[0114] (1) Form a hard mask layer 20 on the undoped polysilicon layer 11;
[0115] (2) Pattern the hard mask layer 20 so that the patterned hard mask layer 20 presents a strip-shaped pattern distributed at intervals;
[0116] (3) Using the patterned hard mask layer 20 as a mask, etch the undoped polysilicon layer 11 and the polysilicon doped layer 10 to obtain the first gate 12 and the second gate 13.
[0117] Among them, Figure 13 Shows a schematic diagram of the structure obtained after forming the patterned hard mask layer 20 in the manufacturing method of the SRAM device of the present invention, Figure 14 Shown as Figure 13 A top view of the structure shown.
[0118] Specifically, based on the graphically processed hard mask layer 20, the undoped polysilicon layer 11 and the polysilicon doped layer 10 are etched. Since the polysilicon doped layer 10 has been doped, its corresponding etching rate will be slower than that before doping. That is to say, the etching rate of the undoped polysilicon layer 11 is greater than that of the polysilicon doped layer 10. That is, during the etching of the undoped polysilicon layer 11 and the polysilicon doped layer 10, the etched area of the second polysilicon is much larger than that of the polysilicon doped layer 10. After forming the first gate 12 and the second gate 13, the bottom width of the first polysilicon doped part 121 of the first gate 12 is greater than the top width of the first polysilicon undoped part 122, and the bottom width of the second polysilicon doped part 131 of the second gate 13 is greater than the top width of the second polysilicon undoped part 132, so as to increase the gap between the first gate 12 and the second gate 13 and improve the ability of the interlayer dielectric layer 19 to completely fill these gaps, thereby avoiding the occurrence of voids in the interlayer dielectric layer 19 and preventing the bridging short circuit between adjacent shared contact holes due to voids. It should be noted that in this embodiment, dry etching is used to etch the undoped polysilicon layer 11 and the polysilicon doped layer 10, and the etching rate of the undoped polysilicon layer 11 is greater than that of the polysilicon doped layer 10.
[0119] As an example, there is a first width difference between the top width L1 and the bottom width L2 of the first gate, and the range of the first width difference is 10 nm to 25 nm. There is a second width difference between the top width L3 and the bottom width L4 of the second gate, and the range of the second width difference is 10 nm to 25 nm. The first width difference and the second width difference can be adjusted by the doping concentration of the polysilicon doped layer 10. The higher the doping concentration of the polysilicon doped layer 10, the larger the values of the first width difference and the second width difference. In this embodiment, the range of the first width difference is preferably 15 nm to 20 nm, and the range of the second width difference is also preferably 15 nm to 20 nm. In other embodiments, the first width difference and the second width difference can be the same or different.
[0120] As an example, please refer to Figure 15 , which shows a schematic diagram of the structure obtained after forming the interlayer dielectric layer in the manufacturing method of the SRAM device of the present invention. Before forming the first polysilicon layer 9 on one side of the substrate 8, it further includes the step of forming a gate oxide layer 21 on one side of the substrate 8.
[0121] As an example, it further includes the step of forming an interlayer dielectric layer 19 on one side of the substrate 8, and the interlayer dielectric layer 19 can completely fill the gap between the first gate 12 and the second gate 13, thereby avoiding bridging short circuits between adjacent shared contact holes.
[0122] Specifically, it further includes the step of forming a shared contact hole (not labeled in the figure) in the interlayer dielectric layer 19. The shared contact hole is located in the interlayer dielectric layer 19 between the first gate 12 and the second gate 13 and extends above the first gate 12 or the second gate 13 for electrically leading out the first gate 12 or the second gate 13.
[0123] As an example, before forming the interlayer dielectric layer 19 on one side of the substrate 8, it further includes the step of forming an oxide layer 22 on the surfaces of the first gate 12 and the second gate 13, and the oxide layer 22 is used to relieve the stress impact of subsequent processes on the first gate 12 and the second gate 13.
[0124] Thus, a gate structure of an SRAM device is fabricated. The gate structure includes a substrate 8, a gate oxide layer 21, a first gate 12, and a second gate 13. Among them, a plurality of separated active regions are provided in the substrate 8, the gate oxide layer 21 is located on one side of the substrate 8, the first gate 12 and the second gate 13 are arranged at intervals on the gate oxide layer 21. The first gate 12 includes a first polysilicon doped portion 121 and a first polysilicon undoped portion 122 located on the first polysilicon doped portion 121. The second gate 13 includes a second polysilicon doped portion 131 and a second polysilicon undoped portion 132 located on the second polysilicon doped portion 131. And the bottom width of the first polysilicon doped portion 121 is greater than the top width of the first polysilicon undoped portion 122, and the bottom width of the second polysilicon doped portion 131 is greater than the top width of the second polysilicon undoped portion 132.
[0125] Please refer to Figure 16 , which shows a capacitance-voltage characteristic curve of an SRAM device. The gate of the SRAM device is polysilicon, and its grain size is too large, resulting in the polysilicon depletion effect. By doping the polysilicon, the grain size of the polysilicon can be reduced, thereby reducing the polysilicon depletion effect. Therefore, in this embodiment, the presence of the polysilicon doped layer can also reduce the grain size, improve the polysilicon depletion effect of the first gate and the second gate, and further improve the stability of the device.
[0126] In summary, the method for manufacturing an SRAM device of the present invention includes: providing a substrate, forming a polysilicon doped layer on one side of the substrate, forming an undoped polysilicon layer on the polysilicon doped layer, etching the undoped polysilicon layer and the polysilicon doped layer to obtain a first gate and a second gate arranged at intervals, wherein the etching rate corresponding to the undoped polysilicon layer is greater than the etching rate corresponding to the polysilicon doped layer, the top width of the first gate is smaller than the bottom width of the first gate, and the top width of the second gate is smaller than the bottom width of the second gate. The method for manufacturing an SRAM device of the present invention can improve the gap filling of the interlayer dielectric layer and avoid the occurrence of voids in the interlayer dielectric layer by changing the gate morphology, thereby preventing the adjacent shared contact holes from bridging and short-circuiting. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0127] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a SRAM device, characterized in that: The following steps are involved: Providing a substrate, and forming a polysilicon doping layer on one side of the substrate; forming an undoped polysilicon layer on the polysilicon doped layer; The undoped polysilicon layer and the polysilicon doped layer are etched to obtain a first gate and a second gate that are spaced apart, wherein an etching speed corresponding to the undoped polysilicon layer is greater than an etching speed corresponding to the polysilicon doped layer, a top width of the first gate is smaller than a bottom width of the first gate, and a top width of the second gate is smaller than a bottom width of the second gate.
2. The method for preparing a SRAM device according to claim 1, wherein: A plurality of separate active regions are arranged in the substrate, and the active regions include a P-type active region and an N-type active region.
3. The method for preparing a SRAM device according to claim 1, characterized in that: Forming the polysilicon doping layer comprises the following steps: forming a first polysilicon layer on one side of the substrate; Ions are implanted into the first polysilicon layer to form the polysilicon doping layer.
4. The method for preparing a SRAM device according to claim 1, wherein: The doping elements in the polysilicon doping layer include one or more of carbon, phosphorus, indium and gallium.
5. The method for preparing a SRAM device according to claim 1, wherein: The thickness of the undoped polysilicon layer is greater than the thickness of the doped polysilicon layer, and the thickness of the doped polysilicon layer is in the range of 6. The method for preparing a SRAM device according to claim 1, characterized in that: Etching the undoped polysilicon layer and the polysilicon doped layer comprises the following steps: forming a hard mask layer on the undoped polysilicon layer; Patterning the hard mask layer so that the patterned hard mask layer presents a strip-shaped pattern with intervals; The patterned hard mask layer is used as a mask to etch the undoped polysilicon layer and the polysilicon doped layer to obtain the first gate and the second gate.
7. The method for preparing a SRAM device according to claim 1, characterized in that: There is a first width difference between the top width of the first gate and the bottom width of the first gate, and the first width difference ranges from 10nm to 25nm. There is a second width difference between the top width of the second gate and the bottom width of the second gate, and the second width difference ranges from 10nm to 25nm.
8. The method for preparing a SRAM device according to claim 1, characterized in that: The method also includes the step of forming an interlayer dielectric layer on one side of the substrate.
9. The method for preparing a SRAM device according to claim 8, characterized in that: The method further includes forming a shared contact hole in the interlayer dielectric layer. The shared contact hole is located in the interlayer dielectric layer between the first gate and the second gate and extends to above the first gate or the second gate.
10. A gate structure of a SRAM device, characterized in that: include: A substrate having a plurality of separate active regions disposed therein; A gate oxide layer, located on one side of the substrate; A first gate and a second gate are arranged on the gate oxide layer at intervals, the first gate includes a first polysilicon doped portion and a first polysilicon non-doped portion located on the first polysilicon doped portion, the second gate includes a second polysilicon doped portion and a second polysilicon non-doped portion located on the second polysilicon doped portion, and the bottom width of the first polysilicon doped portion is greater than the top width of the first polysilicon non-doped portion, and the bottom width of the second polysilicon doped portion is greater than the top width of the second polysilicon non-doped portion.