Manufacturing method of flash memory device

Abstract

The invention provides a manufacturing method of a flash memory device, which comprises the following steps of: providing a substrate which comprises a storage area, a carrier band area and a peripheral logic area, forming a laminated structure on the storage area and the peripheral logic area, and forming a coupling layer, a floating gate polycrystalline silicon layer, an inter-electrode dielectric layer and a control gate polycrystalline silicon layer which are sequentially stacked from bottom to top on the laminated structure; forming a first ONO layer on the control gate polycrystalline silicon layer, wherein the first ONO layer is composed of a first oxide layer, a first nitride layer and a second oxide layer which are sequentially stacked from bottom to top; word line grooves are formed in the first ONO layer on the storage area and the laminated structure below the first ONO layer, tunneling oxide layers are formed in the word line grooves, and then word line polycrystalline silicon layers which fill the word line grooves and cover the first ONO layer are formed; grinding the word line polycrystalline silicon layer and the second oxide layer below the word line polycrystalline silicon layer to the first nitride layer or reserving a part of thickness of the first nitride layer; and removing the first nitride layer. According to the method, the influence of non-uniformity of etching caused by a front layer is avoided, and the grinding thickness difference and the loading effect are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a flash memory device. Background Art

[0002] A method for manufacturing a flash memory device in the prior art includes:

[0003] Step 1: Provide a substrate 201. The substrate 201 includes a storage area, a carrier tape area, and a peripheral logic area. A stacked structure is formed on the storage area and the peripheral logic area. The stacked structure is composed of a coupling layer 202, a floating gate polysilicon layer 204, an inter-pole dielectric layer 205, a control gate polysilicon layer 206, and a hard mask layer 207 stacked in sequence from bottom to top. The material of the hard mask layer 207 is an oxide.

[0004] Step 2: Form a word line trench on the hard mask layer 207 on the storage area and the stacked structure below it. A sidewall structure 209 is formed on the sidewall of the word line trench. A tunneling oxide layer 210 is formed in the word line trench, and then a word line polysilicon layer 208 is formed to fill the word line trench, forming a structure as Figure 1 shown.

[0005] Step 4: Grind the word line polysilicon layer 208 to the hard mask layer 207 to form a structure as Figure 2 shown.

[0006] Step 5: Remove the hard mask layer 207 on the peripheral logic area and the stacked structure below it to form a peripheral logic area polysilicon layer 211 on the peripheral logic area, forming a structure as Figure 3 shown.

[0007] This method stops grinding on the hard mask layer 207 and cannot capture the EPD (grinding stop end point). There are problems such as differences in the thickness of the hard mask layer 207 in the wafer and within the wafer-to-wafer range (for example, there are differences in the thickness of the hard mask layer 207 on the storage area and the peripheral logic area of the same wafer, and there are differences in the thickness of the hard mask layer 207 between different wafers), and poor load effects. The etching windows of the peripheral logic area, the floating gate polysilicon layer 204, and the control gate polysilicon layer 206 are insufficient and difficult to cover, resulting in residues and damage. There are differences in load effects, resulting in the need to establish area connections between the storage area and the peripheral logic area for different products, which brings difficulties to the platform Inline (online) control.

[0008] To solve the above problems, a new method for manufacturing a flash memory device needs to be proposed. Summary of the Invention

[0009] In view of the above-mentioned disadvantages of the prior art, the object of the present invention is to provide a method for manufacturing a flash memory device, which is used to solve the problem in the prior art that due to the difference in the load effect, the area connection between the storage area and the peripheral logic area needs to be established for different products, which brings difficulties to the platform Inline (online) control.

[0010] To achieve the above object and other related objects, the present invention provides a method for manufacturing a flash memory device, including:

[0011] Step 1: Provide a substrate, the substrate includes a storage area, a carrier tape area and a peripheral logic area, and form a stacked structure on the storage area and the peripheral logic area, the stacked structure is composed of a coupling layer, a floating gate polysilicon layer, an inter-pole dielectric layer, and a control gate polysilicon layer stacked in sequence from bottom to top;

[0012] Step 2: Form a first ONO layer on the control gate polysilicon layer, the first ONO layer is composed of a first oxide layer, a first nitride layer, and a second oxide layer stacked in sequence from bottom to top;

[0013] Step 3: Form a word line trench on the first ONO layer on the storage area and the stacked structure below it, form a tunneling oxide layer in the word line trench, and then form a word line polysilicon layer that fills the word line trench and covers the first ONO layer;

[0014] Step 4: Grind the word line polysilicon layer and the second oxide layer below it to the first nitride layer or a reserved part of the first nitride layer;

[0015] Step 5: Remove the etch stop layer.

[0016] Preferably, a shallow trench isolation is formed on the substrate in step 1 to define the active area.

[0017] Preferably, the coupling layer in step 1 is an oxide layer.

[0018] Preferably, the inter-pole dielectric layer in step 1 is a second ONO layer, and the second ONO layer is composed of a third oxide layer, a second nitride layer, and a fourth oxide layer stacked in sequence from bottom to top.

[0019] Preferably, the first oxide layer in step 2 is formed by the method of furnace tube thermal oxidation.

[0020] Preferably, the nitride layer and the second oxide layer in step 2 are grown by chemical vapor deposition or furnace tube method.

[0021] Preferably, the method for forming the word line trench in step three includes: etching the ONO layer in the storage area to form a first trench; forming a first sidewall structure in the first trench, the first sidewall structure covering the sidewalls of the first trench; etching the control gate polysilicon layer and the inter-pole dielectric layer on the bottom wall of the first trench to form a second trench; forming a second sidewall structure in the second trench, the second sidewall structure covering a part of the sidewalls of the second trench; etching the floating gate polysilicon layer and the coupling layer on the bottom wall of the second trench to form a third trench; forming the tunneling oxide layer, the tunneling oxide layer covering the bottom wall and the sidewalls of the third trench.

[0022] Preferably, the method for grinding in step four is chemical mechanical planarization grinding.

[0023] Preferably, the first nitride layer is removed by wet etching in step five.

[0024] Preferably, the first nitride layer is removed by a phosphoric acid solution in step five.

[0025] As described above, the manufacturing method of the flash memory device of the present invention has the following beneficial effects:

[0026] By controlling the grinding, the present invention can stably stop on the first nitride layer. The previous first oxide layer is grown in a furnace tube and has a flat pattern, avoiding the influence of etching non-uniformity caused by the previous layer, improving the grinding thickness difference and the loading effect, creating a relatively stable previous layer, and having better thickness uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of depositing a word line polysilicon layer shown as the prior art;

[0028] Figure 2 Schematic diagram of grinding a word line polysilicon layer shown as the prior art;

[0029] Figure 3 Schematic diagram of etching to remove the stacked structure in the peripheral logic area and forming a polysilicon layer in the peripheral logic area shown as the prior art;

[0030] Figure 4 Schematic diagram of the process flow of the present invention;

[0031] Figure 5 Schematic diagram of forming the first ONO layer of the present invention;

[0032] Figure 6 Schematic diagram of forming a tunneling oxide layer in the word line trench of the present invention;

[0033] Figure 7 Schematic diagram of depositing a word line polysilicon layer of the present invention;

[0034] Figure 8 It shows a schematic diagram of the polished word line polysilicon layer of the present invention;

[0035] Figure 9 It shows a schematic diagram of removing the first nitride layer of the present invention. Specific embodiments

[0036] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] Please refer to Figure 4 , the present invention provides a method for manufacturing a flash memory device, including:

[0038] Step 1: Provide a substrate 101. The substrate 101 includes a storage area, a carrier tape area, and a peripheral logic area. A stacked structure is formed on the storage area and the peripheral logic area. The stacked structure is composed of a coupling layer 102, a floating gate polysilicon layer 104, an inter-pole dielectric layer 105, and a control gate polysilicon layer 106 stacked in sequence from bottom to top;

[0039] In some embodiments, a shallow trench isolation 103 is formed on the substrate 101 in Step 1 to define an active area.

[0040] In some embodiments, the coupling layer 102 in Step 1 is an oxide layer.

[0041] In some embodiments, the inter-pole dielectric layer 105 in Step 1 is a second ONO layer. The second ONO layer is composed of a third oxide layer, a second nitride layer (usually silicon nitride), and a fourth oxide layer stacked in sequence from bottom to top.

[0042] Step 2: Form a first ONO layer on the control gate polysilicon layer 106. The first ONO layer is composed of a first oxide layer 107, a first nitride layer 108, and a second oxide layer 109 stacked in sequence from bottom to top, forming a structure as Figure 5 shown;

[0043] In some embodiments, the first oxide layer 107 in Step 2 is formed by a furnace tube thermal oxidation method, with better thickness stability and better etching uniformity for the subsequent floating gate polysilicon layer 104 and control gate polysilicon layer 106 in the peripheral logic area.

[0044] In some embodiments, the nitride layer and the second oxide layer 109 in Step 2 are grown by chemical vapor deposition or furnace tube method.

[0045] Step 3: Form word line trenches on the first ONO layer on the storage area and the stacked structure below it. During the formation of the word line trenches, sidewalls 110 are usually formed on the sidewalls of the trenches. A tunneling oxide layer 111 is formed in the word line trenches (formed by deposition and back-etching, remaining on the sidewalls of the trenches or on the sidewalls and the bottom of the trenches), forming a structure as shown in Figure 6 Figure []. After that, a word line polysilicon layer 112 that fills the word line trenches and covers the first ONO layer is formed, forming a structure as shown in Figure 7 Figure [].

[0046] In some embodiments, the method for forming the word line trenches in Step 3 includes: etching the ONO layer of the storage area to form a first trench; forming a first sidewall structure in the first trench, the first sidewall structure covering the sidewalls of the first trench; etching the control gate polysilicon layer 106 and the inter-pole dielectric layer 105 on the bottom wall of the first trench to form a second trench; forming a second sidewall structure in the second trench, the second sidewall structure covering part of the sidewalls of the second trench; etching the floating gate polysilicon layer 104 and the coupling layer 102 on the bottom wall of the second trench to form a third trench; forming a tunneling oxide layer 111, the tunneling oxide layer 111 covering the bottom wall and the sidewalls of the third trench.

[0047] Step 4: Grind the word line polysilicon layer 112 and the second oxide layer 109 below it to the first nitride layer 108 or a reserved partial thickness of the first nitride layer 108. The grinding stops at the first nitride layer 108, creating a relatively stable front layer for subsequent etching (ET), with better thickness uniformity, significantly improving the chemical mechanical planarization grinding uniformity and the etching non-uniformity (Loading) effect.

[0048] In some embodiments, the grinding method in Step 4 is chemical mechanical planarization grinding.

[0049] Step 5: Remove the first nitride layer 108.

[0050] In some embodiments, the first nitride layer 108 is removed by wet etching in Step 5.

[0051] In some embodiments, the first nitride layer 108 is removed using a phosphoric acid solution in Step 5, which does not add a silicon nitride removal process and also saves the original wet process, increasing the etching window for the peripheral logic area (PERI) and the etching of the floating gate polysilicon layer 104 and the control gate polysilicon layer 106. The remaining oxide layer is grown in a furnace tube, with better thickness stability, and leaving better etching uniformity for the floating gate polysilicon layer 104 and the control gate polysilicon layer 106 in the peripheral logic area.

[0052] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0053] In summary, the present invention can stably stop on the first nitride layer through control of grinding. The previous first oxide layer is grown in a furnace tube and has a flat pattern, avoiding the influence of etching non-uniformity caused by the previous layer, improving the grinding thickness difference and load effect, creating a relatively stable previous layer, and having good thickness uniformity. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0054] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a flash memory device, characterized in that: At least: Step 1, providing a substrate, wherein the substrate comprises a storage area, a carrier area and a peripheral logic area, and forming a stacked structure on the storage area and the peripheral logic area, wherein the stacked structure consists of a coupling layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, and a control gate polysilicon layer stacked in sequence from bottom to top; Step 2: forming a first ONO layer on the control gate polysilicon layer, wherein the first ONO layer is composed of a first oxide layer, a first nitride layer, and a second oxide layer stacked sequentially from bottom to top; Step 3: forming a word line trench on the first ONO layer on the storage area and the stacked structure thereunder, forming a tunneling oxide layer in the word line trench, and then forming a word line polysilicon layer filling the word line trench and covering the first ONO layer; Step 4, grinding the word line polysilicon layer and the second oxide layer thereunder to the first nitride layer or reserving a portion of the thickness of the first nitride layer; Step five: removing the first nitride layer.

2. The method for manufacturing a flash memory device according to claim 1, wherein: In step 1, shallow trench isolation is formed on the substrate to define an active area.

3. The method for manufacturing a flash memory device according to claim 1, wherein: The coupling layer in step 1 is an oxide layer.

4. The method for manufacturing a flash memory device according to claim 1, wherein: The inter-electrode dielectric layer in step 1 is a second ONO layer, and the second ONO layer is composed of a third oxide layer, a second nitride layer, and a fourth oxide layer stacked in sequence from bottom to top.

5. The method for manufacturing a flash memory device according to claim 1, wherein: The first oxide layer in step 2 is formed by thermal oxidation of a furnace tube.

6. The method for manufacturing a flash memory device according to claim 1, wherein: The nitride layer and the second oxide layer in step 2 are grown by chemical vapor deposition or furnace tube method.

7. The method for manufacturing a flash memory device according to claim 1, wherein: The method for forming the word line groove in step three includes: etching the ONO layer of the storage area to form a first groove; forming a first sidewall structure in the first groove, the first sidewall structure covering the sidewall of the first groove; etching the control gate polysilicon layer and the inter-electrode dielectric layer at the bottom wall of the first groove to form a second groove; forming a second sidewall structure in the second groove, the second sidewall structure covering part of the sidewall of the second groove; etching the floating gate polysilicon layer and the coupling layer at the bottom wall of the second groove to form a third groove; forming the tunneling oxide layer, the tunneling oxide layer covering the bottom wall and sidewall of the third groove.

8. The method for manufacturing a flash memory device according to claim 1, wherein: The grinding method in step 4 is chemical mechanical planarization grinding.

9. The method for manufacturing a flash memory device according to claim 1, wherein: In step five, the first nitride layer is removed by wet etching.

10. The method for manufacturing a flash memory device according to claim 9, wherein: In step five, a phosphoric acid solution is used to remove the first nitride layer.

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