Three-dimensional memory device and manufacturing method thereof

Abstract

The invention relates to a three-dimensional memory device and a manufacturing method thereof. In an embodiment of the disclosed technology, a three-dimensional memory device includes: a stack including a plurality of gate electrodes, each gate electrode including an electrode portion and a pad portion, the pad portion being disposed on one region of the electrode portion, and a plurality of interlayer insulating layers alternately stacked with the plurality of gate electrodes, the stack having a connection region, wherein the pad portions of the plurality of gate electrodes are disposed in a stepped shape; a row connection contact passing through the connection region and passing through a corresponding pad portion of a corresponding gate electrode among the plurality of gate electrodes so as to be connected to the corresponding pad portion of the corresponding gate electrode; and a plurality of first insulating patterns disposed between the row connection contact and a side surface of the electrode portion of the gate electrode facing the row connection contact.

Description

Technical Field

[0001] Various embodiments of the disclosed technology generally relate to semiconductor technology, and more particularly, to a three-dimensional memory device and a method of manufacturing the same. Background Art

[0002] Three-dimensional memory devices including three-dimensionally arranged memory cells have been proposed. The advantage of three-dimensional memory devices is that by stacking memory cells in the vertical direction to increase the stacking number, a larger capacity can be achieved within the same area, thereby providing high performance and excellent power efficiency. Summary of the Invention

[0003] In an embodiment, a three-dimensional memory device may include: a stack including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked with the plurality of gate electrodes, each gate electrode including an electrode portion and a pad portion, the pad portion being disposed on an area of the electrode portion, the stack having a connection area, wherein the pad portions of the plurality of gate electrodes are disposed in a stepped shape; row connection contacts passing through the connection area and through corresponding pad portions of corresponding gate electrodes among the plurality of gate electrodes to connect to the corresponding pad portions of the corresponding gate electrodes; and a plurality of first insulating patterns disposed between the row connection contacts and side surfaces of the electrode portions of the gate electrodes facing the row connection contacts.

[0004] In an embodiment, a method of manufacturing a three-dimensional memory device may include the steps of: forming a pre-stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers; forming a stepped structure in the pre-stack; forming a plurality of sacrificial patterns on an upper surface of the stepped structure; forming a plurality of first holes passing through the sacrificial patterns and the pre-stack; selectively forming a plurality of first insulating patterns on side surfaces of the plurality of sacrificial layers exposed due to the plurality of first holes; and forming a plurality of gate electrodes by replacing the plurality of sacrificial layers and the plurality of sacrificial patterns with an electrode material via the plurality of first holes, and forming a plurality of row connection contacts in the plurality of first holes.

[0005] In an embodiment, a three-dimensional memory device may include: a first semiconductor structure including a peripheral circuit; and a second semiconductor structure disposed on the first semiconductor structure, the second semiconductor structure including: a source plate disposed on the first semiconductor structure; a stack disposed on the source plate, the stack including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked with the plurality of gate electrodes, each gate electrode including an electrode portion and a pad portion, the pad portion being disposed on a region of the electrode portion, the stack having a connection region, wherein the pad portions of the plurality of gate electrodes are disposed in a stepped shape; row connection contacts passing through the connection region and through the corresponding pad portions of the corresponding gate electrodes among the plurality of gate electrodes to connect to the corresponding pad portions of the corresponding gate electrodes; and a plurality of first insulating patterns disposed between the row connection contacts and side surfaces of the electrode portions of the gate electrodes facing the row connection contacts.

[0006] In an embodiment, a three-dimensional memory device may include: a first semiconductor structure having a peripheral circuit and including a first bonding layer including a plurality of first bonding pads connected to the peripheral circuit; and a second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure including: a second bonding layer including a plurality of second bonding pads bonded to the plurality of first bonding pads; a stack disposed on the second bonding layer, the stack including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked with the plurality of gate electrodes, each gate electrode including an electrode portion and a pad portion, the pad portion being disposed on a region of the electrode portion, the stack having a connection region, wherein the pad portions of the plurality of gate electrodes are disposed in a stepped shape; row connection contacts passing through the connection region and through the corresponding pad portions of the corresponding gate electrodes among the plurality of gate electrodes to connect to the corresponding pad portions of the corresponding gate electrodes; and a plurality of first insulating patterns disposed between the row connection contacts and side surfaces of the electrode portions of the gate electrodes facing the row connection contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view showing a part of a three-dimensional memory device according to an embodiment of the disclosed technology.

[0008] Figure 2 is along Figure 1 taken along line A-A' and B-B' of.

[0009] Figure 3 is along Figure 1 taken along line C-C' of.

[0010] Figure 4 is Figure 2 an enlarged view of part P1 of.

[0011] Figure 5 isFigure 2 An enlarged view of part P2.

[0012] Figure 6 is Figure 2 An enlarged view of part P3.

[0013] Figures 7A to 7H is a diagram showing a method of manufacturing a three-dimensional memory device according to an embodiment based on the disclosed technology.

[0014] Figure 8 and Figure 9 is a cross-sectional view of a three-dimensional memory device according to an embodiment based on the disclosed technology. DETAILED DESCRIPTION

[0015] In the following description, although shown in different drawings, the same elements will be referred to by the same reference numerals. Further, in the following description of the present disclosure, when the subject matter of the present disclosure may be unclear, detailed descriptions of known functions and configurations included herein will be omitted. It should be noted that, unless specifically stated otherwise, the terms "comprising", "having", "including", etc. used in the specification and claims should not be construed as being limited to the means listed thereafter. When an indefinite article or a definite article (e.g., "a", "an", and "the") is used in reference to a singular noun, this may include the plural of the noun unless specifically stated otherwise.

[0016] In addition, when describing components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only for distinguishing one component from another, and do not limit the substance, order, sequence, or quantity of the components.

[0017] In the description of the positional relationship of components, when describing that at least two components are "connected", "coupled", or "linked", it will be understood that at least two components may be directly "connected", "coupled", or "linked", but may be indirectly "connected", "coupled", or "linked" when another component is interposed between the two components. Here, the another component may be included in at least one of the at least two components that are "connected", "coupled", or "linked" to each other.

[0018] In the description of the temporal flow relationship of components, operation methods, or manufacturing methods, when the temporal front-back relationship or the process front-back relationship is described, for example, by "after", "subsequently", "next", or "before", non-consecutive cases may be included unless "immediately" or "directly" is used.

[0019] In the case of referring to the numerical values of components or their corresponding information, even without a separate explicit description, the numerical values or their corresponding information may be interpreted as including an error range that can be caused by various factors (e.g., process variables, internal or external shocks, noise, etc.).

[0020] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0021] Various embodiments of the disclosed technology are directed to providing a three-dimensional memory device including contacts passing through gate electrodes and a method of manufacturing the same.

[0022] According to an embodiment of the disclosed technology, a row connection contact passing through a gate electrode can be easily connected to a corresponding gate electrode.

[0023] Figure 1 is a schematic plan view of a three-dimensional memory device based on an embodiment of the disclosed technology.

[0024] Referring to Figure 1 , a three-dimensional memory device based on an embodiment of the disclosed technology may include a stack ST. The stack ST may include a cell region CAR and a connection region CNR extending from the cell region CAR.

[0025] As will be described later with reference to Figure 2 , the stack ST may include a plurality of vertically stacked gate electrodes. The plurality of gate electrodes may include a plurality of word lines and selection lines. The selection lines may include drain selection lines and source selection lines.

[0026] First isolation patterns S1 may be disposed on both sides of the stack ST. The first isolation patterns S1 may extend in a first direction FD and may be adjacent to each other in a second direction SD that intersects the first direction FD. The first direction FD and the second direction SD may intersect perpendicularly to each other. The first direction FD may be an extending direction of the word lines, and the second direction SD may be an extending direction of the bit lines. The stack ST may be stacked in a third direction perpendicular to both the first direction FD and the second direction SD. The term "vertical" may refer to the third direction.

[0027] Although only two first isolation patterns S1 and one stack ST are shown in the figure, a plurality of stacks may be arranged in the second direction SD, and the first isolation patterns S1 may be disposed between two adjacent stacks to isolate the stacks.

[0028] The second isolation pattern S2, the third isolation pattern S3, and the drain select line cut DLC can be configured in the stack ST. The second isolation pattern S2 and the drain select line cut DLC can extend from the cell region CAR to the connection region CNR in the first direction FD. The second isolation pattern S2 can vertically penetrate the stack ST. The drain select line cut DLC can be disposed between adjacent drain select lines. Due to the second isolation pattern S2 and the drain select line cut DLC, the drain select lines can be isolated from each other.

[0029] The third isolation pattern S3 can vertically penetrate the stack ST. The third isolation pattern S3 can extend in the first direction FD in the connection region CNR.

[0030] A plurality of row connection contacts RCT can vertically penetrate the connection region CNR of the stack ST. Each row connection contact RCT can be connected to a corresponding gate electrode to transmit an operating voltage to the gate electrode.

[0031] A plurality of vias TCT can vertically penetrate the stack ST. The vias TCT can provide vertical interconnects that vertically penetrate the three-dimensional memory cell array to help reduce the metal level and decrease the die size. Although Figure 1 the vias TCT are shown passing through the connection region CNR of the stack ST, the position of the vias TCT is not limited thereto. Although not shown, the vias TCT can pass through the cell region CAR of the stack ST.

[0032] The support SS can vertically penetrate the stack ST. The support SS can be used to support the stack ST to prevent the stack ST from collapsing or bending.

[0033] A plurality of cell plugs CP can vertically penetrate the cell region CAR of the stack ST. The plurality of cell plugs CP can be arranged in multiple rows in the second direction SD. The cell plugs CP in each odd row can be offset in the same first direction FD relative to the cell plugs CP in the even rows. Due to this fact, a larger number of cell plugs CP can be arranged within the same area.

[0034] Figure 2 is a cross-sectional view taken along Figure 1 lines A-A' and B-B', Figure 3 is a cross-sectional view taken along Figure 1 lines C-C'.

[0035] Referring to Figure 2 and Figure 3 , the stack ST can include a plurality of interlayer insulating layers 20 and a plurality of gate electrodes 40 alternately stacked on the source electrode plate 10.

[0036] Each of the plurality of gate electrodes 40 may include an electrode portion 41 and a pad portion 42, and the pad portion 42 is disposed on a region of the electrode portion 41. The electrode portion 41 may extend from the cell region CAR of the stack ST to the connection region CNR. In the connection region CNR, the end of the electrode portion 41 of the gate electrode 40 may be provided in a stepped shape. Specifically, referring to Figure 2 , when viewed from left to right, a descending stepped shape may be formed. The pad portion 42 may be disposed on the end of the electrode portion 41. In the connection region CNR, since the pad portion 42 of the gate electrode 40 is provided in a stepped shape, when viewed from left to right, the stepped structure may be configured to ascend.

[0037] The gate electrode 40 may include a plurality of word lines, source selection lines, and drain selection lines. For example, at least one gate electrode 40 starting from the lowermost layer among the plurality of gate electrodes 40 may be used as a source selection line, at least one gate electrode 40 starting from the uppermost layer among the plurality of gate electrodes 40 may be used as a drain selection line, and the gate electrode 40 between the source selection line and the drain selection line may be used as a word line.

[0038] The gate electrode 40 may include a conductive material. For example, the gate electrode 40 may include tungsten (W). The interlayer insulating layer 20 may include silicon oxide.

[0039] The insulating layer 60 may be defined on the stack ST to cover the stack ST. The insulating layer 60 may include an oxide. Except for the stepped structure portion of the stack ST, the sacrificial pattern 50 may be disposed between the stack ST and the insulating layer 60. The sacrificial pattern 50 may include an insulating material having an etching selectivity different from the etching selectivities of the interlayer insulating layer 20 and the insulating layer 60. For example, the sacrificial pattern 50 may include SiCN.

[0040] The cell plug CP may extend to the source plate 10 by vertically passing through the insulating layer 60, the sacrificial pattern 50, and the stack ST. The cell plug CP may include a memory pattern 80 and a channel structure 90.

[0041] Although not shown, the memory pattern 80 may include a tunnel insulating layer, a data storage layer, and a first blocking insulating layer. The tunnel insulating layer may extend along the surface of the channel structure 90 and may include an insulating material capable of charge tunneling. The data storage layer may extend along the surface of the channel structure 90, and the tunnel insulating layer is interposed therebetween. The data storage layer may include a material layer capable of storing data changed using Fowler-Nordheim tunneling. For example, the data storage layer may include a nitride layer capable of charge trapping, but the data storage layer is not limited thereto. The data storage layer may include a phase change material, nanodots, etc. The first blocking insulating layer may extend along the surface of the channel structure 90, and the tunnel insulating layer and the data storage layer are interposed therebetween. The first blocking insulating layer may include an insulating material capable of blocking the movement of charges.

[0042] The channel structure 90 may include a unit channel layer 91, a core insulation pattern 92, and a capping pattern 93. The unit channel layer 91 may serve as a channel of a memory cell string. The unit channel layer 91 may be disposed on the memory pattern 80 and may be formed of a semiconductor material. For example, the unit channel layer 91 may include silicon. The core insulation pattern 92 and the capping pattern 93 may fill a central region of the channel structure 90. The core insulation pattern 92 may include an oxide. The capping pattern 93 may be disposed on the core insulation pattern 92 and may include sidewalls surrounded by an upper end portion of the unit channel layer 91. The capping pattern 93 may include a doped semiconductor layer including at least one of an n-type impurity and a p-type impurity.

[0043] A plurality of row connection contacts RCT may vertically penetrate the insulating layer 60 and the stack ST. Each row connection contact RCT may penetrate a pad portion 42 and an electrode portion 41 of one of the plurality of gate electrodes 40, and may penetrate the electrode portion 41 of the gate electrode 40 located below the one gate electrode 40. The row connection contact RCT may be connected to the pad portion 42 of the one gate electrode 40 and may be integrally formed with the one gate electrode 40.

[0044] A first insulation pattern DP1 may be disposed between the row connection contact RCT and a side surface of the electrode portion 41 of the gate electrode 40 facing the row connection contact RCT. The row connection contact RCT may be electrically isolated from the gate electrode 40 below the one gate electrode 40 through the first insulation pattern DP1.

[0045] The row connection contact RCT may be made of the same material as the gate electrode 40. As will be described later with reference to Figure 7H The row connection contact RCT may be formed together with the gate electrode 40 in a process of forming the gate electrode 40. Therefore, the material for forming the row connection contact RCT may be the same as the material for forming the gate electrode 40.

[0046] As will be described later with reference to Figure 7C The first insulation pattern DP1 may be selectively deposited on the sacrificial layer 22 and may be made of an insulating material having an etching selectivity different from that of the sacrificial layer 22 and the sacrificial pattern 50. For example, the first insulation pattern DP1 may be made of SiOC.

[0047] The via contact TCT may vertically penetrate the insulating layer 60, the sacrificial pattern 50, and the stack ST. The via contact TCT may penetrate the electrode portion 41 of the gate electrode 40.

[0048] A second insulation pattern DP2 may be disposed between the via contact TCT and a side surface of the electrode portion 41 of the gate electrode 40 facing the via contact TCT. Due to the second insulation pattern DP2, the via contact TCT may be electrically isolated from the gate electrode 40.

[0049] The through contact TCT can be made of the same material as the row connection contact RCT and the gate electrode 40. As will be described later with reference to Figure 7H the through contact TCT can be formed together with the row connection contact RCT and the gate electrode 40 in the process of forming the row connection contact RCT and the gate electrode 40. Therefore, the material for forming the through contact TCT can be the same as the material for forming the row connection contact RCT and the gate electrode 40.

[0050] The second insulating pattern DP2 can be made of the same material as the first insulating pattern DP1. As will be described later with reference to Figure 7C the second insulating pattern DP2 can be formed together with the first insulating pattern DP1 in the process of forming the first insulating pattern DP1. Therefore, the material for forming the second insulating pattern DP2 can be the same as the material for forming the first insulating pattern DP1.

[0051] The support SS can vertically pass through the insulating layer 60, the sacrificial pattern 50, and the stack ST. The support SS can pass through the electrode portion 41 of the gate electrode 40.

[0052] The support SS can include an insulating material with an etching selectivity different from that of the hard mask HM (described later with reference to Figure 7D the etching selectivity of the sacrificial layer 22. The support SS can be configured as a single layer. Although not shown, in another embodiment, the support SS can include a liner layer and a filling layer. The liner layer can extend along the surface of the support SS, and the filling layer can be disposed in the central region of the support SS. The liner layer can include a nitride, and the filling layer can include an oxide.

[0053] The third insulating pattern DP3 can be disposed between the support SS and the side surface of the electrode portion 41 of the gate electrode 40 facing the support SS.

[0054] The third insulating pattern DP3 can be made of the same material as the first insulating pattern DP1 and the second insulating pattern DP2. As will be described later with reference to Figure 7C the third insulating pattern DP3 can be formed together with the first insulating pattern DP1 and the second insulating pattern DP2 in the process of forming the first insulating pattern DP1 and the second insulating pattern DP2. Therefore, the material for forming the third insulating pattern DP3 can be the same as the material for forming the first insulating pattern DP1 and the second insulating pattern DP2.

[0055] The second barrier insulating layer 30 may be formed along the surfaces of the gate electrode 40, the row connection contact RCT, the via contact TCT, and the first insulating pattern DP1 and the second insulating pattern DP2. The second barrier insulating layer 30 may surround the outer surfaces of the integrally formed row connection contact RCT and the gate electrode 40. The second barrier insulating layer 30 may include an insulating material having a dielectric constant higher than that of the first barrier insulating layer of the memory pattern 80. For example, the first barrier insulating layer may include silicon oxide, and the second barrier insulating layer 30 may include a metal oxide such as aluminum oxide.

[0056] The first isolation pattern S1 may vertically penetrate the insulating layer 60 and the stack ST. The first isolation pattern S1 may include a sidewall insulating layer 71 and a conductive vertical contact 72. The conductive vertical contact 72 may be disposed in the central region of the first isolation pattern S1. Due to the sidewall insulating layer 71, the conductive vertical contact 72 may be insulated from the plurality of gate electrodes 40. The conductive vertical contact 72 may include a doped semiconductor layer. The conductive vertical contact 72 may be used as a common source line.

[0057] An opening may be defined in the source plate 10, and the insulating patterns 11A and 11B may be disposed in the opening. A first conductive contact plug DCC1 passing through the insulating pattern 11A may be formed under the via contact TCT to connect to the via contact TCT. Although the disclosed technology shows a case where a conductive contact plug connected to the row connection contact RCT is not configured, if necessary, a conductive contact plug passing through the insulating pattern 11B may be formed under the row connection contact RCT to connect to the row connection contact RCT.

[0058] Figure 4 is Figure 2 an enlarged view of a portion P1 of Figure 5 is Figure 2 an enlarged view of a portion P2 of Figure 6 is Figure 2 an enlarged view of a portion P3 of

[0059] Referring to Figure 4 , the first insulating pattern DP1 may have a first surface F1a facing the electrode portion 41 and a second surface F2a facing the row connection contact RCT. The interlayer insulating layer 20 may have a first side surface F3a facing the row connection contact RCT. The first surface F1a of the first insulating pattern DP1 may be aligned with the first side surface F3a of the interlayer insulating layer 20.

[0060] As will be described later with reference to Figure 7B and Figure 7C , a first hole H1 may be formed through the alternately stacked plurality of interlayer insulating layers 20 and the plurality of sacrificial layers 22, and the first insulating pattern DP1 may be formed on the side surfaces of the sacrificial layer 22 defined by the first hole H1.

[0061] Refer again to Figure 4 , the first side surface F3a of the interlayer insulating layer 20 may be a surface defined by the first hole H1 (see Figure 7B ). The first side surface F3a of the interlayer insulating layer 20 may be disposed on the same surface as the side surface of the sacrificial layer 22 on which the first insulating pattern DP1 is formed (see Figure 7B ). Accordingly, the first surface F1a of the first insulating pattern DP1 may be aligned with the first side surface F3a of the interlayer insulating layer 20. The second surface F2a of the first insulating pattern DP1 may include a curved surface.

[0062] The second barrier insulating layer 30 may be disposed between the first surface F1a of the first insulating pattern DP1 and the electrode portion 41. The second barrier insulating layer 30 may be disposed between the second surface F2a of the first insulating pattern DP1 and the row connection contact RCT. The second barrier insulating layer 30 may be disposed between the first side surface F3a of the interlayer insulating layer 20 and the row connection contact RCT.

[0063] Refer to Figure 5 , the second insulating pattern DP2 may have a first surface F1b facing the electrode portion 41 and a second surface F2b facing the via contact TCT. The interlayer insulating layer 20 may have a second side surface F3b facing the via contact TCT. The first surface F1b of the second insulating pattern DP2 may be aligned with the second side surface F3b of the interlayer insulating layer 20.

[0064] As will be described later with reference to Figure 7B and Figure 7C , a second hole H2 may be formed through the alternately stacked plurality of interlayer insulating layers 20 and the plurality of sacrificial layers 22, and the second insulating pattern DP2 may be formed on the side surface of the sacrificial layer 22 defined by the second hole H2.

[0065] Refer again to Figure 5 , the second side surface F3b of the interlayer insulating layer 20 may be a surface defined by the second hole H2 (see Figure 7B ). The second side surface F3b of the interlayer insulating layer 20 may be disposed on the same surface as the side surface of the sacrificial layer 22 on which the second insulating pattern DP2 is formed (see Figure 7B ). Accordingly, the first surface F1b of the second insulating pattern DP2 may be aligned with the second side surface F3b of the interlayer insulating layer 20. The second surface F2b of the second insulating pattern DP2 may include a curved surface.

[0066] The second barrier insulating layer 30 may be disposed between the first surface F1b of the second insulating pattern DP2 and the electrode portion 41. The second barrier insulating layer 30 may be disposed between the second surface F2b of the second insulating pattern DP2 and the via contact TCT. The second barrier insulating layer 30 may be disposed between the second side surface F3b of the interlayer insulating layer 20 and the via contact TCT.

[0067] Refer to Figure 6 Figure 6 , the third insulating pattern DP3 may have a first surface F1c facing the electrode portion 41 and a second surface F2c facing the support SS. The interlayer insulating layer 20 may have a third side surface F3c facing the support SS. The first surface F1c of the third insulating pattern DP3 may be aligned with the third side surface F3c of the interlayer insulating layer 20.

[0068] As will be referred to later Figure 7B and Figure 7C Figure 7C described, a third hole H3 may be formed through the plurality of interlayer insulating layers 20 and the plurality of sacrificial layers 22 that are alternately stacked, and the third insulating pattern DP3 may be formed on the side surface of the sacrificial layer 22 defined by the third hole H3.

[0069] Refer again to Figure 6 Figure 6 , the third side surface F3c of the interlayer insulating layer 20 may be a surface defined by the third hole H3 (see Figure 7B )). The third side surface F3c of the interlayer insulating layer 20 may be disposed on the same surface as the side surface of the sacrificial layer 22 on which the third insulating pattern DP3 is formed (see Figure 7B Figure 7B ). Therefore, the first surface F1c of the third insulating pattern DP3 may be aligned with the third side surface F3c of the interlayer insulating layer 20. The second surface F2c of the third insulating pattern DP3 may include a curved surface.

[0070] The second barrier insulating layer 30 may be disposed between the first surface F1c of the third insulating pattern DP3 and the electrode portion 41. The second barrier insulating layer 30 may not be disposed between the second surface F2c of the third insulating pattern DP3 and the support SS and between the third side surface F3c of the interlayer insulating layer 20 and the support SS.

[0071] Hereinafter, a method of manufacturing a three-dimensional memory device according to an embodiment of the disclosed technology will be described.

[0072] Figures 7A to 7H Figures 7A to 7H is a diagram showing a method of manufacturing a three-dimensional memory device according to an embodiment of the disclosed technology.

[0073] Refer to Figure 7A Figure 7A , a plurality of interlayer insulating layers 20 and a plurality of sacrificial layers 22 may be alternately stacked on the source electrode plate 10. The interlayer insulating layer 20 may include silicon oxide. The sacrificial layer 22 may include a material having an etching selectivity different from that of the interlayer insulating layer 20, for example, a nitride such as silicon nitride.

[0074] Thereafter, a pre-stack PS can be formed by patterning the interlayer insulating layer 20 and the sacrificial layer 22. The pre-stack PS can have a stepped shape. Hereinafter, the portion having the stepped shape may be referred to as a stepped portion. The step can be defined as the portion that is not covered by the upper layer and thus is exposed in the stepped portion. The step can include an upper step surface and a vertical sidewall connected to the upper step surface, and the vertical sidewall extends downward from the upper step surface.

[0075] Thereafter, by conformally forming a sacrificial material layer on the pre-stack PS and patterning the sacrificial material layer, sacrificial patterns 50 can be formed on the upper surface (upper step surface) of the step. As shown, each of the sacrificial patterns 50 can be spaced apart from the vertical sidewall of the upper step connected to the step on which the corresponding sacrificial pattern 50 is formed. The sacrificial pattern 50 can include an insulating material having an etching selectivity different from the etching selectivities of the sacrificial layer 22 and the interlayer insulating layer 20. For example, the sacrificial pattern 50 can include SiCN.

[0076] Thereafter, an insulating layer 60 can be formed to cover the pre-stack PS and the sacrificial patterns 50, and the upper surface of the insulating layer 60 can be planarized.

[0077] Referring to Figure 7B , by forming an etching mask (not shown) on the insulating layer 60 and etching the insulating layer 60, the sacrificial patterns 50, and the pre-stack PS using the etching mask, first holes H1 to third holes H3 and a slit SLT can be formed.

[0078] The first hole H1 can vertically extend through the upper step surface of the stepped portion of the pre-stack PS. The second hole H2 and the third hole H3 can vertically extend through the non-stepped portion of the pre-stack PS.

[0079] The slit SLT can have a line shape. The pre-stack PS can be divided by the slit SLT.

[0080] Referring to Figure 7C , a first insulating pattern DP1 can be selectively formed on the side surface of the sacrificial layer 22 exposed through the first hole H1. The first insulating pattern DP1 can be selectively deposited on the sacrificial layer 22 and can be made of an insulating material having an etching selectivity different from the etching selectivities of the sacrificial layer 22 and the sacrificial pattern 50. For example, the first insulating pattern DP1 can include SiOC.

[0081] When forming the first insulating pattern DP1, the second insulating pattern DP2 can be selectively formed on the side surface of the sacrificial layer 22 exposed through the second hole H2. When forming the first insulating pattern DP1, the third insulating pattern DP3 can be selectively formed on the side surface of the sacrificial layer 22 exposed through the third hole H3. When forming the first insulating pattern DP1, the fourth insulating pattern DP4 can be selectively formed on the side surface of the sacrificial layer 22 exposed through the slit SLT. The second insulating pattern DP2 to the fourth insulating pattern DP4 can be made of the same material as the first insulating pattern DP1.

[0082] Referring to Figure 7D , a hard mask HM covering the first hole H1 to the third hole H3 and the slit SLT can be formed on the insulating layer 60. The hard mask HM can cover the first hole H1 to the third hole H3 and the slit SLT, and can partially fill the upper parts of the slit SLT and the first hole H1 to the third hole H3.

[0083] Thereafter, a first opening OP1 exposing the third hole H3 can be formed in the hard mask HM, and a support SS can be formed in the third hole H3 and the first opening OP1. The support SS can include an insulating material with an etching selectivity different from the etching selectivities of the hard mask HM and the sacrificial layer 22.

[0084] Referring to Figure 7E , a second opening OP2 exposing the slit SLT can be formed in the hard mask HM, and the fourth insulating pattern DP4 formed on the side surface of the slit SLT can be removed (see Figure 7D ).

[0085] Referring to Figure 7F , the sacrificial layer 22 can be selectively removed to obtain a plurality of open electrode regions GR. The electrode regions GR can be vertically formed between vertically adjacent interlayer insulating layers 20 and between the sacrificial pattern 50 and the interlayer insulating layer 20 vertically adjacent to the sacrificial pattern 50.

[0086] The first insulating pattern DP1 to the third insulating pattern DP3 can be exposed through the electrode regions GR. Since the first insulating pattern DP1 to the third insulating pattern DP3 are made of a material with an etching selectivity different from the etching selectivity of the sacrificial layer 22, the first insulating pattern DP1 to the third insulating pattern DP3 will not be removed during the process of removing the sacrificial layer 22.

[0087] Referring to Figure 7G , a third opening OP3 exposing the first hole H1 can be formed in the hard mask HM, and the sacrificial pattern 50 around the first hole H1 can be removed to obtain a plurality of open pad regions PR. The pad regions PR can communicate with the first hole H1 and can extend horizontally from the first hole H1. The first hole H1 can communicate with the pad regions PR and the electrode regions GR.

[0088] Since the sacrificial pattern 50 around the slit SLT is removed in the process of forming the pad region PR, a dummy pad region DPR can be formed. The dummy pad region DPR can communicate with the slit SLT and can extend from the slit SLT in the horizontal direction. The slit SLT can communicate with the dummy pad region DPR.

[0089] Since the first insulating pattern DP1 to the third insulating pattern DP3 are made of a material with an etching selectivity different from that of the sacrificial pattern 50, the first insulating pattern DP1 to the third insulating pattern DP3 are not removed during the process of removing the sacrificial pattern 50.

[0090] Referring to Figure 7H , the hard mask HM can be removed. Therefore, Figure 7G the first hole H1 and the second hole H2 shown can be exposed.

[0091] Thereafter, a second barrier insulating layer 30 can be formed along the surfaces of the electrode region GR, the pad region PR, the dummy pad region DPR, the first hole H1, and the second hole H2 shown in Figure 7G . The second barrier insulating layer 30 is not formed between the pad region PR, the electrode region GR, and the first hole H1 that communicate with each other, and even after the second barrier insulating layer 30 is formed, the pad region PR, the electrode region GR, and the first hole H1 can communicate with each other.

[0092] The electrode region GR, the pad region PR, the first hole H1, and the second hole H2 can be filled with a conductive material, thereby allowing the electrode portion 41 of the gate electrode 40 to be formed in the electrode region GR, the pad portion 42 of the gate electrode 40 to be formed in the pad region PR, the row connection contact RCT to be formed in the first hole H1, and the via contact TCT to be formed in the second hole H2.

[0093] As described above, since the electrode region GR, the pad region PR, and the first hole H1 communicate with each other, the electrode portion 41 and the pad portion 42 of the gate electrode 40 and the row connection contact RCT can be integrally formed.

[0094] Since the slit SLT has a line shape, the slit SLT is not filled with the conductive material when the first hole H1 and the second hole H2 are filled with the conductive material.

[0095] Referring again to Figure 2 , a sidewall insulating layer 71 can be formed on the sidewall of the slit SLT. The process of forming the sidewall insulating layer 71 can include forming an insulating material on the entire surface including the slit SLT and exposing the bottom surface of the slit SLT by etching the insulating material.

[0096] A conductive vertical contact 72 can be formed by filling the slit SLT with a doped semiconductor material. The doped semiconductor material may include n-type impurities.

[0097] A three-dimensional memory device according to an embodiment of the disclosed technology can be provided as a peripheral under cell (PUC) structure or a peripheral on cell (POC) structure.

[0098] Figure 8 and Figure 9 is a cross-sectional view showing a three-dimensional memory device according to an embodiment of the disclosed technology.

[0099] Referring to Figure 8 , a three-dimensional memory device according to an embodiment of the disclosed technology can have a PUC structure. Specifically, the three-dimensional memory device may include a first semiconductor structure 100 and a second semiconductor structure 200, and the second semiconductor structure 200 is constructed on the first semiconductor structure 100. That is, after the first semiconductor structure 100 is first formed, the second semiconductor structure 200 can then be formed on the first semiconductor structure 100.

[0100] The second semiconductor structure 200 may include a memory cell array, and the first semiconductor structure 100 may include a peripheral circuit that controls the operation of the memory cell array. For example, the peripheral circuit may include a row decoder, a page buffer circuit, a voltage generator, a control circuit, etc., but the present disclosure is not limited thereto.

[0101] The first semiconductor structure 100 may include a substrate 110, a peripheral circuit 120, an insulating layer 130, a plurality of lower interconnects UM1 and UM2, and a plurality of lower contacts UMC.

[0102] The substrate 110 may include at least one of a single crystal silicon layer, SOI (silicon on insulator), a silicon layer formed on a silicon germanium (SiGe) layer, a single crystal silicon layer formed on an insulating layer, and a polysilicon layer formed on an insulating layer.

[0103] The peripheral circuit 120 may include a transistor TR. The transistor TR may include impurity regions Jn1 and Jn2, a gate insulating layer GI, and a gate electrode GE. The impurity regions Jn1 and Jn2 may be formed by doping impurities into the substrate 110. The channel region of the transistor TR may be configured between the impurity regions Jn1 and Jn2, and the gate insulating layer GI may be disposed on the channel region. The gate electrode GE may be disposed on the gate insulating layer GI. Although not shown, in addition to the transistor TR, the peripheral circuit 120 may further include any active or passive components, such as at least one of a diode, a resistor, and a capacitor.

[0104] The insulating layer 130 may be disposed on the substrate 110 to cover the transistor TR.

[0105] The lower interconnects UM1 and UM2 and the lower contacts UMC may be disposed in the insulating layer 130. For example, the lower interconnects UM1 and UM2 may include a first lower interconnect UM1 and a second lower interconnect UM2, and the second lower interconnect UM2 is disposed above the first lower interconnect UM1. Figure 8 The case where the lower interconnects UM1 and UM2 are disposed in two layers is shown, but embodiments of the disclosed technology are not limited thereto. The lower interconnects may be disposed in at least three layers.

[0106] The lower interconnects UM1 and UM2 may be configured to have the property of not exhibiting process defects (e.g., hillocks) at the highest temperature (hereinafter referred to as the "process critical temperature") during the process of forming the memory cell array. In other words, as the material for the lower interconnects UM1 and UM2, a conductive material having heat-resistant characteristics at the process critical temperature may be used. For example, the lower interconnects UM1 and UM2 may include a material having a melting point higher than the process critical temperature, such as tungsten (W). Since the lower interconnects UM1 and UM2 are formed before the memory cell array is formed, the lower interconnects UM1 and UM2 may be formed using a conductive material having a high resistivity but a high melting point.

[0107] The peripheral circuit 120 and the lower interconnects UM1 and UM2 may be connected to each other through the lower contacts UMC.

[0108] The second semiconductor structure 200 may be disposed on the insulating layer 130 of the first semiconductor structure 100. The second semiconductor structure 200 may include the three-dimensional memory device described above with reference to Figures 1 to 7H the description.

[0109] The first conductive contact plug DCC1 may be connected to the through contact TCT. Specifically, the lower end of the through contact TCT may be connected to the first conductive contact plug DCC1. The first conductive contact plug DCC1 may be connected to the lower interconnect UM2 by passing through the insulating pattern 11A and the insulating layer 130, and may be connected to the peripheral circuit 120 through the lower contact UMC, the lower interconnect UM1, and the lower interconnect UM2.

[0110] The second conductive contact plug DCC2 may be connected to the row connection contact RCT. Specifically, the lower end of the row connection contact RCT may be connected to the second conductive contact plug DCC2. The second conductive contact plug DCC2 may be connected to the lower interconnect UM2 by passing through the insulating pattern 11B and the insulating layer 130, and may be connected to the peripheral circuit 120 through the lower contact UMC, the lower interconnect UM1, and the lower interconnect UM2.

[0111] Refer to Figure 9, a three-dimensional memory device according to an embodiment of the disclosed technology may have a POC structure. In other words, the first semiconductor structure 100A and the second semiconductor structure 200A may be fabricated on different wafers and then joined to each other for connection.

[0112] Referring to Figure 9 , compared with the first semiconductor structure 100 Figure 8 , the first semiconductor structure 100A may further include a first bonding layer BNL1.

[0113] Specifically, the first semiconductor structure 100A may include a substrate 110, a peripheral circuit 120 defined on the substrate 110, a first bonding layer BNL1, and a plurality of lower interconnects UM1 and UM2 disposed between the substrate 110 and the first bonding layer BNL1.

[0114] An insulating layer 130 may be defined on the substrate 110 to cover the peripheral circuit 120. The plurality of lower interconnects UM1 and UM2 may be disposed in the insulating layer 130.

[0115] For example, the lower interconnects UM1 and UM2 may include at least one of aluminum (Al) and copper (Cu). Since the lower interconnects UM1 and UM2 are formed on a wafer separate from the memory cell array, the materials for configuring the lower interconnects UM1 and UM2 can be selected without considering the thermal budget of the process for forming the memory cell array. Aluminum (Al), copper (Cu), etc. with low resistivity can be selected as the materials for configuring the lower interconnects UM1 and UM2 so that the lower interconnects UM1 and UM2 can have low resistance.

[0116] The first bonding layer BNL1 may include a plurality of first bonding pads PBD and a first bonding insulating pattern 140 that insulates the first bonding pads PBD from each other. The first bonding pads PBD may be connected to the lower interconnects UM2 through lower contacts UMC.

[0117] Compared with Figure 8 the second semiconductor structure 200, the second semiconductor structure 200A may further include a second bonding layer BNL2, insulating layers 220 and 230, and a first upper interconnect M1 and a second upper interconnect M2.

[0118] The second bonding layer BNL2 may include a plurality of second bonding pads CBD and a second bonding insulating pattern 210 that insulates the second bonding pads CBD from each other.

[0119] The second bonding layer BNL2 of the second semiconductor structure 200A can be bonded to the first bonding layer BNL1 of the first semiconductor structure 100A in a face-to-face manner at the bonding interface BS. As a result of hybrid bonding (also known as direct bonding), the bonding interface BS can be configured between the first bonding layer BNL1 and the second bonding layer BNL2, and a metal-metal bond and a dielectric-dielectric bond can be configured simultaneously. At the bonding interface BS, a plurality of first bonding pads PBD and a plurality of second bonding pads CBD can be bonded to each other to configure a plurality of conductive bonds, and the first bonding insulating pattern 140 and the second bonding insulating pattern 210 can be bonded to each other to configure an insulating bond.

[0120] The first upper interconnect M1 can be disposed between the second bonding layer BNL2 and the stack ST. The disclosed technology shows the first upper interconnect M1 disposed in one layer, but is not limited thereto. The first upper interconnect M1 can be disposed in at least two layers.

[0121] The insulating layer 230 can be disposed on the source electrode plate 10 and the insulating patterns 11A and 11B. The second upper interconnect M2 can be disposed in the insulating layer 230. The first conductive contact plug DCC1 can connect the through contact TCT and the second upper interconnect M2 by passing through the insulating pattern 11A and the insulating layer 230. Although not shown, the second upper interconnect M2 can include an external connection pad.

[0122] Although the exemplary embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the drawings should be considered only in a descriptive sense and not for the purpose of limiting the technical scope. The technical scope of the present disclosure is not limited by these embodiments and the drawings.

[0123] Cross-reference to related applications

[0124] This application claims the priority of Korean Patent Application No. 10-2023-0180819, filed with the Korean Intellectual Property Office on December 13, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: A laminate comprising: a plurality of gate electrodes, each gate electrode including an electrode portion and a pad portion, the pad portion being disposed on a region of the electrode portion; and a plurality of interlayer insulating layers, the plurality of interlayer insulating layers and the plurality of gate electrodes being alternately stacked, the stack having a connection region in which the pad portions of the plurality of gate electrodes are arranged in a step shape; a row connection contact passing through the connection region and through a corresponding pad portion of a corresponding gate electrode among the plurality of gate electrodes to be connected to the corresponding pad portion of the corresponding gate electrode; and A plurality of first insulating patterns are disposed between the row connecting pad and a side surface of the electrode portion of the gate electrode facing the row connecting pad.

2. The three-dimensional memory device according to claim 1, wherein: The plurality of first insulating patterns include SiOC.

3. The three-dimensional memory device according to claim 1, wherein: Each of the plurality of first insulating patterns includes a first surface facing the electrode portion and a second surface facing the row connecting pad, and The first surface is aligned with a side surface of the interlayer insulating layer facing the row connection pad.

4. The three-dimensional memory device according to claim 1, wherein: Each of the plurality of first insulating patterns includes a first surface facing the electrode portion and a second surface facing the row connecting pad, and Wherein, the second surface comprises a curved surface.

5. The three-dimensional memory device according to claim 1, wherein: The row connection contact is formed integrally with the corresponding gate electrode.

6. The three-dimensional memory device according to claim 1, further comprising: a through contact extending through the stack; as well as A plurality of second insulation patterns are disposed on a side surface of the gate electrode facing the through-contact.

7. The three-dimensional memory device according to claim 6, wherein: The plurality of second insulation patterns are made of the same material as the plurality of first insulation patterns.

8. The three-dimensional memory device according to claim 7, wherein: Each of the plurality of second insulating patterns includes a first surface facing the electrode portion and a second surface facing the through-contact, and Wherein, the first surface is aligned with a side surface of the interlayer insulating layer facing the through contact.

9. The three-dimensional memory device according to claim 1, further comprising: a support extending through the stack; as well as A plurality of second insulating patterns are disposed on a side surface of the gate electrode facing the supporter.

10. The three-dimensional memory device according to claim 9, wherein: The plurality of second insulation patterns are made of the same material as the plurality of first insulation patterns.

11. The three-dimensional memory device according to claim 9, wherein: Each of the plurality of second insulating patterns includes a first surface facing the electrode portion and a second surface facing the support, and Wherein, the first surface is aligned with a side surface of the interlayer insulating layer facing the support.

12. A three-dimensional memory device, the three-dimensional memory device comprising: a first semiconductor structure, the first semiconductor structure comprising a peripheral circuit; as well as a second semiconductor structure, the second semiconductor structure being disposed on the first semiconductor structure, The second semiconductor structure comprises: A source plate, the source plate is disposed on the first semiconductor structure; A stack, the stack being arranged on the source plate, the stack comprising: a plurality of gate electrodes, each gate electrode including an electrode portion and a pad portion, the pad portion being disposed on a region of the electrode portion; and a plurality of interlayer insulating layers, the plurality of interlayer insulating layers and the plurality of gate electrodes being alternately stacked, the stack having a connection region in which the pad portions of the plurality of gate electrodes are arranged in a step shape; a row connection contact passing through the connection region and through a corresponding pad portion of a corresponding gate electrode among the plurality of gate electrodes to be connected to the corresponding pad portion of the corresponding gate electrode; and A plurality of first insulating patterns are disposed between the row connecting pad and a side surface of the electrode portion of the gate electrode facing the row connecting pad.

13. A three-dimensional memory device, the three-dimensional memory device comprising: a first semiconductor structure having a peripheral circuit and a first bonding layer including a plurality of first bonding pads connected to the peripheral circuit; as well as a second semiconductor structure bonded to the first semiconductor structure, The second semiconductor structure comprises: a second bonding layer including a plurality of second bonding pads bonded to the plurality of first bonding pads; A laminate, the laminate being disposed on the second bonding layer, the laminate comprising: a plurality of gate electrodes, each gate electrode including an electrode portion and a pad portion, the pad portion being disposed on a region of the electrode portion; and a plurality of interlayer insulating layers, the plurality of interlayer insulating layers and the plurality of gate electrodes being alternately stacked, the stack having a connection region in which the pad portions of the plurality of gate electrodes are arranged in a step shape; a row connection contact passing through the connection region and through a corresponding pad portion of a corresponding gate electrode among the plurality of gate electrodes to be connected to the corresponding pad portion of the corresponding gate electrode; and A plurality of first insulating patterns are disposed between the row connecting pad and a side surface of the electrode portion of the gate electrode facing the row connecting pad.

14. A method of manufacturing a three-dimensional memory device, the method comprising the steps of: forming a pre-stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers; forming a stepped structure in the pre-laminate; forming a plurality of sacrificial patterns on an upper surface of the stepped structure; forming a plurality of first holes passing through the sacrificial pattern and the pre-stack; selectively forming a plurality of first insulation patterns on side surfaces of the plurality of sacrificial layers exposed by the plurality of first holes; as well as A plurality of gate electrodes are formed by replacing the plurality of sacrificial layers and the plurality of sacrificial patterns with an electrode material through the plurality of first holes, and a plurality of row connection contacts are formed in the plurality of first holes.

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