Vertical transistor based on two-dimensional material and preparation method thereof
By using graphene and MoTe2 layers in vertical transistors and combining with the van der Waals transfer process, a high-performance homogeneous material CMOS inverter was constructed, which solved the problem of the decrease in the nano-size flow mobility of traditional silicon-based semiconductors and improved the electrical characteristics of vertical transistors.
Patent Information
- Application Number
- CN202510315675.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-06-13
AI Technical Summary
Traditional silicon-based semiconductors have surface defects and dangling bond problems at nanoscale, resulting in a decrease in carrier mobility, and logic circuits based on vertical transistors face challenges in electrical interconnection and high-density integration.
Using a vertical transistor based on a two-dimensional material, including a graphene layer and a MoTe2 layer, a homogeneous material CMOS inverter is realized by stacking a first source metal layer and a second source metal layer on the MoTe2 layer, and a clean and lossless metal semiconductor Schottky junction is constructed through a van der Waals transfer process.
The channel length is not limited by the lithography machine, and the gate has the same intensity for both transistors, improving the electrical characteristics of the inverter based on the vertical transistor.
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Figure CN120152345A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of optical materials, and particularly relates to a vertical transistor based on two-dimensional materials and a preparation method thereof. Background Art
[0002] With the continuous progress of semiconductor technology, the feature size of transistors has been reduced to the nanometer level. However, traditional silicon-based semiconductors have problems such as surface defects and dangling bonds at the nanometer scale, resulting in a significant decrease in carrier mobility. To overcome these problems, researchers have begun to focus on low-dimensional materials, such as graphene, transition metal dichalcogenides (TMDCs), and carbon nanotubes. These materials have excellent surface characteristics and electrical properties. Especially in two-dimensional materials (2DMs), the surface has no dangling bonds and is a passivated surface, which can minimize the interface scattering effect and suppress the decrease in mobility within the nanometer thickness range.
[0003] Vertical field-effect transistors (VFETs) based on low-dimensional materials are considered important candidates for next-generation electronic products due to their unique structure and excellent electrical properties. The channel length of VFETs is determined by the semiconductor thickness and can be easily reduced to below 5 nm while maintaining excellent electrical performance. However, although VFETs perform well in terms of single-transistor performance, their application in logic circuits still faces challenges, especially in achieving electrical interconnection and high-density integration. Summary of the Invention
[0004] In view of the problems existing in the above-mentioned related technologies, the present invention provides a vertical transistor based on two-dimensional materials and a preparation method thereof, which can realize a homogeneous material CMOS inverter through this vertical transistor. The channel length is not limited by the lithography machine, and the gate has the same electrostatic control strength for both transistors, thereby improving the electrical characteristics of the inverter based on the vertical transistor.
[0005] In a first aspect, an embodiment of the present application provides a vertical transistor based on two-dimensional materials, including: a substrate, a graphene layer, a MoTe 2 layer, a first source metal layer, and a second source metal layer. The graphene layer and the MoTe 2 layer are sequentially disposed above the substrate, and the first source metal layer and the second source metal layer are disposed above the MoTe 2 layer.
[0006] Further, the substrate is a SiO 2 / Si substrate.
[0007] Further, the material of the first source metal layer is silver, and the material of the second source metal layer is gold.
[0008] Further, the thickness of the MoTe 2 layer is 2 to 10 nm.
[0009] In a second aspect, an embodiment of the present application provides a method for manufacturing a vertical transistor based on two-dimensional materials, for manufacturing the vertical transistor based on two-dimensional materials as described in any one of the above, including the following steps:
[0010] Form a first source metal layer and a second source metal layer on a substrate;
[0011] Spin-coat an organic solution on the surfaces of the first source metal layer and the second source metal layer, and perform a drying process to form an organic thin film layer; and
[0012] Separate the organic thin film layer, the first source metal layer, and the second source metal layer from the substrate, and transfer them above the MoTe 2 layer provided on a target substrate.
[0013] Further, the step of spin-coating an organic solution on the surfaces of the first source metal layer and the second source metal layer, and performing a drying process to form an organic thin film layer includes:
[0014] Spin-coat an organic solution on the surfaces of the first source metal layer and the second source metal layer, and perform a drying process for 2 to 10 minutes to form an organic thin film layer.
[0015] Further, before separating the organic thin film layer, the first source metal layer, and the second source metal layer from the substrate and transferring them above the MoTe 2 layer provided on a target substrate, it further includes:
[0016] Form a graphene layer and the MoTe 2 layer on the target substrate in sequence.
[0017] Further, before forming the graphene layer and the MoTe 2 layer on the target substrate in sequence, it includes:
[0018] Clean the substrate.
[0019] Further, after separating the organic thin film layer, the first source metal layer, and the second source metal layer from the substrate and transferring them above the MoTe 2 layer provided on a target substrate, it further includes:
[0020] Perform a desorption process on the organic thin film layer and the support layer.
[0021] Further, the organic thin film layer includes a PMMA thin film layer, and the support layer includes a PDMS thin film layer. The desorption treatment of the organic thin film layer and the support layer includes:
[0022] Performing desorption treatment on the PMMA thin film layer and the PDMS by acetone or acetone vapor.
[0023] In the vertical transistor based on two-dimensional materials provided in the embodiments of the present application, the graphene layer and the MoTe 2 layers are sequentially disposed above the substrate, and the first source metal layer and the second source metal layer are disposed above the MoTe 2 layer. The vertical transistor based on two-dimensional materials provided in the embodiments of the present application can implement a homogeneous material CMOS inverter through the vertical transistor. Its channel length is not limited by a lithography machine, and the gate has the same electrostatic control strength for both transistors, thereby being able to improve the electrical characteristics of the inverter based on the vertical transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts.
[0025] Figure 1 It is a schematic structural diagram of the vertical transistor based on two-dimensional materials provided in the embodiments of the present application;
[0026] Figure 2 It is a schematic diagram of the technical structure principle of the vertical transistor based on two-dimensional materials provided in the embodiments of the present application;
[0027] Figure 3 It is a schematic flowchart of the preparation method of the vertical transistor based on two-dimensional materials provided in the embodiments of the present application.
[0028] The realization, functional features and advantages of the purpose of the present application will be further described with reference to the embodiments and the drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.
[0030] It should be understood that, as used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.
[0031] It should also be understood that the terms used in the specification of this application are merely for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification of this application and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific circumstances.
[0032] Referring to Figure 1 and Figure 2 , an embodiment of this application provides a vertical transistor based on two-dimensional materials, including: a substrate, a graphene layer, a MoTe 2 (molybdenum telluride) layer, a first source metal layer and a second source metal layer. The graphene layer and the MoTe 2 layer are sequentially disposed above the substrate, and the first source metal layer and the second source metal layer are disposed above the MoTe 2 layer.
[0033] As Figure 1 and Figure 2 shown, the vertical transistor based on two-dimensional materials provided by the embodiment of this application is to construct vertical transistors with different polarities using the same two-dimensional material and design it into logic devices such as inverters. First, in terms of device structure design, in a CMOS inverter, the drains of the P-type transistor and the N-type transistor are connected. Therefore, the same single-layer graphene is selected as the first layer structure of the two vertical transistors. The graphene layer simultaneously serves as the drains of the two vertical transistors, and MoTe 2 layered materials and source metals are stacked in different regions above it to respectively implement an N-type vertical transistor and a P-type transistor, and there is no need for subsequent redundant processes to connect the drains of the two transistors.
[0034] It should be emphasized that in order to enable the back-gate electric field to penetrate the bottom layer material to regulate the channel material, a single-layer graphene must be used as the bottom drain electrode because its electrostatic shielding effect on the back-gate electric field is almost minimal.
[0035] In addition, when the input is at a low level (logic 0), the gate voltage of the P-type transistor is lower than the source voltage (Vcc). Therefore, the P-type transistor conducts. At this time, the P-type transistor connects the output terminal to Vcc (high level) through the power supply Vcc. Thus, the output is at a high level (logic 1). And the gate voltage of the N-type transistor is lower than the source voltage (ground), so the N-type transistor does not conduct, and the output terminal will not be pulled down. When the input is at a high level (logic 1), the gate voltage of the P-type transistor is higher than the source voltage (Vcc). Therefore, the P-type transistor does not conduct. At this time, the gate voltage of the N-type transistor is higher than the source voltage (ground), so the N-type transistor conducts and pulls the output terminal to ground, making the output at a low level (logic 0). Therefore, in the static state (when the input does not change), this inverter hardly consumes current because when the input is at a high level or a low level, only one transistor conducts while the other transistor is cut off. Therefore, almost no current flows through the circuit. Only when the input signal changes, will there be current flow, which is usually very small.
[0036] Many two-dimensional materials exhibit bipolar characteristics. The Schottky barrier height of the metal-semiconductor junction can be adjusted by changing manufacturing processes and contact metals, etc., so as to realize the regulation of the polarity of two-dimensional transistors. Simply put, when the electron Schottky barrier of the metal-semiconductor contact is much smaller than that of holes, the transistor will exhibit N-type behavior, and vice versa for P-type behavior. Based on this, the vertical transistor based on two-dimensional materials provided in the embodiments of this application uses MoTe 2 as the channel material, which exhibits different polarities based on different process methods in planar transistor applications and has the potential to construct a CMOS circuit based on homogeneous materials for planar transistors. The vertical transistor based on two-dimensional materials provided in the embodiments of this application focuses on the different polarity presentations in the vertical transistor structure.
[0037] Therefore, in the vertical transistor based on two-dimensional materials provided in the embodiments of this application, the graphene layer and the MoTe 2 layer are sequentially arranged above the substrate, and the first source metal layer and the second source metal layer are arranged above the MoTe 2 layer. The vertical transistor based on two-dimensional materials provided in the embodiments of this application can realize a CMOS inverter based on homogeneous materials through this vertical transistor. Its channel length is not limited by the lithography machine, and the gate has the same electrostatic control strength for both transistors, thereby being able to improve the electrical characteristics of the inverter based on vertical transistors.
[0038] In the MoTe 2 layer used in the vertical transistor based on two-dimensional materials provided in the embodiments of this application, the carrier mobility of MoTe 2 is relatively high (up to about 50 cm for a single layer 2 / Vs), and its surface has no dangling bonds, with low interface scattering effect, making it suitable for high-performance transistors, MoTe 2 The vertical stacking characteristics of 2 make it suitable for high-density integrated circuits. Through the van der Waals lamination process, the stacking of multiple vertical transistors can be achieved while maintaining excellent electrical properties. Therefore, by interconnecting p-type and n-type MoTe 2 vertical transistors, an inverter circuit can be constructed, which can fully utilize the thickness advantage and electrical properties of MoTe 2 to break through the limitation of traditional planar transistors in lithography resolution.
[0039] Furthermore, the substrate is a SiO 2 / Si substrate. The substrate can be made of SiO 2 / Si, AlO 3 or Si. Due to their own characteristics, the material of the substrate will have different effects on the interaction between graphene and the substrate, and the specific material of the substrate is selected according to the actual situation.
[0040] Furthermore, the material of the first source metal layer is silver, and the material of the second source metal layer is gold.
[0041] Specifically, as shown in Figure 1 and Figure 2 , the first source metal layer serves as the ground terminal of the constructed CMOS inverter, while the first source metal layer serves as the power supply terminal of the constructed CMOS inverter. The material of the first source metal layer is silver, and the material of the second source metal layer is gold to enhance the conductivity of the source metal layer.
[0042] Furthermore, the thickness of the MoTe 2 layer is 2 to 10 nm, thus ensuring the realization of the functions of vertical transistors. The specific thickness of the MoTe 2 layer should be determined according to the actual situation and is not limited here.
[0043] In addition, referring to Figure 3 , the embodiment of the present application provides a method for manufacturing a vertical transistor based on two-dimensional materials for manufacturing the vertical transistor based on two-dimensional materials as described above, including the following steps:
[0044] S101: Form a first source metal layer and a second source metal layer on the substrate;
[0045] S102: Spin-coat an organic solution on the surfaces of the first source metal layer and the second source metal layer, and perform a drying treatment to form an organic thin film layer; and
[0046] S103: Separate the organic thin film layer, the first source metal layer, and the second source metal layer from the substrate and transfer them onto the MoTe 2 layer above.
[0047] Specifically, the polarity regulation of the MoTe 2 vertical transistor is based on the regulation of the Schottky barrier of the MoTe 2 -metal contact, that is, different work functions are selected to contact it to form different Schottky barriers. This means that the metal-semiconductor contact interface must be ideal enough and there should be no surface states, otherwise it will cause a serious Fermi level pinning effect, resulting in the inability to adjust the Schottky barrier by changing the metal work function. However, traditional metallization processes involve the bombardment of the semiconductor material surface by high-energy particles, resulting in a high density of states and defects on the material surface. For thin-layer two-dimensional materials, the bombardment of high-energy particles may penetrate the entire material. Therefore, the metallization process of the vertical transistor based on two-dimensional materials provided in the embodiments of the present application will be realized by the van der Waals transfer process. A clean and damage-free metal-semiconductor Schottky junction is constructed through dry transfer to minimize the interference of impurities on the transistor performance and change the metal to adjust its Schottky barrier of the metal-semiconductor junction. Specifically, the electron affinity of MoTe 2 is about 3.9 eV and the bandgap is about 1.1 eV. Therefore, when it forms a clean van der Waals contact with an Ag electrode with a work function of 4.26 eV, it will have a lower electron barrier and a higher hole barrier, resulting in its N-type behavior under the regulation of the gate voltage; on the contrary, when it forms a clean van der Waals contact with a gold electrode with a work function of 5.1 eV, it will have a lower hole barrier and a higher electron barrier, resulting in its P-type behavior under the regulation of the gate voltage.
[0048] Therefore, the embodiments of the present application provide a method for manufacturing a vertical transistor based on two-dimensional materials. First, a first source metal layer and a second source metal layer need to be formed on a substrate. Then, an organic solution is spin-coated on the surfaces of the first source metal layer and the second source metal layer and dried to form an organic thin film layer. Finally, the organic thin film layer, the first source metal layer, and the second source metal layer are separated from the substrate and transferred onto the MoTe 2 layer above. The metallization process of the vertical transistor based on two-dimensional materials provided in the embodiments of the present application will be realized by the van der Waals transfer process. A clean and damage-free metal-semiconductor Schottky junction is constructed through dry transfer to minimize the interference of impurities on the transistor performance and change the metal to adjust its Schottky barrier of the metal-semiconductor junction.
[0049] Further, the step of spin-coating an organic solution on the surfaces of the first source metal layer and the second source metal layer and drying to form an organic thin film layer includes:
[0050] Spin-coat an organic solution on the surfaces of the first source metal layer and the second source metal layer, and perform a drying process for 2 to 10 minutes to form an organic thin film layer.
[0051] Specifically, the function of the organic thin film layer is to protect the suspended two-dimensional material device. When transferring the suspended two-dimensional material device, it is necessary to spin-coat an organic solution on the surface of the suspended two-dimensional material device and perform a drying process for 2 to 10 minutes to form an organic thin film layer, so that the suspended two-dimensional material device can be effectively protected.
[0052] It should be noted that the drying time is within the range of 2 to 10 minutes, and the specific drying time depends on the actual situation and is not limited here.
[0053] Further, before separating the organic thin film layer, the first source metal layer and the second source metal layer from the substrate and transferring them above the MoTe 2 layer disposed on the target substrate, it further includes:
[0054] Form a graphene layer and the MoTe 2 layer on the target substrate in sequence.
[0055] Specifically, a mechanical cleavage method can be used to obtain monolayer graphene and MoTe 2 thin layers with a thickness of less than 10 nm from the original crystal, so as to facilitate subsequent operations.
[0056] Further, before forming the graphene layer and the MoTe 2 layer on the target substrate in sequence, it includes:
[0057] Clean the substrate.
[0058] Specifically, in semiconductor processes, substrate cleaning is a crucial step. The purpose of cleaning is to remove contaminants on the substrate surface, which may include dust, grease, metal ions, organic substances, etc. These contaminants will affect the quality of subsequent process steps, such as lithography, etching, ion implantation, etc., thus affecting the performance and reliability of the final device.
[0059] The cleaning step usually includes multiple sub-steps, such as chemical cleaning (using acidic or alkaline solutions to remove organic substances and metal ions), physical cleaning (using ultrasonic waves or sandblasting to remove solid particles), deionized water rinsing (removing residual chemicals and ions), etc. The specific cleaning methods and steps depend on the type of substrate material, the type and concentration of contaminants, and the requirements of subsequent processes.
[0060] Further, after separating the organic thin film layer, the first source metal layer, and the second source metal layer from the substrate and transferring them onto the MoTe 2 layer above a target substrate, the method further includes:
[0061] Performing a desorption treatment on the organic thin film layer and the support layer.
[0062] Specifically, after separating the organic thin film layer, the first source metal layer, and the second source metal layer from the substrate and transferring them onto the MoTe 2 layer above a target substrate, the organic thin film layer and the support layer have lost their value. Therefore, it is necessary to perform a desorption treatment on the organic thin film layer and the support layer to avoid affecting the normal use of the device.
[0063] Further, the organic thin film layer includes a PMMA thin film layer, and the support layer includes a PDMS thin film layer. The performing of the desorption treatment on the organic thin film layer and the support layer includes: performing a desorption treatment on the PMMA thin film layer and the PDMS by using acetone or acetone vapor.
[0064] In the method for preparing a suspended two-dimensional material device provided in the embodiments of the present application, the organic thin film layer includes a polymethyl methacrylate thin film layer (Polymethyl Methacrylate, PMMA) or a polystyrene thin film layer (Polystyrene, PS), the support layer includes a polydimethylsiloxane thin film layer (Polydimethylsiloxane, PDMS) or a silica gel thin film layer, and acetone is a representative low-boiling-point and fast-drying polar solvent with strong dissolving ability and is soluble in water. The organic thin film layer and the support layer made of the above materials can be dissolved in acetone. Therefore, a desorption treatment can be performed on the organic thin film layer and the support layer. In the existing technology of transferring electrodes from a silicon oxide substrate through PMMA, strong acid / alkaline solutions need to be used to corrode the silicon oxide layer, which will inevitably damage the surface of the sample, contaminate the surface of the electrode pattern, and is environmentally unfriendly. However, the method for preparing a suspended two-dimensional material device provided in the embodiments of the present application only needs to use acetone to desorb the organic thin film layer and the support layer without using other toxic and harmful chemical substances, which is environmentally friendly.
[0065] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims
1. A vertical transistor based on two-dimensional materials, characterized in that: include: A substrate, a graphene layer, a MoTe2 layer, a first source metal layer and a second source metal layer, wherein the graphene layer and the MoTe2 layer are sequentially arranged above the substrate, and the first source metal layer and the second source metal layer are arranged above the MoTe2 layer.
2. The vertical transistor according to claim 1, wherein: The substrate is a SiO2 / Si substrate.
3. The vertical transistor according to claim 2, characterized in that The material of the first source metal layer is silver, and the material of the second source metal layer is gold.
4. The vertical transistor according to any one of claims 1 to 3, characterized in that: The thickness of the MoTe2 layer is 2 to 10 nm.
5. A method for preparing a vertical transistor based on a two-dimensional material, used for preparing a vertical transistor based on a two-dimensional material as claimed in any one of claims 1 to 4, characterized in that: The following steps are involved: forming a first source metal layer and a second source metal layer on a substrate; Spin coating an organic solution on the surface of the first source metal layer and the second source metal layer, and performing a drying process to form an organic thin film layer; and The organic thin film layer, the first source metal layer and the second source metal layer are separated from the substrate and transferred onto a MoTe2 layer disposed on a target substrate.
6. The method according to claim 1, characterized in that The step of spin coating the organic solution on the surface of the first source metal layer and the second source metal layer and performing drying treatment to form an organic thin film layer includes: An organic solution is spin-coated on the surface of the first source metal layer and the second source metal layer, and a drying process is performed for 2 to 10 minutes to form an organic thin film layer.
7. The method according to claim 1, characterized in that Before separating the organic thin film layer, the first source metal layer and the second source metal layer from the substrate and transferring them to the MoTe2 layer disposed on the target substrate, the method further includes: A graphene layer and the MoTe2 layer are sequentially formed over the target substrate.
8. The method according to claim 7, characterized in that Before sequentially forming a graphene layer and a MoTe2 layer on the target substrate, the method comprises: The substrate is cleaned.
9. The method according to claim 1, characterized in that After separating the organic thin film layer, the first source metal layer and the second source metal layer from the substrate and transferring them to above the MoTe2 layer disposed on the target substrate, the method further includes: The organic film layer and the support layer are subjected to a desorption treatment.
10. The method according to claim 9, characterized in that The organic film layer includes a PMMA film layer, the support layer includes a PDMS film layer, and the desorption treatment of the organic film layer and the support layer includes: The PMMA film layer and the PDMS are desorbed by acetone or acetone vapor.